TW202117925A - 具有獨立閘極控制之垂直堆疊互補ｆｅｔ裝置 - Google Patents

具有獨立閘極控制之垂直堆疊互補ｆｅｔ裝置 Download PDF

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TW202117925A
TW202117925A TW109132087A TW109132087A TW202117925A TW 202117925 A TW202117925 A TW 202117925A TW 109132087 A TW109132087 A TW 109132087A TW 109132087 A TW109132087 A TW 109132087A TW 202117925 A TW202117925 A TW 202117925A
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gate electrode
transistor
conductive material
gate
type
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TW109132087A
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TWI752640B (zh
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朱利安 弗羅吉爾
謝瑞龍
帕尼特 哈瑞漢德拉 蘇瓦納
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種裝置包括：第一電晶體裝置，屬於第一類型；第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；閘極結構，用於該第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極；閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離；第一溝道半導體材料，用於該第一電晶體裝置，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍；以及第二溝道半導體材料，用於該第二電晶體裝置，其中，該第二閘極電極位於該第二溝道半導體材料之至少部分的周圍。

Description

具有獨立閘極控制之垂直堆疊互補FET裝置
一般而言，本揭露關於半導體裝置的製造，更具體而言，關於形成具有獨立閘極控制的垂直堆疊互補場效應電晶體(FET)裝置的各種新方法以及由此產生的裝置。
在現代積體電路中，例如微處理器、儲存裝置等，大量的電路元件(特別是電晶體)被提供於一有限的芯片區域上。電晶體有各種形狀和形式，例如，平面型電晶體、鰭片式場效應電晶體、奈米線裝置等。該電晶體通常是NMOS(NFET)或PMOS(PFET)類型裝置，其中，“N”和“P”的指定是基於創建該裝置的源汲(source/drain)區域的摻雜劑類型。所謂的CMOS(Complementary Metal Oxide Semiconductor；互補式金屬氧化物半導體)技術或產品是指利用NMOS和PMOS電晶體裝置製造的積體電路產品。無論電晶體裝置的物理配置如何，每個裝置包括源極和汲極區域，以及位於源汲區域的上方和之間的一閘極電極(gate electrode)結構。在該閘極電極上施加一適當的控制電壓之後，在汲極區域和源極區域之間形成一導電溝道區域。
一傳統的場效應電晶體(FET)是一種平面型裝置，其中，該裝置的整個溝道區域是平行於且略低於該半導體基板(substrate)的該平面型上表面而形成。與一平面型場效應電晶體不同，有所謂的三維(3D)裝置，例如一說明性的三維結構的鰭片式場效應電晶體(FinFET)裝置。
一種顯示未來先進IC產品前景的裝置的類型通常被稱為一奈米片裝置。通常，一奈米片裝置具有由複數個垂直間隔的半導體材料片組成的一鰭片式溝道結構。該裝置的一閘極結構位於每個這些間隔的溝道半導體材料層的周圍。這種奈米片裝置可以形成為一高速邏輯電路的一部分。通常，該奈米片裝置可以在一相對較低的電壓下運行，例如1V或更低(基於當今的技術)，且其是針對高速運行和低功耗(特別是用於智慧型手機等移動裝置中使用的IC產品)所專門設計。
一複合環閘(gate-all-around)技術的一實施例是一互補場效應電晶體(CFET)，它是一個三維單片結構，具有垂直堆疊在彼此頂部的NFET和PFET奈米線/奈米片。一CFET佈局通常在一個級別(level)上具有P型FET，並在一相鄰級別(即，高於或低於)上具有N型FET。在這種結構中，較低級別之場效應電晶體的源汲區域藉由介電層與較高級別之場效應電晶體的源汲區域電性隔離。
為了平衡CMOS裝置的閾值電壓，PMOS和NMOS裝置通常使用不同的閘極材料。該閘極材料通常使用一替換閘極製程以使用所需的閘極材料替換一占位符(placeholder)材料而形成。由於奈米片裝置的空間限制，很難藉由實行一替換閘極製程來形成不同的閘極材料。
本揭露關於可以避免或至少減少上述一個或更多問題的影響的各種方法以及由此方法產生的裝置。
以下呈述本發明的簡化摘要，以便對本發明的一些方面提供基本的理解。本摘要不是對本發明的詳盡概述。且不打算用於識別本發明的關鍵或關鍵元素，或用於劃定本發明的範圍。其唯一目的是以簡化形式提出一些概念，以作為後續討論更詳細描述的序言。
一般而言，本揭露申請案揭露關於形成具有獨立閘極控制的垂直堆疊互補場效應電晶體裝置的各種新穎方法以及由此方法產生的裝置。本文揭露的一示例性裝置包括：第一電晶體裝置，屬於第一類型；第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；閘極結構，用於該第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極；閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離；第一溝道半導體材料，用於該第一電晶體裝置，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍；以及第二溝道半導體材料，用於該第二電晶體裝置，其中，該第二閘極電極位於該第二溝道半導體材料之至少部分的周圍。
本文揭露的另一示例性裝置包括：第一電晶體裝置，屬於第一類型；第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；第一溝道半導體材料，用於該第一電晶體裝置；第二溝道半導體材料，用於該第二電晶體裝置，其中，該第一溝道半導體材料和該第二溝道半導體材料包括相同的半導體材料；閘極結構，用於該 第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍，該第二閘極電極位於該第二溝道半導體材料之至少部分的周圍，以及其中，該第一閘極電極和該第二閘極電極包括不同的材料；以及閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離。
本文揭露的又一示例性裝置包括：第一電晶體裝置，屬於第一類型；第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；第一溝道半導體材料，用於該第一電晶體裝置；第二溝道半導體材料，用於該第二電晶體裝置；閘極結構，用於該第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍，該第二閘極電極位於該第二溝道半導體材料之至少部分的周圍，以及其中，該第一閘極電極和該第二閘極電極包括不同的材料；以及閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離。
100:積體電路裝置、互補場效應電晶體裝置或產品
100’:互補場效應電晶體裝置
110:基板、半導體基板或塊體基板
115:奈米片堆疊
120:閘極結構
125,130,135,405,410,415,420:半導體材料層
125L,125U:反摻雜區域
140:硬遮罩層或硬遮罩
145:隔離結構
150:上部或上部區域
155:下部或下部區域
160:下間隔件或間隔件
165,170,180,260,310,425,435:遮罩層
175:上間隔件或間隔件
185:犧牲閘極結構或閘極結構
190:蓋層
195:堆疊空腔
200:側壁間隔件
205:底部間隔件
210:閘極堆疊間隔件
215:源汲空腔
220:內間隔件
225:下源汲區域
230:源汲外延間隔件
235:上源汲區域
240:介電層
245:閘極空腔或空腔
250:內空腔、閘極空腔或空腔
253:閘極絕緣層
255:第一導電材料
265:第一閘極電極
270:第二導電材料
275:第二閘極電極
280:介電蓋層或蓋層
285,290:閘極接觸件
295:第三導電材料
300:虛線框
305:共形間隔層或間隔層
315:第二遮罩層或遮罩層
320:第二共形間隔層或間隔層
400:奈米片堆疊
430,445:端部間隔件
440:端部空腔
本揭露可藉由參考結合附圖的下述描述來理解，其中。相似的參考數字表示相似的元件，且其中：
第1A圖至第1P圖描述了本文所公開的用於在具有垂直堆疊的P型和N型場效應電晶體的一互補場效應電晶體裝置100中形成雙替換閘極的各種新穎方法；
第2A圖至第2D圖描繪了用於形成上和下間隔件的一替換流程；以及
第3A圖至第3D圖描繪了使用一端部間隔配置形成上和下間隔件的一替換流程。
雖然本文所公開的主題容易受到各種修改和替代形式的影響，但其具體實施例已在附圖中以示例的形式予以揭露，並在本文中詳細描述。然而，應當理解的是，本文對於具體實施例的描述並旨在將本發明限定於所公開的特定形式，相反，其目的在於涵蓋所有的修改、等價物和替代物。這些修改、等價物和替代物均屬本發明所附申請專利範圍所定義的精神和範圍內。
本發明的各種說明性實施例的描述如下。為了清楚起見，本說明書中並沒有描述實際施行的所有特徵。當然，在任何此類實際實施例的開發過程中，必須做出許多具體的特定施行決策，以實現開發人員的特定目標，例如符合與系統相關的和與業務相關的約束，這些約束在不同的實施過程中會有所不同。此外，應當瞭解，這種開發工作可能複雜且耗時，但是對於從本揭露中獲益的本領域的普通技術人員而言，這仍然是一項常規工作。
現參照附圖說明本主題。示意性的描繪於附圖中的各種結構、系統和裝置僅用於解釋，以使本揭露不被本領域技術人員所熟知的細節所掩蓋。因此，所附圖式用於描述和解釋本揭露的說明性實施例。本文所使用的詞語和短 語，其含義應與相關領域技術人員對這些詞語和短語的理解相一致。本領域技術人員所理解的術語或短語的特殊定義，即與普通和習慣含義不同的定義，在本文中並不打算藉由一致使用的術語或短語來暗示。如果一個術語或短語具有特殊含義，即除本領域技術人員所理解的含義以外的其他含義，則說明書中將以直接且明確地為該術語或短語提供特殊定義的定義方式明確規定此類特殊定義。本領域技術人員在完全閱讀本申請後容易看出，本文公開的方法可用於製造各種不同的裝置，包括但不限於邏輯裝置、儲存器(memory)裝置等，並且這些裝置可以是NMOS或PMOS裝置。
如本領域技術人員在完全閱讀本申請之後所瞭解的，附圖中未描繪出各種摻雜區域，例如，源汲區域、光暈植入區域、阱區域等。當然，本文所揭露的發明不應被視為僅限於本文所描述的說明性實施例。本文所揭露的積體電路裝置100的各種元件和結構可以使用各種不同的材料並藉由執行各種已知技術而形成，例如，一化學氣相沉積(chemical vapor deposition；CVD)製程、一原子層沉積(atomic layer deposition；ALD)製程、一熱生長製程、旋塗製程等。這些不同材料層的厚度也可能因具體的應用而有所不同。參考所附圖示，現在將更詳細地描述本文所公開的方法和裝置的各種示例性實施例。
第1A圖至第1P圖描繪了本文所揭露的用於在具有垂直堆疊的P型和N型場效應電晶體的一互補場效應電晶體裝置100中形成雙替換閘極的各種新穎方法。在本文所描述的實施例中，互補場效應電晶體裝置100將形成在一半導體基板110中及上方。基板110可以具有多種配置，例如所描繪的塊體配置。也可以使用一絕緣體上半導體(semiconductor-on-insulator；SOI)配置，其包括一塊體半導體層、位於該塊體基板110上的一埋入絕緣層、以及位於該埋入絕 緣層上的一個或複數個半導體材料層。基板110可以由矽製成，或也可以由矽以外的材料製成，例如，矽鍺、III-V族複合半導體材料等。因此，術語“基板”或“半導體基板”應理解為涵蓋所有半導體材料以及所有形式的此類材料。
在本文所描述的實施例中，互補場效應電晶體裝置100可以形成為一高速邏輯電路的一部分。該說明性互補場效應電晶體裝置100包括一奈米片堆疊115，以及橫跨奈米片堆疊115的閘極結構120(在平面圖中以虛線表面)。在一些實施例中，奈米片堆疊115可以是一鰭片狀結構(即，相對於其軸向長度，具有一窄寬度的一奈米片堆疊)。各奈米片堆疊115包括複數個交錯的半導體材料層125,130,135。這些附圖包含產品100的一簡單平面圖，指示不同的橫截面圖的位置。取自裝置100的閘極長度方向(垂直於閘極結構120)的一“X-X”視圖，以及取自裝置100的一閘極寬度方向(沿閘極結構120的一軸向長度)的一“Y-Y”視圖。但是，並不試圖在裝置100的平面圖中顯示附圖中的橫截面圖中所示的各種步驟。
第1A圖描繪了產品100的一個製造階段，其中，已經執行了若干製程操作。首先，半導體材料層125,130,135的堆疊形成在基板110的上方。而後，在該堆疊的上方形成一硬遮罩層140(例如，氮化矽)。使用硬遮罩140執行一蝕刻製程以定義該奈米片堆疊115。形成鄰近於奈米片堆疊115的一隔離結構145(例如，二氧化矽)。通常，半導體材料層125,130,135由不同的半導體材料所製成，以使它們可以相對彼此被選擇性的移除(藉由蝕刻)。在本文描述的實施例中，半導體材料層125,130本質上是犧牲的，而半導體材料層125將成為互補場效應電晶體裝置100的溝道區域材料。在一說明性實施例中，半導體材料層125可包含基本上純矽(pure silicon)，半導體材料層130可以包括矽鍺(SixGe(1-x)， 其中，x在0.65到0.85的範圍內)，而半導體材料層135可以包括矽鍺(SiyGe(1-y)，其中，y在0.25到0.5的範圍內)。半導體材料層125,130,135的厚度可以根據具體的應用而變化，且不必具有相同的厚度。
中間的半導體材料層135將互補場效應電晶體裝置100分為一上部150以及一下部155。在一些實施例中，上部150可以與一N型電晶體相關聯，下部155可以與一P型電晶體相關聯(當然，反之亦可)。為上部和下部所形成的半導體材料層125,130的數量可以根據具體應用而變化。在本文所描述的示例性實施例中，在每個部分150,155中，溝道區域均有一半導體材料層125。互補場效應電晶體裝置100的有效尺寸可以藉由在每個部分150,155中提供由額外的半導體材料層130所隔開的額外的半導體材料層125來調整。
第1B圖揭示了在執行了若干製程後，於奈米片堆疊115上定義一下間隔件160的互補場效應電晶體裝置100。在奈米片堆疊115之上形成間隔材料的一共形層，並執行一各向異性(anisotropic)蝕刻製程以移除間隔材料層的水平部分，並降低間隔層的垂直部分的高度以定義下間隔件160。控制下間隔件160的高度，使得上表面部分地與中間半導體材料135重疊。
第1C圖揭示了一遮罩層165(例如，有機圖案化層(organic patterning layer；OPL))形成在奈米片堆疊115的上方並被圖案化以覆蓋奈米片堆疊115的右側部分且暴露奈米片堆疊115的左側部分，而暴露間隔件160的一部分之後的互補場效應電晶體裝置100。可執行一蝕刻製程以移除間隔件160的暴露部分。
第1D圖揭示在執行若干製程後的互補場效應電晶體裝置100。遮罩層165被剝離。一遮罩層170(例如OPL)形成在奈米片堆疊115的上方並且 被凹陷以覆蓋奈米片堆疊115的一底部部分。一上間隔件175形成在遮罩層170的上方鄰近奈米片堆疊115的位置(例如，使用上述與下間隔件160相類似的製程)。上間隔件175的位置基於遮罩層170的厚度進行控制，以便上間隔件175的下表面覆蓋上部區域150中的半導體材料層125,130，而不覆蓋下部區域155中的半導體材料層125,130。上間隔件175的高度受到控制，使得下表面部分地與中間半導體材料135重疊。
第1E圖揭示在一遮罩層180(例如有機圖案化層(OPL))形成在奈米片堆疊115和先前形成的遮罩層170的上方並被圖案化以覆蓋奈米片堆疊115的左側部分且暴露奈米片堆疊115的右側部分之後的互補場效應電晶體裝置100。執行一蝕刻製程以移除上間隔件175的暴露部分。可以選擇下間隔件160和上間隔件175的材料，以便使它們相對於彼此進行選擇性蝕刻。例如，一個間隔件160，175可以由氮化物基於低K常數材料(例如SiBCN)形成，而另一個間隔件160,175可以由氧化物基於低K常數材料(例如SiOC)形成。
第1F圖揭示在執行若干製程之後，沿著視圖Y-Y和X-X的互補場效應電晶體裝置100。遮罩層170,180被剝離。硬遮罩層140被移除。犧牲閘極結構185形成在其上方，並接觸奈米片堆疊115的頂部和側壁表面。犧牲閘極結構185本質上是犧牲的，因為它們在製程流程的後期會被其他材料所替換以形成功能性閘極結構，如下所述。犧牲閘極結構185可以包括一層或複數層材料，例如一犧牲閘極絕緣層(例如，二氧化矽)，以及未單獨示出的一犧牲閘極材料(例如非晶矽)。用於圖案化犧性閘極結構185的圖案化硬遮罩層所剩餘的蓋層190(例如，氮化矽或包括氮化矽和二氧化矽的堆疊)位於閘極結構185的上方。
第1G圖揭示了在執行一選擇性蝕刻製程以移除半導體材料層135並定義堆疊空腔195之後的互補場效應電晶體裝置100。
第1H圖揭示了在鄰近犧牲閘極結構185形成側壁間隔件200之後的互補場效應電晶體裝置100(即，使用與上述下間隔件160類似的製程)。側壁間隔件200的材料也填充至堆疊空腔195，以定義隔離奈米片堆疊115與基板110的一底部間隔件205以及隔離奈米片堆疊115的上部150與奈米片堆疊115的下部的一閘極堆疊間隔件210。
第1I圖揭示了在執行若干製程之後的互補場效應電晶體裝置100。使用犧牲閘極結構185和側壁間隔件200作為一蝕刻遮罩以執行一蝕刻製程，以定義源汲空腔215。執行一個各向同性(isotropic)蝕刻製程以凹陷半導體材料層130，從而定義其端部的端部空腔。執行一共形沉積製程(例如一ALD製程)以形成一間隔材料層於奈米片堆疊115和犧牲閘極結構185的上方，並且各向異性蝕刻間隔層以於端部空腔中定義內間隔件220。執行複數個沉積製程以於源汲空腔215中定義一下源汲區域225(例如，P型epi)、一源汲外延間隔件230(例如，介電材料)、以及一上源汲區域235(例如N型epi)。沉積並平坦化一介電層240以暴露犧牲閘極結構185(例如，藉由移除蓋層190)。
第1J圖揭示了在執行若干蝕刻製程以移除犧牲閘極結構185和半導體材料層130，而定義閘極空腔245和內空腔250(即圍繞半導體材料層125的閘極空腔250的部分)之後的互補場效應電晶體裝置100。
第1K圖揭示了在執行若干製程之後的互補場效應電晶體裝置100。執行一第一沉積製程以形成一閘極絕緣層253(例如，高K介電，如氧化鉿-如虛線所示)於閘極空腔245,250中。執行一個或複數個沉積製程，以於閘極絕 緣層253上方的空腔245,250中形成一第一導電材料255。執行一回蝕刻製程以從閘極空腔245的上部移除第一導電材料255，同時使內空腔250保持填充狀態。第一導電材料255可以是一功函數材料(work function material；WFM)層或層的堆疊。在一些實施例中，WFM材料可適用於一P型裝置。一示例性PFET WFM材料是錫。可沉積第一導電材料255以完全填充內空腔250和閘極空腔245，然後，回蝕刻以移除閘極空腔245的上部中的部分第一導電材料255。在另一實施例中，可將第一導電材料255沉積為一共形層，其填充內空腔250並勾勒(line)閘極空腔245的上部。可藉由形成一OPL層以覆蓋內空腔250中的第一導電材料255的側面，並執行一蝕刻製程以移除勾勒閘極空腔245的上部的部分第一導電材料255，從而倒角(chamfer)該共形層。
第1L圖揭示了在一遮罩層260(例如OPL)形成在奈米片堆疊115的上方，並被圖案化以覆蓋第一導電材料255的左側部分且暴露右側部分之後的互補場效應電晶體裝置100。遮罩層260、上間隔件175、下間隔件160、和閘極堆疊間隔件210的組合保護下部區域155中的第一導電材料255，並暴露上部區域150中的第一導電材料255。
第1M圖揭示了執行一蝕刻製程以移除第一導電材料255的暴露部分，重新打開上部區域150中的空腔250之後的互補場效應電晶體裝置100。第一導電材料255的剩餘部分定義在下部區域155中的一第一閘極電極265(例如，PFET部分)。
第1N圖揭示了在執行一剝離製程以移除遮罩層260，並執行一個或複數個沉積製程以於閘極絕緣層253上方的空腔245,250中形成一第二導電材料270之後的互補場效應電晶體裝置100。執行一回蝕刻製程以從閘極空腔 245移除第二導電材料270，同時使上部區域150中的內空腔250保持填充狀態。第二導電材料270可以是適於一N型裝置的一WFM層或層的堆疊。一示例性NFET WFM材料是包含TiN/TiC/TiN的堆疊。當然，其他WFM材料可用於第一和第二導電材料255,270。第二導電材料270定義上部區域150中的一第二閘極電極275(例如NFET部分)。
第1O圖揭示了執行若干製程之後的互補場效應電晶體裝置100。執行一沉積製程，隨後執行一平坦化製程，以於閘極空腔245中形成一介電蓋層280。閘極接觸件285,290形成為延伸通過蓋層280(即，以及形成於蓋層280上方的任何其他介電層)以分別接觸第一閘極電極265和第二閘極電極275。在此配置中，第一閘極電極265和第二閘極電極275是獨立的。
第1P圖揭示了在替代製程流程中執行若干製程之後的互補場效應電晶體裝置100。從第1N圖的互補場效應電晶體裝置100開始，執行一個或複數個沉積製程，以於閘極空腔245中形成一第三導電材料295(例如鎢)。執行一回蝕刻製程以凹陷第三導電材料295。執行一沉積製程，隨後執行一平坦化製程，以於閘極空腔245中形成蓋層280。在此配置中，第一閘極電極265和第二閘極電極275代表一共享閘極電極。可形成一單閘極接觸件(未示出)以接觸該共享閘極電極。
第三導電材料295也可與獨立的閘極電極一起使用，其藉由執行一圖案化蝕刻，以切割虛線框300所指示的區域中的第三導電材料295，並用蓋層280填充由此產生的凹槽。
在一些實施例中，間隔件160,175可以被摻雜。例如，與下部155中的N型電晶體相關聯的間隔件160可以摻雜一P型摻雜劑(例如硼B)，與上部 150中的N型電晶體相關聯的間隔件175可以摻雜一N型摻雜劑(例如磷P，砷As)。在製程流程中的任何時候，可以執行一退火製程，使間隔件160,175的摻雜劑擴散到半導體材料層125中，以定義反摻雜區域125U,125L。如果退火製程是在移除第1G圖中的半導體材料層135或移除第1J圖中的半導體材料層130之前進行的，摻雜劑也會擴散到這些層130,135中。然而，摻雜劑並不影響層130,135的蝕刻選擇性。
第2A圖至第2D圖揭示了形成下間隔件和上間隔件160,175的一替代製程流程。從第1A圖所示的互補場效應電晶體裝置100開始，執行一沉積製程以形成一共形間隔層305於奈米片堆疊115的上方。一遮罩層310(例如OPL)形成在奈米片堆疊115和間隔層305的上方，並被圖案化以覆蓋奈米片堆疊115的右側部分且暴露奈米片堆疊115的左側部分。執行一蝕刻製程以移除間隔層305的暴露部分。
第2B圖揭示了執行一剝離製程以移除遮罩層310，以及形成覆蓋下部區域155的一第二遮罩層315之後的互補場效應電晶體裝置100。執行一蝕刻製程以移除間隔層305的暴露部分，從而定義下間隔件160。
第2C圖揭示了執行一沉積製程以形成一第二共形間隔層320於遮罩層315和奈米片堆疊115的上方之後的互補場效應電晶體裝置100。
第2D圖揭示了在執行一各向異性蝕刻製程以從間隔層320形成上間隔件175之後的互補場效應電晶體裝置100。然後，可以根據所描述的從第1E圖開始繼續製程步驟。在此製程流程，間隔件160,175可以由相同材料製成。
第3A圖至第3D圖揭示了形成一互補場效應電晶體裝置100’而不形成上間隔件和下間隔件160,175的一替代製程流程。在一些實施例中，奈米 片堆疊400的配置可以與第1A圖所示的奈米片堆疊115的配置不同。隔離結構145延伸到整體奈米片堆疊400(例如一SOI基板配置)的下方。在本文所描述的實施例中，奈米片堆疊400包括半導體材料層405,410,415,420。半導體材料層410,415本質上是犧牲的，而半導體材料層405將成為互補場效應電晶體裝置100’的溝道區域材料。在一示例性實施例中，半導體材料層405可以包括基本上純矽，半導體材料層410可以包括矽鍺(SixGe(1-x)，其中x的範圍從0.65至0.85)，半導體材料415可以包括矽鍺(SiyGe(1-y)，其中y的範圍從0.25至0.5)。分離上部區域和下部區域150,155的半導體材料層420可以包括基本上純矽，且相較於半導體材料層405，可具有一減少的厚度。半導體材料層405,410,415,420的厚度可根據具體應用而變化，並且它們不需要具有相同的厚度。
第3B圖揭示了執行若干製程之後的互補場效應電晶體裝置100’。一遮罩層425形成在奈米片堆疊400的左側上方。執行一各向同性蝕刻製程以凹陷半導體材料415，以定義其端部上的端部空腔。執行一共形沉積製程，例如一ALD製程，以於奈米片堆疊400的上方形成一間隔材料層，並對該間隔層進行各向異性蝕刻以定義該端部空腔中的端部間隔件430。
第3C圖揭示了執行若干製程之後的互補場效應電晶體裝置100’。一遮罩層435形成在奈米片堆疊400的右側上方，並覆蓋奈米片堆疊400的左側的下部區域155。執行一各向同性蝕刻製程以凹陷半導體材料層410，以定義其端部上的端部空腔440。
第3D圖揭示了執行若干製程之後的互補場效應電晶體裝置100’。執行一剝離製程以移除遮罩層435。執行一共形沉積製程，例如一ALD製程， 以於奈米片堆疊400的上方形成一間隔材料層，並對該間隔層執行各向異性蝕刻，以定義端部空腔440中的端部間隔件445。
端部間隔件430定義下間隔件160，且端部間隔件445定義上間隔件175。處理步驟可根據第1E圖及後續附圖所描述的繼續執行。在一實施例中，分離上部區域和下部區域150,155的半導體材料層420包括基本上純矽，半導體材料層420的端部可以反向摻雜以避免一寄生通道的形成。
以上所公開的具體實施例僅為說明性實施例，因為本發明可以具有本領域技術人員明顯受益於本文所述教學的不同但等效的方式進行修改和實施。例如，上述過程步驟可按不同的順序執行。此外，除申請專利範圍所述之外，本文所示的架構或設計細節不受任何限制。顯而易見地，上述具體實施例可能會被替換或修改，並且所有這些變化都被考慮在本發明的範圍和精神範圍內。請注意，在本說明書和所附申請專利範圍中所使用的用於描述各種製程或結構的諸如“第一”、“第二”、“第三”或“第四”等術語，僅用作對這些步驟/結構的簡略引用，並不一定意味著這些步驟/結構是按照所述順序執行/形成的。當然，根據具體的申請專利範圍，可能需要或可能不需要此類程序的順序。當參考場效應電晶體裝置的結構時，如本文所使用的，空間參考、“頂部”、“底部”、“上”、“下”、“垂直”、“水平”等僅為使用方便。這些參考僅用於教學目的，且不作為場效應電晶體結構的絕對參考。例如，場效應電晶體的空間定向方式可能與圖紙所示的方向不同。因此，本文所尋求的保護如所附申請專利範圍中所述。
100:積體電路裝置、互補場效應電晶體裝置或產品
110:基板、半導體基板或塊體基板
115:奈米片堆疊
120:閘極結構
125,130:半導體材料層
145:隔離結構
150:上部或上部區域
155:下部或下部區域
160:下間隔件或間隔件
175:上間隔件或間隔件
185:犧牲閘極結構或閘極結構
190:蓋層
195:堆疊空腔

Claims (19)

  1. 一種半導體裝置，包括：
    第一電晶體裝置，屬於第一類型；
    第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；
    閘極結構，用於該第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極；
    閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離；
    第一溝道半導體材料，用於該第一電晶體裝置，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍；以及
    第二溝道半導體材料，用於該第二電晶體裝置，其中，該第二閘極電極位於該第二溝道半導體材料之至少部分的周圍。
  2. 如請求項1所述之半導體裝置，其中，該第一電晶體係P型電晶體，而該第二電晶體係N型電晶體。
  3. 如請求項1所述之半導體裝置，其中，該第一閘極電極包括第一導電材料，而該第二閘極電極包括第二導電材料，其中，該第一導電材料係不同於該第二導電材料。
  4. 如請求項3所述之半導體裝置，其中，該第一導電材料包括TiN，而該第二導電材料包括複數個導電材料層。
  5. 如請求項4所述之半導體裝置，其中，該複數個導電材料層包括TiN、TiC和TiN。
  6. 如請求項3所述之半導體裝置，其中，該第一導電材料包括第一功函數材料，而該第二導電材料包括第二功函數材料。
  7. 如請求項1所述之半導體裝置，其中，該閘極結構進一步包括第三導電材料，該第三導電材料係導電耦接到該第一閘極電極和該第二閘極電極。
  8. 如請求項7所述之半導體裝置，其中，該第三導電材料包括鎢。
  9. 如請求項1所述之半導體裝置，其中，該閘極結構進一步包括第三導電材料，該第三導電材料包括彼此電性隔離的第一和第二部分，其中，該第三導電材料之該第一部分係導電耦接到該第一閘極電極，而該第三導電材料之該第二部分係導電耦接到該第二閘極電極。
  10. 如請求項1所述之半導體裝置，其中，該第一溝道半導體材料和該第二溝道半導體材料包括相同的半導體材料。
  11. 一種半導體裝置，包括：
    第一電晶體裝置，屬於第一類型；
    第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；
    第一溝道半導體材料，用於該第一電晶體裝置；
    第二溝道半導體材料，用於該第二電晶體裝置，其中，該第一溝道半導體材料和該第二溝道半導體材料包括相同的半導體材料；
    閘極結構，用於該第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍，該第二閘極電極位 於該第二溝道半導體材料之至少部分的周圍，以及其中，該第一閘極電極和該第二閘極電極包括不同的材料；以及
    閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離。
  12. 如請求項11所述之半導體裝置，其中，該第一電晶體係N型電晶體，而該第二電晶體係P型電晶體。
  13. 如請求項11所述之半導體裝置，其中，該第一閘極電極包括第一導電材料，而該第二閘極電極包括第二導電材料，其中，該第一導電材料係不同於該第二導電材料。
  14. 如請求項13所述之半導體裝置，其中，該第一導電材料包括複數個導電材料層，而該第二導電材料包括TiN。
  15. 如請求項13所述之半導體裝置，其中，該第一導電材料包括第一功函數材料，而該第二導電材料包括第二功函數材料。
  16. 如請求項12所述之半導體裝置，其中，該閘極結構進一步包括第三導電材料，該第三導電材料係導電耦接到該第一閘極電極和該第二閘極電極。
  17. 如請求項12所述之半導體裝置，其中，該閘極結構進一步包括第三導電材料，該第三導電材料包括彼此電性隔離的第一和第二部分，其中，該第三導電材料之該第一部分係導電耦接到該第一閘極電極，而該第三導電材料之該第二部分係導電耦接到該第二閘極電極。
  18. 一種半導體裝置，包括：
    第一電晶體裝置，屬於第一類型；
    第二電晶體裝置，屬於第二類型，垂直地位於該第一電晶體裝置之上，其中，電晶體的該第一類型和第二類型為相反類型；
    第一溝道半導體材料，用於該第一電晶體裝置；
    第二溝道半導體材料，用於該第二電晶體裝置；
    閘極結構，用於該第一電晶體和該第二電晶體，其中，該閘極結構包括用於該第一電晶體之第一閘極電極和用於該第二電晶體之第二閘極電極，其中，該第一閘極電極位於該第一溝道半導體材料之至少部分的周圍，該第二閘極電極位於該第二溝道半導體材料之至少部分的周圍，以及其中，該第一閘極電極和該第二閘極電極包括不同的材料；以及
    閘極堆疊間隔件，垂直地位於該第一閘極電極和該第二閘極電極之間，以便將該第一閘極電極與該第二閘極電極電性隔離。
  19. 如請求項18所述之半導體裝置，其中，該第一閘極電極包括第一功函數材料，而該第二閘極電極包括第二功函數材料，其中，該第一功函數材料和該第二功函數材料包括不同的材料。
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US10784171B2 (en) 2020-09-22
TWI708318B (zh) 2020-10-21

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