WO2019072230A1 - 阵列基板及其制备方法、显示装置及其制备方法 - Google Patents

阵列基板及其制备方法、显示装置及其制备方法 Download PDF

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Publication number
WO2019072230A1
WO2019072230A1 PCT/CN2018/109977 CN2018109977W WO2019072230A1 WO 2019072230 A1 WO2019072230 A1 WO 2019072230A1 CN 2018109977 W CN2018109977 W CN 2018109977W WO 2019072230 A1 WO2019072230 A1 WO 2019072230A1
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Prior art keywords
substrate
layer
binding
insulating support
support portion
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PCT/CN2018/109977
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English (en)
French (fr)
Inventor
陈立强
王红丽
王艳丽
王有为
李建伟
蔡宝鸣
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/642,615 priority Critical patent/US20200194363A1/en
Publication of WO2019072230A1 publication Critical patent/WO2019072230A1/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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Definitions

  • the present application relates to the field of flexible display technologies, and in particular, to an array substrate, a preparation method thereof, a display device, and a preparation method thereof.
  • a display device using a flexible display panel includes a liquid crystal display device, an organic electroluminescence display device, an electrophoretic display device, and the like.
  • the flexible display device can be applied to electronic devices such as smart cards, portable computers, and electronic paper.
  • the flexible substrate is generally disposed on a glass substrate, and then various layer structures required for display are formed on the flexible substrate to form a flexible display panel. Such a process can be compatible with the preparation equipment of the related display panel.
  • the flexible substrate needs to be separated from the glass substrate, and then the back film is attached to the back surface of the flexible substrate (ie, the side of the layer structure not required for display) to planarize the flexible substrate. Then, the cutting is performed, and finally, the process of binding (Bonding) of IC (English name: Integrated Circuit, Chinese name: integrated circuit) is performed.
  • IC International name: Integrated Circuit, Chinese name: integrated circuit
  • An embodiment of the present disclosure provides a method for fabricating an array substrate, comprising: forming a plurality of binding pads in a bonding region of a substrate, wherein the binding region is a coverage area when the IC is bound; An insulating support portion is formed at a position in the binding region of the base substrate where the binding pad is not provided, the insulating support portion for maintaining between the array substrate and an IC to be bound gap.
  • the formed insulating support portion faces away from the upper surface of the substrate substrate to a height of the substrate substrate surface greater than the formed bonding pad faces away from the base substrate The height from the upper surface of one side to the surface of the substrate substrate.
  • a height of the upper surface of the insulating support to the surface of the substrate substrate, and a height of the upper surface of the binding pad to a surface of the substrate substrate The difference between them is less than or equal to the thickness of the binding pin of the IC to be bound.
  • the preparation method further includes: forming at least one insulating layer in a display region of the base substrate;
  • the insulating support formed includes a multilayer structure.
  • the forming at least one insulating layer in the display region of the base substrate includes: forming a sequence away from the substrate in the display region of the base substrate a flat layer body of the substrate, a pixel defining pattern, and a spacer pattern; forming the insulating support portion includes: sequentially forming a first sub-layer, a second sub-layer, and a third sub-layer away from the base substrate; The first sub-layer is formed in the same layer as the flat layer main body; the second sub-layer is formed in the same layer as the pixel defining pattern; and the third sub-layer is formed in the same layer as the spacer pattern .
  • the forming an insulating support portion in the bonding region of the base substrate and at a position where the binding pad is not disposed including: on the base substrate Forming a first insulating film, and patterning the first insulating film to form a flat layer body located in a display region of the base substrate, a first sub-layer located in the bonding region; Forming a second insulating film on the base substrate having the flat layer body and the first sub-layer, and patterning the second insulating film to form a pixel defining pattern in the display region a second sub-layer located in the bonding region; forming a third insulating film on the base substrate on which the pixel defining pattern and the second sub-layer are formed, and forming the third insulating film A patterning process is performed to form a spacer pattern in the display area, a third sub-layer located in the binding area.
  • the preparation method further includes forming an organic fill pattern in a region between the display region of the base substrate and the binding region before forming the flat layer body
  • Forming the insulating support portion further includes: forming a fourth sub-layer on a side of the first sub-layer adjacent to the substrate substrate; wherein the fourth sub-layer is formed in the same layer as the organic filling pattern .
  • the forming an insulating support portion at a position where the bonding pad is not disposed in a bonding region of the base substrate further includes: before forming the flat layer, Forming a fourth insulating film on the base substrate; patterning the fourth insulating film to form an organic filling pattern in a region between the display region and the binding region, at the The fourth sublayer in the bound area.
  • the multilayer structure formed includes at least two sub-layers; wherein an orthographic projection of all of the sub-layers on the substrate substrate at least partially overlaps to form a stacked structure.
  • the multilayer structure formed includes at least two sub-layers; wherein all of the sub-layers are identical in shape.
  • the preparation method further includes: forming at least one insulating layer in a package region of the base substrate; the in the binding region of the base substrate, and not Forming the insulating support portion at a position where the binding pad is disposed includes: at least a portion of the insulating support portion being formed in the same layer as at least one of the insulating layers in the package region.
  • the at least one insulating layer includes an organic protective film layer; forming the insulating support portion includes: forming a fifth sub-layer; wherein the fifth sub-layer and the organic protective film layer The same layer is formed.
  • the forming an insulating support portion at a position where the binding pad is not provided in a bonding region of the base substrate includes: by an inkjet printing method, in the An organic protective film layer located in the package region of the base substrate, and a fifth sub-layer located in the bonding region are formed on the base substrate.
  • the base substrate is a flexible substrate.
  • a further aspect of the present disclosure provides a method of fabricating a display device, comprising: forming the array substrate on a rigid support substrate by using the preparation method according to any one of the preceding claims; wherein the substrate in the array substrate The substrate is a flexible substrate; the array substrate is peeled off from the rigid support substrate; and a protective back film is attached on a side of the flexible substrate that is away from the binding pad and the insulating support; An IC is provided, the IC including a binding pin of the IC; and a binding pin of the IC is bound to the binding pad.
  • an array substrate including: a substrate substrate; a plurality of binding pads located in a binding region of the substrate substrate, wherein the binding region is an overlay when the IC is bound
  • An insulating support portion located at a position in the binding region where the bonding pad is not disposed, the insulating support portion for maintaining a gap between the array substrate and an IC to be bonded.
  • a height of the insulating support portion facing away from an upper surface of the substrate substrate to a surface of the substrate substrate is greater than a side of the binding pad facing away from the substrate substrate The height of the surface to the surface of the substrate substrate.
  • the binding pad is used to bond a binding pin of the IC; a height of the upper surface of the insulating support to the surface of the substrate substrate, and the binding The difference between the height of the upper surface of the pad to the surface of the substrate substrate is less than or equal to the thickness of the bonding pin of the IC to be bonded.
  • the plurality of bonding pads include spaced input input pads and output binding pads; wherein the insulating support is located at the input binding pad and Output between bond pads.
  • the binding pad includes spaced input input pads and output binding pads; wherein the insulating support is disposed at the input binding pad away from the output One side of the bond pad, and/or the insulating support is disposed on a side of the output bond pad that faces away from the input bond pad.
  • the binding pad includes a first set of bonding pads and a second set of bonding pads that are spaced apart, the first set of bonding pads including at least one input bonding a second binding pad group including at least one output binding pad; wherein the insulating support portions are at least one group, and the same group of the insulating support portions are located in the first binding pad group The same side, and located on the same side of the second binding pad group, the distance between each of the insulating support portions of each group of the insulating support portions and the boundary of the second binding pad group All are equal.
  • the first binding pad group includes a plurality of the input binding pads spaced apart by at least one row
  • the second binding pad group includes a plurality of at least one row interval setting The output binding pad
  • each set of the insulating support portion includes a plurality of the insulating support portions disposed at least in a row; wherein at least one of the input binding pads spaced apart from at least one row is spaced apart from at least one row
  • a plurality of the output binding pads, at least one row of the plurality of the insulating support portions spaced apart from each other are parallel to each other.
  • each set of the insulating support portion includes a plurality of spaced apart insulating support posts; or each set of the insulating support portions includes an insulating support strip.
  • a distance between the insulating support and the binding pad is greater than or equal to 50 [mu]m.
  • an area of the upper surface of the insulating support portion facing away from the substrate substrate is smaller than an area of a lower surface of the insulating support portion toward a side of the substrate substrate.
  • the array substrate further includes: at least one insulating layer disposed in a display region of the base substrate; at least a portion of the insulating support portion and at least one of the display regions The insulating layer is formed in the same layer.
  • the insulating support comprises a multilayer structure.
  • the at least one insulating layer disposed in the display region of the base substrate includes: a flat layer body, a pixel defining pattern, and a spacer pattern disposed in turn away from the substrate substrate;
  • the multilayer structure includes: a first sub-layer, a second sub-layer, and a third sub-layer that are sequentially away from the base substrate; wherein the first sub-layer is formed in the same layer as the flat layer main body; The second sub-layer is formed in the same layer as the pixel defining pattern; the third sub-layer is formed in the same layer as the spacer pattern.
  • the array substrate further includes: an organic filling disposed in a region of the flat layer body adjacent to the substrate substrate and located between the display region and the binding region a pattern; the multilayer structure further includes: a fourth sub-layer located on a side of the first sub-layer adjacent to the substrate substrate; wherein the fourth sub-layer is formed in the same layer as the organic filling pattern.
  • the array substrate further includes: an organic protective film layer disposed in a package region of the base substrate; the insulating support portion includes a fifth sub-layer; wherein the fifth sub- The layer is formed in the same layer as the organic protective film layer.
  • the base substrate is a flexible substrate.
  • a further aspect of the present disclosure provides a display device, comprising: the array substrate according to any one of the above; an IC; wherein the IC includes a binding pin of an IC; The foot is bound to the binding pad.
  • FIG. 1 is a schematic structural diagram of a flexible display device for binding an IC by using a COP in an exemplary embodiment of the present disclosure
  • 2A is a schematic diagram of various defects occurring when an IC is directly bonded to a flexible display device in the related art
  • 2B is a specific schematic diagram of a defect that occurs when an IC is directly bonded to a flexible display panel in the related art
  • FIG. 3 is a schematic structural diagram of a binding area of an array substrate according to some embodiments of the present disclosure
  • FIG. 4 is a schematic diagram of a process of binding an IC to the array substrate bonding area shown in FIG. 3;
  • FIG. 5 is a schematic diagram showing structural changes of an array substrate before and after IC crimping according to some embodiments of the present disclosure
  • Figure 6 is a cross-sectional structural view taken along line A-A' of Figure 3;
  • FIG. 7 is a schematic structural diagram of a binding area of another array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural view of the array substrate shown in FIG. 3 including two sets of insulating support portions between an input binding pad and an output binding pad;
  • FIG. 9 is a schematic structural view of an insulating support portion in the array substrate shown in FIG. 3;
  • FIG. 10 is a schematic structural diagram of an array substrate including an organic filling layer according to some embodiments of the present disclosure.
  • FIG. 11 is another schematic structural view of an insulating support portion in the array substrate shown in FIG. 3;
  • FIG. 12 is a schematic diagram of a process for forming an insulating support portion by using an inkjet printing method according to some embodiments of the present disclosure
  • FIG. 13 is a schematic structural diagram of a flexible display device according to some embodiments of the present disclosure.
  • FIG. 14 is a flowchart of a method for preparing an array substrate according to some embodiments of the present disclosure.
  • FIG. 15 is a flow chart of another method for fabricating an array substrate according to some embodiments of the present disclosure.
  • the IC binding in the preparation process of the related display device (for example, a flexible display device), the IC binding generally adopts a COF (English name: Chip On Film, Chinese name: flip chip), that is, The COF is used to bind the IC to the array substrate of the display panel (for example, a flexible display panel); since the COF is a soft material, the line on the array substrate is not broken when crimped. However, since the COF cost is high and the lines on the COF cannot be prepared very finely, the COF bonding method is difficult to apply to a high-resolution display device.
  • COF International name: Chip On Film, Chinese name: flip chip
  • the binding mode of the COP is: directly binding the IC on the binding area A of the display panel 01 (such as the flexible display panel) (labeled as “IC” in FIG. 1 ), and then attaching the FPC.
  • IC flexible Printed Circuit
  • FPC flexible printed circuit board
  • the flexible display panel corresponds to the IC bump (IC binding pin, figure)
  • the back film 21 at the position of 2A which is labeled "IC bump”
  • IC bump is depressed, which in turn causes the flexible substrate 20 of the region to sink, thereby causing a step difference between the depressed region on the flexible substrate 20 and the other regions.
  • the line around the depressed substrate on the flexible substrate 20 is liable to be broken, for example, as shown in the gap 2 (GAP 2) and the gap 4 (GAP 4) in FIG. 2A, on the flexible substrate. 20 There is a line break in the step difference.
  • FIG. 2B is a schematic view showing the process of sinking the back film 21 caused by IC crimping.
  • the pressure sensitive adhesive 30 since the back film 21 and the flexible substrate 20 are usually bonded by the pressure sensitive adhesive 30, when the IC is crimped at On the flexible substrate 20, the pressure sensitive adhesive 30 under the IC's binding pin (IC bump, labeled "IC bump” in Fig. 2B) is pressed and pressed into the area without the IC bump, thereby This causes the flexible substrate 20 to undergo a large degree of bending.
  • the extrusion direction is as indicated by the arrow in Fig. 2B.
  • the IC bump is connected to the binding pad on the flexible display panel to transmit the signal on the IC to the line on the flexible display panel.
  • the portion of the IC other than the IC bump contacts the line on the flexible substrate 20, a short circuit is caused.
  • the preset spacing between the flexible substrate 20 and the IC as 10 ⁇ m as an example, when the IC is crimped on the flexible display panel by, for example, hot pressing, the pressure in the back film corresponding to the IC bump in the flexible display panel The gel will flow around the depressed position on the flexible substrate 20, as shown by gap 1 (GAP 1), gap 3 (GAP 3), gap 4 (GAP 4) in FIG. 2A, so as to correspond to the position around the IC bump position.
  • the flexible substrate 20 is warped, resulting in a decrease in the pitch between the flexible substrate 20 and a portion of the IC other than the IC bump, for example, sequentially decreasing to 8.4 ⁇ m, 3.2 ⁇ m, and 8.9 ⁇ m.
  • FIGS. 3 and 4 illustrate the structure of the array substrate 100 within the bonding area A.
  • the array substrate 100 includes a base substrate 11; a plurality of bonding pads 10 disposed in a bonding area A of the substrate substrate 11, wherein the bonding pads 10 are used to bond ICs as shown in FIG. Binding pin 42, the binding area is the coverage area when the IC is bound.
  • the array substrate 100 further includes: an insulating support portion 12 located at a position where the bonding pad 10 is not disposed in the bonding area A, and the insulating support portion 12 is for maintaining between the array substrate and the IC to be bound gap.
  • the above substrate substrate 11 may be a flexible substrate substrate or a rigid substrate substrate.
  • the flexible substrate may be a flexible substrate such as a plastic substrate.
  • the array substrate formed using the flexible substrate can be bent or folded, and the use function of the display device including the array substrate can be expanded.
  • the rigid substrate can be, for example, a glass substrate.
  • the binding region A of the base substrate 11 in the array substrate 100 refers to a region on the array substrate on which the IC is pre-bonded, that is, a region covered by the bonded IC on the substrate substrate 11 as the binding region A. .
  • the area of the area covered by the IC bound to the base substrate 11 of the array substrate 100, that is, the area of the bonding area A is larger than the outermost contour line area of the plurality of bonding pads 10 as shown in FIG. Area.
  • the structure of the IC is generally as shown in FIG. 4, and includes the IC body 41 and the binding pin 42 of the IC.
  • the positional relationship and the number of the binding pins 42 of the IC body 41 and the IC illustrated in FIG. 4 are merely illustrative and are not intended to limit the specific structure of the IC.
  • one or more ICs may be bound to one array substrate 100.
  • the area in which each IC is overlaid on the array substrate 100 may be set to expose the above-described structure provided by some embodiments.
  • the "insulation" of the insulating support portion 12 means that the original electrical connection relationship between the IC and the corresponding structure in the array substrate is not damaged. Therefore, at least the surface of the insulating support portion 12 is insulated, that is, all materials constituting the insulating support portion 12 may be insulating materials, or the surface layer of the insulating support portion 12 may be made of an insulating material and the inside thereof may be non-insulated.
  • An insulating material for example, a semiconductor material, a metal material, or the like to function to shape the surface layer of the insulating support portion 12).
  • the insulating support portion 12 can be separately prepared, that is, the step of preparing the insulating support portion 12 is added on the basis of the preparation step of the associated array substrate; or the insulating support portion 12 can be located outside the binding region A of the substrate substrate with the array substrate.
  • One or more layers in the structure are simultaneously prepared, so that by changing the pattern of one or more layers in the relevant array substrate, the above-mentioned insulating support portion 12 can be formed in the bonding region of the substrate substrate without increasing the array.
  • the preparation step of the substrate is, that is, the step of preparing the insulating support portion 12 is added on the basis of the preparation step of the associated array substrate; or the insulating support portion 12 can be located outside the binding region A of the substrate substrate with the array substrate.
  • One or more layers in the structure are simultaneously prepared, so that by changing the pattern of one or more layers in the relevant array substrate, the above-mentioned insulating support portion 12 can be formed in the bonding region of the substrate substrate without increasing the array.
  • the binding pin 42 of the IC is bonded to the bonding pad.
  • the pressure sensitive adhesive on the back film corresponding to the position of the binding pin 42 of the IC may flow to the periphery such that the substrate substrate 11 is at a position corresponding to the binding pin 42 of the IC.
  • a sag occurs, and a tilt occurs around the position of the binding pin 42 of the IC.
  • the above-described array substrate 100 provided by some embodiments of the present disclosure further includes an insulating support portion 12 located at a position in the bonding area A of the base substrate 11 and where the bonding pad 10 is not disposed, as shown in FIG.
  • the insulating support portion 12 can function to suppress bending at a position where the binding pad 10 is not provided in the binding region A, so that the pressed portion of the pressure sensitive adhesive 30 is dispersed (as indicated by an arrow in FIG. 5). It is possible to avoid the degree of bending of the entire array substrate due to the concentrated pressing of the pressure sensitive adhesive 30, thereby maintaining the gap between the IC and the array substrate.
  • the insulating support portion 12 exhibits insulation, it is also possible to prevent the line on the raised portion of the base substrate 11 from directly contacting the line on the IC, thereby reducing the short circuit between the line on the array substrate 100 and the line on the IC.
  • the risk of the above-described insulating support 12 can also reduce the probability of the accumulation of conductive particles in the ACF glue occurring at the position corresponding to the binding pin 42 of the IC, thereby reducing the risk of short-circuiting due to the accumulation of conductive particles in the ACF glue.
  • the height of the surface of the insulating support portion 12 facing away from the upper surface 12a of the substrate 11 to the surface of the substrate substrate 11 is greater than the side of the bonding pad 10 facing away from the substrate 11.
  • the following embodiments are merely illustrated by taking the substrate substrate 11 as a flexible substrate substrate 11 as an example.
  • the upper surface 12a of the insulating support portion 12 facing away from the flexible substrate substrate 11 protrudes from the surface of the upper surface 10a of the binding pad 10 facing away from the flexible substrate substrate 11.
  • the relative positions of "upper” and “lower” in some embodiments of the present disclosure may refer to FIG. 4, with the surface of the insulating support portion 12 facing away from the side of the flexible substrate substrate 11 as its upper surface 12a for bonding welding
  • the surface of the disk 10 facing away from the side of the flexible substrate substrate 11 serves as its upper surface 10a.
  • the insulating support portion 12 protrudes from the face on which the upper surface 10a of the bonding pad 10 is located, that is, a portion of the insulating support portion 12 protrudes from the binding pad 10. In this way, when the IC is bonded to the array substrate 100, the insulating support portion 12 protruding from the bonding pad 10 can serve as a support between the IC body 41 and the flexible substrate substrate 11.
  • Some embodiments of the present disclosure do not define the positional relationship of the lower surface of the insulating support portion 12 and the lower surface of the binding pad 10 as long as the upper surface 12a of the insulating support portion 12 protrudes from the upper surface 10a of the bonding pad 10.
  • the face is fine.
  • the lower surface of the insulating support portion 12 and the lower surface of the bonding pad 10 may be In the same plane.
  • the lower surface of the insulating support portion 12 and the bonding pad 10 are simultaneously prepared.
  • the lower surface can be in different planes.
  • the above-described insulating support portion 12 is provided in the flexible base substrate 11 of the above array substrate 100, it should be premised on not affecting the binding between the IC and the above-described binding pad.
  • the height of the insulating support portion 12 can be adjusted according to the model of the IC in the vertical direction of the board surface of the flexible substrate substrate 11.
  • the lower surface of the binding pin 42 of the IC i.e., the surface facing the side of the IC body 41
  • the upper surface of the IC body 41 i.e., the surface toward the side of the binding pad 10.
  • the upper surface 12a of the insulating support portion 12 protrudes from the surface height H of the upper surface 10a of the bonding pad 10 to be less than or equal to the thickness h of the bonding pin 42 of the IC. In this way, when the binding pin 42 of the IC is bound to the binding pad 10 described above, it can be ensured that the intermediate portion of the IC body 41 is not lifted up by the insulating support portion 12, thereby preventing the IC from being affected. Binding effect.
  • the height of the insulating support portion 12 can be set as high as possible within a total height range beyond the crimp pin, thereby providing a more stable support for the IC.
  • the height H of the upper surface 12a of the insulating support portion 12 protruding from the face of the upper surface 10a of the bonding pad 10 is equal to the thickness h of the bonding pin 42 of the IC, that is, when the IC is bonded to the array substrate.
  • the upper surface 12a of the insulating support portion 12 can be in contact with the IC body 41 to provide the IC with as strong a supporting force as possible.
  • the planar size of each of the insulating support portions may be set large to provide sufficient supporting force for the IC; when the pitch between the insulating support portions is small, that is, the insulating support When the portions are disposed closer to each other, the planar size of each of the insulating support portions can be set small.
  • the above arrangement is merely an example.
  • the present disclosure does not limit the planar size of the insulating support portion.
  • the planar size of the insulating support portion can be flexibly adjusted according to the area of the binding region A, the number of insulating support portions, and the arrangement of the insulating support portions.
  • the bonding pin 42 of the IC and the bonding pad 10 are crimped.
  • the pressure sensitive adhesive in the back film at the position corresponding to the binding pin 42 of the IC in the flexible display panel may flow to the surroundings such that the flexible substrate substrate 11 is at a position corresponding to the binding pin 42 of the IC. The sag occurs, and the flexible substrate substrate 11 is tilted around the position of the binding pin 42 of the IC.
  • the upper surface 12a of the insulating support portion 12 protrudes from the surface on which the upper surface 10a of the bonding pad 10 is located, so that the insulating support portion 12 can play a certain supporting role. So that the flexible substrate substrate 11 maintains a fixed interval around the position of the binding pin 42 of the IC and the IC, thereby maintaining a gap between the IC and the array substrate, thus preventing the flexible substrate The line on the raised portion of the 11 contacts the line on the IC, thereby reducing the risk of shorting the line on the array substrate to the line on the IC.
  • the insulating support portion 12 can make the flexible substrate substrate maintain a fixed pitch around the binding pin position of the IC and the IC, the flexible lining at the position corresponding to the binding pin 42 of the IC can be lowered.
  • the probability reduces the probability of clustering of conductive particles in the ACF glue at the position corresponding to the binding pin 42 of the IC, thereby reducing the risk of shorting due to the accumulation of conductive particles.
  • the particle size of a single conductive particle in the ACF glue is usually about 5 ⁇ m.
  • the conductive particles are concentrated more, for example, about 10 conductive particles are gathered together to form the flexible substrate of the bonding pad 10 and the adjacent region. A short circuit occurs between the lines on 10.
  • the distance L between the insulating support portion 12 and the above-described binding pad 10 is less than 50 ⁇ m (that is, the sum of the particle diameters of about 10 conductive particles), the insulating support portion 12 is gathered and tied as described above. Conducting particles between the pads 10 may increase the risk of shorting the lines on the array substrate to the lines on the IC. Therefore, considering the property of the ACF glue, the distance L between the insulating support portion 12 and the binding pad 10 is greater than or equal to 50 ⁇ m.
  • the “distance L” means the distance between the insulating support portion 12 on the side of the bonding pad 10 and the bonding pad 10 near the insulating support portion 12 in the plane of the flexible base substrate 11.
  • the area of the upper surface 12a of the insulating support portion 12 facing away from the flexible substrate substrate 11 is smaller than the lower surface 12b of the side of the insulating support portion 12 toward the flexible substrate substrate 11. Area.
  • the cross section of the insulating support portion 12 is a trapezoidal shape that is large and small.
  • the lower portion of the insulating support portion 12 can provide a more stable support for the upper portion thereof because the insulating support portion 12 itself has a structure that is small and large. The role is to provide a more stable support for the IC.
  • the binding pin 42 of the IC typically includes an input binding pin (Input bump) and an output binding pin (Output bump).
  • the Input bump is used to input an external power supply into the IC
  • the Output bump is used to input an IC signal to the array substrate bound to the IC.
  • the above-mentioned binding pad 10 generally includes: an input binding pad 101 and an output binding pad 102 which are disposed at intervals.
  • the input binding pad 101 corresponds to the Input bump
  • the output binding pin 102 corresponds to the Output bump.
  • the number and arrangement shape of the bonding pads 10 are merely illustrative, and are not intended to limit the number and arrangement shape of the bonding pads 10.
  • the arrangement shape and number of the binding pins 42 of the IC are changed, the arrangement shape and number of the bonding pads 10 also change when the array substrate is prepared.
  • the bonding pad 10 includes a first bonding pad group a1 and a second bonding pad group a2 which are spaced apart, the first binding
  • the fixed pad group a1 includes at least one input binding pad 101
  • the second binding pad group a2 includes at least one output binding pad 102
  • the insulating support portion 12 is divided into at least one group, and the same set of insulating support portions 12 are located
  • the first side of the first bonding pad group a1 is located on the same side of the second bonding pad group a2.
  • the distance between each of the insulating support portions in each of the sets of insulating support portions 12 and the boundary of the second binding pad group a2 is equal.
  • each of the insulating support portions and the first binding pad group a1 in each group of the insulating support portions 12 The distance between the boundaries is also equal everywhere.
  • the same group of insulating support portions 12 are located on the same side of the first bonding pad group a1 and on the same side of the second bonding pad group a2, the same group of insulating support portions 12 and the first There are three example setting positions between the bonding pad group a1 and the second bonding pad group a2:
  • the same set of insulating support portions 12 are disposed between the first bonding pad group a1 and the second bonding pad group a2.
  • the same set of insulating support portions 12' are disposed on the side of the first binding pad group a1 facing away from the second bonding pad group a2.
  • the same set of insulating support portions 12" are disposed on a side of the second binding pad group a2 facing away from the first binding pad group a1.
  • the distance L1 between only one set of the insulating support portion 12' and the boundary of the first binding pad group a1 is equal to the other set of the insulating support portion 12 and the first binding pad group.
  • the distance L2 between the boundaries of a1 is illustrated as an example, and L1 and L2 may or may not be equal.
  • the insulating support portions 12 are located on the same side of the first binding pad group a1 and on the same side of the second binding pad group a2
  • the insulating support portions 12' are the same group.
  • the insulating support portions 12 are the same group.
  • the first binding pad group a1 includes a plurality of input binding pads 101 that are spaced apart at least one row
  • the second binding pad group a2 includes at least a plurality of output binding pads 102 arranged at intervals in a row, each set of insulating support portions including at least one row of spaced apart insulating support portions 12; wherein at least one row of spaced apart input bond pads 101 are spaced apart from at least one row
  • the plurality of output binding pads 102 are disposed, and the plurality of insulating support portions 12 disposed at least in a row are parallel to each other, so that the row terminal structures in the binding region are arranged more neatly, facilitating binding and pairing of the ICs.
  • the IC supports it.
  • each set of insulating supports 12 may include a plurality of spaced apart insulating support posts as shown in FIG. 3 or FIG. 7; or each set of insulating supports 12 includes an insulating support strip.
  • the insulating support portion 12 includes a plurality of spaced apart insulating support pillars, some embodiments of the present disclosure do not limit the shape and number of the insulating support pillars, and the insulating support portion 12 may be on the flexible base substrate 11 as long as the IC is bonded. It can be used to support the IC body 41.
  • the shape of the upper surface of the insulating support post may be circular or rectangular.
  • only the shape of the upper surface of the insulating support post is rectangular as an example.
  • the planar size of the insulating support pillar when the planar size of the insulating support pillar is less than 50 ⁇ m, the support effect of the single insulating support pillar is poor, and it is difficult to maintain a fixed spacing between the flexible base substrate 11 and the IC body 41 when the IC is bonded. .
  • the planar size of the insulating support pillar is larger than 200 ⁇ m, since the area of the bonded region A is small, it is difficult to form an insulating support column having the above-described 200 ⁇ m planar size between the input bonding pad 101 and the output bonding pad 102. Therefore, the planar size of the insulating support column is 50 ⁇ m to 200 ⁇ m. The number of insulating support columns can be adjusted according to the size of the IC.
  • the above-mentioned planar size means the length or width of the rectangle.
  • the above-mentioned planar size means the diameter of the circular shape.
  • the insulating support 12 is disposed between the input bond pad 101 and the output bond pad 102.
  • the flexible base substrate 11 at the position of the binding pin 42 corresponding to the IC is depressed due to the pressure of the crimping, so that the flexible substrate substrate 11 corresponds to the binding reference.
  • a tilt occurs at a position around the foot 42.
  • a fixed pitch can be maintained between the flexible base substrate 11 and the intermediate portion of the IC body 41, thereby reducing the flexible lining.
  • the probability that the line on the base substrate 11 is in contact with the line on the IC body 41 further reduces the risk of short circuit.
  • the array substrate 100 includes at least two sets of insulating support portions 12 between the input bond pads 101 and the output bond pads 102, each set including a plurality of spaced apart insulating supports.
  • the portion 12 is for improving the overall supporting effect of the insulating support portion 12.
  • the insulating support 12 is disposed on a side of the input bond pad 101 that faces away from the output bond pad 102 or on a side of the output bond pad 102 that faces away from the input bond pad 101. .
  • the flexible base substrate 11 at the position corresponding to the binding pin 42 of the IC is depressed by the pressure of the crimping, so that the peripheral flexible substrate 11 corresponds to the binding
  • the tilting occurs at a position around the fixed pin 42.
  • a fixed pitch can be maintained between the flexible base substrate 11 and the edge portion of the IC body 41, thereby reducing the flexible lining.
  • the insulating support portion 12 is disposed on the first binding pad group a1 and the plurality of output binding pads 102 formed by the plurality of input binding pads 101. Between the second binding pad group a2, the first binding pad group a1 formed by the plurality of input binding pads 101 faces away from the second binding pad group a2 formed by the plurality of output binding pads 102 The side, and the second binding pad group a2 formed by the plurality of output binding pads 102 face away from the side of the first binding pad group a1 formed by the plurality of input bonding pads 101.
  • the insulating support portion 12 can maintain a fixed pitch between the portion of the IC body 41 that does not correspond to the binding pin 42 of the IC and the flexible substrate substrate 11 of the tilted portion, thereby enabling The probability of the line on the warped portion of the flexible substrate substrate 11 being in contact with the line on the IC body 41 is lowered, further reducing the risk of short circuit.
  • the insulating support portion 12 may be formed simultaneously with the relevant film layer outside the bonding region A of the flexible substrate substrate 11 in the array substrate 100 to avoid an increase in preparation insulation. The step of the support portion 12.
  • the array substrate further includes: at least one insulating layer disposed in the display region of the flexible substrate; at least a portion of the insulating support portion may be formed in the same layer as the at least one insulating layer in the display region to simplify preparation Process.
  • “same layer fabrication” as used in some embodiments of the present disclosure means that the same film layer (which may be a film or a multilayer film) made of the same material is patterned (or referred to as composition). a process to simultaneously form different patterns, that is, "at least a portion of the above-mentioned insulating support portion” and “at least one insulating layer in the display region” as referred to in the above embodiments of the present disclosure; wherein "the same layer” means The different patterns are obtained by patterning the same film layer, so that the above array substrate provided by some embodiments of the present disclosure is in the process of preparation, compared with different patterning processes for different patterns. By adjusting the pattern of the mask used in the patterning process, different patterns can be formed in one patterning process, simplifying the preparation process of the array substrate.
  • the different patterns obtained by patterning the same film layer may be located on the same substrate surface, or different patterns may be located on different substrate surfaces, which may be flexibly adjusted according to the corresponding design requirements of the array substrate. Some embodiments of the present disclosure do not limit this.
  • the above insulating support portion includes a multilayer structure.
  • the multilayer structure includes at least two sub-layers; the orthographic projections of all of the sub-layers on the substrate substrate at least partially overlap to form a stacked structure.
  • the shape of all the sub-layers can also be the same to simplify the patterning process in the production of each sub-layer.
  • the at least one insulating layer disposed in the display region of the base substrate may include a flat layer body, a pixel defining pattern, and a spacer pattern disposed in turn away from the substrate substrate.
  • the flat layer body and the pixel defining pattern are an organic film layer
  • the spacer pattern may be an organic film layer or an inorganic film layer
  • the organic film layer may be a light sensing material such as light.
  • the glue is formed.
  • the multilayer structure of the insulating support portion 12 includes a first sub-layer (or referred to as a first pattern) 121' and a second sub-layer sequentially away from the substrate substrate 11. (or referred to as a second pattern) 122' and a third sub-layer (or referred to as a third pattern) 123'; wherein the first sub-layer 121' is formed in the same layer as the flat layer body in the display area, the second sub- The layer 122' is formed in the same layer as the pixel defining pattern in the display area, and the third sub-layer 123' is formed in the same layer as the spacer pattern in the display area.
  • the first sub-layer 121' and the flat layer main body constitute a flat layer (English name: Planarazition, abbreviated as: PLN layer), and the first sub-layer 121' is a pattern 121' in which the flat layer is located in the binding area A.
  • PLN layer Planarazition
  • the second sub-layer 122 ′ and the pixel defining pattern form a pixel defining layer (Pixel definition layer, English abbreviation: PDL layer), and the second sub-layer 122 ′ is a pattern 122 ′ where the pixel defining layer is located in the binding area A and
  • the spacer layer (English full name: Photospacer, English abbreviation: PS layer) is located in the pattern 123' of the binding area A.
  • the third sub-layer 123' and the spacer pattern constitute a spacer layer, and the third sub-layer 123' is a pattern 123' in which the spacer layer is located in the binding region A.
  • each of the insulating support portions 12 is located in a pattern 121' of the bonding area A by a flat layer disposed in a stacked manner, a pattern 122' in which the pixel defining layer is located in the binding area A, and a pattern 123 in which the spacer layer is located in the binding area A. 'Constituent.
  • the flat layer when the flat layer, the pixel defining layer, and the spacer layer are mainly composed of an organic material, the flat layer may be sequentially formed by a patterning process including steps of coating, exposure, development, etching, and the like.
  • the pattern 121' of the region A, the pixel defining layer is located at the pattern 122' of the binding region A, and the spacer layer and the pattern 123' of the spacer layer at the binding region A.
  • the spacer layer and the pattern of the spacer layer in the bonding area A can be formed by a step including coating, exposing, and developing without performing an etching process. 123' to simplify the preparation process of the above-described insulating support portion 12.
  • the planar size of the single insulating support pillar may be, for example, 50 ⁇ m to 100 ⁇ m when the insulating support pillar is formed by the above-described patterning process.
  • the above-mentioned plane size refers to the length or width of the rectangle; when the shape of the upper surface of the insulating support column is a circle, the above-mentioned plane size means the circle diameter.
  • the support portion 12 has a three-layer structure as shown in FIG.
  • the insulating support portion 12 of the three-layer structure may have an overall thickness of 4 ⁇ m to 8 ⁇ m.
  • the line in the flexible display device is susceptible to breakage at the folded position.
  • the array substrate further includes an organic filling pattern 124 on the flexible substrate substrate 11 corresponding to the folded position, which is generally located between the display area and the binding area A.
  • the organic filling pattern 124 may be a filling layer mainly composed of a PI material.
  • the organic filling pattern 124 may also be referred to as a PI filling layer (Polyimide Filling, English abbreviation: PI filling).
  • the organic fill pattern 124 is disposed between the flat layer 121 and the flexible substrate substrate 11, and the organic fill pattern 124 is disposed between the source/drain metal layer 16 and the flexible substrate substrate 11.
  • the array substrate 100 further includes a buffer barrier layer 13 and a gate insulating layer (Gate Insulator, English abbreviation: GI) 14 and an interlayer insulating layer which are sequentially disposed on the flexible substrate substrate 11. (English full name: Interlayer Dieletric, English abbreviation: ILD) 15, wherein the buffer barrier 13 can block water vapor.
  • a buffer barrier layer 13 and a gate insulating layer (Gate Insulator, English abbreviation: GI) 14 and an interlayer insulating layer which are sequentially disposed on the flexible substrate substrate 11.
  • ILD International full name: Interlayer Dieletric, English abbreviation: ILD
  • the insulating support portion 12 may further include a fourth sub-layer (or referred to as a fourth pattern) 124' located on a side of the first sub-layer 121' adjacent to the substrate substrate 11;
  • the fourth sub-layer 124' is formed in the same layer as the organic filling pattern at the folded position.
  • the fourth sub-layer 124' and the organic filling pattern constitute an organic filling layer
  • the fourth sub-layer 124' is a pattern 124' in which the organic filling layer is located in the binding region A.
  • the insulating support portion 12 has a four-layer structure, that is, the insulating support portion 12 includes: the organic filling layer 124 sequentially disposed on the flexible substrate substrate 11 is located in the pattern 124' of the binding region A, and the flat layer is located The pattern 121' of the fixed area A, the pattern 122' of the pixel defining layer is located at the binding area A, and the pattern 123' of the spacer layer A is located in the binding area A.
  • the insulating support portion 12 of the four-layer structure may have an overall thickness of 6 ⁇ m to 10 ⁇ m.
  • the array substrate 100 when the flexible display device composed of the array substrate 100 is a thin film package (English name: Thin Film Encapsulation, TFE), the array substrate 100 further includes a flexible lining. a thin film encapsulation layer on the base substrate 11 that blocks moisture from entering the organic luminescent material layer in the flexible display device to prevent the organic luminescent material layer from failing.
  • TFE Thin Film Encapsulation
  • the thin film encapsulation layer generally comprises two inorganic film layers and an organic film layer between the two inorganic film layers, and the organic film layer can be formed by inkjet printing.
  • the insulating support portion may include a fifth sub-layer (or a fifth pattern); wherein the fifth sub-layer may be the same as the organic protective film layer in the package region of the organic film layer in the thin film encapsulation layer The layer is formed.
  • the insulating support portion 12 includes a pattern in which the organic film layer is located in the bonding region A.
  • the insulating support portion 12 can be formed by inkjet printing. At this time, the insulating support portion 12 is formed in the same layer as the organic protective film layer in the package region.
  • the insulating support portion can be printed in the binding region A of the flexible substrate 11 by controlling the position of the printing head 17 and the printing time while forming the organic protective film layer by inkjet printing. 12.
  • the density of the insulating support portion 12 to be formed may be adjusted in accordance with the size of the insulating support portion 12. For example, when the material for printing the insulating support portion 12 has good fluidity, the planar size of the insulating support portion 12 formed by printing is large, and it is necessary to reduce the printing density of the insulating support portion 12 at this time; when used for printing When the material flowability of the insulating support portion 12 is poor, the planar size of the insulating support portion 12 formed by printing can be controlled to be small, and the printing density of the insulating support portion 12 can be increased at this time.
  • the insulating support portion 12 can be cured by ultraviolet light to enhance its stability.
  • the insulating support portion 12 includes a plurality of spaced apart insulating support columns, and the insulating support columns formed by inkjet printing have a planar size of 50 ⁇ m to 200 ⁇ m and a thickness of 5 ⁇ m to 10 ⁇ m.
  • the above-mentioned plane size refers to the length or width of the rectangle; when the shape of the upper surface of the insulating support column is a circle, the above-mentioned plane size means the circle diameter.
  • the insulating support portion 12 can be formed in the same layer as the organic protective film layer in the thin film encapsulation layer.
  • a further aspect of some embodiments of the present disclosure provides a display device (for example, a flexible display device) 200.
  • the flexible display device includes any of the array substrates 100 and ICs as described above (FIG. 13 Marked as "IC"); wherein the IC includes a binding pin of the IC; the binding pin of the IC is bonded to the array substrate 100 through the bonding pad of the array substrate.
  • the binding pin of the IC is referred to the foregoing FIG. 4, and details are not described herein again.
  • the flexible display device has the same structure and advantageous effects as the array substrate provided by the foregoing embodiments. Since the foregoing embodiments have already described the beneficial effects of the array substrate in detail, they are not described herein again.
  • the flexible display device may be an OLED (Organic Light-Emitting Diode) flexible display panel including the above array substrate, or may be an OLED display device including the above array substrate.
  • OLED Organic Light-Emitting Diode
  • Another aspect of some embodiments of the present disclosure provides a method for fabricating the above array substrate 100, as shown in FIG. 14, including steps 101-102:
  • S101 and S102 may be performed simultaneously; or S101 may be executed first and S102 may be executed first; or S102 may be executed first and S101 may be executed again.
  • the height of the surface of the insulating support portion 12 formed away from the upper surface 12a of the substrate substrate 11 to the surface of the substrate substrate 11 is larger than the formed bonding pad 10 facing away from the substrate.
  • the upper surface of the insulating support portion 12 facing away from the flexible substrate substrate 11 protrudes from the surface of the upper surface of the binding pad 10 facing away from the flexible substrate substrate 11, and the portion where the insulating support portion 12 protrudes may be an IC. Provide further support.
  • the height of the insulating support portion 12 should be as high as possible without affecting the normal binding between the IC and the above-described binding pads. This provides the IC with as strong a support as possible.
  • the height from the upper surface 12a of the insulating support portion 12 to the surface of the base substrate 11 in the vertical direction of the board surface of the base substrate 11, and the upper surface 10a of the bonding pad 10 to the base substrate 11 The difference between the heights of the surfaces is less than or equal to the thickness of the binding pins of the IC to be bonded.
  • the height of the insulating support portion 12 can be adjusted according to the model of the IC.
  • the lower surface of the binding pin 42 of the IC is in the same plane as the upper surface of the IC body 41, in order not to affect the relationship between the IC and the bonding pad.
  • the height H of the surface of the insulating support portion 12 protruding from the upper surface 10a of the bonding pad 10 is less than or equal to the thickness h of the binding pin 42 of the IC, so that the binding pin 42 of the IC is
  • the bonding pads 10 are bonded together, it is ensured that the intermediate portion of the IC body 41 is not lifted by the insulating support portion 12, and thus does not affect the binding effect of the IC.
  • the insulating support portion 12 may be separately prepared, that is, the step of preparing the insulating support portion 12 may be added on the basis of the preparation step of the related array substrate; or the flexible lining may be located in the array substrate.
  • One or more layers of the structure other than the bonding area A of the base substrate are simultaneously prepared, that is, the above-mentioned insulating support portion 12 can be prepared by changing the pattern of one or more layers of the structure in the relevant array substrate, thereby not increasing the array.
  • the preparation step of the substrate is performed by changing the pattern of one or more layers of the structure in the relevant array substrate, thereby not increasing the array.
  • the insulating support portion 12 may be formed in the same layer as the partial structure in the display region, that is,
  • the above preparation method further includes forming at least one insulating layer in a display region of the base substrate. At least a portion of the insulating support portion is formed in the same layer as at least one of the insulating layers in the display region.
  • “same layer fabrication” as used in some embodiments of the present disclosure means that the same film layer (which may be a film or a multilayer film) made of the same material is patterned (or referred to as composition). a process to simultaneously form different patterns, that is, "at least a portion of the above-mentioned insulating support portion” and “at least one insulating layer in the display region” as referred to in the above embodiments of the present disclosure; wherein "the same layer” means The different patterns are obtained by patterning the same film layer, so that the above array substrate provided by some embodiments of the present disclosure is in the process of preparation, compared with different patterning processes for different patterns. By adjusting the pattern of the mask used in the patterning process, different patterns can be formed in one patterning process, simplifying the preparation process of the array substrate.
  • the different patterns obtained by patterning the same film layer may be located on the same substrate surface, or different patterns may be located on different substrate surfaces, which may be flexibly adjusted according to the corresponding design requirements of the array substrate. Some embodiments of the present disclosure do not limit this.
  • insulating support portion As a multi-layer structure as an example, several exemplary preparation processes are provided below to describe in detail the fabrication process of the above-described insulating support portion:
  • the method of forming the insulating support portion 12 is as shown in FIG. 15, and includes steps 201-203:
  • the first sub-layer 121' and the flat layer main body constitute a flat layer, and the first sub-layer 121' is a pattern in which the flat layer 121 is located in the bonded region.
  • the patterning in some embodiments of the present disclosure refers to a patterning process, which may include a photolithography process, or other processes including photolithography processes and etching steps for forming a predetermined pattern.
  • Photolithography process including film formation, exposure, development and the like.
  • a lithography process in some embodiments of the present disclosure refers to a process of forming a pattern using a photoresist, a reticle, an exposure machine, or the like.
  • the apparatus and process for forming the first sub-layer are compatible with the apparatus for preparing the associated array substrate.
  • the first sub-layer may be formed in the bonding region A of the flexible substrate 11 by controlling the shape of the mask, exposing, developing, and etching the photoresist exposed to the photoresist.
  • the gate substrate, the gate insulating layer, the active layer, and the source/drain metal are usually formed on the flexible substrate substrate 11.
  • the process of forming the above-mentioned film layer by the layer and the like is the same as the related preparation process, and will not be described herein.
  • the second sub-layer 122' and the pixel defining pattern constitute a pixel defining layer, and the second sub-layer 122' is a pattern in which the pixel defining layer is located in the binding region.
  • the pixel defining pattern in the display area is generally meshed, thereby defining a sub-pixel area.
  • the third sub-layer and the spacer pattern form a spacer layer, and the third sub-layer is a pattern in which the spacer layer is located in the binding region.
  • the formed insulating support portion 12 includes the first sub-layer, the second sub-layer, and the third sub-layer described above.
  • the formed insulating support portion 12 has a three-layer structure.
  • the insulating support portion 12 can be formed simultaneously with the associated film layer in the array substrate, and thus need not be separately prepared, simplifying the process of forming the array substrate including the insulating support portion 12.
  • the array substrate further includes an organic filling layer 124 on the flexible substrate substrate 11 at a position corresponding to the folded position, and the organic filling layer 124 is further disposed on the source/drain metal layer 16. Between the flexible substrate substrate 11. Typically, the folded position is between the display area and the binding area A.
  • the above preparation method further includes:
  • a fourth insulating film is formed on the flexible substrate substrate 11, and the fourth insulating film is patterned to form an organic filling pattern between the display region and the bonding region A, and a bond on the flexible substrate substrate 11.
  • the fourth sub-layer and the organic filling pattern constitute an organic filling layer 124, and the fourth sub-layer is a pattern in which the organic filling layer 124 is located in the binding region.
  • the insulating support portion 12 further includes the above-described fourth sub-layer.
  • the pre-folding region may be first determined; then the shape of the mask plate is controlled according to the pre-folding region; when the fourth insulating film is patterned, Exposing the fourth insulating film by using the mask as described above, an organic filling pattern may be formed between the display region of the flexible substrate 11 and the bonding region A at a position corresponding to the folding position; and at the bonding region A forms the fourth sub-layer described above.
  • the formed insulating support portion 12 has a four-layer structure.
  • the four-layer structure of the insulating support portion 12 can appropriately increase the height of the insulating support portion 12 to further reduce the gap between the flexible substrate substrate 11 and the IC body 41 when IC bonding is performed.
  • the pitch is such that the surface of the flexible substrate substrate 11 after the IC bonding is flatter, thereby further reducing the risk of breakage of the wiring of the flexible substrate substrate 11 and accumulation of conductive particles on the flexible substrate substrate 11, while further avoiding the flexible liner
  • the circuit on the base substrate 11 is in contact with the IC body 41 to cause a risk of short circuit.
  • the method further includes: forming at least one insulating layer in a package region of the base substrate; at least a portion of the insulating support portion is formed in the same layer as at least one insulating layer in the package region form.
  • the at least one insulating layer may include an organic protective film layer; forming the insulating support portion includes: forming a fifth sub-layer; wherein the fifth sub-layer is formed in the same layer as the organic protective film layer.
  • the insulating support portion 12 includes the fifth sub-layer may be formed by inkjet printing, for example:
  • An organic protective film layer located on a package region of the flexible substrate substrate 11 and a fifth sub-layer located in the bonding region A of the flexible substrate substrate 11 are formed on the flexible substrate substrate 11 by an inkjet printing method;
  • the method of fabricating the array substrate further includes the steps of forming a desired layer structure on the flexible substrate substrate 11, such as forming a gate, a source, a drain, and a light-emitting layer, before forming the thin film encapsulation layer. Wait for the steps.
  • the steps of forming the above layer structure are the same as those of the related array substrate, and are not described herein again.
  • the thin film encapsulation layer generally comprises two inorganic film layers and an organic film layer between the two inorganic film layers, wherein the organic film layer can be formed by inkjet printing.
  • the fifth sub-layer and the organic protective film layer constitute an organic film layer, which is an organic film layer in the thin film encapsulation layer.
  • the insulating support portion 12 includes a fifth sub-layer.
  • the above-described insulation can be printed on the binding area A of the flexible substrate 11 by controlling the position and printing time of the print head 17 while forming the organic film layer by inkjet printing.
  • the support portion 12; the insulating support portion 12 may be cured by ultraviolet curing.
  • the binding pin 42 of the IC when the flexible display panel is constructed by using the above array substrate, and the binding pin 42 of the IC is bound to the binding pad 10, the binding pin corresponding to the IC in the flexible display panel during the crimping process
  • the pressure sensitive adhesive in the back film at the 42 position flows to the surroundings, so that the flexible substrate substrate 11 is sunk at a position corresponding to the binding pin 42 of the IC, and the flexible substrate substrate 11 corresponds to the binding of the IC.
  • a tilt occurs around the position of the foot 42. Since the array substrate further includes the insulating support portion 12 at the position where the binding pad 10 is not provided in the bonding region A of the flexible substrate substrate 11, the upper surface of the insulating support portion 12 protrudes above the bonding pad 10.
  • the surface on which the surface is located, so the insulating support portion 12 can play a certain supporting role so as to maintain a fixed spacing between the flexible substrate substrate 11 and the IC around the position of the binding pin 42 of the IC, thus It is possible to prevent the line on the warped portion of the flexible substrate substrate 11 from coming into contact with the line on the IC, thereby reducing the risk of occurrence of a short circuit.
  • the insulating support portion 12 can maintain a fixed pitch between the flexible substrate substrate and the IC around the binding pin position of the IC, the flexibility at the position corresponding to the binding pin 42 of the IC can be reduced.
  • the step difference between the base substrate 11 and the flexible substrate substrate 11 at the peripheral position is such that the surface of the flexible substrate substrate 11 is relatively flat after the IC bonding process is completed, thereby reducing the line breakage of the flexible substrate substrate 11 on the one hand.
  • the probability of occurrence of conduction of conductive particles at the position corresponding to the binding pin 42 of the IC is lowered, thereby reducing the risk of short-circuiting of the conductive particles.
  • a further aspect of some embodiments of the present disclosure provides a method for fabricating a display device.
  • the display device may be a flexible display device.
  • the method for preparing the flexible display device includes the following steps:
  • the method for preparing an array substrate is to form an array substrate on a rigid supporting substrate (such as a glass substrate); wherein the substrate in the array substrate is a flexible substrate; the rigid supporting substrate may be a flexible substrate
  • the substrate provides a relatively stable support to form a corresponding structure on the flexible substrate.
  • An IC is provided that includes an IC binding pin; the IC's binding pin is bound to the bonding pad.
  • the above-described preparation method may further include a process of cutting the peeled mother board before performing IC bonding.
  • the above flexible display device includes the method of fabricating any of the array substrates as described above, and has the same steps and advantageous effects as the method of preparing the array substrate provided by the foregoing embodiments.
  • the steps and beneficial effects of the method for fabricating the array substrate have been described in detail since the foregoing embodiments, and are not described herein again.

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Abstract

本公开实施例提供一种阵列基板及其制备方法、显示装置及其制备方法，该阵列基板的制备方法包括：在衬底基板的绑定区域中形成多个绑定焊盘，所述绑定区域为绑定IC时的覆盖区域；在所述柔性衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，所述绝缘支撑部用于维持所述阵列基板与待绑定的IC之间的间隙。

Description

阵列基板及其制备方法、显示装置及其制备方法
本申请要求于2017年10月13日提交中国专利局、申请号为201710954432.X、申请名称为“一种阵列基板及其制备方法、柔性显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及柔性显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置及其制备方法。
背景技术
随着显示技术的发展，柔性显示面板由于具有轻薄、良好的抗冲击性能等特性，被广泛应用于越来越多的电子设备中。利用柔性显示面板的显示装置包括液晶显示装置、有机电致发光显示装置和电泳显示装置等。例如，柔性显示装置可以应用于智能卡、便携式计算机以及电子纸等电子设备。在制作柔性显示装置时，一般是先将柔性基板设置在玻璃基板上，再在柔性基板上制作显示所需的各层结构，以形成柔性显示面板。这样的工艺能够与相关显示面板的制备设备相兼容。柔性显示面板制作完成后，需要将柔性基板与玻璃基板相分离，之后在柔性基板的背面(即没有制作显示所需的各层结构的一面)贴附背膜，以使柔性基板平整化，之后再进行切割，最后进行IC(英文全称：Integrated Circuit，中文名称：集成电路)的绑定(Bonding)等工艺。
公开内容
本公开实施例一方面提供一种阵列基板的制备方法，包括：在衬底基板的绑定区域中形成多个绑定焊盘，所述绑定区域为IC绑定时的覆盖区域；在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，所述绝缘支撑部用于维持所述阵列基板与待绑定的IC之间的间隙。
在本公开一些实施例中，形成的所述绝缘支撑部背离所述衬底基板一侧的上表面至所述衬底基板表面的高度大于形成的所述绑定焊盘背离所述衬底基板一侧的上表面至所述衬底基板表面的高度。
在本公开一些实施例中，所述绝缘支撑部的所述上表面至所述衬底基板表面的高度，与所述绑定焊盘的所述上表面至所述衬底基板表面的高度 之间的差值小于或等于待绑定的IC的绑定引脚的厚度。
在本公开一些实施例中，所述制备方法还包括：在所述衬底基板的显示区域中形成至少一层绝缘层；
所述在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：所述绝缘支撑部的至少一部分与所述显示区域中的至少一层所述绝缘层同层制作形成。
在本公开一些实施例中，形成的所述绝缘支撑部包括多层结构。
在本公开一些实施例中，所述在所述衬底基板的所述显示区域中形成至少一层绝缘层，包括：在所述衬底基板的所述显示区域中形成依次远离所述衬底基板的平坦层主体、像素界定图案和隔垫物图案；形成所述绝缘支撑部包括：依次形成远离所述衬底基板的第一子层、第二子层和第三子层；其中，所述第一子层与所述平坦层主体同层制作形成；所述第二子层与所述像素界定图案同层制作形成；所述第三子层与所述隔垫物图案同层制作形成。
在本公开一些实施例中，所述在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：在所述衬底基板上形成第一绝缘薄膜，并对所述第一绝缘薄膜进行构图处理，以形成位于所述衬底基板的显示区域中的平坦层主体、位于所述绑定区域中的第一子层；在形成有所述平坦层主体和所述第一子层的所述衬底基板上形成第二绝缘薄膜，并对所述第二绝缘薄膜进行构图处理，以形成位于所述显示区域中的像素界定图案、位于所述绑定区域中的第二子层；在形成有所述像素界定图案和所述第二子层的所述衬底基板上形成第三绝缘薄膜，并对所述第三绝缘薄膜进行构图处理，以形成位于所述显示区域中的隔垫物图案、位于所述绑定区域中的第三子层。
在本公开一些实施例中，所述制备方法还包括：在形成所述平坦层主体之前，在所述衬底基板的所述显示区域与所述绑定区域之间的区域中形成有机填充图案；形成所述绝缘支撑部还包括：形成位于所述第一子层靠近所述衬底基板一侧的第四子层；其中，所述第四子层与所述有机填充图案同层制作形成。
在本公开一些实施例中，所述在所述衬底基板的绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，还包括：在形成所述平坦层之前，在所述衬底基板上形成第四绝缘薄膜；对所述第四绝缘薄膜进行构图 处理，以形成位于所述显示区域与所述绑定区域之间的区域中的有机填充图案、位于所述绑定区域中的第四子层。
在本公开一些实施例中，形成的所述多层结构包括至少两层子层；其中，所有的所述子层在所述衬底基板上的正投影至少部分交叠，以形成堆叠结构。
在本公开一些实施例中，形成的所述多层结构包括至少两层子层；其中，所有的所述子层的形状均相同。
在本公开一些实施例中，所述制备方法还包括：在所述衬底基板的封装区域中形成至少一层绝缘层；所述在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：所述绝缘支撑部的至少一部分与所述封装区域中的至少一层所述绝缘层同层制作形成。
在本公开一些实施例中，所述至少一层绝缘层包括有机保护膜层；形成所述绝缘支撑部包括：形成第五子层；其中，所述第五子层与所述有机保护膜层同层制作形成。
在本公开一些实施例中，所述在所述衬底基板的绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：通过喷墨打印方法，在所述衬底基板上形成位于所述衬底基板的所述封装区域的有机保护膜层、位于所述绑定区域中的第五子层。
在本公开一些实施例中，所述衬底基板为柔性衬底基板。
本公开实施例再一方面提供一种显示装置的制备方法，包括：采用如上述任一项所述的制备方法在刚性支撑基板上形成所述阵列基板；其中，所述阵列基板中的衬底基板为柔性衬底基板；将所述阵列基板从所述刚性支撑基板上剥离；在所述柔性衬底基板远离所述绑定焊盘和所述绝缘支撑部的一侧贴附保护背膜；提供一IC，所述IC包括IC的绑定引脚；将所述IC的绑定引脚绑定在所述绑定焊盘上。
本公开实施例另一方面提供一种阵列基板，包括：衬底基板；位于所述衬底基板的绑定区域中的多个绑定焊盘，所述绑定区域为IC绑定时的覆盖区域；位于所述绑定区域中、且未设置所述绑定焊盘的位置处的绝缘支撑部，所述绝缘支撑部用于维持所述阵列基板与待绑定的IC之间的间隙。
在本公开一些实施例中，所述绝缘支撑部背离所述衬底基板一侧的上表面至所述衬底基板表面的高度大于所述绑定焊盘背离所述衬底基板一侧的上表面至所述衬底基板表面的高度。
在本公开一些实施例中，所述绑定焊盘用于绑定IC的绑定引脚；所述绝缘支撑部的所述上表面至所述衬底基板表面的高度，与所述绑定焊盘的所述上表面至所述衬底基板表面的高度之间的差值小于或等于待绑定的所述IC的绑定引脚的厚度。
在本公开一些实施例中，所述多个绑定焊盘包括间隔设置的输入绑定焊盘和输出绑定焊盘；其中，所述绝缘支撑部位于所述输入绑定焊盘和所述输出绑定焊盘之间。
在本公开一些实施例中，所述绑定焊盘包括间隔设置的输入绑定焊盘和输出绑定焊盘；其中，所述绝缘支撑部设置在所述输入绑定焊盘背离所述输出绑定焊盘的一侧，和/或，所述绝缘支撑部设置在所述输出绑定焊盘背离所述输入绑定焊盘的一侧。
在本公开一些实施例中，所述绑定焊盘包括间隔设置的第一绑定焊盘组和第二绑定焊盘组，所述第一绑定焊盘组包括至少一个输入绑定焊盘，所述第二绑定焊盘组包括至少一个输出绑定焊盘；其中，所述绝缘支撑部分为至少一组，同一组所述绝缘支撑部位于所述第一绑定焊盘组的同一侧、且位于所述第二绑定焊盘组的同一侧，每一组所述绝缘支撑部中的各所述绝缘支撑部与所述第二绑定焊盘组的边界之间的距离均相等。
在本公开一些实施例中，所述第一绑定焊盘组包括至少一行间隔设置的多个所述输入绑定焊盘，所述第二绑定焊盘组包括至少一行间隔设置的多个所述输出绑定焊盘，每组所述绝缘支撑部包括至少一行间隔设置的多个所述绝缘支撑部；其中，至少一行间隔设置的多个所述输入绑定焊盘与至少一行间隔设置的多个所述输出绑定焊盘、至少一行间隔设置的多个所述绝缘支撑部之间均相互平行。
在本公开一些实施例中，每一组所述绝缘支撑部包括多个间隔分布的绝缘支撑柱；或者，每一组所述绝缘支撑部包括一个绝缘支撑条。
在本公开一些实施例中，所述绝缘支撑部与所述绑定焊盘之间的距离大于或等于50μm。
在本公开一些实施例中，所述绝缘支撑部背离所述衬底基板一侧的上表面的面积小于所述绝缘支撑部朝向所述衬底基板一侧的下表面的面积。
在本公开一些实施例中，所述阵列基板还包括：设置在所述衬底基板的显示区域中的至少一层绝缘层；所述绝缘支撑部的至少一部分与所述显示区域中的至少一层所述绝缘层同层制作形成。
在本公开一些实施例中，所述绝缘支撑部包括多层结构。
在本公开一些实施例中，设置在所述衬底基板的显示区域中的至少一层绝缘层包括：依次远离所述衬底基板设置的平坦层主体、像素界定图案和隔垫物图案；所述多层结构包括：依次远离所述衬底基板的第一子层、第二子层和第三子层；其中，所述第一子层与所述平坦层主体同层制作形成；所述第二子层与所述像素界定图案同层制作形成；所述第三子层与所述隔垫物图案同层制作形成。
在本公开一些实施例中，述阵列基板还包括：设置在所述平坦层主体靠近所述衬底基板一侧、且位于所述显示区域与所述绑定区域之间的区域中的有机填充图案；所述多层结构还包括：位于所述第一子层靠近所述衬底基板一侧的第四子层；其中，所述第四子层与所述有机填充图案同层制作形成。
在本公开一些实施例中，所述阵列基板还包括：设置在所述衬底基板的封装区域中的有机保护膜层；所述绝缘支撑部包括第五子层；其中，所述第五子层与所述有机保护膜层同层制作形成。
在本公开一些实施例中，所述衬底基板为柔性衬底基板。
本公开实施例又一方面提供一种显示装置，其中，包括：如上述任一项所述的阵列基板；IC；其中，所述IC包括IC的绑定引脚；所述IC的绑定引脚绑定在所述绑定焊盘上。
附图说明
图1为本公开示例性实施例中采用COP的方式绑定IC的柔性显示装置的结构示意图；
图2A为相关技术中直接在柔性显示装置上绑定IC时发生的各种不良的示意图；
图2B为相关技术中直接在柔性显示面板上绑定IC时发生的不良的具体示意图；
图3为本公开一些实施例提供的一种阵列基板的绑定区域的结构示意图；
图4为在图3所示的阵列基板绑定区域上绑定IC的过程示意图；
图5为本公开一些实施例提供的一种阵列基板在IC压接前后的结构变化示意图；
图6为图3中A-A’方向的剖面结构示意图；
图7为本公开一些实施例提供的另一种阵列基板的绑定区域的结构示意图；
图8为在图3所示的阵列基板包括两组位于输入绑定焊盘和输出绑定焊盘之间的绝缘支撑部的结构示意图；
图9为图3所示的阵列基板中的绝缘支撑部的一种结构示意图；
图10为本公开一些实施例提供的阵列基板包括有机填充层时的结构示意图；
图11为图3所示的阵列基板中的绝缘支撑部的另一种结构示意图；
图12为本公开一些实施例提供的一种采用喷墨打印方式形成绝缘支撑部的过程示意图；
图13为本公开一些实施例提供的一种柔性显示装置的结构示意图；
图14为本公开一些实施例提供的一种阵列基板的制备方法流程图；
图15为本公开一些实施例提供的另一种阵列基板的制备方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开示例性实施例中，在相关显示装置(例如为柔性显示装置)的制备工艺中，IC绑定一般采用COF(英文全称：Chip On Film，中文名称：覆晶薄膜)的方式，即利用COF将IC绑定在显示面板(例如为柔性显示面板)的阵列基板上；由于COF为软性材质，压接时不会造成阵列基板上的线路断裂。然而，由于COF成本较高，且COF上的线路无法制备的非常细，因此，COF的绑定方式难以应用至高分辨率的显示装置中。
因此，采用COP(英文全称：Chip on plastic，即，直接在柔性基板上绑定芯片)的方式绑定IC是今后的发展方向。
如图1所示，COP的绑定方式为：在显示面板01(如柔性显示面板)的绑定区域A上直接绑定IC(图1中即标记为“IC”)，之后再贴附FPC(英文全称：Flexible Printed Circuit，中文名称：柔性印刷电路板，图1中即标记为“FPC”)。其中，柔性显示面板01上被IC覆盖的区域即为上述的绑定区域A。但是，通过COP的绑定方式将IC直接压接在柔性显 示面板01上时，如图2A所示，存在以下缺陷：
(1)、由于IC硬度较高，将IC直接压接(压接方式例如为热压)在柔性显示面板上时，会造成柔性显示面板上对应于IC bump(IC的绑定引脚，图2A中即标记为“IC bump”)位置处的背膜21下陷，继而使得该区域的柔性基板20下陷，从而使得柔性基板20上发生下陷的区域与其他区域之间形成段差。
这样一来，易导致柔性基板20上位于下陷位置处周围的线路发生断裂(Clack)，例如，如图2A中的间隙2(GAP 2)、和间隙4(GAP 4)所示，在柔性基板20存在段差处发生线路断裂。
图2B为IC压接造成的背膜21下陷过程示意图，从图2B中可以看出，由于背膜21与柔性基板20之间通常是通过压敏胶30相粘结的，当IC压接在柔性基板20上时，IC的绑定引脚(IC bump，图2B中即标记为“IC bump”)下的压敏胶30被压着后，会被挤压至没有IC bump的区域，从而造成柔性基板20发生较大程度的弯曲。其中，挤压方向如图2B中箭头所示。
(2)、以COP的绑定方式将IC绑定在柔性显示面板01上时，IC需要通过ACF(英文名称：Anisotropic Conductive Film，中文名称：各向异性导电胶)与柔性显示面板绑定在一起。ACF中分散有导电粒子，在上述下陷位置处，会发生例如图2A中间隙5(GAP 5)所示的，导电粒子聚集现象，增加柔性显示面板线路发生短路的风险。
(3)、在进行IC绑定时，IC bump与柔性显示面板上的绑定焊盘相连接，从而将IC上的信号传输给柔性显示面板上的线路。当IC中除了IC bump的部分与柔性基板20上的线路接触时，会造成短路。以柔性基板20与IC之间的预设间距为10μm为例，当采用例如热压的方式将IC压接在柔性显示面板上时，柔性显示面板中对应于IC bump处的背膜中的压敏胶会向柔性基板20上的下陷位置周围流动，如图2A中的间隙1(GAP 1)、间隙3(GAP 3)、间隙4(GAP 4)所示，使得对应于IC bump位置周围的柔性基板20发生翘起，导致柔性基板20与IC上除IC bump之外的部分之间的间距减小，例如依次减小为8.4μm、3.2μm、8.9μm。
这样一来，会增加IC上的信号与柔性显示面板上的线路之间发生短路的风险。例如，如图2A中的间隙2(GAP 2)和间隙3(GAP 3)所示时，柔性基板20几乎与IC的中间部分相接触，从而易造成短路。
本公开一些实施例一方面提供一种阵列基板100，图3和图4示出了该阵列基板100在绑定区域A内的结构。该阵列基板100包括衬底基板11；设置在衬底基板11的绑定区域A中的多个绑定焊盘10，其中，该绑定焊盘10如图4所示，用于绑定IC的绑定引脚42，绑定区域为IC绑定时的覆盖区域。该阵列基板100还包括：位于绑定区域A中、且未设置绑定焊盘10的位置处的绝缘支撑部12，该绝缘支撑部12用于维持阵列基板与待绑定的IC之间的间隙。
上述衬底基板11可以为柔性衬底基板或刚性衬底基板。其中，柔性衬底基板可以为塑料基板等柔韧性较好的基板。采用柔性衬底基板形成的阵列基板可以被弯曲或者被折叠，可扩展包括该阵列基板的显示装置的使用功能。刚性衬底基板例如可以为玻璃基板。
上述阵列基板100中的衬底基板11的绑定区域A，是指在阵列基板上预绑定IC的区域，即将衬底基板11上被绑定的IC所覆盖的区域作为上述绑定区域A。通常，绑定在阵列基板100的衬底基板11上的IC所覆盖区域的面积，即绑定区域A的面积大于如图3所示的多个绑定焊盘10的最外侧轮廓线构成区域的面积。
IC的结构通常如图4所示，包括IC本体41和IC的绑定引脚42。图4中示意出的IC本体41和IC的绑定引脚42的位置关系及数量只是一种示意，并非对IC的具体结构的限定。
并且，在一个阵列基板100上可能绑定一个或多个IC，在此情况下，每个IC覆盖在阵列基板100上的区域均可以设置成本公开一些实施例提供的上述结构。
上述绝缘支撑部12的“绝缘”，是指不破坏IC与阵列基板中相应结构的原本电连接关系。因此，绝缘支撑部12至少其表层是绝缘的，即，构成绝缘支撑部12的所有材料可以均为绝缘材料，或者，也可以是，绝缘支撑部12的表层是由绝缘材料构成、内部包含非绝缘材料(例如半导体材料、金属材料等，以起到给绝缘支撑部12的表层塑形的作用)。
绝缘支撑部12可以单独制备，即在相关阵列基板制备步骤的基础上，增加制备绝缘支撑部12的步骤；或者，绝缘支撑部12也可以与阵列基板位于衬底基板的绑定区域A以外的结构中的一层或者多层同时制备，这样，通过改变相关阵列基板中的一层或多层的图案，即可形成位于衬底基板的绑定区域中的上述绝缘支撑部12，无需增加阵列基板的制备步骤。
基于此，如图4所示，当利用上述阵列基板构成显示面板，并将IC的绑定引脚42与绑定焊盘10进行绑定时，在IC的绑定引脚42与绑定焊盘10的压接过程中，对应于IC的绑定引脚42位置处的背膜上的压敏胶会向周围流动，使得衬底基板11在对应于IC的绑定引脚42的位置处发生下陷，而对应于IC的绑定引脚42位置周围发生翘起。由于本公开一些实施例提供的上述阵列基板100还包括位于衬底基板11的绑定区域A中、且未设置绑定焊盘10的位置处的绝缘支撑部12，如图5所示，该绝缘支撑部12能够起到抑制绑定区域A中未设置绑定焊盘10的位置处发生弯曲的作用，使得压敏胶30被挤压的部分分散开来(如图5中箭头所示)，可避免由于压敏胶30被集中挤压，从而削弱阵列基板整体的发生弯曲的程度，从而维持IC与阵列基板之间的间隙。
并且，由于该绝缘支撑部12呈现绝缘性，还可以防止衬底基板11的翘起部分上的线路直接与IC上的线路接触，从而降低了阵列基板100上的线路与IC上的线路发生短路的风险；上述绝缘支撑部12还可以降低在对应于IC的绑定引脚42位置处发生ACF胶中的导电粒子聚集的概率，进而降低由于ACF胶中的导电粒子聚集而发生短路的风险。
在本公开一些实施例中，如图4所示，绝缘支撑部12背离衬底基板11一侧的上表面12a至衬底基板11表面的高度大于绑定焊盘10背离衬底基板11一侧的上表面10a至衬底基板11表面的高度。
以下实施例仅以衬底基板11具体为柔性衬底基板11为例进行示意。
即，绝缘支撑部12背离柔性衬底基板11一侧的上表面12a突出于绑定焊盘10背离柔性衬底基板11一侧的上表面10a所在的面。
这里，本公开一些实施例中的“上”和“下”的相对位置可参考图4，以绝缘支撑部12背离柔性衬底基板11的一侧的表面作为其上表面12a，以绑定焊盘10背离柔性衬底基板11的一侧的表面作为其上表面10a。
由于绝缘支撑部12的上表面12a突出于绑定焊盘10的上表面10a所在的面，即绝缘支撑部12的部分突出于绑定焊盘10。这样一来，当在阵列基板100上绑定IC时，突出于绑定焊盘10的绝缘支撑部12可以在IC本体41与柔性衬底基板11之间起到支撑作用。
本公开一些实施例不对绝缘支撑部12的下表面和绑定焊盘10的下表面的位置关系进行限定，只要保证绝缘支撑部12的上表面12a突出于绑定焊盘10的上表面10a所在的面即可。
示例的，当绝缘支撑部12单独制备，即在相关阵列基板制备步骤的基础上，增加制备绝缘支撑部12的步骤时，绝缘支撑部12的下表面和绑定焊盘10的下表面可以在同一平面内。
又示例的，当绝缘支撑部12与阵列基板中位于柔性衬底基板的绑定区域A以外的结构中的一层或者多层同时制备时，绝缘支撑部12的下表面与绑定焊盘10的下表面可以在不同的平面内。
在上述阵列基板100的柔性衬底基板11中设置上述绝缘支撑部12时，应当以不影响IC与上述绑定焊盘之间的绑定为前提。沿柔性衬底基板11的板面的垂直方向，绝缘支撑部12的高度可以根据IC的型号进行调节。
示例的，如图4所示，以IC的绑定引脚42的下表面(即朝向IC本体41一侧的表面)与IC本体41的上表面(即朝向绑定焊盘10一侧的表面)处于同一平面时，为了不影响IC与绑定焊盘10之间的绑定，沿柔性衬底基板11的板面的垂直方向(如图4中的单向箭头所示)，沿柔性衬底基板11板面的垂直方向，绝缘支撑部12的上表面12a至柔性衬底基板11表面的高度，与绑定焊盘10的上表面10a至柔性衬底基板11表面的高度之间的差值小于或等于待绑定的IC的绑定引脚的厚度。
即，绝缘支撑部12的上表面12a突出于绑定焊盘10的上表面10a所在面高度H小于或等于IC的绑定引脚42的厚度h。这样，将IC的绑定引脚42与上述绑定焊盘10绑定在一起时，可以确保IC本体41的中间部分不会被绝缘支撑部12顶起而发生翘起，从而不会影响IC的绑定效果。
这里，在不超出压接引脚总高度范围内，绝缘支撑部12的高度可以设置地尽可能地高，从而为IC提供更为稳定的支撑作用。
示例的，绝缘支撑部12的上表面12a突出于绑定焊盘10的上表面10a所在面的高度H等于IC的绑定引脚42的厚度h，即在将IC绑定到阵列基板上时，绝缘支撑部12的上表面12a能够接触到IC本体41，从而为IC提供尽可能牢固的支撑力。
这里，当绝缘支撑部的数量较少时，每个绝缘支撑部的平面尺寸可以设置地较大，从而为IC提供足够的支撑力；当绝缘支撑部之间分布的间距较小时，即绝缘支撑部设置的较为靠近时，每个绝缘支撑部的平面尺寸可以设置地较小。
以上设置方式仅为示例，本公开对绝缘支撑部的平面尺寸不作限定，绝缘支撑部的平面尺寸可根据绑定区域A的面积、绝缘支撑部的数量及绝 缘支撑部的排列方式灵活调整。
基于此，当利用上述阵列基板构成柔性显示面板，并将IC的绑定引脚42与绑定焊盘10进行绑定时，在IC的绑定引脚42与绑定焊盘10的压接过程中，柔性显示面板中对应于IC的绑定引脚42位置处的背膜中的压敏胶会向周围流动，使得柔性衬底基板11在对应于IC的绑定引脚42的位置处发生下陷，而柔性衬底基板11对应于IC的绑定引脚42位置周围发生翘起。由于在本公开一些实施例提供的上述阵列基板中，绝缘支撑部12的上表面12a突出于绑定焊盘10的上表面10a所在的面，因此，绝缘支撑部12可以起到一定的支撑作用，以使得柔性衬底基板11对应于IC的绑定引脚42的位置周围与IC之间保持固定的间距，从而维持IC与阵列基板之间的间隙，这样一来，可以防止柔性衬底基板11的翘起部分上的线路与IC上的线路相接触，从而降低了阵列基板上的线路与IC上的线路发生短路的风险。
并且，由于绝缘支撑部12可以使得柔性衬底基板对应于IC的绑定引脚位置周围与IC之间保持固定的间距，因此可以降低对应于IC的绑定引脚42的位置处的柔性衬底基板11与周围位置处的柔性衬底基板11间的段差，使得完成IC绑定工艺后，柔性衬底基板11的表面较为平坦，从而一方面，降低了柔性衬底基板11发生线路断裂的几率；另一方面，降低了在对应于IC的绑定引脚42位置处发生ACF胶中导电粒子聚集的概率，进而降低由于导电粒子聚集而发生短路的风险。
ACF胶中的单颗导电粒子的粒径通常为5μm左右，当导电粒子聚集较多时，例如10颗左右的导电粒子聚集在一起即会使得绑定焊盘10与相邻区域的柔性衬底基板10上的线路之间发生短路。
因此，如图3所示，当绝缘支撑部12与上述绑定焊盘10间的距离L小于50μm(即大约10颗导电粒子的粒径之和)时，聚集在绝缘支撑部12与上述绑定焊盘10之间的导电粒子，可能会增加阵列基板上的线路与IC上的线路发生短路的风险。因此，考虑到ACF胶的性质，绝缘支撑部12与绑定焊盘10之间的距离L大于或等于50μm。
这里的“距离L”，是指在柔性衬底基板11的板面内，绝缘支撑部12靠近绑定焊盘10一侧，与绑定焊盘10靠近绝缘支撑部12之间的间距。
在本公开一些实施例中，如图6所示，绝缘支撑部12背离柔性衬底基板11一侧的上表面12a的面积小于该绝缘支撑部12朝向柔性衬底基板11 一侧的下表面12b的面积。
即，沿柔性衬底基板11板面的垂直方向(如图6中的单向箭头所示)，绝缘支撑部12的截面呈上小下大的梯形。这样，当IC压接到阵列基板上时，当压接的压力较大时，由于绝缘支撑部12自身呈上小下大的结构，绝缘支撑部12的下部能够为其上部提供更稳固的支撑作用，从而为IC提供更稳固的支撑效果。
在本公开一些实施例中，IC的绑定引脚42通常包括：间隔设置的输入绑定引脚(Input bump)和输出绑定引脚(Output bump)。其中，Input bump用于将外接电源输入至IC内部，Output bump用于向与该IC绑定的阵列基板输入IC信号。
相对应的，如图3所示，上述绑定焊盘10通常包括：间隔设置的输入绑定焊盘101和输出绑定焊盘102。IC绑定时，输入绑定焊盘101与Input bump相对应，输出绑定引脚102与Output bump相对应。
这里，本领域技术人员应当知悉，本公开一些实施提供的附图中，绑定焊盘10的数目和排列形状只是一种示意，并非对绑定焊盘10的数目和排列形状的限定。当IC的绑定引脚42的排列形状和数目发生变化时，制备阵列基板时，绑定焊盘10的排列形状和数目也会随之发生变化。
在本公开一些实施例提供的上述阵列基板100中，如图3所示，绑定焊盘10包括间隔设置的第一绑定焊盘组a1和第二绑定焊盘组a2，第一绑定焊盘组a1包括至少一个输入绑定焊盘101，第二绑定焊盘组a2包括至少一个输出绑定焊盘102；绝缘支撑部12分为至少一组，同一组绝缘支撑部12位于第一绑定焊盘组a1的同一侧、且位于第二绑定焊盘组a2的同一侧。每一组绝缘支撑部12中的各绝缘支撑部与第二绑定焊盘组a2的边界之间的距离均相等。
这里，由于第一绑定焊盘组a1和第二绑定焊盘组a2之间的距离相对固定，因此每一组绝缘支撑部12中的各绝缘支撑部与第一绑定焊盘组a1的边界之间的距离也处处相等。
在上述的“同一组绝缘支撑部12位于第一绑定焊盘组a1的同一侧、且位于第二绑定焊盘组a2的同一侧”的情况下，同一组绝缘支撑部12与第一绑定焊盘组a1、第二绑定焊盘组a2之间有三种示例的设置位置：
例如图3所示，同一组绝缘支撑部12设置于第一绑定焊盘组a1与第二绑定焊盘组a2之间。
或者，如图7所示，同一组绝缘支撑部12’设置于第一绑定焊盘组a1背离第二绑定焊盘组a2的一侧。
又或者，如图7所示，同一组绝缘支撑部12”设置于第二绑定焊盘组a2背离第一绑定焊盘组a1的一侧。
这里，在以上图7中，仅以一组绝缘支撑部12’与第一绑定焊盘组a1的边界之间的距离L1，等于另一组绝缘支撑部12与第一绑定焊盘组a1的边界之间的距离L2为例进行示意，L1和L2可以相等，也可以不相等。
根据上述“同一组绝缘支撑部12位于第一绑定焊盘组a1的同一侧、且位于第二绑定焊盘组a2的同一侧”的设置方式，则绝缘支撑部12’为同一组，绝缘支撑部12为同一组。
在本公开一些实施例中，如图3或图7所示，第一绑定焊盘组a1包括至少一行间隔设置的多个输入绑定焊盘101，第二绑定焊盘组a2包括至少一行间隔设置的多个输出绑定焊盘102，每组绝缘支撑部包括至少一行间隔设置的多个绝缘支撑部12；其中，至少一行间隔设置的多个输入绑定焊盘101与至少一行间隔设置的多个输出绑定焊盘102、至少一行间隔设置的多个绝缘支撑部12之间均相互平行，从而使得绑定区域中的各行端子结构排列更为整齐，便于IC的绑定与对IC进行支撑。
在本公开一些实施例中，每一组绝缘支撑部12可以如图3或图7所示，包括多个间隔分布的绝缘支撑柱；或者，每一组绝缘支撑部12包括一个绝缘支撑条。
当绝缘支撑部12包括多个间隔分布的绝缘支撑柱时，本公开一些实施例对绝缘支撑柱的形状和数目不做限定，只要绑定IC时，绝缘支撑部12可以在柔性衬底基板11与IC本体41之间起到一定的支撑作用即可。
示例的，绝缘支撑柱的上表面的形状可以为圆形或矩形。本公开一些实施例附图中，仅以绝缘支撑柱的上表面的形状为矩形为例进行示意的。
在本公开一些实施例中，当绝缘支撑柱的平面尺寸小于50μm时，单个绝缘支撑柱的支撑效果较差，IC绑定时难以使得柔性衬底基板11与IC本体41之间保持固定的间距。当绝缘支撑柱的平面尺寸大于200μm时，由于绑定区域A的面积较小，难以在输入绑定焊盘101和输出绑定焊盘102间形成具有上述200μm平面尺寸的绝缘支撑柱。因此，绝缘支撑柱的平面尺寸为50μm～200μm。绝缘支撑柱的数目可以根据IC的尺寸进行调节。
这里，当绝缘支撑柱的上表面的形状为矩形时，上述平面尺寸是指该 矩形的长度或者宽度。当绝缘支撑柱的上表面的形状为圆形时，上述平面尺寸是指该圆形的直径。
在本公开一些实施例中，如图3所示，绝缘支撑部12设置于输入绑定焊盘101和输出绑定焊盘102之间。
在此情况下，当进行IC绑定时，对应于IC的绑定引脚42位置处的柔性衬底基板11由于受到压接的压力发生下陷，使得柔性衬底基板11中对应于绑定引脚42的周围位置处出现翘起，在此情况下，由于绝缘支撑部12的支撑作用，可以使得柔性衬底基板11与IC本体41的中间部分之间保持固定的间距，从而能降低柔性衬底基板11上的线路与IC本体41上的线路接触的概率，进而降低了短路的风险。
示例的，如图8所示，阵列基板100包括至少两组位于输入绑定焊盘101和输出绑定焊盘102之间的绝缘支撑部12，每组均包括一行间隔设置的多个绝缘支撑部12，以提高绝缘支撑部12的整体支撑效果。
在本公开一些实施例中，绝缘支撑部12设置于输入绑定焊盘101背离输出绑定焊盘102的一侧，或者设置于输出绑定焊盘102背离输入绑定焊盘101的一侧。
在此情况下，当进行IC的绑定时，对应于IC的绑定引脚42位置处的柔性衬底基板11由于受到压接的压力发生下陷，使得周柔性衬底基板11中对应于绑定引脚42的周围位置处出现翘起，此时，由于绝缘支撑部12的支撑作用，可以使得柔性衬底基板11与IC本体41的边缘部分之间保持固定的间距，从而能降低柔性衬底基板11的翘起部分上的线路与IC本体41上的线路接触的概率，从而降低短路的风险。
在本公开一些实施例中，如图7所示，绝缘支撑部12设置于：多个输入绑定焊盘101构成的第一绑定焊盘组a1和多个输出绑定焊盘102构成的第二绑定焊盘组a2之间、多个输入绑定焊盘101构成的第一绑定焊盘组a1背离多个输出绑定焊盘102构成的第二绑定焊盘组a2的一侧、以及多个输出绑定焊盘102构成的第二绑定焊盘组a2背离多个输入绑定焊盘101构成的第一绑定焊盘组a1的一侧。
这样，当进行IC的绑定时，绝缘支撑部12可以使得IC本体41中未对应IC的绑定引脚42的部分与翘起部分的柔性衬底基板11之间保持固定的间距，从而能降低柔性衬底基板11的翘起部分上的线路与IC本体41上的线路接触的概率，进一步降低短路的风险。
在本公开一些实施例中，为了简化阵列基板的制备工艺，绝缘支撑部12可以与阵列基板100中位于柔性衬底基板11的绑定区域A以外的相关膜层同时形成，以避免增加制备绝缘支撑部12的步骤。
例如，阵列基板还包括：设置在柔性衬底基板的显示区域中的至少一层绝缘层；上述绝缘支撑部的至少一部分可以与显示区域中的至少一层绝缘层同层制作形成，以简化制备工艺。
这里，本公开一些实施例中所指的“同层制作形成”是指，对采用同种材料制成的同一膜层(可以为一层膜或多层膜)进行构图处理(或称为构图工艺)，以同时形成不同的图案，即本公开上述实施例中所指的“上述绝缘支撑部的至少一部分”与“显示区域中的至少一层绝缘层”；其中的“同层”即指的是不同的图案是通过对同一膜层进行构图处理后获得的，这样，相比于对不同的图案采用不同的构图处理的方式，本公开一些实施例提供的上述阵列基板在制备的过程中，通过调整构图处理中所采用的掩膜板的图案即可在一次构图处理中形成不同的图案，简化阵列基板的制备工艺。
需要指出的是，对同一膜层进行构图处理所获得的不同的图案，可以是位于同一衬底表面，或者，不同的图案可以位于不同的衬底表面，可根据阵列基板的相应设计要求灵活调整，本公开一些实施例对此不作限定。
示例的，上述绝缘支撑部包括多层结构。
多层结构包括至少两层子层；所有的子层在衬底基板上的正投影至少部分交叠，以形成堆叠结构。
所有的子层的形状也可均相同，以简化各子层制作时的构图工艺。
本领域技术人员悉知，设置在衬底基板的显示区域中的至少一层绝缘层可包括：依次远离衬底基板设置的平坦层主体、像素界定图案和隔垫物图案。
通常，平坦层主体与像素界定图案为有机膜层，隔垫物图案可以为有机膜层或无机膜层；当隔垫物图案为有机膜层时，该有机膜层可以采用光感材料例如光刻胶形成。
在本公开一些实施例中，如图9所示，绝缘支撑部12的多层结构包括：依次远离衬底基板11的第一子层(或称为第一图案)121’、第二子层(或称为第二图案)122’和第三子层(或称为第三图案)123’；其中，第一子层121’与显示区域中的平坦层主体同层制作形成，第二子层122’ 与显示区域中的像素界定图案同层制作形成，第三子层123’与显示区域中的隔垫物图案同层制作形成。
这里，第一子层121’与平坦层主体构成平坦层(英文全称：Planarazition，英文简称：PLN层)，第一子层121’即为平坦层位于绑定区域A的图案121’。
第二子层122’与像素界定图案构成像素界定层(英文全称：Pixel definition layer，英文简称：PDL层)，第二子层122’即为像素界定层位于绑定区域A的图案122’以及隔垫物层(英文全称：Photospacer，英文简称：PS层)位于绑定区域A的图案123’。
第三子层123’与隔垫物图案构成隔垫物层，第三子层123’即为隔垫物层位于绑定区域A的图案123’。
即，每个绝缘支撑部12均由层叠设置的平坦层位于绑定区域A的图案121’、像素界定层位于绑定区域A的图案122’以及隔垫物层位于绑定区域A的图案123’构成。
在此情况下，当平坦层、像素界定层以及隔垫物层均主要由有机材料构成时，可以通过包括涂胶、曝光、显影、刻蚀等步骤的构图工艺，依次形成平坦层位于绑定区域A的图案121’、像素界定层位于绑定区域A的图案122’以及隔垫物层以及隔垫物层位于绑定区域A的图案123’。
当隔垫物层主要由光刻胶材料构成时，可以无需进行刻蚀工艺，通过包括涂胶、曝光、显影的步骤即可形成隔垫物层以及隔垫物层位于绑定区域A的图案123’，以简化形成上述绝缘支撑部12的制备工艺。
这里，当绝缘支撑部12包括间隔设置的多个绝缘支撑柱时，在通过上述构图工艺形成绝缘支撑柱时，单个绝缘支撑柱的平面尺寸示例的可以为50μm～100μm。
其中，当绝缘支撑柱的上表面的形状为矩形时，上述平面尺寸是指该矩形的长度或者宽度；当绝缘支撑柱的上表面的形状为圆形时，上述平面尺寸是指该圆形的直径。
当绝缘支撑部12包括：平坦层位于绑定区域A的图案121’、像素界定层位于绑定区域A的图案122’以及隔垫物层位于绑定区域A的图案123’时，形成的绝缘支撑部12如图9所示，为三层结构。
示例的，三层结构的绝缘支撑部12的整体厚度可以达到4μm～8μm。
在本公开一些实施例中，对于走线折叠的柔性显示装置，例如扇出型 (fanout)走线折叠的柔性显示装置，在折叠位置处，柔性显示装置中的线路易发生断裂。为了避免出现上述情况，通常如图10所示，阵列基板还包括位于柔性衬底基板11上对应于折叠位置处的有机填充图案124，该折叠位置通常位于显示区域和绑定区域A之间。
示例的，有机填充图案124可以为主要由PI材料构成的填充层，在此情况下，该有机填充图案124又可以称为PI填充层(英文全称：Polyimide Filling，英文简称：PI filling)。
有机填充图案124设置在平坦层121和柔性衬底基板11之间，并且有机填充图案124设置在源漏金属层16与柔性衬底基板11之间。
示例的，如图10所示，上述阵列基板100还包括依次设置在柔性衬底基板11上的缓冲阻挡层13、栅绝缘层(英文全称：Gate Insulator，英文缩写：GI)14以及间绝缘层(英文全称：Interlayer Dieletric，英文缩写：ILD)15，其中，缓冲阻挡层13可以对水汽进行阻挡。
在此情况下，如图11所示，绝缘支撑部12还可以包括位于第一子层121’靠近衬底基板11一侧的第四子层(或称为第四图案)124’；其中，第四子层124’与折叠位置处的有机填充图案同层制作形成。
这里，第四子层124’与有机填充图案构成有机填充层，第四子层124’即为有机填充层位于绑定区域A的图案124’。
在此情况下，绝缘支撑部12为四层结构，即，绝缘支撑部12包括：依次设置在柔性衬底基板11上的有机填充层124位于绑定区域A的图案124’、平坦层位于绑定区域A的图案121’、像素界定层位于绑定区域A的图案122’以及隔垫物层位于绑定区域A的图案123’。
示例的，四层结构的绝缘支撑部12的整体厚度可以达到6μm～10μm。
在本公开提供的另一些实施例中，当由上述阵列基板100构成的柔性显示装置采用薄膜封装(英文全称：Thin Film Encapsulation，英文简称：TFE)时，上述阵列基板100还包括设置在柔性衬底基板11上的薄膜封装层，该薄膜封装层能阻挡水汽侵入柔性显示装置中的有机发光材料层，防止有机发光材料层失效。
其中，薄膜封装层通常包括两层无机膜层以及位于两层无机膜层之间的有机膜层，有机膜层可以采用喷墨打印的方式形成。
相应的，上述绝缘支撑部可包括第五子层(或称为第五图案)；其中，该第五子层可以与上述薄膜封装层中的有机膜层位于封装区域中的有机保 护膜层同层制作形成。
在此情况下，绝缘支撑部12包括有机膜层位于绑定区域A的图案。
绝缘支撑部12可以采用喷墨打印的方式形成。此时，绝缘支撑部12与封装区域中的有机保护膜层同层形成。
如图12所示，可以在采用喷墨打印的方式形成有机保护膜层的同时，通过控制打印喷头17的位置和打印时间，在柔性衬底基板11的绑定区域A中打印上述绝缘支撑部12。
这里，待形成的绝缘支撑部12的密度可以随绝缘支撑部12的尺寸进行调整。示例的，当用于打印绝缘支撑部12的材料流动性较好时，通过打印形成的绝缘支撑部12的平面尺寸较大，此时需要减小绝缘支撑部12的打印密度；当用于打印绝缘支撑部12的材料流动性较差时，通过打印形成的绝缘支撑部12的平面尺寸可以被控制的较小，此时可以增加绝缘支撑部12的打印密度。
在打印完成后，可以采用紫外光对绝缘支撑部12进行固化，以增强其稳定性。
示例的，绝缘支撑部12包括多个间隔设置的绝缘支撑柱，采用喷墨打印的方式形成的绝缘支撑柱的平面尺寸为50μm～200μm，厚度为5μm～10μm。
其中，当绝缘支撑柱的上表面的形状为矩形时，上述平面尺寸是指该矩形的长度或者宽度；当绝缘支撑柱的上表面的形状为圆形时，上述平面尺寸是指该圆形的直径。
通过以上打印过程，绝缘支撑部12可以与薄膜封装层中的有机保护膜层同层形成。
本公开一些实施例再一方面提供一种显示装置(例如为柔性显示装置)200，如图13所示，该柔性显示装置包括如上所述的任一种阵列基板100、IC(图13中即标记为“IC”)；其中，IC包括IC的绑定引脚；IC的绑定引脚通过阵列基板的绑定焊盘绑定在阵列基板100上。
这里，IC的绑定引脚请参阅前述的图4，此处不再赘述。
该柔性显示装置具有与前述实施例提供的阵列基板相同的结构和有益效果。由于前述实施例已经对该阵列基板的有益效果进行了详细的描述，此处不再赘述。
示例的，该柔性显示装置可以为包括上述阵列基板的OLED(Organic Light-Emitting Diode，有机电致发光二极管)柔性显示面板，也可以为包 括上述阵列基板的OLED显示装置。
本公开一些实施例另一方面提供一种上述阵列基板100的制备方法，如图14所示，包括步骤101-102：
S101、在衬底基板11的绑定区域中形成多个绑定焊盘10；其中，上述绑定焊盘10用于绑定IC的绑定引脚42，绑定区域即为IC绑定时的覆盖区域；
S102、在衬底基板11的绑定区域A中、且未设置绑定焊盘10的位置处形成绝缘支撑部12，绝缘支撑部12用于维持阵列基板与待绑定的IC之间的间隙。
这里，上述S101与S102可以同时进行；或者，也可以先执行S101、再执行S102；再或者，也可以先执行S102、再执行S101。
在本公开一些实施例中，如图4所示，形成的绝缘支撑部12背离衬底基板11一侧的上表面12a至衬底基板11表面的高度大于形成的绑定焊盘10背离衬底基板11一侧的上表面10a至衬底基板11表面的高度。
即，绝缘支撑部12的背离柔性衬底基板11一侧的上表面突出于绑定焊盘10背离柔性衬底基板11一侧的上表面所在的面，绝缘支撑部12突出的部分可以为IC提供进一步的支撑力。
在本公开一些实施例中，沿柔性衬底基板11板面的垂直方向，绝缘支撑部12的高度应当以不影响IC与上述绑定焊盘之间的正常绑定为前提尽可能地高，从而为IC提供尽可能牢固的支撑力。
即如图4所示，沿衬底基板11板面的垂直方向，绝缘支撑部12的上表面12a至衬底基板11表面的高度，与绑定焊盘10的上表面10a至衬底基板11表面的高度之间的差值小于或等于待绑定的IC的绑定引脚的厚度。
其中，绝缘支撑部12的高度可以根据IC的型号进行调节。
示例的，当IC的结构如图4所示时，以IC的绑定引脚42的下表面与IC本体41的上表面处于同一平面为例，为了不影响IC与绑定焊盘之间的正常绑定，绝缘支撑部12突出于绑定焊盘10的上表面10a所在的面的高度H小于或等于IC的绑定引脚42的厚度h，这样，将IC的绑定引脚42与上述绑定焊盘10绑定在一起时，可以确保IC本体41的中间部分不会因为被绝缘支撑部12顶起而发生翘起，因此不会影响IC的绑定效果。
在本公开一些实施例提供的上述阵列基板中，绝缘支撑部12可以单独 制备，即在相关阵列基板制备步骤的基础上，增加制备绝缘支撑部12的步骤；也可以与阵列基板中位于柔性衬底基板的绑定区域A以外的结构中的一层或者多层同时制备，即可以通过改变相关阵列基板中一层或多层结构的图案，来制备上述的绝缘支撑部12，从而不增加阵列基板的制备步骤。
这里，为简化绝缘支撑部12的制作难度，绝缘支撑部12可以与显示区域中的部分结构同层制作形成，即：
上述制备方法还包括：在衬底基板的显示区域中形成至少一层绝缘层。绝缘支撑部的至少一部分与显示区域中的至少一层绝缘层同层制作形成。
这里，本公开一些实施例中所指的“同层制作形成”是指，对采用同种材料制成的同一膜层(可以为一层膜或多层膜)进行构图处理(或称为构图工艺)，以同时形成不同的图案，即本公开上述实施例中所指的“上述绝缘支撑部的至少一部分”与“显示区域中的至少一层绝缘层”；其中的“同层”即指的是不同的图案是通过对同一膜层进行构图处理后获得的，这样，相比于对不同的图案采用不同的构图处理的方式，本公开一些实施例提供的上述阵列基板在制备的过程中，通过调整构图处理中所采用的掩膜板的图案即可在一次构图处理中形成不同的图案，简化阵列基板的制备工艺。
需要指出的是，对同一膜层进行构图处理所获得的不同的图案，可以是位于同一衬底表面，或者，不同的图案可以位于不同的衬底表面，可根据阵列基板的相应设计要求灵活调整，本公开一些实施例对此不作限定。
以形成的绝缘支撑部包括多层结构为例，下面提供若干示例的制备过程，以详细描述上述绝缘支撑部的制作过程：
在衬底基板的显示区域中形成依次远离衬底基板的平坦层、像素界定图案和隔垫物图案；形成绝缘支撑部包括：形成依次远离衬底基板的第一子层、第二子层和第三子层；其中，第一子层与平坦层同层制作形成，第二子层与像素界定图案同层制作形成，第三子层与隔垫物图案同层制作形成。
示例的，形成绝缘支撑部12的方法如图15所示，包括步骤201-203：
S201、在柔性衬底基板11上形成第一绝缘薄膜，并对第一绝缘薄膜201进行构图处理，以形成位于柔性衬底基板11的显示区域中的平坦层主 体、位于柔性衬底基板11的绑定区域A中的第一子层121’；
第一子层121’与平坦层主体构成平坦层，第一子层121’即为平坦层121位于绑定区域中的图案。
本公开一些实施例中的构图是指构图工艺，构图工艺可以包括光刻工艺，或，包括光刻工艺以及刻蚀步骤等其他用于形成预定图形的工艺。光刻工艺，包括成膜、曝光、显影等工艺。
示例的，本公开一些实施例中的光刻工艺，指利用光刻胶、掩模板、曝光机等形成图形的工艺。
本公开一些实施例中，形成包括第一子层的设备和工艺与制备相关阵列基板的设备相兼容。例如，通过控制掩膜板的形状，并对光刻胶进行曝光、显影以及刻蚀被光刻胶露出的膜层，可以在柔性衬底基板11的绑定区域A形成上述第一子层。
本领域技术人员应知悉，制备阵列基板时，在柔性衬底基板11上形成平坦层121之前，通常还包括在柔性衬底基板11上形成栅极、栅绝缘层、有源层、源漏金属层等工艺，形成上述膜层的工艺与相关制备工艺相同，此处不作赘述。
S202、在形成有平坦层主体和第一子层121’的柔性衬底基板11上形成第二绝缘薄膜，并对第二绝缘薄膜进行构图处理，以形成位于显示区域中的像素界定图案、位于绑定区域A中的第二子层122’；
第二子层122’与像素界定图案构成像素界定层，第二子层122’即为像素界定层位于绑定区域中的图案。
这里，显示区中的像素界定图案通常为网状，从而限定出一个个亚像素的区域。
S203、在形成有像素界定图案和第二子层的柔性衬底基板11上形成第三绝缘薄膜，并对第三绝缘薄膜进行构图处理，以形成位于显示区域中的隔垫物图案、位于绑定区域A的第三子层；
第三子层与隔垫物图案构成隔垫物层，第三子层即为隔垫物层位于绑定区域中的图案。
即，形成的绝缘支撑部12包括上述的第一子层、第二子层以及第三子层。
这样一来，形成的绝缘支撑部12为三层结构。绝缘支撑部12可以与阵列基板中的相关膜层同时形成，因此无需单独制备，简化了形成包括绝 缘支撑部12的阵列基板的工艺。
此外，对于走线折叠型显示装置，例如扇出型(fanout)走线折叠的柔性显示装置，在折叠位置处，柔性显示装置中线路易发生断裂。为了避免出现上述情况，通常如图10所示，阵列基板还包括位于柔性衬底基板11上与折叠位置对应的位置处的有机填充层124、且有机填充层124还设置在源漏金属层16和柔性衬底基板11之间。通常，折叠位置位于显示区域和绑定区域A之间。
这样一来，在形成平坦层121之前，上述制备方法还包括：
在柔性衬底基板11上形成第四绝缘薄膜，并对第四绝缘薄膜进行构图处理，以形成位于显示区域和绑定区域A之间的有机填充图案、以及位于柔性衬底基板11的绑定区域A的第四子层；
第四子层与有机填充图案构成有机填充层124，第四子层即为有机填充层124位于绑定区域中的图案。
在此情况下，绝缘支撑部12还包括上述第四子层。
这里，对于走线折叠型柔性显示装置，在制备阵列基板时，示例的，可以首先确定出预折叠区域；然后根据预折叠区域控制掩膜板的形状；在对上述第四绝缘薄膜构图时，利用上述掩膜板对第四绝缘薄膜进行曝光，可以在柔性衬底基板11的显示区域和绑定区域A之间，与上述折叠位置对应的位置处，形成有机填充图案；同时在绑定区域A形成上述第四子层。
在此情况下，形成的绝缘支撑部12为四层结构。
相比于三层结构的绝缘支撑部12，四层结构的绝缘支撑部12能够适当增加绝缘支撑部12的高度，以进一步降低IC绑定时，柔性衬底基板11与IC本体41之间的间距，使得IC绑定后柔性衬底基板11的表面更平坦，从而进一步降低柔性衬底基板11的线路发生断裂和在柔性衬底基板11上发生导电粒子聚集的风险，同时可以进一步避免柔性衬底基板11上的电路与IC本体41相接触造成短路的风险。
在本公开另一些实施例中，上述制备方法还包括：在衬底基板的封装区域中形成至少一层绝缘层；上述绝缘支撑部的至少一部分与封装区域中的至少一层绝缘层同层制作形成。
示例的，上述至少一层绝缘层可以包括有机保护膜层；形成上述绝缘支撑部包括形成：第五子层；其中，第五子层与有机保护膜层同层制作形成。
上述绝缘支撑部12包括第五子层的情况可以采用喷墨打印的方式形成，示例的：
通过喷墨打印方法，在柔性衬底基板11上形成位于柔性衬底基板11的封装区域的有机保护膜层、位于柔性衬底基板11的绑定区域A中的第五子层；
本领域技术人员知悉，在形成薄膜封装层之前，阵列基板的制备方法还包括在柔性衬底基板11上形成显示所需的层结构的步骤，例如形成栅极、源极、漏极以及发光层等的步骤。形成上述层结构的步骤与相关阵列基板的制备工艺相同，此处不再赘述。并且，薄膜封装层通常包括两层无机膜层以及位于两层无机膜层之间的有机膜层，其中有机膜层可以采用喷墨打印的方式形成。
这里，第五子层和有机保护膜层构成有机膜层，该有机膜层为薄膜封装层中的有机膜层。在此情况下，绝缘支撑部12包括第五子层。
示例的，如图12所示，可以在采用喷墨打印的方式在形成有机膜层的同时，通过控制打印喷头17的位置和打印时间，在柔性衬底基板11的绑定区域A打印上述绝缘支撑部12；之后可以采用紫外光固化的方式固化绝缘支撑部12。
基于此，当利用上述阵列基板构成柔性显示面板，并将IC的绑定引脚42与绑定焊盘10进行绑定时，压接过程中，柔性显示面板中对应于IC的绑定引脚42位置处的背膜中的压敏胶会向周围流动，使得柔性衬底基板11在对应于IC的绑定引脚42的位置处发生下陷，柔性衬底基板11对应于IC的绑定引脚42的位置周围发生翘起。由于阵列基板还包括位于柔性衬底基板11的绑定区域A中、未设置绑定焊盘10的位置处的绝缘支撑部12，绝缘支撑部12的上表面突出于绑定焊盘10的上表面所在的面，因此绝缘支撑部12可以起到一定的支撑作用，以使得对应于IC的绑定引脚42的位置周围的柔性衬底基板11与IC之间保持固定的间距，这样一来，可以防止柔性衬底基板11的翘起部分上的线路与IC上的线路接触，从而降低了发生短路的风险。
同时，由于绝缘支撑部12可以使得对应于IC的绑定引脚位置周围的柔性衬底基板与IC之间保持固定的间距，因此可以降低对应于IC的绑定引脚42的位置处的柔性衬底基板11与周围位置处的柔性衬底基板11间的段差，使得完成IC绑定工艺后，柔性衬底基板11的表面较为平坦，从而 一方面，降低了柔性衬底基板11发生线路断裂的几率；另一方面，降低在对应于IC的绑定引脚42位置处发生导电粒子聚集的几率，进而降低导电粒子聚集发生短路的风险。
本公开一些实施例又一方面提供了一种显示装置的制备方法，该显示装置示例的可以为柔性显示装置，该柔性显示装置的制备方法包括如下步骤：
采用上述任一实施例提供的阵列基板的制备方法在刚性支撑基板(如玻璃基板)上形成阵列基板；其中，阵列基板中的衬底基板为柔性衬底基板；刚性支撑基板可以为柔性衬底基板提供较稳定的支撑，以便在柔性衬底基板上形成相应的结构。
将阵列基板从刚性支撑基板上剥离；
在柔性衬底基板远离绑定焊盘和绝缘支撑部的一侧贴附保护背膜，以使剥离后的柔性衬底基板平整化；
提供一IC，该IC包括IC的绑定引脚；将IC的绑定引脚绑定在绑定焊盘上。
这里，当形成的上述柔性的阵列基板为包括多个子阵列基板的母板时，在进行IC绑定前，上述制备方法还可包括对剥离后的母板进行切割的工艺。
上述柔性显示装置包括如上所述的任一种阵列基板的制备方法，具有与前述实施例提供的阵列基板的制备方法相同的步骤和有益效果。由于前述实施例已经对该阵列基板的制备方法的步骤和有益效果进行了详细的描述，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (33)

  1. 一种阵列基板的制备方法，包括：
    在衬底基板的绑定区域中形成多个绑定焊盘，所述绑定区域为IC绑定时的覆盖区域；
    在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，所述绝缘支撑部用于维持所述阵列基板与待绑定的IC之间的间隙。
  2. 根据权利要求1所述的制备方法，其中，形成的所述绝缘支撑部背离所述衬底基板一侧的上表面至所述衬底基板表面的高度大于形成的所述绑定焊盘背离所述衬底基板一侧的上表面至所述衬底基板表面的高度。
  3. 根据权利要求2所述的制备方法，其中，所述绝缘支撑部的所述上表面至所述衬底基板表面的高度，与所述绑定焊盘的所述上表面至所述衬底基板表面的高度之间的差值小于或等于待绑定的IC的绑定引脚的厚度。
  4. 根据权利要求1所述的制备方法，其中，所述制备方法还包括：在所述衬底基板的显示区域中形成至少一层绝缘层；
    所述在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：所述绝缘支撑部的至少一部分与所述显示区域中的至少一层所述绝缘层同层制作形成。
  5. 根据权利要求4所述的制备方法，其中，形成的所述绝缘支撑部包括多层结构。
  6. 根据权利要求5所述的制备方法，其中，所述在所述衬底基板的所述显示区域中形成至少一层绝缘层，包括：在所述衬底基板的所述显示区域中形成依次远离所述衬底基板的平坦层主体、像素界定图案和隔垫物图案；
    形成所述绝缘支撑部包括：依次形成远离所述衬底基板的第一子层、第二子层和第三子层；其中，
    所述第一子层与所述平坦层主体同层制作形成；
    所述第二子层与所述像素界定图案同层制作形成；
    所述第三子层与所述隔垫物图案同层制作形成。
  7. 根据权利要求6所述的制备方法，其中，所述在所述衬底基板 的所述绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：
    在所述衬底基板上形成第一绝缘薄膜，并对所述第一绝缘薄膜进行构图处理，以形成位于所述衬底基板的显示区域中的平坦层主体、位于所述绑定区域中的第一子层；
    在形成有所述平坦层主体和所述第一子层的所述衬底基板上形成第二绝缘薄膜，并对所述第二绝缘薄膜进行构图处理，以形成位于所述显示区域中的像素界定图案、位于所述绑定区域中的第二子层；
    在形成有所述像素界定图案和所述第二子层的所述衬底基板上形成第三绝缘薄膜，并对所述第三绝缘薄膜进行构图处理，以形成位于所述显示区域中的隔垫物图案、位于所述绑定区域中的第三子层。
  8. 根据权利要求6所述的制备方法，其中，所述制备方法还包括：在形成所述平坦层主体之前，在所述衬底基板的所述显示区域与所述绑定区域之间的区域中形成有机填充图案；
    形成所述绝缘支撑部还包括：形成位于所述第一子层靠近所述衬底基板一侧的第四子层；其中，所述第四子层与所述有机填充图案同层制作形成。
  9. 根据权利要求8所述的制备方法，其中，所述在所述衬底基板的绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，还包括：
    在形成所述平坦层之前，在所述衬底基板上形成第四绝缘薄膜；
    对所述第四绝缘薄膜进行构图处理，以形成位于所述显示区域与所述绑定区域之间的区域中的有机填充图案、位于所述绑定区域中的第四子层。
  10. 根据权利要求5所述的制备方法，其中，形成的所述多层结构包括至少两层子层；其中，所有的所述子层在所述衬底基板上的正投影至少部分交叠，以形成堆叠结构。
  11. 根据权利要求5所述的制备方法，其中，形成的所述多层结构包括至少两层子层；其中，所有的所述子层的形状均相同。
  12. 根据权利要求1所述的制备方法，其中，所述制备方法还包括：在所述衬底基板的封装区域中形成至少一层绝缘层；
    所述在所述衬底基板的所述绑定区域中、且未设置所述绑定焊盘 的位置处形成绝缘支撑部，包括：
    所述绝缘支撑部的至少一部分与所述封装区域中的至少一层所述绝缘层同层制作形成。
  13. 根据权利要求12所述的制备方法，其中，所述至少一层绝缘层包括有机保护膜层；
    形成所述绝缘支撑部包括：形成第五子层；其中，所述第五子层与所述有机保护膜层同层制作形成。
  14. 根据权利要求13所述的制备方法，其中，所述在所述衬底基板的绑定区域中、且未设置所述绑定焊盘的位置处形成绝缘支撑部，包括：
    通过喷墨打印方法，在所述衬底基板上形成位于所述衬底基板的所述封装区域的有机保护膜层、位于所述绑定区域中的第五子层。
  15. 根据权利要求1至14任一项所述的制备方法，其中，所述衬底基板为柔性衬底基板。
  16. 一种显示装置的制备方法，包括：
    采用如权利要求1至15任一项所述的制备方法在刚性支撑基板上形成所述阵列基板；其中，所述阵列基板中的衬底基板为柔性衬底基板；
    将所述阵列基板从所述刚性支撑基板上剥离；
    在所述柔性衬底基板远离所述绑定焊盘和所述绝缘支撑部的一侧贴附保护背膜；
    提供一IC，所述IC包括IC的绑定引脚；将所述IC的绑定引脚绑定在所述绑定焊盘上。
  17. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板的绑定区域中的多个绑定焊盘，所述绑定区域为IC绑定时的覆盖区域；
    位于所述绑定区域中、且未设置所述绑定焊盘的位置处的绝缘支撑部，所述绝缘支撑部用于维持所述阵列基板与待绑定的IC之间的间隙。
  18. 根据权利要求17所述的阵列基板，其中，所述绝缘支撑部背离所述衬底基板一侧的上表面至所述衬底基板表面的高度大于所述绑 定焊盘背离所述衬底基板一侧的上表面至所述衬底基板表面的高度。
  19. 根据权利要求18所述的阵列基板，其中，所述绑定焊盘用于绑定IC的绑定引脚；
    所述绝缘支撑部的所述上表面至所述衬底基板表面的高度，与所述绑定焊盘的所述上表面至所述衬底基板表面的高度之间的差值小于或等于待绑定的所述IC的绑定引脚的厚度。
  20. 根据权利要求17所述的阵列基板，其中，所述多个绑定焊盘包括间隔设置的输入绑定焊盘和输出绑定焊盘；其中，
    所述绝缘支撑部位于所述输入绑定焊盘和所述输出绑定焊盘之间。
  21. 根据权利要求17所述的阵列基板，其中，所述绑定焊盘包括间隔设置的输入绑定焊盘和输出绑定焊盘；其中，
    所述绝缘支撑部设置在所述输入绑定焊盘背离所述输出绑定焊盘的一侧，和/或，所述绝缘支撑部设置在所述输出绑定焊盘背离所述输入绑定焊盘的一侧。
  22. 根据权利要求17所述的阵列基板，其中，所述绑定焊盘包括间隔设置的第一绑定焊盘组和第二绑定焊盘组，所述第一绑定焊盘组包括至少一个输入绑定焊盘，所述第二绑定焊盘组包括至少一个输出绑定焊盘；其中，
    所述绝缘支撑部分为至少一组，同一组所述绝缘支撑部位于所述第一绑定焊盘组的同一侧、且位于所述第二绑定焊盘组的同一侧，每一组所述绝缘支撑部中的各所述绝缘支撑部与所述第二绑定焊盘组的边界之间的距离均相等。
  23. 根据权利要求22所述的阵列基板，其中，
    所述第一绑定焊盘组包括至少一行间隔设置的多个所述输入绑定焊盘，所述第二绑定焊盘组包括至少一行间隔设置的多个所述输出绑定焊盘，每组所述绝缘支撑部包括至少一行间隔设置的多个所述绝缘支撑部；
    其中，至少一行间隔设置的多个所述输入绑定焊盘与至少一行间隔设置的多个所述输出绑定焊盘、至少一行间隔设置的多个所述绝缘支撑部之间均相互平行。
  24. 根据权利要求22所述的阵列基板，其中，每一组所述绝缘支撑部包括多个间隔分布的绝缘支撑柱；或者，每一组所述绝缘支撑部 包括一个绝缘支撑条。
  25. 根据权利要求17所述的阵列基板，其中，所述绝缘支撑部与所述绑定焊盘之间的距离大于或等于50μm。
  26. 根据权利要求17所述的阵列基板，其中，所述绝缘支撑部背离所述衬底基板一侧的上表面的面积小于所述绝缘支撑部朝向所述衬底基板一侧的下表面的面积。
  27. 根据权利要求17所述的阵列基板，其中，所述阵列基板还包括：设置在所述衬底基板的显示区域中的至少一层绝缘层；
    所述绝缘支撑部的至少一部分与所述显示区域中的至少一层所述绝缘层同层制作形成。
  28. 根据权利要求27所述的阵列基板，其中，所述绝缘支撑部包括多层结构。
  29. 根据权利要求28所述的阵列基板，其中，设置在所述衬底基板的显示区域中的至少一层绝缘层包括：依次远离所述衬底基板设置的平坦层主体、像素界定图案和隔垫物图案；
    所述多层结构包括：依次远离所述衬底基板的第一子层、第二子层和第三子层；其中，
    所述第一子层与所述平坦层主体同层制作形成；
    所述第二子层与所述像素界定图案同层制作形成；
    所述第三子层与所述隔垫物图案同层制作形成。
  30. 根据权利要求29所述的阵列基板，其中，所述阵列基板还包括：设置在所述平坦层主体靠近所述衬底基板一侧、且位于所述显示区域与所述绑定区域之间的区域中的有机填充图案；
    所述多层结构还包括：位于所述第一子层靠近所述衬底基板一侧的第四子层；其中，所述第四子层与所述有机填充图案同层制作形成。
  31. 根据权利要求17所述的阵列基板，其中，所述阵列基板还包括：设置在所述衬底基板的封装区域中的有机保护膜层；
    所述绝缘支撑部包括第五子层；其中，所述第五子层与所述有机保护膜层同层制作形成。
  32. 根据权利要求17至31任一项所述的阵列基板，其中，所述衬底基板为柔性衬底基板。
  33. 一种显示装置，其中，包括：
    如权利要求17-32任一项所述的阵列基板；
    IC；其中，
    所述IC包括IC的绑定引脚；所述IC的绑定引脚绑定在所述绑定焊盘上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110989233A (zh) * 2019-12-20 2020-04-10 厦门天马微电子有限公司 显示面板及显示装置

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* Cited by examiner, † Cited by third party
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WO2020133262A1 (zh) * 2018-12-28 2020-07-02 深圳市柔宇科技有限公司 一种改善导电粒子聚集的连接基体、导电结合结构和触控传感器
US11037915B2 (en) * 2019-02-14 2021-06-15 Facebook Technologies, Llc Integrated display devices
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CN111403460A (zh) * 2020-03-27 2020-07-10 武汉华星光电半导体显示技术有限公司 Oled显示面板及显示装置
CN111554202B (zh) * 2020-05-27 2022-08-09 上海中航光电子有限公司 一种显示面板和显示装置
CN113327960B (zh) * 2021-03-12 2024-05-24 京东方科技集团股份有限公司 显示面板及显示装置
WO2024065412A1 (zh) * 2022-09-29 2024-04-04 京东方科技集团股份有限公司 覆晶薄膜及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060109631A (ko) * 2005-04-18 2006-10-23 엘지전자 주식회사 유기 전계 발광 소자
CN104733643A (zh) * 2013-12-19 2015-06-24 昆山国显光电有限公司 一种oled显示装置的绑定结构
CN205318069U (zh) * 2015-12-30 2016-06-15 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN107238962A (zh) * 2017-07-27 2017-10-10 京东方科技集团股份有限公司 一种显示基板的制作方法、显示基板及显示装置
CN107564923A (zh) * 2017-10-13 2018-01-09 京东方科技集团股份有限公司 一种阵列基板及其制备方法、柔性显示装置
CN207303094U (zh) * 2017-10-13 2018-05-01 京东方科技集团股份有限公司 一种阵列基板、柔性显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8424748B2 (en) * 2009-12-21 2013-04-23 Intel Corporation Solder in cavity interconnection technology
US8936967B2 (en) * 2011-03-23 2015-01-20 Intel Corporation Solder in cavity interconnection structures
CN104992945A (zh) * 2015-05-28 2015-10-21 京东方科技集团股份有限公司 显示基板及其制作方法以及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060109631A (ko) * 2005-04-18 2006-10-23 엘지전자 주식회사 유기 전계 발광 소자
CN104733643A (zh) * 2013-12-19 2015-06-24 昆山国显光电有限公司 一种oled显示装置的绑定结构
CN205318069U (zh) * 2015-12-30 2016-06-15 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN107238962A (zh) * 2017-07-27 2017-10-10 京东方科技集团股份有限公司 一种显示基板的制作方法、显示基板及显示装置
CN107564923A (zh) * 2017-10-13 2018-01-09 京东方科技集团股份有限公司 一种阵列基板及其制备方法、柔性显示装置
CN207303094U (zh) * 2017-10-13 2018-05-01 京东方科技集团股份有限公司 一种阵列基板、柔性显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110989233A (zh) * 2019-12-20 2020-04-10 厦门天马微电子有限公司 显示面板及显示装置

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