WO2018235715A1 - モジュールおよびその製造方法 - Google Patents

モジュールおよびその製造方法 Download PDF

Info

Publication number
WO2018235715A1
WO2018235715A1 PCT/JP2018/022700 JP2018022700W WO2018235715A1 WO 2018235715 A1 WO2018235715 A1 WO 2018235715A1 JP 2018022700 W JP2018022700 W JP 2018022700W WO 2018235715 A1 WO2018235715 A1 WO 2018235715A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
resin layer
sealing resin
solder ball
main surface
Prior art date
Application number
PCT/JP2018/022700
Other languages
English (en)
French (fr)
Inventor
喜孝 松川
彰夫 勝部
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201880040581.8A priority Critical patent/CN110832636B/zh
Priority to JP2019525513A priority patent/JP6784330B2/ja
Priority to KR1020217039027A priority patent/KR102374316B1/ko
Priority to KR1020197033134A priority patent/KR102463386B1/ko
Publication of WO2018235715A1 publication Critical patent/WO2018235715A1/ja
Priority to US16/716,647 priority patent/US11276631B2/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499Material of the matrix
    • H01L2224/81594Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/815 - H01L2224/81591
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8193Reshaping
    • H01L2224/81947Reshaping by mechanical means, e.g. "pull-and-cut", pressing, stamping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/81948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Definitions

  • the present invention relates to a module and a method of manufacturing the same.
  • the module 100 described in Patent Document 1 includes an electrode pad 102 and an electrode pad 102 on a semiconductor chip 103 having an electrode pad 102 formed on the main surface of a semiconductor substrate 101.
  • a substantially spherical conductive ball 105 electrically connected is formed.
  • a resin layer 106 is formed on the semiconductor chip 103 so that the top of the conductive ball 105 is exposed, and an external connection terminal 107 made of a solder ball is provided on the top of the conductive ball 105 exposed from the resin layer 106. ing.
  • the conductive ball 105 is placed at a predetermined position of the wire 104 to form a support for connecting the wire 104 and the external connection terminal 107 in the resin layer 106.
  • a support of the desired height in a very short time as compared with the formation of the support by the plating method.
  • Patent No. 4626008 see paragraphs 0023 to 0025, FIG. 6, etc.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a module in which an external connection terminal without a constriction shape is formed of solder balls to improve reliability and mechanical strength.
  • a module according to the present invention comprises a substrate, a connection electrode provided on one main surface of the substrate, a first component mounted on the one main surface of the substrate, and the substrate Provided on the one main surface of the substrate and an external connection terminal consisting of solder balls disposed on the one main surface of the substrate via the connection electrode, and sealing the one main surface of the substrate and the first component A portion of the external connection terminal is exposed from the surface of the sealing resin layer opposite to the opposite surface to the one main surface of the substrate, and the external connection terminal is The height of the substrate from the one main surface is higher than the height of the sealing resin layer from the one main surface of the substrate, and there is a gap between the external connection terminal and the sealing resin layer.
  • An external connection terminal of the sealing resin layer surrounding the external connection terminal; Facing surface is characterized in that a curved curvilinear in the one main surface perpendicular cross-section of the substrate.
  • the external connection terminal is formed of the solder ball and has a shape without a constriction, so that the mechanical strength and reliability of the external connection terminal can be improved.
  • the external connection terminal is formed of solder, it is possible to realize high precision of the position of the external connection terminal by the self alignment effect at the time of reflow.
  • the solder balls are exposed and protruded from the sealing resin layer, it is not necessary to plate the terminal portions, and the manufacturing cost can be suppressed.
  • the opposing surface of the sealing resin layer surrounding the external connection terminal facing the external connection terminal is a curved surface forming a curve in a cross section perpendicular to one main surface of the substrate, whereby the opposing surface is a straight line in the cross section. Since the load for the stress in the horizontal direction with respect to the substrate is dispersed as compared with the case of the curved surface, the occurrence of peeling can be suppressed.
  • the external connection terminal may be formed by one solder ball.
  • the solder balls since the solder balls have a shape projecting in a circle from the sealing resin layer, they can be used as bumps when connecting to the mother substrate as they are.
  • the external connection terminal may not be in contact with the sealing resin layer at all.
  • the stress due to the difference between the thermal expansion coefficient of the solder and the resin can be reduced, and the generation of the crack in the solder ball can be suppressed. .
  • a part of the first component may be exposed from the opposite surface of the sealing resin layer. In this case, a reduction in the height of the module can be realized.
  • the surface exposed from the opposite surface of the sealing resin layer of the first component may be flush with the opposite surface of the sealing resin layer. In this case, a reduction in the height of the module can be realized.
  • the second component may be mounted on the other main surface of the substrate.
  • the mounting area can be increased by mounting the component also on the other main surface of the substrate, and the degree of freedom in design can be improved.
  • a step of laminating a sealing resin layer for sealing the component and the solder ball on the one main surface of the substrate, and the solder ball is opposed to the one main surface of the sealing resin layer Polishing the opposite surface of the sealing resin layer and a part of the solder ball so as to be exposed from the surface opposite to the surface; and the height of the solder ball from the one main surface of the substrate And reheating the substrate in a reflow furnace such that the height of the sealing resin layer is higher than the height of the sealing resin layer from the one main surface of the substrate.
  • solder balls are deformed into spherical shapes by surface tension and a shape protruding from the polished surface of the sealing resin layer. Therefore, it is not necessary to form a bump for connecting to the mother substrate again. Further, since the solder balls are mounted as the external connection terminals, there is no need to perform plating, so that abnormal plating does not occur, and a module with high reliability and mechanical strength can be manufactured.
  • a module with high reliability and mechanical strength can be provided, and a reduction in height of the module can be realized.
  • FIG. 1 It is a sectional view of a module concerning one embodiment of the present invention. It is an expanded sectional view which shows the example of the mounting method of the solder ball of the module of FIG. It is a figure which shows the manufacturing process of the module of FIG. It is a figure which shows the manufacturing process of the module of FIG. It is a figure which shows the process of mounting the module of FIG. 1 in a motherboard. It is a figure for demonstrating the shape of the sealing resin layer of solder ball periphery. It is a figure which shows the conventional module.
  • FIG. 1 is a cross-sectional view of the module 1 and FIG. 2 is an enlarged cross-sectional view showing an example of a method of mounting solder balls of the module 1.
  • the module 1 is mounted on a substrate 2, a plurality of components 3 mounted on the upper surface 2a of the substrate 2, a component 4 mounted on the lower surface 2b, and the lower surface 2b.
  • a plurality of solder balls 5 serving as external connection terminals, sealing resin layers 6 a and 6 b stacked on the upper surface 2 a and the lower surface 2 b of the substrate 2 and sealing the substrate 2, the components 3 and the components 4 And a shield film 7 covering the upper surface, and mounted on a mother substrate (not shown) via solder balls 5.
  • the substrate 2 is made of, for example, low-temperature co-fired ceramic, glass epoxy resin, etc., and via conductors (not shown) and various wiring electrodes (not shown) are formed inside. Further, on the upper surface 2 a and the lower surface 2 b of the substrate 2, connection electrodes 8 for connecting to the plurality of components 3, the components 4 and the solder balls 5 are formed.
  • the substrate 2 may have either a single layer structure or a multilayer structure.
  • the component 3 (corresponding to the “second component” of the present invention) is formed of, for example, a semiconductor element made of Si or the like, and an electronic component such as a chip capacitor, a chip inductor, a chip resistor, or a chip antenna.
  • the component 3 is sealed by the sealing resin layer 6a.
  • the component 4 (corresponding to the “first component” in the present invention) is a semiconductor component such as a semiconductor element formed of Si or the like, and is mounted on the lower surface 2 b of the substrate 2.
  • the component 4 is sealed by the sealing resin layer 6b, but a part thereof corresponds to the surface 60b of the sealing resin layer 6b (the "surface opposite to the surface facing the one main surface” of the present invention). It may be exposed from).
  • the solder balls 5 are mounted on the lower surface 2 b (corresponding to the “one main surface” of the present invention) of the substrate 2 and connected to the connection electrodes 8 on the lower surface 2 b.
  • the solder ball 5 is partly exposed and protruded from the surface 60b of the sealing resin layer 6b, and the module body 1 is connected to the mother substrate in the portion exposed from the surface 60b of the sealing resin layer 6b. It functions as an external connection terminal.
  • the height of the solder ball 5 and the sealing resin layer 6b from the lower surface 2b of the substrate 2 is higher than the latter, and a portion of the solder ball 5 protrudes from the surface 60b of the sealing resin layer 6b.
  • the module 1 can be connected to the mother substrate by connecting the protruding portions of the solder balls 5 to the electrodes of the mother substrate as bumps.
  • a gap 9 (corresponding to the "gap" in the present invention) between the solder ball 5 and the sealing resin layer 6b. That is, there is a portion where the solder ball 5 and the sealing resin layer 6b are not in contact with each other.
  • connection electrode 8 is electrically connected to the wiring layer 11.
  • the opposing surface 61 b of the sealing resin layer facing the outer peripheral surface 50 a of the solder ball 5 is a curved surface that forms a curve in a cross section perpendicular to the lower surface 2 b of the substrate 2.
  • the opposing surface 61b has a shape in which a part of the sphere is hollowed out of the sealing resin layer 6b.
  • the sealing resin layer 6 a is provided on the upper surface 2 a of the substrate 2 so as to cover the upper surface 2 a of the substrate 2 and the respective components 3.
  • the sealing resin layer 6 b is provided on the lower surface 2 b of the substrate 2 so as to cover the component 4. Further, as shown in FIGS. 2A to 2C, the solder balls 5 are surrounded by the sealing resin layer 6b.
  • the sealing resin layers 6a and 6b can be formed of a resin generally employed as a sealing resin such as an epoxy resin containing a silica filler. Alumina fillers can also be used because of their high thermal conductivity.
  • the shield film 7 is for shielding various electrodes in the substrate 2 and electromagnetic waves from the outside with respect to the respective components 3 and 4, and the side surface and the upper surface (surface 60 a of the sealing resin layer 6 a) of the module 1 It is arranged to cover. Further, the shield film 7 can be formed in a multilayer structure having an adhesive film, a conductive film laminated on the adhesive film, and a protective film laminated on the conductive film.
  • a substrate 2 on which components can be mounted is prepared on the upper surface 2a and the lower surface 2b, solder paste is applied to the lower surface 2b of the substrate 2, and connection electrodes 8 are printed.
  • the amount of the applied solder paste may be increased, and the solder ball 5 may be formed utilizing the fact that the solder paste becomes ball-like when heated later in a reflow furnace. .
  • heat treatment is performed to fix the component 4 and the solder ball 5 on the lower surface 2 b of the substrate 2. Flux cleaning may be performed after the heat treatment in the reflow furnace.
  • the sealing resin layer 6b is laminated on the lower surface 2b of the substrate 2 so as to cover the component 4 and the solder ball 5.
  • the surface 60b of the sealing resin layer 6b is polished until the solder balls 5 are exposed.
  • the polishing amount of the sealing resin layer 6b is adjusted so that parts other than the solder balls 5 are not exposed.
  • the height of the sealing resin layer 6b may be adjusted so that a part of the component 4 is exposed from the surface 60b of the sealing resin layer 6b.
  • solder paste is applied to the upper surface 2 a of the substrate 2 to print the connection electrodes 8, and the components 3 are mounted. Thereafter, a flux is applied to the exposed surfaces 5a of the solder balls 5 on the surface 60b of the sealing resin layer 6b, and heat treatment is performed in a reflow furnace. Flux cleaning may be performed after the heat treatment in the reflow furnace.
  • each component 3 is fixed to the substrate 2 as shown in FIG. 3E, and the solder ball 5 protrudes from the surface 60b of the sealing resin layer 6b by surface tension of the solder. It becomes a shape that
  • the sealing resin layer 6a is laminated on the upper surface 2a of the substrate 2 so as to cover the respective components 3.
  • the module 1 is completed by depositing the shield film 7 using a sputtering apparatus or a vacuum evaporation apparatus.
  • FIG. 5A is a view showing a state after the surface 60b of the sealing resin layer 6b is polished to expose the solder balls 5 from the surface 60b of the sealing resin layer 6b.
  • the surface 60 b of the sealing resin layer 6 b and the exposed surface 5 a of the solder ball 5 form the same plane.
  • the solder ball 5 becomes substantially spherical due to the surface tension of the solder and the sealing resin It protrudes from the surface 60b of the layer 6b.
  • void 9 which is a portion where the solder ball 5 and the sealing resin layer 6b are not in contact with each other.
  • the portion protruding from the surface 60b of the solder ball 5 can be mounted on the mother substrate 12 as it is as a solder bump.
  • the external connection terminal of the module 1 is formed by one solder ball 5, it has a shape without a constriction, and the reliability and the mechanical strength can be improved. Further, by using the solder balls 5 for the external connection terminals, it is possible to realize high precision of the positions of the external connection terminals by the self alignment effect when the heat treatment is performed in the reflow furnace. Moreover, since a part of solder ball 5 is exposed from surface 60b of sealing resin layer 6b and a part of solder ball 5 protrudes from surface 60b of the sealing resin layer, the solder ball is not plated. 5 can be used as an external connection terminal.
  • the presence of the air gap 9 between the solder ball 5 and the sealing resin layer 6 b makes it possible to reduce the stress due to the difference in thermal expansion coefficient between the solder and the resin, and a crack occurs in the solder ball 5. Can be suppressed.
  • the height of the module 1 can be reduced by polishing the surface 60b of the sealing resin layer 6b until the component 4 is exposed.
  • a flux is applied to the exposed surfaces 5a of the solder balls 5 and heat treatment is performed in a reflow furnace. It becomes spherical and has a shape protruding from the surface 60b, and can be used as a bump for mounting on a mother substrate as it is.
  • the opposing surface of the sealing resin layer facing the outer peripheral surface of the external connection terminal is a curved surface forming a curve in a cross section perpendicular to one main surface of the substrate, whereby the opposing surface is a curved surface forming a straight line in the cross section.
  • the opposing surface 61b1 is a straight line in the cross section, the cross-sectional area of the sealing resin layer 6b1 linearly decreases between A1-B1, and the sealing resin layer 6b1 between B1-C. The cross section does not decrease.
  • the cross-sectional area reduction rate of the sealing resin layer 6b1 changes rapidly with B1 as a boundary, so when stress is applied in the horizontal direction of the module 1, the load is concentrated on B1 and sealing is performed from the substrate 2 Peeling of the resin layer 6b1 is likely to occur.
  • the opposing surface 61b2 has a curved line in the cross section as in the embodiment described above, the decrease in the cross sectional area of the sealing resin layer 6b2 is not linear between A2 and B2, and the cross sectional area decreases from A2 to B2. Since the rate gradually decreases, there is no abrupt change in the cross-sectional area reduction rate at B2. For this reason, concentration of the load in B2 can be avoided and generation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

モジュール1は、基板2と、基板2の上面2aに実装された複数の部品3と、下面2bに実装された部品4と、下面2bに実装され、外部接続端子として機能する半田ボール5と、基板2の上面2aおよび上面2bに積層された封止樹脂層6a、6bと、モジュール1の側面と上面を覆うシールド膜7とを備える。半田ボール5は、封止樹脂層6bの表面60bから一部が露出しており、露出した部分が封止樹脂層6bから突出した形状となっている。半田ボール5の突出部分を外部接続端子としてマザー基板の電極と接続することにより、モジュール1をマザー基板に接続することができる。半田ボール5と封止樹脂層6bとの間には空隙部9があり、半田と樹脂との熱膨張係数の差によるストレスを軽減して、半田ボール5にクラックが発生することを抑制することができる。

Description

モジュールおよびその製造方法
 本発明は、モジュールとその製造方法に関する。
 従来、基板に略球状の導電性支柱を配置することにより外部接続端子を形成する技術が知られている。例えば、図7に示すように、特許文献1に記載のモジュール100は、半導体基板101の主面に形成されている電極パッド102を有する半導体チップ103上に、配線104を介して電極パッド102と電気的に接続されている略球状の導電性ボール105が形成されている。半導体チップ103上には、導電性ボール105の頂部が露出するように樹脂層106が形成され、樹脂層106から露出した導電性ボール105の頂部には半田ボールからなる外部接続端子107が設けられている。このような構成のモジュール100では、導電性ボール105を配線104の所定の位置に載置することにより、樹脂層106内に配線104と外部接続端子107とを接続するための支柱を形成することができ、めっき法による支柱の形成に比べて極めて短時間に目的の高さの支柱を形成することができる。
特許第4626008号公報(段落0023~0025、図6など参照)
 しかしながら、特許文献1のように、導電性ボール105の頂部に外部接続端子107を設ける場合、マザー基板に実装する際に、導電性ボール105と外部接続端子107との接続部分がくびれた形状となるため、信頼性や機械的強度が低下するという問題がある。また、導電性ボール105の頂部は樹脂層106と同一平面上にあり、マザー基板と接続する際のバンプとして、半田ボールからなる外部接続端子107を設ける必要があり、製造工程の数が増加するという課題や、樹脂層106に半田ボールからなる外部接続端子107を載せるため低背化が難しいという課題がある。
 本発明は、上記した課題に鑑みてなされたものであり、くびれ形状のない外部接続端子を半田ボールにより形成し、信頼性や機械的強度を向上させたモジュールを提供することを目的とする。
 上記した目的を達成するために、本発明のモジュールは、基板と、前記基板の一方主面に設けられた接続電極と、前記基板の前記一方主面に実装された第1部品と、前記基板の前記一方主面に前記接続電極を介して配設された半田ボールからなる外部接続端子と、前記基板の前記一方主面に設けられ、前記基板の一方主面および前記第1部品を封止する封止樹脂層とを備え、前記外部接続端子の一部は、前記封止樹脂層の前記基板の前記一方主面との対向面と反対側の面から露出し、前記外部接続端子の前記基板の前記一方主面からの高さは、前記封止樹脂層の前記基板の前記一方主面からの高さよりも高く、前記外部接続端子と前記封止樹脂層との間には隙間があり、前記外部接続端子を囲っている前記封止樹脂層の前記外部接続端子との対向面は、前記基板の前記一方主面と垂直な断面において曲線をなす曲面であることを特徴としている。
 この構成によると、外部接続端子が半田ボールにより形成されており、くびれのない形状となるため、外部接続端子の機械的強度や信頼性を向上させることができる。また、半田により外部接続端子を形成するため、リフロー時のセルフアライメント効果により外部接続端子の位置の高精度化を実現することができる。また、半田ボールが封止樹脂層より露出して突出した形状となっているため、端子部にめっきを施す必要がなく、製造コストを抑制することができる。
 また、外部接続端子を囲っている封止樹脂層の前記外部接続端子との対向面が、基板の一方主面と垂直な断面において曲線をなす曲面であることにより、対向面が断面において直線をなす曲面である場合と比較して、基板に対する水平方向への応力に対する負荷が分散されるため、剥離の発生を抑制することができる。
 また、前記外部接続端子は、1つの半田ボールにより形成されていてもよい。この場合、半田ボールが封止樹脂層から丸く突出した形状となるため、このままマザー基板へ接続する際のバンプとして利用することができる。
 また、前記外部接続端子と前記封止樹脂層とが全く接していなくてもよい。この場合、半田ボールと封止樹脂層とが接していないことにより、半田と樹脂との熱膨張係数の差によるストレスを軽減することができ、半田ボールへのクラックの発生を抑制することができる。
 また、前記第1部品の一部は、前記封止樹脂層の前記反対側の面から露出していてもよい。この場合、モジュールの低背化を実現することができる。
 前記第1部品の前記封止樹脂層の前記反対側の面から露出している面は、前記封止樹脂層の前記反対側の面と同一平面上にあってもよい。この場合、モジュールの低背化を実現することができる。
 また、前記基板の他方主面に第2部品が実装されていてもよい。この場合、基板の他方主面にも部品を実装することで実装面積を広くすることができ、設計自由度を向上させることができる。
 また、本発明のモジュールの製造方法は、基板の一方主面の実装電極に部品と半田ボールを搭載する工程と、前記基板をリフロー炉で加熱し、前記部品と前記半田ボールを前記基板に固定する工程と、前記部品と前記半田ボールとを封止する封止樹脂層を前記基板の前記一方主面に積層する工程と、前記半田ボールが前記封止樹脂層の前記一方主面との対向面と反対側の面から露出するように、前記封止樹脂層の前記反対側の面および前記半田ボールの一部を研磨する工程と、前記半田ボールの前記基板の前記一方主面からの高さが前記封止樹脂層の前記基板の前記一方主面からの高さよりも高くなるように、前記基板をリフロー炉で再加熱する工程とを備えることを特徴としている。
 この場合、封止樹脂層を研磨して半田ボールを露出させた後、リフロー炉で加熱処理を行うと、半田ボールが表面張力により球状に変形して封止樹脂層の研磨面より突出した形状となり、半田ボールをバンプとして利用することができる。このため、改めてマザー基板へ接続するためのバンプを形成する必要がない。また、半田ボールを外部接続端子として搭載するので、めっきを施す必要がないため、めっき異常析出が発生せず、信頼性や機械的強度の高いモジュールを製造することができる。
 本発明によれば、信頼性や機械的強度の高いモジュールを提供することができ、また、モジュールの低背化を実現することができる。
本発明の一実施形態に係るモジュールの断面図である。 図1のモジュールの半田ボールの実装方法の例を示す拡大断面図である。 図1のモジュールの製造工程を示す図である。 図1のモジュールの製造工程を示す図である。 図1のモジュールをマザー基板に実装する工程を示す図である。 半田ボール周辺の封止樹脂層の形状を説明するための図である。 従来のモジュールを示す図である。
 本発明の一実施形態に係るモジュール1について、図1および図2を参照して説明する。なお、図1はモジュール1の断面図、図2はモジュール1の半田ボールの実装方法の例を示す拡大断面図である。
 この実施形態に係るモジュール1は、図1に示すように、基板2と該基板2の上面2aに実装された複数の部品3と、下面2bに実装された部品4と、下面2bに搭載され外部接続端子となる複数の半田ボール5と、基板2の上面2aおよび下面2bに積層され、基板2、各部品3および部品4を封止する封止樹脂層6a、6bと、モジュール1の側面および上面を被覆するシールド膜7とを備え、半田ボール5を介してマザー基板(図示省略)に搭載される。
 基板2は、例えば、低温同時焼成セラミックスやガラスエポキシ樹脂などで形成され、内部にビア導体(図示省略)や各種の配線電極(図示省略)が形成される。また、基板2の上面2aおよび下面2bには、複数の部品3、部品4および半田ボール5と接続するための接続電極8が形成される。なお、基板2は単層構造および多層構造のいずれであってもよい。
 部品3(本発明の「第2部品」に相当する)は、例えば、Si等で形成された半導体素子や、チップコンデンサ、チップインダクタ、チップ抵抗、チップアンテナなどの電子部品で構成される。部品3は封止樹脂層6aにより封止されている。
 部品4(本発明の「第1部品」に相当する)は、Si等で形成された半導体素子などの半導体部品であり、基板2の下面2bに実装されている。なお、部品4は封止樹脂層6bにより封止されているが、一部が封止樹脂層6bの表面60b(本発明の「一方主面との対向面と反対側の面」に相当する)から露出していてもよい。
 半田ボール5は、基板2の下面2b(本発明の「一方主面」に相当する)に実装され、下面2bの接続電極8に接続される。また、半田ボール5は、封止樹脂層6bの表面60bから一部が露出して突出しており、封止樹脂層6bの表面60bから露出している部分は、モジュール1をマザー基板に接続する際の外部接続端子として機能する。換言すると、半田ボール5および封止樹脂層6bそれぞれの基板2の下面2bからの高さは、前者が後者より高く、半田ボール5の一部が封止樹脂層6bの表面60bから突出した形状となっており、半田ボール5の突出部分をバンプとしてマザー基板の電極と接続することにより、モジュール1をマザー基板に接続することができる。また、半田ボール5と封止樹脂層6bとの間には空隙部9(本発明の「隙間」に相当する)がある。すなわち、半田ボール5と封止樹脂層6bとが接していない部分がある。
 また、半田ボール5の実装方法には、図2(a)に示すような、接続電極8の周縁部がソルダーレジスト10により覆われているオーバーレジスト構造や、図2(b)に示すような、接続電極8とソルダーレジスト10との間にクリアランスがある、すなわち、接続電極8とソルダーレジスト10とが接触していないクリアランスレジスト構造、図2(c)に示すような構造などがある。また、図2(a)~(c)に示すように、接続電極8は配線層11と電気的に接続されている。また、半田ボール5の外周面50aと対向する封止樹脂層の対向面61bは、基板2の下面2bと垂直な断面において曲線をなす曲面である。換言すれば、対向面61bは封止樹脂層6bから球体の一部をくり抜いたような形状をしている。
 封止樹脂層6aは、基板2の上面2aおよび各部品3を被覆するように基板2の上面2aに設けられる。また、封止樹脂層6bは、基板2の下面2b、部品4を被覆するように基板2の下面2bに設けられる。また、図2(a)~(c)に示すように、半田ボール5は封止樹脂層6bに囲まれている。封止樹脂層6a、6bは、シリカフィラ入りのエポキシ樹脂等の封止樹脂として一般的に採用される樹脂で形成することができる。また、高熱伝導のため、アルミナフィラを使用することもできる。
 シールド膜7は、基板2内の各種電極や、各部品3、4に対する外部からの電磁波を遮蔽するためのものであり、モジュール1の側面と上面(封止樹脂層6aの表面60a)とを被覆するように配置される。また、シールド膜7は、密着膜と、密着膜に積層された導電膜と、導電膜に積層された保護膜とを有する多層構造で形成することができる。
 (モジュールの製造方法)
 次に、本発明のモジュール1の製造方法の一例について、図3および図4を参照して説明する。
 まず、図3(a)に示すように、その上面2aおよび下面2bに部品を実装可能な基板2を用意し、基板2の下面2bに半田ペーストを塗布して接続電極8を印刷して、部品4および半田ボール5を実装する。なお、半田ボール5を実装する代わりに、半田ペーストの塗布量を多くして、後にリフロー炉で加熱する際に半田ペーストがボール状になることを利用して半田ボール5を形成してもよい。その後、リフロー炉に投入して加熱処理を行い、基板2の下面2bに部品4と半田ボール5を固定する。リフロー炉での加熱処理の後にフラックス洗浄を行ってもよい。
 次に、図3(b)に示すように、部品4と半田ボール5を被覆するように基板2の下面2bに封止樹脂層6bを積層する。
 次に、図3(c)に示すように、封止樹脂層6bの表面60bを、半田ボール5が露出するまで研磨する。この時、半田ボール5以外の部品が露出しないように封止樹脂層6bの研磨量を調節する。なお、封止樹脂層6bの表面60bから部品4の一部が露出するように封止樹脂層6bの高さを調整してもよい。
 次に、図3(d)に示すように、基板2の上面2aに半田ペーストを塗布して接続電極8を印刷し、各部品3を実装する。その後、封止樹脂層6bの表面60bの半田ボール5の露出面5aにフラックスを塗布して、リフロー炉にて加熱処理を行う。リフロー炉での加熱処理の後にフラックス洗浄を行ってもよい。
 リフロー炉で加熱処理を行うと、図3(e)に示すように、各部品3が基板2に固定され、また、半田の表面張力により半田ボール5が封止樹脂層6bの表面60bから突出した形状となる。
 次に、図4(a)に示すように、各部品3を被覆するように基板2の上面2aに封止樹脂層6aを積層する。
 次に、図4(b)に示すように、スパッタ装置や真空蒸着装置を用いてシールド膜7を成膜することにより、モジュール1が完成する。
 なお、基板2の上面2aに各部品3を実装した後にリフロー炉で加熱処理を行って各部品3を基板2に固定した後、封止樹脂層6bの表面60bを研磨して、露出面5aにフラックスを塗布し、再度リフロー炉で加熱処理を行ってもよい。
 ここで、モジュール1の表面60bの研磨からマザー基板への実装までの一連の工程を、図5を参照して説明する。なお、図5では、シールド膜7が図示省略されている。
 図5(a)は、封止樹脂層6bの表面60bを研磨して半田ボール5を封止樹脂層6bの表面60bから露出させた後を示す図である。このとき、封止樹脂層6bの表面60bと半田ボール5の露出面5aとは同一平面を形成している。半田ボール5の露出面5aにフラックスを塗布し、リフロー炉で加熱処理を行うと、図5(b)に示すように、半田の表面張力により、半田ボール5は、略球状になり封止樹脂層6bの表面60bから突出した形状となる。このとき、半田ボール5と封止樹脂層6bとが接触していない部分である空隙部9ができる。図5(c)に示すように、半田ボール5の表面60bから突出した部分をそのまま半田バンプとして利用して、マザー基板12へ実装することができる。
 したがって、上記した実施形態によれば、モジュール1の外部接続端子は1つの半田ボール5により形成されているためくびれのない形状となり、信頼性や機械的強度を向上させることができる。また、外部接続端子に半田ボール5を使用することで、リフロー炉で加熱処理を行う際のセルフアライメント効果により、外部接続端子の位置の高精度化を実現することができる。また、封止樹脂層6bの表面60bから半田ボール5の一部が露出し、また、半田ボール5の一部が封止樹脂層の表面60bから突出しているため、めっきを施すことなく半田ボール5を外部接続端子として使用することができる。さらに、外部接続端子に金属ピンを使用した場合と比べて、めっき処理が不要であるため封止樹脂層6bの表面60bを研磨する際の研磨残渣によるめっき異常析出が発生しない。また、半田ボール5と封止樹脂層6bとの間に空隙部9があることにより、半田と樹脂との熱膨張係数の差によるストレスを軽減することができ、半田ボール5にクラックが発生するのを抑制することができる。
 また、封止樹脂層6bの表面60bを部品4が露出するまで研磨することにより、モジュール1の低背化が可能である。
 また、封止樹脂層6bの表面60bを半田ボール5が露出するまで研磨した後、半田ボール5の露出面5aにフラックスを塗布してリフロー炉で加熱処理を行うことにより、半田ボール5が略球状となって表面60bから突出した形状となり、このままマザー基板に実装する際のバンプとして利用することができる。
 また、外部接続端子の外周面と対向する封止樹脂層の対向面が、基板の一方主面と垂直な断面において曲線をなす曲面であることにより、対向面が断面において直線をなす曲面である場合と比較して、基板に対する水平方向への応力に対する負荷が分散されるため、剥離の発生を抑制することができる。図6に示すように、断面において対向面61b1が直線をなす場合、A1-B1間において封止樹脂層6b1の断面積が線型的に減少し、B1-C間においては封止樹脂層6b1の断面積は減少しない。このとき、B1を境界として封止樹脂層6b1の断面積減少率が急激に変化するため、モジュール1の水平方向への応力がかかった場合に、B1に負荷が集中して基板2から封止樹脂層6b1の剥離が発生しやすい。一方、上記した実施形態のように、断面において対向面61b2が曲線をなす場合、A2-B2間において封止樹脂層6b2の断面積の減少は線形ではなく、A2からB2に向かうに従い断面積減少率が徐々に小さくなるため、B2における急激な断面積減少率の変化がない。このため、B2における負荷の集中を回避することができ、基板2からの封止樹脂層6b2の剥離の発生を抑制することができる。
 なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能である。
 また、本発明は、種々のモジュールに適用することができる。
 1    モジュール
 2    基板
 3    部品(第1部品)
 4    部品(第2部品)
 5    半田ボール(外部接続端子)
 6a、6b    封止樹脂層
 61b    対向面
 8    接続電極
 

Claims (7)

  1.  基板と、
     前記基板の一方主面に設けられた接続電極と、
     前記基板の前記一方主面に実装された第1部品と、
     前記基板の前記一方主面に前記接続電極を介して配設された半田ボールからなる外部接続端子と、
     前記基板の前記一方主面に設けられ、前記基板の前記一方主面および前記第1部品を封止する封止樹脂層とを備え、
     前記外部接続端子の一部は、前記封止樹脂層の前記基板の前記一方主面との対向面と反対側の面から露出し、
     前記外部接続端子の前記基板の前記一方主面からの高さは、前記封止樹脂層の前記基板の前記一方主面からの高さよりも高く、
     前記外部接続端子と前記封止樹脂層との間には隙間があり、
      前記外部接続端子を囲っている前記封止樹脂層の前記外部接続端子との対向面は、前記基板の前記一方主面と垂直な断面において曲線をなす曲面である
     ことを特徴とするモジュール。
  2.  前記外部接続端子は、1つの半田ボールにより形成されていることを特徴とする請求項1に記載のモジュール。
  3.  前記外部接続端子と前記封止樹脂層とが全く接していないことを特徴とする請求項1または2のいずれかに記載のモジュール。
  4.  前記第1部品の一部は、前記封止樹脂層の前記反対側の面から露出していることを特徴とする請求項1ないし3のいずれかに記載のモジュール。
  5.  前記第1部品の前記封止樹脂層の前記反対側の面から露出している面は、前記封止樹脂層の前記反対側の面と同一平面上にあることを特徴とする請求項4に記載のモジュール。
  6.  前記基板の他方主面に第2部品が実装されていることを特徴とする請求項1ないし5のいずれかに記載のモジュール。
  7.  基板の一方主面の実装電極に部品と半田ボールを搭載する工程と、
     前記基板をリフロー炉で加熱し、前記部品と前記半田ボールを前記基板に固定する工程と、
     前記基板、前記部品および前記半田ボールを封止する封止樹脂層を前記基板の前記一方主面に設ける工程と、
     前記半田ボールが前記封止樹脂層の前記一方主面との対向面と反対側の面から露出するように、少なくとも前記封止樹脂層の前記反対側の面および前記半田ボールの一部を研磨する工程と、
     前記半田ボールの前記基板の前記一方主面からの高さが前記封止樹脂層の前記基板の前記一方主面からの高さよりも高くなるように、前記基板をリフロー炉で再加熱する工程とを備える
     ことを特徴とするモジュールの製造方法。
     
PCT/JP2018/022700 2017-06-20 2018-06-14 モジュールおよびその製造方法 WO2018235715A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201880040581.8A CN110832636B (zh) 2017-06-20 2018-06-14 模块及其制造方法
JP2019525513A JP6784330B2 (ja) 2017-06-20 2018-06-14 モジュールおよびその製造方法
KR1020217039027A KR102374316B1 (ko) 2017-06-20 2018-06-14 모듈 및 그 제조 방법
KR1020197033134A KR102463386B1 (ko) 2017-06-20 2018-06-14 모듈 및 그 제조 방법
US16/716,647 US11276631B2 (en) 2017-06-20 2019-12-17 Module and method of manufacturing module

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-120160 2017-06-20
JP2017120160 2017-06-20

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/716,647 Continuation US11276631B2 (en) 2017-06-20 2019-12-17 Module and method of manufacturing module

Publications (1)

Publication Number Publication Date
WO2018235715A1 true WO2018235715A1 (ja) 2018-12-27

Family

ID=64735580

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/022700 WO2018235715A1 (ja) 2017-06-20 2018-06-14 モジュールおよびその製造方法

Country Status (5)

Country Link
US (1) US11276631B2 (ja)
JP (1) JP6784330B2 (ja)
KR (2) KR102463386B1 (ja)
CN (1) CN110832636B (ja)
WO (1) WO2018235715A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021005674A (ja) * 2019-06-27 2021-01-14 株式会社村田製作所 電子部品モジュール、電子部品ユニット、および、電子部品モジュールの製造方法
WO2021085180A1 (ja) * 2019-10-30 2021-05-06 株式会社村田製作所 電子部品モジュール、および、電子部品モジュールの製造方法
WO2021090694A1 (ja) * 2019-11-07 2021-05-14 株式会社村田製作所 モジュール
US20220005773A1 (en) * 2020-07-01 2022-01-06 Sandisk Technologies Llc Semiconductor structure containing pre-polymerized protective layer and method of making thereof
WO2022075417A1 (ja) * 2020-10-08 2022-04-14 株式会社村田製作所 基板構造体、モジュール、基板構造体の製造方法、および、モジュールの製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10861779B2 (en) 2018-06-22 2020-12-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an electrical contact with a high-melting-point part and method of manufacturing the same
US20200312733A1 (en) * 2019-03-29 2020-10-01 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US20220066036A1 (en) * 2020-08-25 2022-03-03 Lumentum Operations Llc Package for a time of flight device
CN112930589B (zh) * 2021-01-26 2024-05-10 长江存储科技有限责任公司 衬底结构及其制造和封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040868A (ja) * 1998-07-22 2000-02-08 Ibiden Co Ltd プリント配線板
JP2015216219A (ja) * 2014-05-09 2015-12-03 マイクロン テクノロジー, インク. 半導体装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4626008Y1 (ja) 1967-12-23 1971-09-07
US20070102827A1 (en) * 1997-12-08 2007-05-10 3M Innovative Properties Company Solvent Assisted Burnishing of Pre-Underfilled Solder-Bumped Wafers for Flipchip Bonding
JP2000040711A (ja) * 1998-07-23 2000-02-08 Sony Corp 樹脂封止型半導体装置とその製造方法
JP4626008B2 (ja) 2000-04-04 2011-02-02 日本テキサス・インスツルメンツ株式会社 半導体装置
JP4105202B2 (ja) * 2006-09-26 2008-06-25 新光電気工業株式会社 半導体装置の製造方法
US20100072600A1 (en) * 2008-09-22 2010-03-25 Texas Instrument Incorporated Fine-pitch oblong solder connections for stacking multi-chip packages
KR101056747B1 (ko) * 2009-04-14 2011-08-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP5421863B2 (ja) * 2010-06-28 2014-02-19 新光電気工業株式会社 半導体パッケージの製造方法
KR20130084866A (ko) * 2012-01-18 2013-07-26 삼성전자주식회사 양면이 몰딩된 반도체 패키지
KR102067155B1 (ko) * 2013-06-03 2020-01-16 삼성전자주식회사 연결단자를 갖는 반도체 장치 및 그의 제조방법
KR102063794B1 (ko) 2013-06-19 2020-01-08 삼성전자 주식회사 적층형 반도체 패키지
KR102108087B1 (ko) * 2013-07-11 2020-05-08 삼성전자주식회사 반도체 패키지
KR102229202B1 (ko) * 2013-11-07 2021-03-17 삼성전자주식회사 트렌치 형태의 오프닝을 갖는 반도체 패키지 및 그 제조방법
KR102157551B1 (ko) * 2013-11-08 2020-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9559064B2 (en) * 2013-12-04 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in package-on-package structures
US9613933B2 (en) * 2014-03-05 2017-04-04 Intel Corporation Package structure to enhance yield of TMI interconnections
KR102457119B1 (ko) * 2015-09-14 2022-10-24 삼성전자주식회사 반도체 패키지의 제조 방법
US10256173B2 (en) * 2016-02-22 2019-04-09 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
KR101824726B1 (ko) * 2017-02-23 2018-02-01 앰코 테크놀로지 코리아 주식회사 반도체 패키지

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040868A (ja) * 1998-07-22 2000-02-08 Ibiden Co Ltd プリント配線板
JP2015216219A (ja) * 2014-05-09 2015-12-03 マイクロン テクノロジー, インク. 半導体装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021005674A (ja) * 2019-06-27 2021-01-14 株式会社村田製作所 電子部品モジュール、電子部品ユニット、および、電子部品モジュールの製造方法
US11317541B2 (en) 2019-06-27 2022-04-26 Murata Manufacturing Co., Ltd. Electronic component module, electronic component unit, and method for manufacturing electronic component module
JP7124795B2 (ja) 2019-06-27 2022-08-24 株式会社村田製作所 電子部品モジュール、電子部品ユニット、および、電子部品モジュールの製造方法
WO2021085180A1 (ja) * 2019-10-30 2021-05-06 株式会社村田製作所 電子部品モジュール、および、電子部品モジュールの製造方法
WO2021090694A1 (ja) * 2019-11-07 2021-05-14 株式会社村田製作所 モジュール
US20220005773A1 (en) * 2020-07-01 2022-01-06 Sandisk Technologies Llc Semiconductor structure containing pre-polymerized protective layer and method of making thereof
US11776922B2 (en) * 2020-07-01 2023-10-03 Sandisk Technologies Llc Semiconductor structure containing pre-polymerized protective layer and method of making thereof
WO2022075417A1 (ja) * 2020-10-08 2022-04-14 株式会社村田製作所 基板構造体、モジュール、基板構造体の製造方法、および、モジュールの製造方法

Also Published As

Publication number Publication date
KR102374316B1 (ko) 2022-03-15
KR20190138839A (ko) 2019-12-16
JPWO2018235715A1 (ja) 2020-05-07
CN110832636A (zh) 2020-02-21
CN110832636B (zh) 2023-09-08
JP6784330B2 (ja) 2020-11-11
US11276631B2 (en) 2022-03-15
KR20210150598A (ko) 2021-12-10
US20200118913A1 (en) 2020-04-16
KR102463386B1 (ko) 2022-11-04

Similar Documents

Publication Publication Date Title
JP6784330B2 (ja) モジュールおよびその製造方法
US7161242B2 (en) Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element
US7180012B2 (en) Module part
US20070170582A1 (en) Component-containing module and method for producing the same
WO2001071806A1 (fr) Dispositif a semi-conducteur, procede de realisation d'un dispositif electronique, dispositif electronique, et terminal d'informations portable
JP2008085089A (ja) 樹脂配線基板および半導体装置
JPH0945809A (ja) 半導体装置及び半導体装置実装用基板
KR20090042717A (ko) 실리콘 인터포저 및 이를 결합한 반도체 장치 패키지와 반도체 장치
WO2007114106A1 (ja) 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法
US20210007224A1 (en) Contact pads for electronic substrates and related methods
JP4844216B2 (ja) 多層回路配線基板及び半導体装置
US8525355B2 (en) Semiconductor device, electronic apparatus and semiconductor device fabricating method
JP2002217514A (ja) マルチチップ半導体装置
US11322472B2 (en) Module
EP1041618A1 (en) Semiconductor device and manufacturing method thereof, circuit board and electronic equipment
JP4894347B2 (ja) 半導体集積回路素子搭載用基板および半導体装置
US10314166B2 (en) Printed wiring board
US11264366B2 (en) Module
JP4952365B2 (ja) 両面実装回路基板に対する電子部品の実装構造、半導体装置、及び両面実装半導体装置の製造方法
JP2008078164A (ja) 半導体装置とその製造方法
JP2002231761A (ja) 電子部品実装体および電子部品
US10679920B2 (en) Semiconductor device having semiconductor package in a wiring board opening
JP5067107B2 (ja) 回路基板および半導体装置
JP5062022B2 (ja) 電子部品装置
JPH11317470A (ja) バンプを有する電子部品

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18820642

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20197033134

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2019525513

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18820642

Country of ref document: EP

Kind code of ref document: A1