CN110832636B - 模块及其制造方法 - Google Patents

模块及其制造方法 Download PDF

Info

Publication number
CN110832636B
CN110832636B CN201880040581.8A CN201880040581A CN110832636B CN 110832636 B CN110832636 B CN 110832636B CN 201880040581 A CN201880040581 A CN 201880040581A CN 110832636 B CN110832636 B CN 110832636B
Authority
CN
China
Prior art keywords
substrate
resin layer
sealing resin
external connection
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880040581.8A
Other languages
English (en)
Other versions
CN110832636A (zh
Inventor
松川喜孝
胜部彰夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN110832636A publication Critical patent/CN110832636A/zh
Application granted granted Critical
Publication of CN110832636B publication Critical patent/CN110832636B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499Material of the matrix
    • H01L2224/81594Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/815 - H01L2224/81591
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8193Reshaping
    • H01L2224/81947Reshaping by mechanical means, e.g. "pull-and-cut", pressing, stamping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/81948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

模块(1)具备:基板(2)、安装于基板(2)的上表面(2a)的多个部件(3)、安装于下表面(2b)的部件(4)、安装于下表面(2b)并作为外部连接端子发挥功能的焊球(5)、在基板(2)的上表面(2a)和下表面(2b)层叠的密封树脂层(6a、6b)、以及覆盖模块(1)的侧面和上表面的屏蔽膜(7)。焊球(5)的局部从密封树脂层(6b)的表面(60b)暴露,焊球(5)成为暴露的部分从密封树脂层(6b)突出的形状。通过将焊球(5)的突出部分作为外部连接端子而与母基板的电极连接,从而能够将模块(1)与母基板连接。在焊球(5)与密封树脂层(6b)之间存在空隙部(9),使因焊料与树脂间的热膨胀系数之差产生的应力减少,能够抑制在焊球(5)上产生裂缝。

Description

模块及其制造方法
技术领域
本发明涉及模块及其制造方法。
背景技术
以往,公知有通过在基板上配置大致球状的导电性支柱而形成外部连接端子的技术。例如,如图7所示,专利文献1记载的模块100在具有在半导体基板101的主面形成的电极焊盘102的半导体晶片103之上形成有经由布线104而与电极焊盘102电连接的大致球状的导电性球105。在半导体晶片103之上,使导电性球105的顶部暴露地形成有树脂层106,在导电性球105的从树脂层106暴露的顶部上设置有由焊球构成的外部连接端子107。在这样的结构的模块100中,通过将导电性球105载置于布线104的规定位置,从而能够在树脂层106内形成用于连接布线104和外部连接端子107的支柱,与由镀敷法得到的支柱的形成相比,能够在极短时间形成作为目标的高度的支柱。
专利文献1:日本特许第4626008号公报(参照段落0023~0025、图6等)
然而,如专利文献1那样,当在导电性球105的顶部设置外部连接端子107的情况下,在向母基板安装时,导电性球105与外部连接端子107间的连接部分成为收腰的形状,因此存在可靠性、机械强度降低这样的问题。另外,导电性球105的顶部处于与树脂层106同一平面上,作为与母基板连接时的凸块,需要设置由焊球构成的外部连接端子107,存在制造工序的数量增加这样的课题、为了在树脂层106载置由焊球构成的外部连接端子107而不易低矮化这样的课题。
发明内容
本发明是鉴于上述的课题而完成的,目的在于提供通过焊球形成不是收腰形状的外部连接端子,从而提高可靠性、机械强度的模块。
为了实现上述的目的,本发明的模块的特征在于,具备:基板;连接电极,其设置于上述基板的一个主面;第1部件,其安装于上述基板的上述一个主面;外部连接端子,其由经由上述连接电极而配设于上述基板的上述一个主面的焊球构成;以及密封树脂层,其设置于上述基板的上述一个主面,并对上述基板的一个主面和上述第1部件进行密封,上述外部连接端子的局部从上述密封树脂层的和与上述基板的上述一个主面对置的对置面相反侧的面暴露,上述外部连接端子的从上述基板的上述一个主面起算的高度比上述密封树脂层的从上述基板的上述一个主面起算的高度高,在上述外部连接端子与上述密封树脂层之间存在间隙,包围上述外部连接端子的上述密封树脂层的与上述外部连接端子对置的对置面为在与上述基板的上述一个主面垂直的截面中成为曲线的曲面。
根据该结构,外部连接端子由焊球形成,成为没有收腰的形状,因此能够提高外部连接端子的机械强度、可靠性。另外,由焊料形成外部连接端子,因此能够通过回流焊时的自对准效应实现外部连接端子的位置的高精度化。另外,焊球成为从密封树脂层暴露并突出的形状,因此不需要在端子部实施镀敷,从而能够抑制制造成本。
另外,包围外部连接端子的密封树脂层的与上述外部连接端子对置的对置面是在与基板的一个主面垂直的截面中成为曲线的曲面,与对置面为在截面中成为直线的曲面的情况比较,针对向基板施加的在水平方向上的应力的负荷分散,因此能够抑制剥离的产生。
另外,也可以是,上述外部连接端子由一个焊球形成。在这种情况下,焊球成为从密封树脂层以圆形突出的形状,因此能够保持原样作为向母基板连接时的凸块而利用。
另外,也可以是,上述外部连接端子和上述密封树脂层完全不接触。在这种情况下,焊球与密封树脂层不接触,由此能够减少由焊料与树脂间的热膨胀系数之差产生的应力,能够抑制焊球的裂缝的产生。
另外,也可以是,上述第1部件的局部从上述密封树脂层的上述相反侧的面暴露。在这种情况下,能够实现模块的低矮化。
也可以是,上述第1部件的从上述密封树脂层的上述相反侧的面暴露的面处于与上述密封树脂层的上述相反侧的面在同一平面上。在这种情况下,能够实现模块的低矮化。
另外,也可以是,在上述基板的另一个主面安装有第2部件。在这种情况下,通过在基板的另一个主面也安装部件,从而能够扩大安装面积,能够提高设计自由度。
另外,本发明的模块的制造方法的特征在于,具备以下工序:在基板的一个主面的安装电极搭载部件和焊球;利用回流焊炉对上述基板进行加热,并将上述部件和上述焊球固定于上述基板;将密封上述部件和上述焊球的密封树脂层层叠于上述基板的上述一个主面;对上述密封树脂层的和与上述一个主面对置的对置面相反侧的面和上述焊球的局部进行研磨,以使上述焊球从上述密封树脂层的上述相反侧的面暴露;以及利用回流焊炉再次对上述基板进行加热,以使得上述焊球的从上述基板的上述一个主面起算的高度比上述密封树脂层的从上述基板的上述一个主面起算的高度高。
在这种情况下,若在对密封树脂层进行研磨,使焊球暴露之后,利用回流焊炉进行加热处理,则焊球由于表面张力而变形成球状,成为从密封树脂层的研磨面突出的形状,从而能够将焊球利用为凸块。因此,不需要再形成用于向母基板连接的凸块。另外,将焊球作为外部连接端子而搭载,因此不需要实施镀敷,因此能够不产生镀敷异常析出,就制造可靠性好、机械强度高的模块。
根据本发明,能够提供可靠性、机械强度高的模块,而且能够实现模块的低矮化。
附图说明
图1是本发明的一实施方式所涉及的模块的剖视图。
图2是表示图1的模块的焊球的安装方法的例子的放大剖视图。
图3是表示图1的模块的制造工序的图。
图4是表示图1的模块的制造工序的图。
图5是表示将图1的模块向母基板安装的工序的图。
图6是用于对焊球周边的密封树脂层的形状进行说明的图。
图7是表示以往的模块的图。
具体实施方式
参照图1和图2对本发明的一实施方式所涉及的模块1进行说明。此外,图1是模块1的剖视图,图2是表示模块1的焊球的安装方法的例子的放大剖视图。
如图1所示,该实施方式所涉及的模块1具备:基板2、在该基板2的上表面2a安装的多个部件3、安装于下表面2b的部件4、搭载于下表面2b并成为外部连接端子的多个焊球5、在基板2的上表面2a和下表面2b层叠并对基板2、各部件3和部件4进行密封的密封树脂层6a、6b、以及被覆模块1的侧面和上表面的屏蔽膜7,并经由焊球5搭载于母基板(省略图示)。
基板2例如由低温同时烧制陶瓷、玻璃环氧树脂等形成,在内部形成有导通孔导体(省略图示)、各种布线电极(省略图示)。另外,在基板2的上表面2a和下表面2b形成有用于与多个部件3、部件4和焊球5连接的连接电极8。此外,基板2可以是单层构造和多层构造中任一种。
部件3(相当于本发明的“第2部件”)通过例如由Si等形成的半导体元件、贴片电容、贴片电感、贴片电阻、贴片天线等电子部件构成。部件3由密封树脂层6a密封。
部件4(相当于本发明的“第1部件”)是由Si等形成的半导体元件等半导体部件,并安装于基板2的下表面2b。此外,部件4由密封树脂层6b密封,但也可以是,部件4的局部从密封树脂层6b的表面60b(相当于本发明的“和与一个主面对置的对置面相反侧的面”)暴露。
焊球5安装于基板2的下表面2b(相当于本发明的“一个主面”),并与下表面2b的连接电极8连接。另外,焊球5的局部从密封树脂层6b的表面60b暴露并突出,焊球5的从密封树脂层6b的表面60b暴露的部分作为将模块1向母基板连接时的外部连接端子发挥功能。换言之,对于焊球5和密封树脂层6b各自从基板2的下表面2b起算的高度而言,前者比后者高,焊球5的局部成为从密封树脂层6b的表面60b突出的形状,通过将焊球5的突出部分作为凸块而与母基板的电极连接,从而能够将模块1连接于母基板。另外,在焊球5与密封树脂层6b之间存在空隙部9(相当于本发明的“间隙”)。即,存在焊球5与密封树脂层6b不接触的部分。
另外,焊球5的安装方法存在图2的(a)所示那样的连接电极8的周缘部由阻焊剂10覆盖的覆盖保护层构造、图2的(b)所示那样的连接电极8与阻焊剂10之间存在间隔即连接电极8与阻焊剂10不接触的间隔保护层构造、图2的(c)所示那样的构造等。另外,如图2的(a)~(c)所示,连接电极8与布线层11电连接。另外,密封树脂层的与焊球5的外周面50a对置的对置面61b是在与基板2的下表面2b垂直的截面中成为曲线的曲面。换言之,对置面61b成为从密封树脂层6b挖掉球体的一部分那样的形状。
密封树脂层6a被覆基板2的上表面2a和各部件3地设置于基板2的上表面2a。另外,密封树脂层6b被覆基板2的下表面2b、部件4地设置于基板2的下表面2b。另外,如图2的(a)~(c)所示,焊球5由密封树脂层6b围起。密封树脂层6a、6b能够由一般作为含二氧化硅填料的环氧树脂等密封树脂采用的树脂形成。另外,也能够为了高热传导,而使用氧化铝填料。
屏蔽膜7用于针对基板2内的各种电极、各部件3、4阻隔来自外部的电磁波,并配置为被覆模块1的侧面和上表面(密封树脂层6a的表面60a)。另外,屏蔽膜7能够由具有紧贴膜、层叠于紧贴膜的导电膜、以及层叠于导电膜的保护膜的多层构造形成。
(模块的制造方法)
接下来,参照图3和图4对本发明的模块1的制造方法的一个例子进行说明。
首先,如图3的(a)所示,准备能够在自身上表面2a和下表面2b安装部件的基板2,在基板2的下表面2b涂覆焊料膏并印刷连接电极8,安装部件4和焊球5。此外,也可以取代安装焊球5,而使焊料膏的涂覆量变多,之后利用回流焊炉进行加热时焊料膏成为球状,以此形成焊球5。其后,投入回流焊炉进行加热处理,在基板2的下表面2b固定部件4和焊球5。也可以在由回流焊炉进行加热处理后进行焊剂清洗。
接下来,如图3的(b)所示,被覆部件4和焊球5地在基板2的下表面2b层叠密封树脂层6b。
接下来,如图3的(c)所示,对密封树脂层6b的表面60b进行研磨直至焊球5暴露为止。此时,调节密封树脂层6b的研磨量,以防止除焊球5以外的部件暴露。此外,也可以调整密封树脂层6b的高度,以使部件4的局部从密封树脂层6b的表面60b暴露。
接下来,如图3的(d)所示,在基板2的上表面2a涂覆焊料膏并印刷连接电极8,安装各部件3。其后,也可以在密封树脂层6b的表面60b的焊球5的暴露面5a涂覆焊剂,通过回流焊炉进行加热处理。也可以在利用回流焊炉进行加热处理之后进行焊剂清洗。
如图3的(e)所示,若利用回流焊炉进行加热处理,则各部件3固定于基板2,另外,由于焊料的表面张力而使焊球5成为从密封树脂层6b的表面60b突出的形状。
接下来,如图4的(a)所示,被覆各部件3地,在基板2的上表面2a层叠密封树脂层6a。
接下来,如图4的(b)所示,通过使用溅射装置、真空蒸镀装置,使屏蔽膜7成膜,从而完成模块1。
此外,也可以是,在基板2的上表面2a安装各部件3之后,利用回流焊炉进行加热处理,而将各部件3固定于基板2,然后,对密封树脂层6b的表面60b进行研磨,在暴露面5a涂覆焊剂,再次利用回流焊炉进行加热处理。
此处,参照图5对从模块1的表面60b的研磨至模块1的向母基板的安装为止的一系列的工序进行说明。此外,图5中,将屏蔽膜7省略图示。
图5的(a)是表示对密封树脂层6b的表面60b进行研磨并使焊球5从密封树脂层6b的表面60b暴露出来后的图。此时,密封树脂层6b的表面60b和焊球5的暴露面5a形成同一平面。如图5的(b)所示,若在焊球5的暴露面5a涂覆焊剂,利用回流焊炉进行加热处理,则通过焊料的表面张力,焊球5成为大致球状并成为从密封树脂层6b的表面60b突出的形状。此时,形成焊球5与密封树脂层6b不接触的部分亦即空隙部9。如图5的(c)所示,能够将焊球5的从表面60b突出的部分保持原样利用为焊料凸块,向母基板12安装。
因此,根据上述的实施方式,模块1的外部连接端子由一个焊球5形成,因此成为没有收腰的形状,能够提高可靠性、机械强度。另外,在外部连接端子使用焊球5,从而通过利用回流焊炉进行加热处理时的自对准效应,能够实现外部连接端子的位置的高精度化。另外,焊球5的局部从密封树脂层6b的表面60b暴露,而且焊球5的局部从密封树脂层的表面60b突出,因此能够不实施镀敷,就将焊球5用作外部连接端子。并且,与针对外部连接端子使用金属销的情况相比,不需要镀敷处理,因此不产生因对密封树脂层6b的表面60b进行研磨时的研磨残渣而引起的镀敷异常析出。另外,在焊球5与密封树脂层6b之间存在空隙部9,由此能够减少由焊料与树脂间的热膨胀系数之差产生的应力,能够抑制在焊球5上产生裂缝。
另外,通过对密封树脂层6b的表面60b进行研磨直至部件4暴露为止,从而能够实现模块1的低矮化。
另外,在对密封树脂层6b的表面60b进行研磨直至焊球5暴露后,在焊球5的暴露面5a涂覆焊剂并利用回流焊炉进行加热处理,由此焊球5成为大致球状并成为从表面60b突出的形状,能够保持原样利用为向母基板安装时的凸块。
另外,密封树脂层的与外部连接端子的外周面对置的对置面为在与基板的一个主面垂直的截面中成为曲线的曲面,由此与对置面为在截面中成为直线的曲面的情况比较,针对向基板施加的在水平方向上的应力的负荷分散,因此能够抑制剥离的产生。如图6所示,当在截面中对置面61b1成为直线的情况下,在A1-B1之间密封树脂层6b1的截面积线性减少,在B1-C之间密封树脂层6b1的截面积不减少。此时,密封树脂层6b1的截面积减少率以B1作为边界而急剧变化,因此在对模块1施加了沿水平方向的应力的情况下,负荷容易在B1集中而是密封树脂层6b1从基板2产生剥离。另一方面,如上述的实施方式那样,当在截面中对置面61b2成为曲线的情况下,在A2-B2之间密封树脂层6b2的截面积的减少不是线性的,随着从A2朝向B2,截面积减少率慢慢变小,因此没有B2的急剧的截面积减少率的变化。因此,能够避免B2处的负荷的集中,能够抑制密封树脂层6b2产生从基板2剥离。
此外,本发明不限定于上述实施方式,只要不脱离其主旨,除了上述内容以外,能够进行各种变更。
工业上的可利用性
另外,本发明能够应用于各种模块。
附图标记说明
1...模块;2...基板;3...部件(第1部件);4...部件(第2部件);5...焊球(外部连接端子);6a、6b...密封树脂层;61b...对置面;8...连接电极。

Claims (6)

1.一种封装模块,其特征在于,具备:
基板;
连接电极,其设置于所述基板的一个主面;
第1部件,其安装于所述基板的所述一个主面;
外部连接端子,其由经由所述连接电极而配设于所述基板的所述一个主面的焊球构成;以及
密封树脂层,其设置于所述基板的所述一个主面,并对所述基板的所述一个主面和所述第1部件进行密封,
所述外部连接端子的局部从所述密封树脂层的和与所述基板的所述一个主面对置的对置面相反侧的面暴露,
所述外部连接端子的从所述基板的所述一个主面起算的高度比所述密封树脂层的从所述基板的所述一个主面起算的高度高,
在所述外部连接端子与所述密封树脂层之间存在间隙,
包围所述外部连接端子的所述密封树脂层的与所述外部连接端子对置的对置面为在与所述基板的所述一个主面垂直的截面中成为曲线的曲面,
所述外部连接端子和所述密封树脂层完全不接触,
所述外部连接端子由一个焊球形成,成为没有收腰的形状。
2.根据权利要求1所述的封装模块,其特征在于,
所述外部连接端子由一个焊球形成。
3.根据权利要求1或2中任一项所述的封装模块,其特征在于,
所述第1部件的局部从所述密封树脂层的所述相反侧的面暴露。
4.根据权利要求3所述的封装模块,其特征在于,
所述第1部件的从所述密封树脂层的所述相反侧的面暴露的面处于与所述密封树脂层的所述相反侧的面在同一平面上。
5.根据权利要求1或2所述的封装模块,其特征在于,
在所述基板的另一个主面安装有第2部件。
6.一种封装模块的制造方法,其特征在于,具备以下工序:
在基板的一个主面的安装电极搭载部件和焊球;
利用回流焊炉对所述基板进行加热,将所述部件和所述焊球固定于所述基板;
将密封所述基板、所述部件和所述焊球的密封树脂层设置于所述基板的所述一个主面;
至少对所述密封树脂层的和与所述一个主面对置的对置面相反侧的面和所述焊球的局部进行研磨,以使所述焊球从所述密封树脂层的所述相反侧的面暴露;以及
利用回流焊炉再次对所述基板进行加热,以使得所述焊球的从所述基板的所述一个主面起算的高度比所述密封树脂层的从所述基板的所述一个主面起算的高度高。
CN201880040581.8A 2017-06-20 2018-06-14 模块及其制造方法 Active CN110832636B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2017-120160 2017-06-20
JP2017120160 2017-06-20
PCT/JP2018/022700 WO2018235715A1 (ja) 2017-06-20 2018-06-14 モジュールおよびその製造方法

Publications (2)

Publication Number Publication Date
CN110832636A CN110832636A (zh) 2020-02-21
CN110832636B true CN110832636B (zh) 2023-09-08

Family

ID=64735580

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880040581.8A Active CN110832636B (zh) 2017-06-20 2018-06-14 模块及其制造方法

Country Status (5)

Country Link
US (1) US11276631B2 (zh)
JP (1) JP6784330B2 (zh)
KR (2) KR102463386B1 (zh)
CN (1) CN110832636B (zh)
WO (1) WO2018235715A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10861779B2 (en) 2018-06-22 2020-12-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an electrical contact with a high-melting-point part and method of manufacturing the same
US20200312733A1 (en) * 2019-03-29 2020-10-01 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
JP7124795B2 (ja) 2019-06-27 2022-08-24 株式会社村田製作所 電子部品モジュール、電子部品ユニット、および、電子部品モジュールの製造方法
WO2021085180A1 (ja) * 2019-10-30 2021-05-06 株式会社村田製作所 電子部品モジュール、および、電子部品モジュールの製造方法
WO2021090694A1 (ja) * 2019-11-07 2021-05-14 株式会社村田製作所 モジュール
US11776922B2 (en) * 2020-07-01 2023-10-03 Sandisk Technologies Llc Semiconductor structure containing pre-polymerized protective layer and method of making thereof
US20220066036A1 (en) * 2020-08-25 2022-03-03 Lumentum Operations Llc Package for a time of flight device
WO2022075417A1 (ja) * 2020-10-08 2022-04-14 株式会社村田製作所 基板構造体、モジュール、基板構造体の製造方法、および、モジュールの製造方法
CN112930589B (zh) * 2021-01-26 2024-05-10 长江存储科技有限责任公司 衬底结构及其制造和封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040711A (ja) * 1998-07-23 2000-02-08 Sony Corp 樹脂封止型半導体装置とその製造方法
KR20100113676A (ko) * 2009-04-14 2010-10-22 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4626008Y1 (zh) 1967-12-23 1971-09-07
US20070102827A1 (en) * 1997-12-08 2007-05-10 3M Innovative Properties Company Solvent Assisted Burnishing of Pre-Underfilled Solder-Bumped Wafers for Flipchip Bonding
JP4066522B2 (ja) 1998-07-22 2008-03-26 イビデン株式会社 プリント配線板
JP4626008B2 (ja) 2000-04-04 2011-02-02 日本テキサス・インスツルメンツ株式会社 半導体装置
JP4105202B2 (ja) * 2006-09-26 2008-06-25 新光電気工業株式会社 半導体装置の製造方法
US20100072600A1 (en) * 2008-09-22 2010-03-25 Texas Instrument Incorporated Fine-pitch oblong solder connections for stacking multi-chip packages
JP5421863B2 (ja) * 2010-06-28 2014-02-19 新光電気工業株式会社 半導体パッケージの製造方法
KR20130084866A (ko) * 2012-01-18 2013-07-26 삼성전자주식회사 양면이 몰딩된 반도체 패키지
KR102067155B1 (ko) * 2013-06-03 2020-01-16 삼성전자주식회사 연결단자를 갖는 반도체 장치 및 그의 제조방법
KR102063794B1 (ko) 2013-06-19 2020-01-08 삼성전자 주식회사 적층형 반도체 패키지
KR102108087B1 (ko) * 2013-07-11 2020-05-08 삼성전자주식회사 반도체 패키지
KR102229202B1 (ko) * 2013-11-07 2021-03-17 삼성전자주식회사 트렌치 형태의 오프닝을 갖는 반도체 패키지 및 그 제조방법
KR102157551B1 (ko) * 2013-11-08 2020-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9559064B2 (en) * 2013-12-04 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in package-on-package structures
US9613933B2 (en) * 2014-03-05 2017-04-04 Intel Corporation Package structure to enhance yield of TMI interconnections
JP2015216219A (ja) * 2014-05-09 2015-12-03 マイクロン テクノロジー, インク. 半導体装置
KR102457119B1 (ko) * 2015-09-14 2022-10-24 삼성전자주식회사 반도체 패키지의 제조 방법
US10256173B2 (en) * 2016-02-22 2019-04-09 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
KR101824726B1 (ko) * 2017-02-23 2018-02-01 앰코 테크놀로지 코리아 주식회사 반도체 패키지

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040711A (ja) * 1998-07-23 2000-02-08 Sony Corp 樹脂封止型半導体装置とその製造方法
KR20100113676A (ko) * 2009-04-14 2010-10-22 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법

Also Published As

Publication number Publication date
KR102374316B1 (ko) 2022-03-15
KR20190138839A (ko) 2019-12-16
JPWO2018235715A1 (ja) 2020-05-07
CN110832636A (zh) 2020-02-21
JP6784330B2 (ja) 2020-11-11
WO2018235715A1 (ja) 2018-12-27
US11276631B2 (en) 2022-03-15
KR20210150598A (ko) 2021-12-10
US20200118913A1 (en) 2020-04-16
KR102463386B1 (ko) 2022-11-04

Similar Documents

Publication Publication Date Title
CN110832636B (zh) 模块及其制造方法
JP4858541B2 (ja) 中継基板および電子回路実装構造体
US6646338B2 (en) Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument
US6756685B2 (en) Semiconductor device
US7816783B2 (en) Resin wiring substrate, and semiconductor device and laminated semiconductor device using the same
JP4873005B2 (ja) 複合基板及び複合基板の製造方法
US20120322202A1 (en) Semiconductor device and manufacturing method of the semiconductor device
KR20070045894A (ko) 적층형 반도체모듈
JP6981537B2 (ja) 高周波モジュール
JPH0945809A (ja) 半導体装置及び半導体装置実装用基板
US20210144853A1 (en) Contact pads for electronic substrates and related methods
US8093505B2 (en) Layered electronic circuit device
JP4965989B2 (ja) 電子部品内蔵基板および電子部品内蔵基板の製造方法
JP4844216B2 (ja) 多層回路配線基板及び半導体装置
KR101741648B1 (ko) 전자파 차폐 수단을 갖는 반도체 패키지 및 그 제조 방법
JP2002208657A (ja) 半導体装置及び半導体装置実装用基板
KR101043471B1 (ko) 반도체 패키지 및 이의 제조 방법
JP2021158240A (ja) 電子装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant