WO2018201788A1 - 一种薄膜晶体管及其制备方法、阵列基板、显示面板 - Google Patents

一种薄膜晶体管及其制备方法、阵列基板、显示面板 Download PDF

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WO2018201788A1
WO2018201788A1 PCT/CN2018/077928 CN2018077928W WO2018201788A1 WO 2018201788 A1 WO2018201788 A1 WO 2018201788A1 CN 2018077928 W CN2018077928 W CN 2018077928W WO 2018201788 A1 WO2018201788 A1 WO 2018201788A1
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layer
buffer layer
light shielding
thin film
film transistor
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PCT/CN2018/077928
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English (en)
French (fr)
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王国英
宋振
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京东方科技集团股份有限公司
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Priority to US16/097,486 priority Critical patent/US20210226067A1/en
Publication of WO2018201788A1 publication Critical patent/WO2018201788A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present application relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, an array substrate, and a display panel.
  • the oxide gate transistor (TFT) of the top gate structure does not have an overlap region with the source and the drain, and thus has a small parasitic capacitance (Cgs), so that it can be applied to have a high resolution and a high refresh rate.
  • OLED organic light-emitting diode
  • the oxide in the oxide TFT is sensitive to light, the electrical properties of the oxide in the channel region of the TFT change under illumination, and the oxide of the TFT in the top gate structure lacks the trench of the bottom gate to the TFT. In the occlusion of the track region, the TFT is prone to a large threshold voltage (V TH ) drift, which exceeds the compensation range of the compensation circuit, causing problems such as residual images on the display screen.
  • V TH threshold voltage
  • a thin film transistor includes a light shielding layer and a buffer layer over the light shielding layer, an active layer above the buffer layer, and the active layer includes a channel. a region and a source region and a drain region located on both sides of the channel region, the buffer layer being disposed such that light cannot be incident to the channel region via the buffer layer.
  • a thin film transistor provided by the embodiment of the present invention can prevent light from entering the channel region through the buffer layer due to the thickness of the buffer layer, thereby enhancing the light shielding effect on the channel region of the thin film transistor and improving the light stability of the thin film transistor. In turn, the operational stability of the thin film transistor can be improved.
  • the light shielding layer comprises a metal and the buffer layer comprises a metal oxide.
  • the material of the light shielding layer comprises a molybdenum-niobium alloy, and the material of the buffer layer comprises aluminum oxide.
  • the alumina is an aluminum bismuth alloy formed by anodizing.
  • the buffer layer has a thickness in the range of about 100 nm to 200 nm.
  • the projection of the buffer layer on the light shielding layer falls within the light shielding layer.
  • the thin film transistor further includes: a gate insulating layer over the channel region; a gate over the gate insulating layer; at the gate, the source region, a drain region, the buffer layer, and an insulating layer over the light shielding layer; and a source electrode and a drain electrode over the insulating layer, wherein the insulating layer includes a first via, a second a via hole and a third via hole, wherein the source electrode and the drain electrode are connected to the source region and the drain region through the first via hole and the second via hole, respectively, One of the drain electrode and the source electrode is connected to the light shielding layer through the third via.
  • the thickness of the buffer layer is also set such that light cannot be incident to the source region and the drain region via the buffer layer.
  • An array substrate provided by the embodiment of the present application includes the thin film transistor provided by the embodiment of the present application.
  • a display panel provided by the embodiment of the present application includes the array substrate provided by the embodiment of the present application.
  • a method for fabricating a thin film transistor according to an embodiment of the present application includes:
  • An active layer is formed over the buffer layer, the active layer including a channel region and a source region and a drain region on both sides of the channel region, wherein a thickness of the buffer layer is set In order to prevent light from entering the channel region via the buffer layer.
  • the light shielding layer comprises a metal and the buffer layer comprises a metal oxide.
  • forming the light shielding layer and forming the buffer layer include: forming a first metal layer as the light shielding layer on the substrate;
  • the second metal layer is subjected to an oxidation treatment to form the buffer layer.
  • the first metal comprises a molybdenum-niobium alloy
  • the second metal comprises an aluminum-niobium alloy
  • the oxidation treatment includes treating the aluminum-bismuth alloy by an anodization process to obtain alumina.
  • the thin film transistor fabrication method further includes: forming a gate insulating layer on the channel region;
  • first via Forming a first via, a second via, and a third via on the insulating layer, wherein the first via reaches an upper surface of the source region, and the second via reaches the drain An upper surface of the polar region, the third via reaching an upper surface of the light shielding layer not covered by the buffer layer;
  • a source electrode and a drain electrode on the interlayer insulating layer, wherein the source electrode and the drain electrode pass through the first via hole and the second via hole respectively to the source region Connected to the drain, and one of the source electrode and the drain electrode is connected to the light shielding layer through the third via.
  • forming the first via, the second via, and the third via employ a one-time etching process.
  • the thickness of the buffer layer is also set such that light cannot be incident to the source region and the drain region via the buffer layer.
  • FIG. 1 is a schematic structural view of a prior art thin film transistor
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application.
  • FIG. 3 is a schematic flow chart of a method for fabricating a thin film transistor according to an embodiment of the present application
  • FIG. 4 is a schematic flow chart of another method for fabricating a thin film transistor according to an embodiment of the present application.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and The derivative should refer to the public text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • an oxide TFT structure of a top gate structure includes: a light shielding layer 1, a silicon oxide layer 2, a first conductor region 3, a channel region 4, a second conductor region 5, and a gate insulating layer 6. a gate 7, an interlayer insulating layer 8, a source 9 and a drain 10.
  • the arrow in the figure represents the direction of the optical path, and the silicon oxide layer serves as a buffer layer, and the light can pass through the silicon oxide layer.
  • the silicon oxide layer is disposed in a whole layer and has a thick thickness
  • the light shielding layer is disposed to block only light incident to the channel region perpendicular to the direction of the light shielding layer, and light not perpendicular to the direction of the light shielding layer can still be
  • the side faces of the silicon oxide layer are incident on the channel region, affecting the electrical properties of the oxide in the channel region.
  • Such a top gate structure oxide TFT has a poor light-shielding effect on the channel region, and the TFT has poor operational stability.
  • the embodiment of the present application provides a thin film transistor, a method for fabricating the same, an array substrate, and a display panel for enhancing the light shielding effect on a channel region of a thin film transistor, thereby improving the light stability of the thin film transistor, thereby improving the operation of the thin film transistor. stability.
  • the thin film transistor includes: a light shielding layer 1, a buffer layer 11 on the light shielding layer 1, and an active layer on the buffer layer 11 a layer (eg, a semiconductor layer) including three: a channel region 4 and source and drain regions on both sides of the channel region 4, wherein the thickness of the buffer layer 11 is set such that Light cannot enter the channel region via the buffer layer 11.
  • a layer eg, a semiconductor layer
  • one of the source region and the drain region may be set as the first conductor region 3 located on the left side of the channel region, and the other of the source region and the drain region may be set as Located in the second conductorized region 5 on the right side of the channel region.
  • the following description will be made by taking the source region as the first conductor region 3 and the drain region as the second conductor region 5 and the active layer as a semiconductor layer.
  • the thickness of the buffer layer is also set such that light cannot be incident on the channel region via the source region and the drain region.
  • the thin film transistor further includes: a gate insulating layer 6 over the channel region 4, a gate electrode 7 over the gate insulating layer 6, and the gate electrode 7, the first conductorized region 3, The second conductor region 5, the buffer layer 11 and the insulating layer 8 over the light shielding layer 1, and the source 9 and the drain 10 over the insulating layer 8 (for example, an interlayer insulating layer)
  • the insulating layer 8 includes a first via 12, a second via 13, and a third via 14, and the source 9 is connected to the first conductor region 3 through the first via 12
  • the drain electrode 10 is connected to the second conductor region 5 through the second via hole 13 , and the drain electrode 10 is connected to the light shielding layer 1 through the third via hole 14 . It will be appreciated that the transistor can also be arranged such that its source electrode is connected to the light shielding layer through the third via.
  • a thin film transistor provided by an embodiment of the present application is configured such that a thickness of a buffer layer of the thin film transistor is such that light cannot enter the channel region via the buffer layer.
  • the thickness of the buffer layer of the thin film transistor is further set such that light cannot be incident to the source region and the drain region via the buffer layer.
  • first conductor region 3 and the second conductor region 5 are regions formed after the semiconductor layer is subjected to the conductor treatment, and the channel region 4 is a region of the semiconductor layer that has not been subjected to the conductor treatment.
  • the light shielding layer is a metal light shielding layer.
  • the "metal” here includes metal elements and metal alloys. It should be noted that the light shielding layer is connected to the low potential end of the source electrode and the drain electrode of the thin film transistor, so that the induced charge of the metal light shielding layer can be prevented from affecting the characteristics of the thin film transistor.
  • the drain electrode serves as a low potential end of the source electrode and the drain electrode, and the light shielding layer is connected to the drain electrode.
  • the source electrode serves as the low potential end of the source electrode and the drain electrode, the source electrode is connected to the light shielding layer through the third via hole.
  • the material of the light shielding layer comprises a molybdenum-niobium alloy (MoNb), and the material of the buffer layer comprises aluminum oxide (AlO x ).
  • MoNb molybdenum-niobium alloy
  • AlO x aluminum oxide
  • the "x" may include a non-stoichiometric ratio.
  • the material of the light shielding layer may also be other metal materials that can achieve the light shielding function, and the buffer layer may also use other metal oxides.
  • the alumina is an aluminum bismuth alloy (AlNd) formed by anodizing.
  • AlNd forms AlO x as a buffer layer by anodization
  • AlO x has good compactness.
  • the problem of a large number of film vacuum and poor film density caused by depositing a thin layer of SiO x can be avoided, and under the same film thickness condition, AlO
  • the dielectric constant of x is greater than the dielectric constant of silicon oxide.
  • AlO x is selected as the buffer layer, and the performance of the thin film transistor can be improved while thinning the buffer layer.
  • the buffer layer has a thickness in the range of about 100 nm to 200 nm.
  • the size of the buffer layer is smaller than the size of the light shielding layer in a direction parallel to the buffer layer. In other words, the projection of the buffer layer on the light shielding layer falls within the light shielding layer. Therefore, in one embodiment, in the thin film transistor shown in FIG. 2, the first via 12, the second via 13, and the third via 14 may be formed in a one-time etching process.
  • the silicon oxide buffer layer is thick and disposed in a whole layer, and the first via hole cannot be used to ensure the third via hole is inscribed, so the third via hole and the first via hole and the second via hole
  • the etching is divided into two steps.
  • the thin film transistor provided by the embodiment of the present application has a thinner thickness of the buffer layer due to the projection of the buffer layer on the light shielding layer, and the insulating layer is in the semiconductor layer and the light shielding layer.
  • the thickness regions of the layer regions are substantially uniform, so that the via holes can be simultaneously etched in the conductive region and the light shielding layer region, that is, the first via hole, the second via hole, and the third via hole can be formed by one etching process,
  • the hole etching precision simplifies the preparation process of the thin film transistor and reduces the process difficulty of the thin film transistor fabrication.
  • An array substrate provided by the embodiment of the present application includes the thin film transistor provided by the embodiment of the present application.
  • a display panel provided by the embodiment of the present application includes the array substrate provided by the embodiment of the present application.
  • the display panel provided by the embodiment of the present application may be an organic light emitting diode (OLED) display panel, a liquid crystal display panel, or the like.
  • OLED organic light emitting diode
  • an active layer eg, a semiconductor layer
  • the active layer comprising: a channel region and a source region and a drain region on both sides of the channel region, wherein
  • the thickness of the buffer layer is set such that light cannot be incident to the channel region via the buffer layer.
  • the thickness of the buffer layer is also set such that light cannot be incident on the source region and the drain region via the buffer layer.
  • the light shielding layer comprises a metal and the buffer layer may comprise a metal oxide.
  • forming the light shielding layer and forming the buffer layer includes depositing a first metal layer (eg, a molybdenum-niobium alloy) as a light shielding layer on the base substrate (eg, a glass substrate), in the first metal layer
  • a second metal layer eg, an aluminum-niobium alloy
  • the second metal layer is oxidized to form the buffer layer.
  • the aluminum-bismuth alloy may be oxidized using an anodization process to obtain alumina used as a buffer layer.
  • the method for preparing a thin film transistor as shown in FIG. 2 is exemplified by a light shielding layer material including MoNb, a buffer layer material including AlO x , and an active layer including a semiconductor layer as an example. 4, as follows:
  • MoNb can also have good adhesion to the glass substrate during the preparation of the thin film transistor
  • the thickness of the thin layer of AlNd may be, for example, 100 nm to 200 nm;
  • the source 9 is connected to the first conductor region 3 through the first via 12
  • the drain 10 is connected to the second conductor region 5 through the second via 13 .
  • the drain 10 is connected to the MoNb 16 layer through the third via 14 .
  • step S402 AlNd completely oxidized into AlO x, during the preparation of thin film transistor can be controlled to a voltage applied to the light-shielding layer, so that AlNd not completely oxidized, AlNd layer retains a certain thickness.
  • an anodizing process is used to oxidize an aluminum-bismuth alloy to obtain an aluminum oxide as a buffer layer, which is simple in process and easy to implement.
  • a thin film transistor, an array substrate, a display panel, and a thin film transistor manufacturing method provided by the embodiments of the present application, by providing a thin buffer layer, the buffer layer is set such that light cannot pass through the buffer layer. And incident on the channel region, that is, the thickness of the buffer layer is set such that light originally incident on the active layer (for example, the semiconductor layer) is completely blocked, so that light cannot be incident on the active layer through the buffer layer.
  • the channel region can enhance the light shielding effect on the channel region of the thin film transistor, improve the light stability of the thin film transistor, and thereby improve the working stability of the thin film transistor.
  • the thickness of the insulating layer in the active layer and the light shielding layer region is Generally, the via holes can be simultaneously etched in the conductive region and the light shielding layer region, that is, the first via hole, the second via hole, and the third via hole can be formed by one etching process, thereby ensuring the etching precision of the via hole.
  • the thin film transistor preparation process is simplified, and the process difficulty of thin film transistor fabrication is reduced.

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Abstract

一种薄膜晶体管及其制备方法、阵列基板、显示面板，用以增强对薄膜晶体管的沟道区域（4）的遮光效果，从而改善薄膜晶体管的光照稳定性，提高薄膜晶体管的工作稳定性。该薄膜晶体管包括：遮光层（1）和位于所述遮光层（1）之上的缓冲层（11），位于所述缓冲层（11）之上的有源层，所述有源层包括沟道区域（4）以及位于所述沟道区域（4）两侧的源极区域（3）和漏极区域（5），所述缓冲层（11）的厚度被设置为使得光线不能经由所述缓冲层（11）而入射到沟道区域（4）。

Description

一种薄膜晶体管及其制备方法、阵列基板、显示面板
相关申请的交叉引用
本申请要求于2017年05月04日递交的中国专利申请第201710307274.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示面板。
背景技术
顶栅结构的氧化物薄膜晶体管(TFT)栅极与源极和漏极不存在交叠区域，因而其具有较小的寄生电容(Cgs)，从而可以应用于具有高分辨率和高刷新频率、窄边框、低功耗的大尺寸有机发光二极管(OLED)显示产品。但是由于氧化物TFT中的氧化物对光照敏感，在光照下TFT沟道区域的氧化物的电学特性会发生变化，对于顶栅结构的氧化物TFT而言，由于缺少了底栅对TFT的沟道区域的遮挡，TFT容易发生较大的阈值电压(V TH)漂移，超出了补偿电路的补偿范围，造成显示画面出现残像等问题。
发明内容
本申请实施例提供的一种薄膜晶体管，该薄膜晶体管包括：遮光层和位于所述遮光层之上的缓冲层，位于所述缓冲层之上的有源层，所述有源层包括沟道区域以及位于所述沟道区域两侧的源极区域和漏极区域，所述缓冲层的厚度被设置为使得光线不能经由所述缓冲层而入射到所述沟道区域。
本申请实施例提供的一种薄膜晶体管，由于所述缓冲层的厚度使得光线无法通过缓冲层入射到沟道区域，从而可以增强对薄膜晶体管沟道区域的遮光效果，提高薄膜晶体管的光照稳定性，进而可以提高薄膜晶体管的工作稳定性。
在一个实施例中，所述遮光层包括金属，所述缓冲层包括金属氧化物。在一个实施例中，所述遮光层的材料包括钼铌合金，所述缓冲层的材料包括氧化铝。
在一个实施例中，所述氧化铝是铝钕合金通过阳极氧化处理形成的。
在一个实施例中，所述缓冲层的厚度在约100nm～200nm范围内。
在一个实施例中，所述缓冲层在所述遮光层上的投影落在所述遮光层内。
在一个实施例中，该薄膜晶体管还包括：位于所述沟道区域之上的栅绝缘层；位于所述栅绝缘层之上的栅极；位于所述栅极、所述源极区域、所述漏极区域、所述缓冲层和所遮光层之上的绝缘层；以及位于所述绝缘层之上的源极电极和漏极电极，其中，所述绝缘层包括第一过孔、第二过孔以及第三过孔，所述源极电极和所述漏极电极分别通过所述第一过孔和所述第二过孔与所述源极区域和所述漏极区域连接，所述漏极电极和所述源极电极中的一者通过所述第三过孔与所述遮光层连接。
在一个实施例中，所述缓冲层的厚度还被设置为使得光线不能经由所述缓冲层而入射到所述源极区域和所述漏极区域。
本申请实施例提供的一种阵列基板，包括本申请实施例提供的薄膜晶体管。
本申请实施例提供的一种显示面板，包括本申请实施例提供的阵列基板。
本申请实施例提供的一种薄膜晶体管制备方法，该方法包括：
在衬底基板上形成遮光层；
在所述遮光层之上形成缓冲层；
在所述缓冲层之上形成有源层，所述有源层包括沟道区域以及位于所 述沟道区域两侧的源极区域和漏极区域，在其中，所述缓冲层的厚度被设置为使得光线不能经由所述缓冲层而入射到所述所述沟道区域。
在一个实施例中，所述遮光层包括金属，所述缓冲层包括金属氧化物。
在一个实施例中，形成所述遮光层和形成所述缓冲层包括：在所述衬底上形成作为所述遮光层的第一金属层；
在所述第一金属层上形成第二金属层；
对所述第二金属层进行氧化处理，以形成所述缓冲层。
在一个实施例中，所述第一金属包括钼铌合金，所述第二金属包括铝钕合金；
所述氧化处理包括：采用阳极氧化工艺对铝钕合金进行处理，以得到氧化铝。
在一个实施例中，所述薄膜晶体管制备方法进一步包括：在所述沟道区域上形成栅极绝缘层；
在所述栅极绝缘层上形成栅极电极；
在所述栅极电极、所述源极区域、所述漏极区域、所述缓冲层和所述遮光层上形成绝缘层；
在所述绝缘层上形成第一过孔、第二过孔和第三过孔，其中，所述第一过孔到达所述源极区域的上表面，所述第二过孔到达所述漏极区域的上表面，所述第三过孔到达所述遮光层的未被所述缓冲层覆盖的上表面；
在所述层间绝缘层上形成源极电极和漏极电极，其中，所述源极电极和漏极电极分别通过所述第一过孔和所述第二过孔而与所述源极区域和所述漏极连接，并且，所述源极电极和漏极电极中的一者通过所述第三过孔而与所述遮光层连接。
在一个实施例中，形成所述第一过孔、第二过孔和第三过孔采用一次刻蚀工艺。
在一个实施例中，所述缓冲层的厚度还被设置为使得光线不能经由所述缓冲层而入射到所述源极区域和所述漏极区域。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术薄膜晶体管的结构示意图；
图2为本申请实施例提供的一种薄膜晶体管结构示意图；
图3为本申请实施例提供的一种薄膜晶体管制备方法的流程示意图；
图4为本申请实施例提供的另一种薄膜晶体管制备方法的流程示意图。
具体实施方式
当介绍本公开文本的元素及其实施例时，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
在制作顶栅结构的氧化物TFT时通常在面板上制作一层遮光层进行遮光。如图1所示，一种顶栅结构的氧化物TFT结构包括：遮光层1、氧化硅层2、第一导体化区域3、沟道区域4、第二导体化区域5、栅绝缘层6、栅极7、层间绝缘层8、源极9以及漏极10。其中，图中箭头代表光路 方向，氧化硅层作为缓冲层，光可以通过氧化硅层。在图1的方案中，氧化硅层整层设置并且其厚度较厚，设置遮光层只能遮挡垂直于遮光层方向入射到沟道区域的光，非垂直于遮光层方向上的光仍然可以从氧化硅层的侧面入射到沟道区域，影响沟道区氧化物的电学特性。这样的顶栅结构氧化物TFT，对沟道区域的遮光效果较差，TFT的工作稳定性差。
本申请实施例提供了一种薄膜晶体管及其制备方法、阵列基板、显示面板，用以增强对薄膜晶体管的沟道区域的遮光效果，从而提高薄膜晶体管的光照稳定性，进而提高薄膜晶体管的工作稳定性。
本申请实施例提供的一种薄膜晶体管，如图2所示，该薄膜晶体管包括：遮光层1、位于所述遮光层1之上的缓冲层11以及位于所述缓冲层11之上的有源层(例如，半导体层)，所述有源层包括三：沟道区域4以及位于沟道区域4两侧的源极区域和漏极区域，其中，所述缓冲层11的厚度被设置为使得光线不能经由缓冲层11而入射到沟道区域。
在图2中，可以将源极区域和漏极区域中的一者设置为位于沟道区域左侧的第一导体化区域3，而将源极区域和漏极区域中的另一者设置为位于在沟道区域右侧的第二导体化区域5。为了描述方便起见，以下以源极区域为第一导体化区域3而漏极区域为第二导体化区域5且有源层为半导体层为示例进行说明。
在一个实施例中，缓冲层的厚度还被设置为使得光线不能经由源极区域和漏极区域而入射到沟道区。
该薄膜晶体管还包括：位于沟道区域4之上的栅绝缘层6、位于所述栅绝缘层6之上的栅极7、位于所述栅极7、所述第一导体化区域3、所述第二导体化区域5、所述缓冲层11和所遮光层1之上的绝缘层8、以及位于所述绝缘层8(例如，层间绝缘层)之上的源极9和漏极10；其中，绝缘层8包括第一过孔12、第二过孔13以及第三过孔14，所述源极9通过所述第一过孔12与所述第一导体化区域3连接，所述漏极10通过所述第二过孔13与所述第二导体化区域5连接，所述漏极电极10通过所述第三过孔14与所述遮光层1连接。可以理解，也可以将晶体管设置为其源极电 极通过第三过孔而与遮光层连接。
本申请实施例提供的一种薄膜晶体管，通过将该薄膜晶体管的缓冲层的厚度设置为使得光线不能经由缓冲层而入射到沟道区域。在一个实施例中，该薄膜晶体管的缓冲层的厚度被进一步设置为为使得光线不能经由该缓冲层而入射到源极区域和所述漏极区域。通过这样设置所述缓冲层的厚度，从而使得原本要入射到有源层(例如，半导体层)的光完全被遮住，从而使得光线无法通过缓冲层入射到有源层的沟道区域，从而可以增强对薄膜晶体管沟道区域的遮光效果，提高薄膜晶体管的光照稳定性，进而可以提高薄膜晶体管的工作稳定性。
需要说明的是，第一导体化区域3和第二导体化区域5是半导体层经过导体化处理之后形成的区域，而沟道区域4是半导体层中未经过导体化处理的区域。
在一个实施例中，所述遮光层为金属遮光层。这里的“金属”包括金属单质和金属合金。需要说明的是，将遮光层与薄膜晶体管源极电极、漏极电极中的低电位端连接，从而可以防止金属遮光层产生感应电荷对薄膜晶体管的特性造成影响。本申请实施例提供的如图2所示的薄膜晶体管，漏极电极作为源极电极和漏极电极中的低电位端，将遮光层与漏极电极相连。同理，当源极电极作为源极电极和漏极电极中的低电位端时，将源极电极通过第三过孔与遮光层相连。
在一个实施例中，所述遮光层的材料包括钼铌合金(MoNb)，所述缓冲层的材料包括氧化铝(AlO x)。这里的“x”可以包括非化学计量比当然，遮光层的材料也可以采用其他可以实现遮光功能的金属材料，缓冲层也可以采用其他金属氧化物。
在一个实施例中，所述氧化铝是铝钕合金(AlNd)通过阳极氧化处理形成的。
需要说明的是，AlNd通过阳极氧化处理形成AlO x作为缓冲层，AlO x致密性较好。相比于对现有技术中SiO x层进行减薄，可以避免在沉积薄层SiO x时造成的膜层真空数目多、膜层致密性差的问题，并且在相同的膜层 厚度条件下，AlO x的介电常数大于氧化硅的介电常数，本申请实施例选择AlO x作为缓冲层，可以在对缓冲层进行减薄的同时保证提高薄膜晶体管的性能。
在一个实施例中，所述缓冲层的厚度在约100nm～200nm范围内。
在一个实施例中，在平行于所述缓冲层的方向上，所述缓冲层的尺寸小于所述遮光层的尺寸。换而言之，缓冲层在遮光层上的投影落在遮光层内。因此，在一个实施例中，如图2所示的薄膜晶体管中，第一过孔12、第二过孔13以及第三过孔14可以在一次性刻蚀工艺中形成。
现有技术中的薄膜晶体管，氧化硅缓冲层较厚并整层设置，采用一次刻蚀工艺并不能将保证第三过孔刻穿，因此第三过孔与第一过孔和第二过孔的刻蚀分为两个步骤；本申请实施例提供的薄膜晶体管，由于缓冲层在遮光层上的投影落在遮光层内，并且所述缓冲层的厚度较薄，绝缘层在半导体层和遮光层区域的厚度区域大体一致，从而可以在导体化区域和遮光层区域同时刻蚀过孔，即可以采用一次刻蚀工艺形成第一过孔、第二过孔以及第三过孔，在保证过孔刻蚀精度的同时，简化了薄膜晶体管制备流程，降低了薄膜晶体管制备的工艺难度。
本申请实施例提供的一种阵列基板，包括本申请实施例提供的薄膜晶体管。
本申请实施例提供的一种显示面板，包括本申请实施例提供的阵列基板。
例如，本申请实施例提供的显示面板可以有机发光二极管(OLED)显示面板或液晶显示面板等。
本申请实施例提供的一种薄膜晶体管制备方法，如图3所示，该方法包括：
S301、在衬底基板上形成遮光层；
S302、在所述遮光层之上形成缓冲层；
S303、在所述缓冲层之上形成有源层(例如，半导体层)，所述有源层包括：沟道区域以及位于所述沟道区域两侧的源极区域和漏极区域，其 中，所述缓冲层的厚度被设置为使得光线不能经由所述缓冲层而入射到所述沟道区域。在一实施例中，该缓冲层的厚度还被设置为使得光线不能经由所述缓冲层而入射到所述源极区域和所述漏极区域。
在一个实施例中，遮光层包括可以金属，缓冲层可以包括金属氧化物。
在一个实施例中，形成遮光层和形成缓冲层包括：在衬底基板(例如，玻璃基板)上沉积作为遮光层的第一金属层(例如，钼铌合金)，在所述第一金属层(例如，钼铌合金)之上形成(例如，沉积)第二金属层(例如，铝钕合金)；对第二金属层进行氧化处理，以形成该缓冲层。
在一个实施例中，可以采用阳极氧化工艺对铝钕合金进行氧化处理，得到用作缓冲层的氧化铝。
下面以遮光层材料包括MoNb，缓冲层材料包括AlO x，有源层包括半导体层为示例，对本申请实施例提供的如图2所示的薄膜晶体管制备方法进行举例说明，薄膜晶体管制备步骤参见图4，具体如下：
S401、在玻璃基板15上沉积MoNb 16，在MoNb 16之上沉积薄层AlNd 17，涂覆光刻胶，光刻形成遮光层；
MoNb除了起到遮光作用外，还可以在薄膜晶体管制备过程中与玻璃基板存在较好的粘附性；
薄层AlNd的厚度例如可以是100nm～200nm；
S402、给遮光层施加电压，通过阳极氧化工艺使得AlNd17全部被氧化成AlO x18作为缓冲层；
S403、沉积半导体材料，刻蚀形成半导体层19；
S404、沉积栅绝缘层6材料，沉积栅极7材料，在顶层金属上涂覆光刻胶20，并刻蚀出栅极图形；
S405、之后以栅极图形为掩膜，通过自对准向下刻蚀形成栅绝缘层6，在刻蚀到半导体层之后，对半导体层进行导体化处理得到第一导体化区域3和第二导体化区域5，同时将第一导体化区域和第二导体化区域之外的缓冲层刻蚀掉，从而在第一导体化区域和第二导体化区域之外的区域露出遮光层；
S406、沉积层间绝缘层，采用一次干刻工艺形成第一过孔12、第二过孔13和第三过孔14；
S407、沉积源漏极金属层，刻蚀形成源极电极9和漏极电极10(其中，源极电极和漏极电极的位置可以互换，电极9也可以用作漏极电极而电极10也可以用作漏极电极)；
其中，所述源极9通过所述第一过孔12与所述第一导体化区域3连接，所述漏极10通过所述第二过孔13与所述第二导体化区域5连接，所述漏极10通过所述第三过孔14与MoNb 16层连接。
需要说明的是，步骤S402中，AlNd完全被氧化成AlO x，在制备薄膜晶体管的过程中，也可以控制给遮光层施加的电压，使得AlNd未完全被氧化，保留一定厚度的AlNd层。
本申请实施例提供的薄膜晶体管制备方法，采用阳极氧化工艺使得铝钕合金被氧化得到氧化铝作为缓冲层，工艺简单，易于实现。
综上所述，本申请实施例提供的一种薄膜晶体管、阵列基板、显示面板及薄膜晶体管制备方法，通过设置薄层的缓冲层，所述缓冲层的厚度被设置为使得光线不能经由缓冲层而入射到沟道区域，即设置所述缓冲层的厚度，从而使得原本要入射到有源层(例如，半导体层)的光完全被遮住，从而使得光线无法通过缓冲层入射到有源层的沟道区域，从而可以增强对薄膜晶体管沟道区域的遮光效果，提高薄膜晶体管的光照稳定性，进而可以提高薄膜晶体管的工作稳定性。此外，本申请实施例提供的薄膜晶体管，由于在缓冲层在遮光层上的投影落在遮光层内，并且所述缓冲层的厚度较薄，绝缘层在有源层和遮光层区域的厚度区域大体一致，从而可以在导体化区域和遮光层区域同时刻蚀过孔，即可以采用一次刻蚀工艺形成第一过孔、第二过孔以及第三过孔，在保证过孔刻蚀精度的同时，简化了薄膜晶体管制备流程，降低了薄膜晶体管制备的工艺难度。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在 内。

Claims (17)

  1. 一种薄膜晶体管包括：遮光层；位于所述遮光层之上的缓冲层；位于所述缓冲层之上的有源层，所述有源层包括沟道区域以及位于所述沟道区域两侧的源极区域和漏极区域，其中，所述缓冲层的厚度被设置为使得光线不能经由所述缓冲层而入射到所述沟道区域。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述遮光层包括金属，所述缓冲层包括金属氧化物。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述遮光层的材料包括钼铌合金，所述缓冲层的材料包括氧化铝。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述氧化铝是铝钕合金通过阳极氧化处理形成的。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述缓冲层的厚度在约100nm～200nm范围内。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述缓冲层在所述遮光层上的投影落在所述遮光层内。
  7. 根据权利要求5所述的薄膜晶体管，其中，所述薄膜晶体管还包括：位于所述沟道区域之上的栅绝缘层；位于所述栅绝缘层之上的栅极电极；位于所述栅极电极、所述源极区域、所述漏极区域、所述缓冲层和所遮光层之上的绝缘层；以及位于所述绝缘层之上的源极电极和漏极电极，其中，所述绝缘层包括第一过孔、第二过孔以及第三过孔，所述源极电极和所述漏极电极分别通过所述第一过孔和所述第二过孔而与所述源极区域和所述漏极区域连接，所述漏极电极和所述漏极中的一者通过所述第三过孔与所述遮光层连接。
  8. 根据权利要求1～7中任选一所述的薄膜晶体管，其中，所述缓冲层的厚度还被设置为使得光线不能经由所述缓冲层而入射到所述源极区域和所述漏极区域。
  9. 一种阵列基板，其中，包括权利要求1～8中任一权利要求所述的薄膜晶体管。
  10. 一种显示面板，其中，包括权利要求9所述的阵列基板。
  11. 一种薄膜晶体管制备方法，其中，该方法包括：
    在衬底基板上形成遮光层；
    在所述遮光层之上形成缓冲层；
    在所述缓冲层之上形成有源层，其中，所述有源层包括：沟道区域以及位于所述沟道区域两侧的源极区域和漏极区域，，
    其中，所述缓冲层的厚度被设置为使得光线不能经由所述缓冲层而入射到所述沟道区域。
  12. 根据权利要求11所述的方法，其中，所述遮光层包括金属，所述缓冲层包括金属氧化物。
  13. 根据权利要求12所述的方法，其中，形成所述遮光层和形成所述缓冲层包括：在所述衬底上形成作为所述遮光层的第一金属层；
    在所述第一金属层上形成第二金属层；
    对所述第二金属层进行氧化处理，以形成所述缓冲层。
  14. 根据权利要求13所述的方法，其中，所述第一金属包括钼铌合金，所述第二金属层包括铝钕合金；
    所述氧化处理包括：采用阳极氧化工艺对铝钕合金进行处理，以得到氧化铝。
  15. 根据权利要求11～14中任一项所述的方法，进一步包括：
    在所述沟道区域上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极电极；
    在所述栅极电极、所述源极区域、所述漏极区域、所述缓冲层和所述遮光层上形成绝缘层；
    在所述绝缘层上形成第一过孔、第二过孔和第三过孔，其中，所述第一过孔到达所述源极区域的上表面，所述第二过孔到达所述漏极区域的上表面，所述第三过孔到达所述遮光层的未被所述缓冲层覆盖的上表面；
    在所述层间绝缘层上形成源极电极和漏极电极，其中，所述源极电极和漏极电极分别通过所述第一过孔和所述第二过孔而与所述源极区域和 所述漏极连接，并且，所述源极电极和漏极电极中的一者通过所述第三过孔而与所述遮光层连接。
  16. 根据权利要求15所述的方法，其中，形成所述第一过孔、第二过孔和第三过孔采用一次刻蚀工艺。
  17. 根据权利要求11～14中任一项所述的方法，其中，所述缓冲层的厚度还被设置为使得光线不能经由所述缓冲层而入射到所述源极区域和所述漏极区域。
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