WO2020140763A1 - 显示基板、显示装置和显示基板的制造方法 - Google Patents

显示基板、显示装置和显示基板的制造方法 Download PDF

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WO2020140763A1
WO2020140763A1 PCT/CN2019/126652 CN2019126652W WO2020140763A1 WO 2020140763 A1 WO2020140763 A1 WO 2020140763A1 CN 2019126652 W CN2019126652 W CN 2019126652W WO 2020140763 A1 WO2020140763 A1 WO 2020140763A1
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Prior art keywords
electrode
substrate
active layer
layer
transistor
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PCT/CN2019/126652
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English (en)
French (fr)
Inventor
牛亚男
彭宽军
王久石
曹占锋
张锋
姚琪
黎午升
关峰
陈蕾
彭锦涛
周婷婷
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京东方科技集团股份有限公司
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Priority to US16/772,272 priority Critical patent/US11495623B2/en
Publication of WO2020140763A1 publication Critical patent/WO2020140763A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present disclosure belongs to the field of display technology, and more specifically, relates to a display substrate, a display device, and a method of manufacturing a display substrate.
  • the interlayer dielectric layer (usually made of inorganic material) in the lateral oxide semiconductor-based transistor is thick, and the interlayer in the oxide semiconductor-based transistor The dielectric layer is prone to cracks, which leads to a decrease in its insulation performance, and a tendency to cause poor leakage and breakdown, resulting in reduced reliability of the display substrate.
  • the present disclosure provides a display substrate including a first transistor on a substrate and including a first gate, a first electrode, a second electrode, and a first active layer, wherein the first gate
  • the electrode is located on the side of the first active layer away from the substrate, the first electrode and the second electrode are located on the side of the first gate away from the substrate, and the first electrode and the second electrode are connected to the first active layer;
  • Two transistors which are located on the substrate and on the same side of the substrate as the first transistor, and include a second gate, a third electrode, a fourth electrode, and a second active layer, wherein the fourth electrode is located away from the third electrode
  • the second active layer covers the sides of the third and fourth electrodes and is connected to the third and fourth electrodes, and the second gate is located on the side of the second active layer away from the substrate, wherein ,
  • the first transistor is a horizontal thin film transistor
  • the second transistor is a vertical thin film transistor
  • the first active layer includes silicon material
  • the second active layer includes oxide semiconductor
  • the second active layer includes a first portion and a second portion, the first portion covers the sides of the third electrode and the fourth electrode and is connected to the third electrode and the fourth electrode;
  • the four electrodes are located on the same side of the first part; and the second part is approximately parallel to the substrate.
  • the first transistor further includes: a first gate insulating layer between the first active layer and the first gate, wherein the first active layer is located near the first gate insulating layer The side of the base.
  • the second transistor further includes: a second gate insulating layer between the second active layer and the second gate, wherein the second active layer is located near the substrate of the second gate insulating layer And the orthographic projection of the second gate insulating layer on the substrate covers the orthographic projection of the second active layer on the substrate.
  • the display substrate further includes: a buffer layer located on the side of the first active layer close to the substrate; a driving electrode located on the side of the fourth electrode far from the substrate; and, a planarization layer , Which is located on the side of the driving electrode close to the substrate.
  • the present disclosure provides a display device including the display substrate according to the present disclosure, and one or more integrated circuits connected to the display substrate.
  • the present disclosure provides a method of manufacturing a display substrate, including: forming a first transistor on a substrate, the first transistor being formed as a horizontal thin film transistor and including a first gate, a first electrode, a second electrode, and a first An active layer; a second transistor is formed on the same side of the substrate, the second transistor is formed as a vertical thin film transistor and includes a second gate, a third electrode, a fourth electrode and a second active layer, wherein the first has The source layer includes a silicon material, the second active layer includes an oxide semiconductor material, the third electrode and the first gate are formed in the same layer, and the fourth electrode is formed in the same layer as the first electrode and the second electrode .
  • the steps of forming the first transistor and forming the second transistor include: forming a first active layer on the substrate; forming a first gate insulating layer on a side of the first active layer away from the substrate; The first gate and the third electrode are formed on the side of the first gate insulating layer away from the substrate through a patterning process, the first gate and the third electrode are formed to be separated from each other; An interlayer dielectric layer is formed on one side of the substrate; a first electrode, a second electrode, and a fourth electrode are formed on the side of the interlayer dielectric layer away from the substrate by a patterning process, the first electrode and the second electrode are formed Active layer connection; forming a slot in a predetermined area on the first gate insulating layer and the interlayer dielectric layer to expose the side of the third electrode; forming a second active layer in the slot, the second active layer is formed To connect with the side of the third electrode and the side of the fourth electrode, and the third electrode and the fourth electrode are located on the
  • the step of forming the second gate insulating layer on the side of the second active layer away from the substrate includes: forming a second gate insulating material film on the side of the second active layer away from the substrate; A patterning process is performed on the second gate insulating material film to form a second gate insulating layer, so that the orthographic projection of the second gate insulating layer on the substrate covers the orthographic projection of the second active layer on the substrate.
  • the method further includes: before the step of forming the first active layer on the substrate, forming a buffer layer on the substrate to cover the substrate; wherein the groove is formed such that the bottom surface of the groove and the buffer layer The surface of the side away from the base is at the same level.
  • the method further includes forming a gate line in a specific region of the interlayer dielectric layer on a side away from the substrate, so that the gate line is connected to the first gate.
  • the method further includes forming a planarization layer on the side of the first transistor and the second transistor away from the substrate to cover the first transistor and the second transistor.
  • the method further includes: forming a groove in the planarization layer, the groove being formed such that the bottom surface of the groove and the surface of the side of the fourth electrode away from the substrate are at the same level; and, A driving electrode is formed in the slot, wherein the driving electrode is formed to be connected to the fourth electrode.
  • the second gate insulating layer is formed such that the orthographic projection of the second gate insulating layer on the substrate completely overlaps the orthographic projection of the second active layer on the substrate.
  • FIG. 1 is a schematic diagram showing the structure of a display substrate according to some embodiments of the present disclosure
  • FIG. 2A to 2C illustrate a method of manufacturing a display substrate according to some embodiments of the present disclosure.
  • the present disclosure particularly provides a display substrate, a display device, and a method of manufacturing a display substrate, which substantially eliminates one or more of the problems due to limitations and defects of the related art.
  • the present disclosure provides a display substrate.
  • the display substrate includes: a first transistor on the substrate and including a first gate, a first electrode, a second electrode, and a first active layer; and a second transistor on the substrate and It is on the same side of the substrate as the first transistor and includes a second gate, a third electrode, a fourth electrode, and a second active layer.
  • the first transistor is a horizontal thin film transistor
  • the second transistor is a vertical thin film transistor
  • the first active layer includes silicon material
  • the second active layer includes oxide semiconductor material
  • the third electrode and the first gate It is arranged in the same layer
  • the fourth electrode is arranged in the same layer as the first electrode and the second electrode.
  • the phrase "disposed in the same layer” means that the two are formed by the same material layer and are therefore in the same layer in the stacking relationship, but this does not mean that the distance between them and the substrate is equal, It does not mean that the other layer structures between them and the substrate are identical.
  • the term "patterning process” refers to a step of forming a structure with a specific pattern, which may be a photolithography process, which includes forming a material layer, coating a photoresist, exposing, developing, etching, photolithography One or more of the steps such as stripping of the resist; of course, the “patterning process” can also be other processes such as imprinting process, inkjet printing process.
  • FIG. 1 is a schematic diagram illustrating the structure of a display substrate according to some embodiments of the present disclosure.
  • the display substrate includes a substrate 1, a first transistor and a second transistor provided on the substrate 1, wherein the first transistor is a horizontal thin film transistor and the second transistor is a vertical thin film transistor.
  • the first transistor includes: a first gate 32, a first electrode 33, a second electrode 34, and a first active layer 31, and the second transistor includes: a second gate 44, a third electrode 41, a fourth electrode 42, and a first Two active layers; the material of the first active layer 31 includes a silicon material, the material of the second active layer includes an oxide semiconductor material; the third electrode 41 and the first gate 32 are disposed in the same layer, and the fourth electrode 42 It is provided in the same layer as the first electrode 33 and the second electrode 34.
  • the second transistor is a vertical thin film transistor
  • the third electrode 41 of the second transistor is formed of a material layer forming the first gate 32 of the first transistor
  • the fourth electrode 42 of the second transistor It is formed of a material layer forming the first electrode 33 of the first transistor, and the third electrode 41 and the fourth electrode 42 in the second transistor are spaced apart by the interlayer dielectric layer 6 manufactured when the first transistor is formed.
  • the horizontal thin film transistor refers to: due to the structure, the carriers inside the transistor move along the horizontal direction of the transistor cross section, in other words, the carriers in the transistor channel are along the direction parallel to the substrate Movement;
  • vertical thin-film transistor refers to: due to the structure, the carrier inside the transistor moves along the vertical direction of the transistor cross-section, in other words, the carrier in the transistor channel moves in a direction perpendicular to the substrate.
  • the thickness of the inorganic substance in the display substrate is reduced.
  • the third electrode and the fourth electrode (that is, the source and drain) in the second transistor are both arranged in the same layer as the structure in the first transistor, this further reduces the number of electrodes configured to form the second transistor Layer (also an inorganic material). The above two effects reduce the thickness of the inorganic substance in the display substrate, which is beneficial to improve the reliability of the display substrate.
  • a first gate insulating layer 5 is provided between the first active layer 31 and the first gate 32, and the first active layer 31 is located on the side of the first gate insulating layer 5 close to the substrate 1 , That is, the first transistor is a top-gate thin film transistor.
  • the first transistor is a bottom-gate thin film transistor, it can also be applied in this application.
  • the second active layer includes a first portion 431, the first portion 431 is located on the side of the third electrode 41 and the fourth electrode 42, and the third electrode 41 and the fourth electrode 42 are located on the same side of the first portion 431; The side of the third electrode 41 facing the first portion 431 and the side of the fourth electrode 42 facing the first portion 431 are connected to the first portion 431. The first part 431 is connected to both the third electrode 41 and the fourth electrode 42. In subsequent applications, a conductive channel is formed in the first portion 431.
  • a first gate insulating layer 5 is provided between the first active layer 31 and the first gate 32, and the first active layer 31 is located on the side of the first gate insulating layer 5 close to the substrate 1 .
  • the display substrate further includes a buffer layer 2 disposed between the base 1 and the first active layer 31 and laid in an entire layer to cover the base 1.
  • the first active layer 31 is in contact with the buffer layer 2; the second active layer further includes The second portion 432 connected to the first portion 431 is substantially parallel to the substrate 1 and in contact with the surface of the buffer layer 2 away from the substrate 1 as the manufacturing process allows.
  • the second portion 432 is provided to ensure that the contact portion between the third electrode 41 and the second active layer is not too close to the boundary of the second active layer.
  • the second portion 432 is located on the upper surface of the buffer layer 2.
  • the position of the second portion 432 may be further away from the substrate 1 than this embodiment, and the function of the second transistor may also be achieved.
  • a second gate insulating layer 7 is provided between the second active layer and the second gate 44; the orthographic projection of the second gate insulating layer 7 on the substrate 1 and the second active layer on the substrate The orthographic projections on 1 completely overlap. Since the role of the second gate insulating layer 7 is only to separate the second gate 44 from the second active layer, the area of the second gate insulating layer 7 can be as small as possible, which is to further reduce the thickness of the inorganic substance in the display substrate . In this extreme case, the boundary of the second gate insulating layer 7 and the boundary of the second active layer are flush. Of course, the area of the second gate insulating layer 7 may also be larger than that of this embodiment, as shown in FIG. 1. In some embodiments, the second gate insulating layer 7 may also be arranged such that its orthographic projection on the substrate 1 does not overlap with the orthographic projection of the first transistor on the substrate 1.
  • the present disclosure provides a display device including the display substrate described herein or manufactured by the method described herein and one or more integrated circuits connected to the display substrate.
  • the display device may be any product or component with a display function such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • OLED organic light-emitting diode
  • the present disclosure provides a method of manufacturing a display substrate.
  • the method includes: forming a first transistor on the substrate 1, the first transistor is a horizontal thin film transistor, the first transistor includes a first gate 32, a first electrode 33, a second electrode 34 and a first The source layer 31, the first active layer 31 includes a silicon material; a second transistor is formed on the substrate 1, the second transistor is a vertical thin film transistor, the second transistor includes a second gate 44, a third electrode 41, a fourth electrode 42 and a second active layer, the second active layer includes an oxide semiconductor material, wherein the third electrode 41 and the first gate 32 are formed in the same layer, and the fourth electrode 42 and the first electrode 33, the first The two electrodes 34 are formed in the same layer.
  • the first gate electrode 32 and the third electrode 41 are manufactured using the same material layer, and the fourth electrode 42, the first electrode 33, and the second electrode 34 are manufactured using the same material layer, so that the thickness of the inorganic substance in the display substrate can be reduced .
  • 2A to 2C illustrate a method of manufacturing a display substrate according to some embodiments of the present disclosure.
  • the steps of forming the first transistor and forming the second transistor specifically include the following steps.
  • a first active layer 31 made of silicon material is formed on the substrate 1.
  • the substrate 1 may be a substrate of a flexible material or a rigid substrate such as glass.
  • the first active layer 31 may be formed after forming a barrier layer (Barrier) and a buffer layer 2 (Buffer) on the substrate 1.
  • the outer shape of the first active layer 31 is obtained through a patterning process.
  • the silicon material may be amorphous silicon or polysilicon obtained by dehydrogenating amorphous silicon and laser annealing process.
  • the first gate insulating layer 5 is formed on the side of the first active layer 31 away from the substrate 1.
  • the first gate electrode 32 and the third electrode 41 are formed on the side of the first gate insulating layer 5 away from the substrate 1 through a patterning process. That is, the first gate electrode 32 of the first transistor and the third electrode 41 of the second transistor are simultaneously formed using the same material layer.
  • the first interlayer dielectric layer 6 is formed on the side of the first gate electrode 32 and the third electrode 41 away from the substrate 1.
  • the first electrode 33, the second electrode 34, and the fourth electrode 42 are formed on the side of the first interlayer dielectric layer 6 away from the substrate 1 by a patterning process, wherein the first electrode 33 and the second electrode 34 It is formed to be connected to the first active layer 31, and the fourth electrode 42 and the third electrode 41 are formed to be sequentially arranged in a direction perpendicular to the substrate 1. That is, the first electrode 33, the second electrode 34, and the fourth electrode 42 of the second transistor are simultaneously formed using the same material layer.
  • the product form at this time is shown in FIG. 2A. At this time, the gate lines 32a may be formed simultaneously.
  • a groove is formed in a predetermined area on the first gate insulating layer 5 and the first interlayer dielectric layer 6, so that the side of the third electrode 41 is exposed, as shown in FIG. 2B.
  • the purpose of the slot is to expose the side of the third electrode 41, and of course the side of the fourth electrode 42 is also exposed before.
  • the grooved bottom surface is at the same level as the surface of the buffer layer 2 away from the base 1. In some embodiments, the grooved bottom surface may also be slightly lower than the surface of the buffer layer 2 away from the substrate 1. In practical applications, considering the width-to-length ratio of the slot and the requirements of the process, the bottom surface of the slot may also be higher than the surface of the buffer layer 2 away from the substrate 1, for example, during slotting, only part of the first gate insulation is removed Layer 5.
  • a second active layer is formed in the slot, the side surfaces of the third electrode 41 and the fourth electrode 42 are connected to the second active layer, and the third electrode 41 and the fourth electrode 42 are located in the second The same side of the source layer. Since the side surfaces of the third electrode 41 and the fourth electrode 42 in the same direction are exposed after the sixth step is completed, a second active layer is formed on these two side surfaces, thus forming a structure of a vertical thin film transistor.
  • a second gate insulating layer 7 is formed on the side of the second active layer away from the substrate 1.
  • the second gate insulating layer 7 may have an entire layer structure, or may be distributed only in the region where the second transistor is provided.
  • forming the second gate insulating layer 7 specifically includes: first, forming a second gate insulating material film on the side of the second active layer away from the substrate 1; subsequently, patterning the second gate insulating material film Process to remove part of the second gate insulating material, the remaining second gate insulating material constitutes the second gate insulating layer 7, the orthographic projection of the second gate insulating layer 7 on the substrate 1 covers the second active layer on the substrate 1 Orthographic projection.
  • the orthographic projection of the second gate insulating layer 7 on the substrate 1 completely overlaps the orthographic projection of the second active layer on the substrate 1.
  • the second gate 44 is formed on the side of the second gate insulating layer 7 away from the substrate 1. Specifically, a patterning process is used to obtain the shape of the second gate 44. The product form after this step is completed is shown in FIG. 2C.
  • the subsequent process can be performed according to the existing technology.
  • a structure such as a planarization layer 8, a driving electrode 9 (which can be used as an anode of an organic light-emitting diode), a pixel defining layer 10, and a support pillar 11 are then formed.
  • FIG. 1 shows a partial structure of an organic light emitting diode display substrate.
  • the driving electrode 9 may also be used to drive the liquid crystal to turn over.

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Abstract

本公开提供了显示基板、显示装置和显示基板的制造方法。本公开的显示基板中，第一晶体管包括：第一栅极、第一电极、第二电极和第一有源层，第二晶体管包括：第二栅极、第三电极、第四电极和第二有源层；第一有源层包括硅材料，第二有源层包括氧化物半导体材料；第三电极与第一栅极设置在同一层中，并且第四电极与第一电极、第二电极设置在同一层中。

Description

显示基板、显示装置和显示基板的制造方法 技术领域
本公开属于显示技术领域，更具体地，涉及显示基板、显示装置、显示基板的制造方法。
背景技术
现有技术中已出现将硅基晶体管与氧化物半导体基晶体管制造在同一显示基板上的方案，二者均为横向(水平型)晶体管。受制于横向氧化物半导体基晶体管的驱动能力以及其器件的稳定性，横向氧化物半导体基晶体管中的层间介质层(通常是由无机材料构成)较厚，氧化物半导体基晶体管中的层间介质层中容易产生裂纹，导致其绝缘性能下降、容易发生漏电和击穿的不良，造成显示基板可靠性降低。
发明内容
一方面，本公开提供一种显示基板，该显示基板包括第一晶体管，其位于基底上，并且包括第一栅极、第一电极、第二电极和第一有源层，其中，第一栅极位于第一有源层的远离基底的一侧，第一电极和第二电极位于第一栅极的远离基底的一侧，并且第一电极和第二电极与第一有源层连接；第二晶体管，其位于基底上并且与第一晶体管在基底的同一侧，并且包括第二栅极、第三电极、第四电极和第二有源层，其中，第四电极位于第三电极的远离基底的一侧，第二有源层覆盖第三电极和第四电极的侧面且与第三电极和第四电极连接，并且第二栅极位于第二有源层的远离基底的一侧，其中，第一晶体管为水平型薄膜晶体管，第二晶体管为垂直型薄膜晶体管；第一有源层包括硅材料，第二有源层包括氧化物半导体材料；第三电极与第一栅极设置在同一层中，并且第四电极与第一电极、第二电极设置在同一层中。
根据本公开的一些实施例，第二有源层包括第一部分和第二部分，该第一部分覆盖第三电极和第四电极的侧面且与第三电极和第四电极连接；第三电极和第四电极位于第一部分的同一侧；并且第二部分与 基底大致平行。
根据本公开的一些实施例，第一晶体管还包括：第一栅绝缘层，其位于第一有源层和第一栅极之间，其中，第一有源层位于第一栅绝缘层的靠近基底的一侧。
根据本公开的一些实施例，第二晶体管还包括：第二栅绝缘层，其位于第二有源层和第二栅极之间其中，第二有源层位于第二栅绝缘层的靠近基底的一侧，并且第二栅绝缘层在基底上的正投影覆盖第二有源层在基底上的正投影。
根据本公开的一些实施例，显示基板还包括：缓冲层，其位于第一有源层的靠近基底的一侧；驱动电极，其位于第四电极的远离基底的一侧；以及，平坦化层，其位于驱动电极的靠近基底的一侧。
另一方面，本公开提供一种显示装置，包括根据本公开的显示基板、以及与显示基板连接的一个或多个集成电路。
另一方面，本公开提供一种显示基板的制造方法，包括：在基底上形成第一晶体管，第一晶体管形成为水平型薄膜晶体管并且包括第一栅极、第一电极、第二电极和第一有源层；在基底的同一侧形成第二晶体管，第二晶体管形成为垂直型薄膜晶体管并且包括第二栅极、第三电极、第四电极和第二有源层，其中，第一有源层包括硅材料，第二有源层包括氧化物半导体材料，第三电极与第一栅极形成为在同一层中，并且第四电极与第一电极、第二电极形成为在同一层中。
根据本公开的一些实施例，形成第一晶体管和形成第二晶体管的步骤包括：在基底上形成第一有源层；在第一有源层的远离基底的一侧形成第一栅绝缘层；通过一次构图工艺在第一栅绝缘层的远离基底的一侧形成第一栅极和第三电极，第一栅极与第三电极形成为彼此分离；在第一栅极和第三电极的远离基底的一侧形成层间介质层；通过一次构图工艺在层间介质层的远离基底的一侧形成第一电极、第二电极和第四电极，第一电极和第二电极形成为与第一有源层连接；在第一栅绝缘层和层间介质层上的预定区域形成开槽，以使得第三电极的侧面露出；在开槽内形成第二有源层，第二有源层形成为与第三电极的侧面和第四电极的侧面连接，并且第三电极和第四电极位于第二有 源层的同一侧；在第二有源层的远离基底的一侧形成第二栅绝缘层；以及，在第二栅绝缘层的远离基底的一侧形成第二栅极。
根据本公开的一些实施例，在第二有源层的远离基底的一侧形成第二栅绝缘层的步骤包括：在第二有源层的远离基底的一侧形成第二栅绝缘材料薄膜；对第二栅绝缘材料薄膜进行构图工艺以形成第二栅绝缘层，使得第二栅绝缘层在基底上的正投影覆盖第二有源层在基底上的正投影。
根据本公开的一些实施例，方法还包括：在基底上形成第一有源层的步骤之前，在基底上形成缓冲层以覆盖基底；其中，开槽形成为使得开槽的底表面与缓冲层的远离基底的一侧的表面在同一水平。
根据本公开的一些实施例，方法还包括：在层间介质层的远离基底的一侧的特定区域形成栅线，使得栅线与第一栅极连接。
根据本公开的一些实施例，方法还包括：在第一晶体管和第二晶体管的远离基底的一侧形成平坦化层，以覆盖第一晶体管和第二晶体管。
根据本公开的一些实施例，方法还包括：在平坦化层中形成开槽，开槽形成为使得开槽的底表面与第四电极的远离基底的一侧的表面在同一水平；以及，在开槽中形成驱动电极，其中，驱动电极形成为与第四电极连接。
根据本公开的一些实施例，第二栅绝缘层形成为使得第二栅绝缘层在基底上的正投影与第二有源层在基底上的正投影完全重叠。
附图说明
以下附图仅为根据所公开的各种实施例的用于示意性目的的示例，而不旨在限制本发明的范围。
图1是示出根据本公开的一些实施例的显示基板的结构的示意图；
图2A至图2C示出了根据本公开的一些实施例的制造显示基板的方法。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施例对本公开作进一步详细描述。应注意，本文仅出于说明和描述的目的呈现了一些实施例的以下描述。其并非旨在穷举或限于所公开的精确形式，并且为了避免冗余而省略相同部分。
本公开特别提供了显示基板、显示装置和显示基板的制造方法，其实质上消除了由于相关技术的限制和缺陷而导致的问题中的一个或多个。在一方面，本公开提供了一种显示基板。在一些实施例中，显示基板包括：第一晶体管，其位于基底上，并且包括第一栅极、第一电极、第二电极和第一有源层；以及第二晶体管，其位于基底上并且与第一晶体管在基底的同一侧，并且包括第二栅极、第三电极、第四电极和第二有源层。其中，第一晶体管为水平型薄膜晶体管，第二晶体管为垂直型薄膜晶体管；第一有源层包括硅材料，第二有源层包括氧化物半导体材料；并且，第三电极与第一栅极设置在同一层中，第四电极与第一电极、第二电极设置在同一层中。
在本申请中，短语“设置在同一层中”是指二者是由同一个材料层形成并且因此在层叠关系上处于同一层中，但这并不代表它们与基底之间的距离相等，也不代表它们与基底之间的其它层结构完全相同。
在本申请中，术语“构图工艺”是指形成具有特定图形的结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步；当然，“构图工艺”也可为压印工艺、喷墨打印工艺等其它工艺。
图1是示出根据本公开的一些实施例的显示基板的结构的示意图。参照图1，显示基板包括基底1、设置在基底1上的第一晶体管和第二晶体管，其中，第一晶体管为水平型薄膜晶体管，第二晶体管为垂直型薄膜晶体管。第一晶体管包括：第一栅极32、第一电极33、第二电极34和第一有源层31，第二晶体管包括：第二栅极44、第三电极41、第四电极42和第二有源层；第一有源层31的材料包括硅材料，第二有源层的材料包括氧化物半导体材料；第三电极41与第一栅极32设置在同一层中，第四电极42与第一电极33、第二电极34设置在同一层中。
在这种结构的显示基板中，第二晶体管为垂直型薄膜晶体管，第二晶体管的第三电极41由形成第一晶体管的第一栅极32的材料层形成，第二晶体管的第四电极42由形成第一晶体管的第一电极33的材料层形成，并且第二晶体管中的第三电极41和第四电极42之间通过形成第一晶体管时制造的层间介质层6间隔开。
在本申请中，水平型薄膜晶体管指的是：由于结构的关系，晶体管内部的载流子是沿着晶体管断面的水平方向运动的，换言之，晶体管沟道中载流子沿着与基底平行的方向运动；垂直型薄膜晶体管指的是：由于结构的关系，晶体管内部的载流子是沿着晶体管断面的垂直方向运动的，换言之，晶体管沟道中载流子沿着与基底垂直的方向运动。
由于无需像现有技术那样为氧化物半导体基薄膜晶体管配置较厚的层间介质层，减少了显示基板中无机物的厚度。此外，由于第二晶体管中的第三电极和第四电极(也即是源漏极)均与第一晶体管中的结构设置在同一层中，这进一步减少了为形成第二晶体管而配置的电极层(也是无机物材料)。以上两方面的效应都减少了显示基板中无机物的厚度，有利于提高显示基板的可靠性。
在一些实施例中，在第一有源层31和第一栅极32之间设置有第一栅绝缘层5，第一有源层31位于第一栅绝缘层5的靠近基底1的一侧，也即第一晶体管为顶栅型薄膜晶体管。当然，第一晶体管如果为底栅型薄膜晶体管也可以应用于本申请中。
在一些实施例中，第二有源层包括第一部分431，第一部分431位于第三电极41和第四电极42的侧面，并且第三电极41和第四电极42位于第一部分431的同一侧；第三电极41的朝向第一部分431的侧面和第四电极42朝向第一部分431的侧面与第一部分431连接。第一部分431与第三电极41和第四电极42均连接。在后续应用中，第一部分431中形成导电沟道。
在一些实施例中，在第一有源层31和第一栅极32之间设置有第一栅绝缘层5，第一有源层31位于第一栅绝缘层5的靠近基底1的一侧。显示基板还包括设置在基底1与第一有源层31之间并且整层铺设 以覆盖基底1的缓冲层2，第一有源层31与缓冲层2接触；第二有源层还包括与第一部分431连接的第二部分432，第二部分432在制造工艺允许的情况下与基底1大致平行并且与缓冲层2的远离基底1的表面接触。
第二部分432的设置是为了保证第三电极41与第二有源层的接触部分不要过于靠近第二有源层的边界。在这种实施方式中，第二部分432位于缓冲层2的上表面。当然，第二部分432的位置也可以比这种实施方式更远离基底1一些，同样可实现第二晶体管的功能。
在一些实施例中，在第二有源层和第二栅极44之间设置有第二栅绝缘层7；第二栅绝缘层7在基底1上的正投影与第二有源层在基底1上的正投影完全重叠。由于第二栅绝缘层7的作用仅是将第二栅极44与第二有源层间隔开，第二栅绝缘层7的面积可以尽量小，这也是进一步减少显示基板中无机物的厚度。在这种极限情况下，第二栅绝缘层7的边界与第二有源层的边界是平齐的。当然，第二栅绝缘层7也可以比这种实施方式的面积更大一些，如图1所示。在一些实施例中，第二栅绝缘层7也可以设置为其在基底1上的正投影与第一晶体管在基底1上的正投影无重叠等。
另一方面，本公开提供了一种显示装置，其包括本文所述的或通过本文所述的方法制造的显示基板以及与显示基板连接的一个或多个集成电路。具体地，显示装置可为液晶显示面板、有机发光二极管(OLED)显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
另一方面，本公开提供了一种显示基板的制造方法。在一些实施例中，方法包括：在基底1上形成第一晶体管，第一晶体管为水平型薄膜晶体管，第一晶体管包括第一栅极32、第一电极33、第二电极34和第一有源层31，第一有源层31包括硅材料；在基底1上形成第二晶体管，第二晶体管为垂直型薄膜晶体管，第二晶体管包括第二栅极44、第三电极41、第四电极42和第二有源层，第二有源层包括氧化物半导体材料，其中，第三电极41与第一栅极32形成为在同一层中，并且第四电极42与第一电极33、第二电极34形成为在同一层中。
也就是，利用同一材料层制造第一栅极32和第三电极41，并且利用同一材料层制造第四电极42、第一电极33、第二电极34，从而可以减少显示基板中无机物的厚度。
图2A至图2C示出了根据本公开的一些实施例的制造显示基板的方法。参照图2A至图2C，形成第一晶体管和形成第二晶体管的步骤具体包括以下步骤。
第一步，在基底1上形成由硅材料构成的第一有源层31。基底1可以是柔性材料的基底，也可以是诸如玻璃之类的刚性基底。在一些实施例中，还可以在基底1上制作阻挡层(Barrier)以及缓冲层2(Buffer)之后再形成第一有源层31。通过构图工艺得到第一有源层31的外形。其中，硅材料可以是非晶硅，也可以是将非晶硅进行脱氢以及激光退火工艺得到的多晶硅。
第二步，在第一有源层31的远离基底1的一侧形成第一栅绝缘层5。
第三步，通过一次构图工艺在第一栅绝缘层5的远离基底1的一侧形成第一栅极32和第三电极41。即采用同一材料层同时形成第一晶体管的第一栅极32和第二晶体管的第三电极41。
第四步，在第一栅极32和第三电极41的远离基底1的一侧形成第一层间介质层6。
第五步，通过一次构图工艺在第一层间介质层6的远离基底1的一侧形成第一电极33、第二电极34和第四电极42，其中，第一电极33和第二电极34形成为与第一有源层31连接，并且第四电极42和第三电极41形成为沿与基底1垂直的方向依次设置。即采用同一材料层同时形成第一晶体管的第一电极33、第二电极34、第二晶体管的第四电极42。此时的产品形态如图2A所示。此时，也可以同步形成栅线32a。
第六步，在第一栅绝缘层5和第一层间介质层6上的预定区域形成开槽，以使得第三电极41的侧面露出，如图2B所示。开槽的目的是暴露第三电极41的侧面，当然第四电极42的侧面此前也是暴露的。
在一些实施例中，在显示基板中形成有缓冲层2的情况下，开槽 的底表面与缓冲层2的远离基底1的表面在同一水平。在一些实施例中，开槽的底表面也可以略低于缓冲层2的远离基底1的表面。在实际应用中，考虑开槽的宽长比以及工艺的要求，开槽的底表面也可以高于缓冲层2的远离基底1的表面，例如，在开槽时，仅去除部分第一栅绝缘层5。
第七步，在开槽内形成第二有源层，第三电极41的侧面和第四电极42的侧面与第二有源层连接，并且第三电极41和第四电极42位于第二有源层的同一侧。由于第六步完成后第三电极41和第四电极42的同一方向的侧面均暴露出，在这两个侧面向形成第二有源层，如此形成垂直型薄膜晶体管的结构。
第八步，在第二有源层的远离基底1的一侧形成第二栅绝缘层7。第二栅绝缘层7可以是整层结构，也可以仅在第二晶体管设置的区域有分布。在一些实施例中，形成第二栅绝缘层7具体包括：首先，在第二有源层的远离基底1的一侧形成第二栅绝缘材料薄膜；随后，对第二栅绝缘材料薄膜进行构图工艺，以去除部分第二栅绝缘材料，保留的第二栅绝缘材料构成第二栅绝缘层7，第二栅绝缘层7在基底1上的正投影覆盖第二有源层在基底1上的正投影。在一些实施例中，第二栅绝缘层7在基底1上的正投影与第二有源层在基底1上的正投影完全重叠。
第九步，在第二栅绝缘层7的远离基底1的一侧形成第二栅极44。具体地，利用构图工艺得到第二栅极44的形状。该步骤完成后的产品形态如图2C所示。
完成第九步之后，可以依据现有技术进行后续的工艺。例如如图1所示，随后形成平坦化层8、驱动电极9(可以作为有机发光二极管的阳极)、像素界定层10、支撑柱11等结构。图1示出的是有机发光二极管显示基板的部分结构，当然驱动电极9也可以是用来驱动液晶翻转的。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出 各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (14)

  1. 一种显示基板，包括：
    第一晶体管，位于基底上，并且包括第一栅极、第一电极、第二电极和第一有源层，其中，所述第一栅极位于所述第一有源层的远离所述基底的一侧，所述第一电极和所述第二电极位于所述第一栅极的远离所述基底的一侧，并且所述第一电极和所述第二电极与所述第一有源层连接；和
    第二晶体管，位于所述基底上并且与所述第一晶体管在所述基底的同一侧，并且包括第二栅极、第三电极、第四电极和第二有源层，其中，所述第四电极位于所述第三电极的远离所述基底的一侧，所述第二有源层覆盖所述第三电极和所述第四电极的侧面且与所述第三电极和所述第四电极连接，并且所述第二栅极位于所述第二有源层的远离所述基底的一侧；
    其中，所述第一晶体管为水平型薄膜晶体管，所述第二晶体管为垂直型薄膜晶体管；
    所述第一有源层包括硅材料，所述第二有源层包括氧化物半导体材料；并且
    所述第三电极与所述第一栅极设置在同一层中，所述第四电极与所述第一电极、所述第二电极设置在同一层中。
  2. 根据权利要求1所述的显示基板，其中所述第二有源层包括第一部分和第二部分，所述第一部分覆盖所述第三电极和所述第四电极的侧面且与所述第三电极和所述第四电极电连接；
    所述第三电极和所述第四电极位于所述第一部分的同一侧；并且所述第二部分与所述基底大致平行。
  3. 根据权利要求1至2任一项所述的显示基板，其中
    所述第一晶体管还包括：第一栅绝缘层，其位于所述第一有源层和所述第一栅极之间，
    其中，所述第一有源层位于所述第一栅绝缘层的靠近所述基底的一侧。
  4. 根据权利要求2或3所述的显示基板，其中
    所述第二晶体管还包括：第二栅绝缘层，其位于所述第二有源层和所述第二栅极之间，
    其中，所述第二有源层位于所述第二栅绝缘层的靠近所述基底的一侧，并且
    所述第二栅绝缘层在所述基底上的正投影覆盖所述第二有源层在所述基底上的正投影。
  5. 根据权利要求4所述的显示基板，还包括：
    缓冲层，其位于所述第一有源层的靠近所述基底的一侧；
    驱动电极，其位于所述第四电极的远离所述基底的一侧；以及
    平坦化层，其位于所述驱动电极的靠近所述基底的一侧。
  6. 一种显示装置，包括权利要求1至5中任一项所述的显示基板、以及与所述显示基板连接的一个或多个集成电路。
  7. 一种显示基板的制造方法，包括：
    在基底上形成第一晶体管，所述第一晶体管形成为水平型薄膜晶体管并且包括第一栅极、第一电极、第二电极和第一有源层；
    在所述基底的同一侧形成第二晶体管，所述第二晶体管形成为垂直型薄膜晶体管并且包括第二栅极、第三电极、第四电极和第二有源层，
    其中，所述第一有源层包括硅材料，所述第二有源层包括氧化物半导体材料，并且
    所述第三电极与所述第一栅极形成为在同一层中，所述第四电极与所述第一电极、所述第二电极形成为在同一层中。
  8. 根据权利要求7所述的制造方法，其中
    形成所述第一晶体管和形成所述第二晶体管的步骤包括：
    在所述基底上形成所述第一有源层；
    在所述第一有源层的远离所述基底的一侧形成第一栅绝缘层；
    通过一次构图工艺在所述第一栅绝缘层的远离所述基底的一侧形成所述第一栅极和所述第三电极，所述第一栅极与所述第三电极形成为彼此分离；
    在所述第一栅极和所述第三电极的远离所述基底的一侧形成层间介质层；
    通过一次构图工艺在所述层间介质层的远离所述基底的一侧形成所述第一电极、所述第二电极和所述第四电极，所述第一电极和所述第二电极形成为与所述第一有源层连接；
    在所述第一栅绝缘层和所述层间介质层上的预定区域形成开槽，以使得所述第三电极的侧面露出；
    在所述开槽内形成所述第二有源层，所述第二有源层形成为与所述第三电极的侧面和所述第四电极的侧面连接，并且所述第三电极和所述第四电极位于所述第二有源层的同一侧；
    在所述第二有源层的远离所述基底的一侧形成所述第二栅绝缘层；以及
    在所述第二栅绝缘层的远离所述基底的一侧形成所述第二栅极。
  9. 根据权利要求8所述的制造方法，其中
    在所述第二有源层的远离所述基底的一侧形成所述第二栅绝缘层的步骤包括：
    在所述第二有源层的远离所述基底的一侧形成第二栅绝缘材料薄膜；
    对所述第二栅绝缘材料薄膜进行构图工艺以形成所述第二栅绝缘层，使得所述第二栅绝缘层在所述基底上的正投影覆盖所述第二有源层在所述基底上的正投影。
  10. 根据权利要求9所述的制造方法，还包括：
    在所述基底上形成所述第一有源层的步骤之前，在所述基底上形成缓冲层以覆盖所述基底；
    其中，所述开槽形成为使得所述开槽的底表面与所述缓冲层的远离所述基底的一侧的表面在同一水平。
  11. 根据权利要求10所述的制造方法，还包括：
    在所述层间介质层的远离所述基底的一侧的特定区域形成栅线，使得所述栅线与所述第一栅极连接。
  12. 根据权利要求11所述的制造方法，还包括：
    在所述第一晶体管和所述第二晶体管的远离所述基底的一侧形成平坦化层，以覆盖所述第一晶体管和所述第二晶体管。
  13. 根据权利要求12所述的制造方法，还包括：
    在所述平坦化层中形成开槽，所述开槽形成为使得所述开槽的底表面与所述第四电极的远离所述基底的一侧的表面在同一水平；以及
    在所述开槽中形成驱动电极，
    其中，所述驱动电极形成为与所述第四电极连接。
  14. 根据权利要求9所述的制造方法，其中
    所述第二栅绝缘层形成为使得所述第二栅绝缘层在所述基底上的正投影与所述第二有源层在所述基底上的正投影完全重叠。
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