WO2018170972A1 - 优化4m制程的tft阵列制备方法 - Google Patents

优化4m制程的tft阵列制备方法 Download PDF

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WO2018170972A1
WO2018170972A1 PCT/CN2017/080508 CN2017080508W WO2018170972A1 WO 2018170972 A1 WO2018170972 A1 WO 2018170972A1 CN 2017080508 W CN2017080508 W CN 2017080508W WO 2018170972 A1 WO2018170972 A1 WO 2018170972A1
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layer
tft array
source
drain
fabricating
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刘晓娣
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing

Definitions

  • the present invention relates to the field of liquid crystal displays, and in particular, to a method for preparing a TFT array for optimizing a 4M process.
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • FIG. 1 is a schematic diagram of a conventional 4M process, showing a second mask process in the existing 4M process.
  • Existing 4M processes generally include:
  • the gate layer 12 is formed on the glass substrate 11, and the gate layer 12 is patterned; then the gate insulating layer 13, the active layer, the source and drain layers 16, and the photoresist layer are prepared. 17, the active layer may include a channel layer 14, a contact layer 15;
  • the second mask in this example is a gray scale mask, and the photoresist layer 17 is exposed and developed; the first wet etching, patterning the source and drain layers 16 to form a source and drain region And the metal wire structure of the active region; the first dry etching forms an active layer island structure, that is, the patterned channel layer 14, the contact layer 15; oxygen ashing, reducing the thickness of the photoresist layer 17 to expose the trench The source and drain layers 16 of the track region; the second wet etching, patterning the source and drain; the second etching, etching the active layer, that is, etching the channel layer 14 and the contact layer 15 to form a thin film transistor structure;
  • a transparent electrode layer is prepared and the transparent electrode layer is patterned.
  • the present invention provides a method for preparing a TFT array for optimizing a 4M process, including:
  • Step 10 in the first mask process, preparing a gate layer on the glass substrate, and patterning the gate layer; then preparing a gate insulating layer, an active layer, a source drain layer, and a photoresist layer;
  • Step 20 in the second mask process, the photoresist layer is exposed and developed; the first wet etching, patterning the source and drain layers, forming the source and drain regions and the active region of the metal wire structure; Oxygen ashing reduces the size of the active layer tailing of the source and drain metal layers; the first dry etching forms an active layer island structure; the second oxygen ashing reduces the thickness of the photoresist layer to expose the channel region Source drain layer; second wet etching, patterned source and drain; third oxygen ashing, reducing contact layer tailing; second dry etching, etching active layer to form a thin film transistor structure;
  • Step 30 in the third mask process, preparing a passivation layer, and patterning the passivation layer;
  • Step 40 In the fourth mask process, a transparent electrode layer is prepared, and the transparent electrode layer is patterned.
  • the TFT array is a TFT array of a display area or a GOA circuit area.
  • the second mask is a gray scale mask or a halftone mask.
  • the gate layer is prepared by sputtering, sol-gel, atomic layer deposition, evaporation, or printing.
  • the material of the gate layer is Cu, Cu/Mo, Mo/Cu/Mo, MoNb/Cu/MoNb, Ti/Cu/Ti, Al, Al/Mo, or Mo/Al/Mo.
  • the gate insulating layer is prepared by plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, or sputtering.
  • the material of the gate insulating layer is silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or tantalum oxide.
  • the active layer includes a channel layer and a contact layer.
  • the channel layer and the contact layer are formed by depositing a silicon substrate, sputtering a metal oxide semiconductor layer, or atomically depositing a metal oxide semiconductor layer.
  • the metal oxide is IGZO, IZO, or ITZO.
  • the invention also provides a method for preparing a TFT array for optimizing a 4M process, comprising:
  • Step 10 in the first mask process, preparing a gate layer on the glass substrate, and patterning the gate layer; then preparing a gate insulating layer, an active layer, a source drain layer, and a photoresist layer;
  • Step 20 in the second mask process, the photoresist layer is exposed and developed; the first wet etching, patterning the source and drain layers, forming the source and drain regions and the active region of the metal wire structure; Secondary oxygen ashing reduces the size of the active layer tailing of the source and drain metal layers; the first dry etching forms an active layer island structure; the second oxygen ashing reduces the thickness of the photoresist layer to expose the channel The source and drain layers of the region; the second wet etching, patterning the source and drain; the third oxygen ashing, reducing the contact layer tailing; the second etching, etching the active layer to form a thin film transistor structure;
  • Step 30 in the third mask process, preparing a passivation layer, and patterning the passivation layer;
  • Step 40 in the fourth mask process, preparing a transparent electrode layer, and patterning the transparent electrode layer;
  • the TFT array is a TFT array of a display area or a GOA circuit area
  • the second mask is a gray scale mask or a halftone mask.
  • the TFT array preparation method for optimizing the 4M process of the present invention adds a two-step oxygen ashing step to the original process, which is performed in the same chamber of the original process, without additional use of a separate machine, which is beneficial to reduce Cost, improve yield; achieve improved TFT optical stability and electrical performance, aperture ratio, reliability and power reduction, improve the overall performance of the array substrate, and successfully eliminate heavy doping residues in the channel region on the basis of the original process (Reduced by about 0.9 um), which is reduced by about 1 um in the amorphous silicon region.
  • Figure 1 is a schematic view of a conventional 4M process
  • FIG. 2 is a schematic diagram of a process for preparing a TFT array for optimizing a 4M process according to the present invention
  • FIG. 3 is a flow chart of a method for fabricating a TFT array for optimizing a 4M process according to the present invention.
  • FIG. 3 is a flow chart of a method for fabricating a TFT array for optimizing a 4M process according to the present invention.
  • the preparation method mainly includes:
  • Step 10 in the first mask process, preparing a gate layer on the glass substrate, and patterning the gate layer; then preparing a gate insulating layer, an active layer, a source drain layer, and a photoresist layer;
  • Step 20 in the second mask process, the photoresist layer is exposed and developed; the first wet etching, patterning the source and drain layers, forming the source and drain regions and the active region of the metal wire structure; Oxygen ashing reduces the size of the active layer tailing of the source and drain metal layers; the first dry etching forms an active layer island structure; the second oxygen ashing reduces the thickness of the photoresist layer to expose the channel region Source drain layer; second wet etching, patterned source and drain; third oxygen ashing, reducing contact layer tailing; The second dry etching, etching the active layer to form a thin film transistor structure;
  • Step 30 in the third mask process, preparing a passivation layer, and patterning the passivation layer;
  • Step 40 In the fourth mask process, a transparent electrode layer is prepared, and the transparent electrode layer is patterned.
  • the present invention specifically relates to an optimized 4M process backplane development that can be used for TFT array development and display including display area and GOA circuit area, and circuit performance optimization.
  • the invention comprises the preparation of a gate electrode, which can prepare Cu, Cu/Mo, Mo/Cu/Mo, MoNb/Cu/MoNb, Ti/Cu/Ti by sputtering, sol-gel, atomic layer deposition, evaporation, printing, etc. Electrode materials such as Al, Al/Mo, Mo/Al/Mo, and patterned.
  • the invention includes the preparation of a gate insulating layer, and specifically comprises a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide or cerium oxide prepared by plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, sputtering or the like.
  • the present invention includes depositing a silicon-based, sputtering, and atomic layer-deposited metal oxide semiconductor layer such as IGZO, IZO, ITZO, etc. as a channel layer and a contact layer.
  • the second mask can be a gray scale mask or a halftone mask.
  • the passivation layer deposition, the contact hole etching, and the transparent electrode such as ITO extraction in steps 30 and 40 can be used in the prior art, and will not be described herein.
  • FIG. 2 is a schematic diagram of a process for fabricating a TFT array for optimizing a 4M process of the present invention, showing a second mask process, that is, a portion of the present invention optimized for an existing process.
  • the gate layer 22 is formed on the glass substrate 21, and the gate layer 22 is patterned; then the gate insulating layer 23, the active layer, the source and drain electrodes are prepared.
  • the layer 26, the photoresist layer 27, and the active layer may include a channel layer 24 and a contact layer 25. Then, in the second mask process where the gray scale mask is applied:
  • the first oxygen ashing reduces the size of the active layer tailing on the side of the source and drain metal layer 26; increasing the main role of the oxygen ashing is to reduce the amorphous silicon residue;
  • the first dry etching forming an active layer island structure, that is, the patterned channel layer 24, the contact layer 25;
  • the third oxygen ashing reduces the tailing of the contact layer; increasing the oxygen ashing is mainly to reduce the heavy doped silicon residue;
  • the second dry etching etches the active layer, that is, etches the channel layer 24 and the contact layer 25 to form a thin film transistor structure.
  • the TFT array preparation method for optimizing the 4M process of the present invention is added on the basis of the original process.
  • Two-step oxygen ashing step which will be carried out in the same chamber of the original process, without additional use of a separate machine, which will help reduce costs and improve yield; achieve improved TFT optical stability and electrical performance, and aperture ratio
  • the reliability and the purpose of reducing power consumption, and improving the overall performance of the array substrate can successfully eliminate heavy doping residuals (reduced by about 0.9 um) in the channel region and reduce by about 1 um in the amorphous silicon region on the basis of the original process.

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Abstract

提供一种优化4M制程的TFT阵列制备方法，该方法包括：步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层；步骤30、在第三道光罩制程中，制备钝化层并图案化；步骤40、在第四道光罩制程中，制备透明电极层并图案化。原制程基础上，成功在沟道区消除重掺杂残留(减少约0.9um)，在不定形硅区减少约1um。

Description

优化4M制程的TFT阵列制备方法 技术领域
本发明涉及液晶显示器领域，尤其涉及一种优化4M制程的TFT阵列制备方法。
背景技术
液晶显示器(LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
为了降低成本、提高良率，各家显示阵列基板制备和研究厂商和机构不断开发新的制程工艺和技术，其中，4M(四道光罩)代替5M(五道光罩)为业内研发和制程趋势。在4M制程中存在第二层金属边缘有不定形硅和重掺杂硅残留问题，第二层金属即源漏极层金属。该问题影响TFT(薄膜晶体管)光学稳定性和电学性能，开口率，功耗和可靠性，这是由于其采用HTM(半色调光罩)或GTM(灰阶光罩)曝光图形化过程引起。
参见图1，其为现有4M制程示意图，显示了现有4M制程中的第二道光罩制程。现有4M制程一般包括：
在第一道光罩制程中，在玻璃基板11上制备栅极层12，并图形化栅极层12；然后制备栅极绝缘层13、有源层、源漏极层16、光刻胶层17，有源层可以包括沟道层14、接触层15；
在第二道光罩制程中，此示例中第二道光罩为灰阶光罩，对光刻胶层17进行曝光显影；第一次湿刻，图形化源漏极层16，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构，也就是图形化沟道层14、接触层15；氧气灰化，降低光刻胶层17厚度以露出沟道区域的源漏极层16；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，也就是刻蚀开沟道层14、接触层15，形成薄膜晶体管结构；
在第三道光罩制程中，制备钝化层，并图案化钝化层；
在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
针对现有4M制程中存在的第二层金属边缘有不定形硅和重掺杂硅残留的问题，亟需一种优化4M制程的TFT阵列制备方法。
发明内容
本发明的目的在于通过制程方法变更，减少或消除第二层金属边缘有不定形硅和重掺杂硅残留问题。
为实现上述目的，本发明提供一种优化4M制程的TFT阵列制备方法，包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
其中，所述TFT阵列为显示区或GOA电路区的TFT阵列。
其中，该第二道光罩为灰阶光罩或半色调光罩。
其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
其中，所述有源层包括沟道层和接触层。
其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
其中，所述金属氧化物为IGZO，IZO，或者ITZO。
本发明还提供一种优化4M制程的TFT阵列制备方法，包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一 次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层；
其中，所述TFT阵列为显示区或GOA电路区的TFT阵列；
其中，该第二道光罩为灰阶光罩或半色调光罩。
综上，本发明优化4M制程的TFT阵列制备方法在原制程基础上添加两步氧气灰化步骤，该步骤会在原制程的同个腔室中进行，不额外增加单独的机台使用，有利于降低成本，提高良率；达到提高TFT光学稳定性和电学性能，开口率，可靠性以及减低功耗目的，提高阵列基板的整体性能，可以在原制程基础上，成功在沟道区消除重掺杂残留(减少约0.9um)，在不定形硅区减少约1um。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有4M制程示意图；
图2为本发明优化4M制程的TFT阵列制备方法的制程示意图；
图3为本发明优化4M制程的TFT阵列制备方法的流程图。
具体实施方式
图3为本发明优化4M制程的TFT阵列制备方法的流程图。该制备方法主要包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾； 第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
本发明具体涉及一种优化的4M制程工艺背板开发，可用于包括显示区和GOA电路区TFT阵列开发和显示以及电路性能优化。本发明包括栅电极制备，可通过溅射，溶胶凝胶，原子层沉积，蒸发，打印等方式制备Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，Mo/Al/Mo等电极材料，并图形化。本发明包括栅绝缘层制备，具体包括等离子体化学气相沉积，常压化学气相沉积，溅射等制备的氮化硅，氧化硅，氮氧化硅，氧化铝，氧化铪等介质材料。本发明包括沉积硅基，溅射和原子层沉积金属氧化物半导体层，如IGZO，IZO，ITZO等做为沟道层和接触层。第二道光罩可采用灰阶光罩或半色调光罩。步骤30及40中钝化层沉积，接触孔刻蚀，和透明电极如ITO引出等，可采用现有技术，在此不再赘述。
参见图2，其为本发明优化4M制程的TFT阵列制备方法的制程示意图，显示了第二道光罩制程，也就是本发明对现有制程优化的部分。
在第二道光罩制程前的第一道光罩制程中，在玻璃基板21上制备栅极层22，并图形化栅极层22；然后制备栅极绝缘层23、有源层、源漏极层26、光刻胶层27，有源层可以包括沟道层24、接触层25。然后，在应用灰阶光罩的第二道光罩制程中：
应用灰阶光罩，对光刻胶层27进行曝光显影；
第一次湿刻，图形化源漏极层26，形成源漏极区域和有源区域的金属导线结构；
第一次氧气灰化，减少源漏金属层26边的有源层拖尾大小；增加此次氧气灰化主要作用是减少不定形硅残留；
第一次干刻，形成有源层岛状结构，也就是图形化沟道层24、接触层25；
第二次氧气灰化，降低光刻胶层27厚度以露出沟道区域的源漏极层16；
第二次湿刻，图形化源漏极；
第三次氧气灰化，减少接触层拖尾；增加此次氧气灰化主要作用为减少重掺杂硅残留；
第二次干刻，刻蚀有源层，也就是刻蚀开沟道层24、接触层25，形成薄膜晶体管结构。
综上，本发明优化4M制程的TFT阵列制备方法在原制程基础上添加 两步氧气灰化步骤，该步骤会在原制程的同个腔室中进行，不额外增加单独的机台使用，有利于降低成本，提高良率；达到提高TFT光学稳定性和电学性能，开口率，可靠性以及减低功耗目的，提高阵列基板的整体性能，可以在原制程基础上，成功在沟道区消除重掺杂残留(减少约0.9um)，在不定形硅区减少约1um。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (18)

  1. 一种优化4M制程的TFT阵列制备方法，包括：
    步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
    步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
    步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
    步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
  2. 如权利要求1所述的优化4M制程的TFT阵列制备方法，其中，所述TFT阵列为显示区或GOA电路区的TFT阵列。
  3. 如权利要求1所述的优化4M制程的TFT阵列制备方法，其中，该第二道光罩为灰阶光罩或半色调光罩。
  4. 如权利要求1所述的优化4M制程的TFT阵列制备方法，其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
  5. 如权利要求4所述的优化4M制程的TFT阵列制备方法，其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
  6. 如权利要求1所述的优化4M制程的TFT阵列制备方法，其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
  7. 如权利要求6所述的优化4M制程的TFT阵列制备方法，其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
  8. 如权利要求1所述的优化4M制程的TFT阵列制备方法，其中，所述有源层包括沟道层和接触层。
  9. 如权利要求8所述的优化4M制程的TFT阵列制备方法，其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
  10. 如权利要求9所述的优化4M制程的TFT阵列制备方法，其中，所述金属氧化物为IGZO，IZO，或者ITZO。
  11. 一种优化4M制程的TFT阵列制备方法，包括：
    步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
    步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
    步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
    步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层；
    其中，所述TFT阵列为显示区或GOA电路区的TFT阵列；
    其中，该第二道光罩为灰阶光罩或半色调光罩。
  12. 如权利要求11所述的优化4M制程的TFT阵列制备方法，其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
  13. 如权利要求12所述的优化4M制程的TFT阵列制备方法，其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
  14. 如权利要求11所述的优化4M制程的TFT阵列制备方法，其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
  15. 如权利要求14所述的优化4M制程的TFT阵列制备方法，其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
  16. 如权利要求11所述的优化4M制程的TFT阵列制备方法，其中，所述有源层包括沟道层和接触层。
  17. 如权利要求16所述的优化4M制程的TFT阵列制备方法，其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
  18. 如权利要求17所述的优化4M制程的TFT阵列制备方法，其中，所述金属氧化物为IGZO，IZO，或者ITZO。
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