CN104659109B - 一种薄膜晶体管及其制作方法、阵列基板 - Google Patents

一种薄膜晶体管及其制作方法、阵列基板 Download PDF

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CN104659109B
CN104659109B CN201510125633.XA CN201510125633A CN104659109B CN 104659109 B CN104659109 B CN 104659109B CN 201510125633 A CN201510125633 A CN 201510125633A CN 104659109 B CN104659109 B CN 104659109B
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high resistance
resistance area
tft
film transistor
thin film
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CN104659109A (zh
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李小龙
刘政
陆小勇
龙春平
张慧娟
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种薄膜晶体管及其制作方法、阵列基板,该薄膜晶体管包括:设置在衬底上的有源层,所述有源层包括中间沟道区,分别设置在所述中间沟道区外侧的第一高阻区和第二高阻区,以及设置在所述第一高阻区外侧的源区和设置在所述第二高阻区外侧的漏区;其中,所述有源层的基体材料为金刚石单晶。该薄膜晶体管通过在有源层的中间沟道区外侧设置高阻区,降低了载流子的迁移率,有效抑制了单晶金刚石薄膜晶体管的漏电流。

Description

一种薄膜晶体管及其制作方法、阵列基板
技术领域
本发明涉及显示技术领域,具体涉及一种薄膜晶体管及其制作方法、阵列基板。
背景技术
常用的平板显示面板包括液晶显示面板(Liquid Crystal Display,简称LCD)和有机发光二极管(Organic Light-Emitting Diode,简称OLED)显示面板,不管是LCD还是OLED显示面板,都包括阵列基板,阵列基板中包括多个呈阵列排布的薄膜晶体管(ThinFilm Transistor,简称TFT)构成的像素电路,每一像素电路对应一个子像素单元,薄膜晶体管作为显示面板像素的控制开关,直接关系到高性能平板显示面板的发展方向。
目前,阵列基板中的薄膜晶体管包括栅极、源漏极以及形成在源漏极与栅极之间的有源层,为提高显示面板的性能,需要尽量提高有源层的载流子迁移率,金刚石单晶拥有较高的载流子迁移率以及良好的TFT特性,是潜在的下一代TFT优良材料,然而,由于该材料具有较大的迁移率,导致TFT器件的漏电流较大,影响TFT的工作特性,长期影响会导致TFT特性恶化,影响产品的品质。
发明内容
针对现有技术中的缺陷,本发明提供了一种薄膜晶体管及其制作方法、阵列基板,以减少薄膜晶体管的漏电流。
第一方面,本发明提供一种薄膜晶体管,包括:设置在衬底上的有源层,所述有源层包括中间沟道区,分别设置在所述中间沟道区外侧的第一高阻区和第二高阻区,以及设置在所述第一高阻区外侧的源区和设置在所述第二高阻区外侧的漏区;
其中,所述有源层的基体材料为金刚石单晶。
可选的,所述中间沟道区、源区和漏区的基体材料为(111)面金刚石单晶,所述第一高阻区和第二高阻区的基体材料为(100)面金刚石单晶。
可选的,所述有源层经过等离子体和极性气体处理。
可选的,所述薄膜晶体管还包括:设置在所述源区上的源极和设置在所述漏区上的漏极,并且所述源极与所述源区之间和所述漏极与所述漏区之间还包括碳化金属层。
可选的,所述薄膜晶体管还包括:栅绝缘层和栅电极;
所述栅绝缘层设置在所述有源区上,所述栅电极设置在所述栅绝缘层上;所述栅绝缘层还设置有暴露所述源区的第一过孔和所述漏区第二过孔,所述源极和所述漏极分别形成在所述源区的第一过孔中和所述漏区第二过孔中。
第二方面,本发明还提供了一种阵列基板,包括上述的薄膜晶体管。
第三方面,本发明还提供了一种薄膜晶体管的制作方法,包括:
在衬底上沉积金刚石单晶,形成有源层;
分别在所述有源层的中间沟道区外侧设置第一高阻区和第二高阻区;
对位于所述第一高阻区外侧的有源层和位于所述第二高阻区外侧的有源层进行掺杂,从而分别形成源区和漏区。
可选的,所述沉积的金刚石单晶为(111)面金刚石单晶;
所述分别在所述有源层的中间沟道区外侧设置第一高阻区和第二高阻区包括:
刻蚀掉预定第一高阻区和预定第二高阻区的(111)面金刚石单晶,沉积(100)面金刚石单晶。
可选的,所述方法还包括:
在所述有源层上形成栅绝缘层,在所述栅绝缘层上形成栅电极;
在所述源区和所述漏区分别刻蚀第一过孔和第二过孔,分别沉积金属形成源极和漏极。
可选的,所述方法还包括:
对所述源极和漏极进行快速热退火处理,以分别在所述源极与所述源区之间和所述漏极与所述漏区之间形成碳化金属层。
可选的,所述在衬底上沉积金刚石单晶,包括:
在所述衬底上沉积(111)面金刚石单晶,沉积温度为780-850℃,沉积压力16-18KPa,甲烷与氢气流量比为0.5%-1%,沉积功率为3-5KW,沉积速率为0.01-0.02um/min,沉积时间为10-15min。
可选的,所述刻蚀掉预定第一高阻区和预定第二高阻区的(111)面金刚石单晶,沉积(100)面金刚石单晶,包括:
在预定第一高阻区和第二高阻区沉积(100)面金刚石单晶,沉积温度为900-1000℃,沉积压力21-23KPa,甲烷与氢气流量比为3%-4%,沉积功率为5-7KW,沉积速率为0.1-0.2um/min,沉积时间为2-3min。
由上述技术方案可知,本发明提供的一种薄膜晶体管及其制作方法、阵列基板,该薄膜晶体管通过在有源层的中间沟道区外侧设置高阻区,降低了载流子的迁移率,有效抑制了单晶金刚石薄膜晶体管的漏电流。
附图说明
图1为本发明一实施例提供的薄膜晶体管的结构示意图;
图2为本发明一实施例提供的薄膜晶体管的制作方法的流程示意图;
图3A至图3E为本发明一实施例提供的薄膜晶体管的制作过程的结构示意图;
其中附图标记说明:
1、衬底;2、有源层;3、栅绝缘层;4、栅极;5、层间介质层;6、源极;7、漏极;8、碳化金属层;9、第一过孔;10、第二过孔;21、中间沟道区;22、第一高阻区;23、第二高阻区;24、源区;25、漏区。
具体实施方式
下面结合附图,对发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案,而不能以此来限制本发明的保护范围。
金刚石单晶高导热性、宽带隙、高载流子迁移率(>1300V·S/cm2)等优良性能。因此,金刚石既能作为有源器件材料,也能作为无源器件材料应用于半导体技术领域。但是由于金刚石单晶本身拥有较高的载流子迁移率,导致制成的半导体器件拥有较高的载流子迁移率而使零伏漏电流较大(10-10-10-7mV);另外由于源电极和漏电极用来实现半导体器件电流的输入和输出,一般由金属制成,电极与半导体层的接触其实质为金属与金刚石单晶之间的接触,金属与金刚石单晶之间的接触电阻会直接影响薄膜晶体管的电流-电压(IV)特性,接触电阻越大,器件源漏极间的寄生电阻越大,不仅会加大电路的功耗和噪声,也会影响了电路的速度,即金刚石单晶与金属之间不能够形成理想的欧姆接触。
本发明实施例就是利用金刚石单晶的优点,采用金刚石单晶制作半导体器件,解决上述由金刚石单晶制成的半导体器件的漏电流较大的问题。
图1示出了本发明实施例提供的薄膜晶体管的结构示意图,如图1所示,该薄膜晶体管包括:设置在衬底1上的有源层2,所述有源层2包括中间沟道区21,分别设置在所述中间沟道区21外侧的第一高阻区22和第二高阻区23,以及设置在所述第一高阻区22外侧的源区24和设置在所述第二高阻区23外侧的漏区25。高阻区指的是该区域的电阻率较中间沟道区以及源区、漏区的电阻率要高。
上述薄膜晶体管中有源层2的基体材料为金刚石单晶。通过在有源层2的中间沟道区21外侧设置第一高阻区22和第二高阻区23,降低了载流子的迁移率,可有效抑制薄膜晶体管的漏电流。
在本实施例中,中间沟道区21外侧设置第一高阻区22和第二高阻区23,在所述第一高阻区22外侧的源区24和设置在所述第二高阻区23外侧的漏区25,这样,当电子在源区、沟道区和漏区传输过程中,必然会经过第一高阻区22和第二高阻区23,从而降低了电子的传输速度以及动能,实现抑制漏电流的目的。
具体的,上述中间沟道区、源区和漏区的基体材料为(111)面金刚石单晶,所述第一高阻区和第二高阻区的基体材料为(100)面金刚石单晶,这样一方面由于采用不同晶体取向的金刚石单晶,减缓了载流子的迁移,抑制了薄膜晶体管的漏电流;另一方面(100)面的金刚石单晶的载流子迁移率低也可以作为缓冲区。
可理解的是,上述第一高阻区和第二高阻区的长度大小,本实施例不对其进行限定,需要根据实际情况预设第一高阻区和第二高阻区的长度,优选的是在保证该薄膜晶体管导电性能稳定的情况下减少漏电流。
在本发明的一个优选的实施例中,为了提高薄膜晶体管的稳定性,对有源层上的(111)面和(100)面金刚石单晶即上述中间沟道区、源区和漏区的基体的(111)面金刚石单晶以及第一高阻区和第二高阻区的基体的(100)面金刚石单晶经过等离子体和极性气体处理。上述等离子体可以为氧气等离子体,极性气体可以包括N2或NH3等气体。
在本发明的一个优选的实施例中,上述薄膜晶体管还包括:设置在所述源区24上的源极6和设置在所述漏区25上的漏极7,并且所述源极6与所述源区24之间和所述漏极7与所述漏区25之间还包括碳化金属层8。通过在源极6与源区24之间和漏极7与漏区25之间设置碳化金属层,有助于源极与源区和漏极与漏区之间形成良好的欧姆接触,提高了该薄膜晶体管的稳定性。
在本发明的一个优选的实施例中,上述薄膜晶体管还包括:栅绝缘层3和栅电极4;栅绝缘层3设置在所述有源区2上,所述栅电极4设置在所述栅绝缘层3上;所述栅绝缘层3还设置有暴露所述源区的第一过孔和所述漏区第二过孔,所述源极和所述漏极分别形成在所述源区的第一过孔中和所述漏区第二过孔中。
在本发明的一个优选的实施例中,为了对上述薄膜晶体管内部的导体区、金属之间的电绝缘以及与周围环境的隔离防护,在栅电极4上设置层间介质层5(Inter LayerDielectric,ILD),与栅绝缘层3相同的是,也在栅绝缘层3暴露所述源区的第一过孔和所述漏区第二过孔的位置处设置过孔,并且设置的过孔与第一过孔和第二过孔的位置相同。
上述薄膜晶体管,通过在有源层的中间沟道区外侧设置高阻区,使得高阻区与其他有源层的各区采用不同晶体取向的金刚石单晶,降低了载流子的迁移率,有效抑制了薄膜晶体管的漏电流;将有源层经过等离子体和极性气体处理,形成了稳定的沟道区;在源极与源区之间和漏极与漏区之间设置碳化金属层,有助于源极与源区和漏极与漏区之间形成良好的欧姆接触,提高了该薄膜晶体管的稳定性。
图2示出了本发明实施例提供的薄膜晶体管的制作方法的流程示意图,如图2所示,该方法包括如下步骤:
步骤201、在衬底上沉积金刚石单晶,形成有源层;
上述沉积的金刚石单晶为(111)面金刚石单晶。
步骤202、分别在所述有源层的中间沟道区外侧设置第一高阻区和第二高阻区;
步骤203、对位于所述第一高阻区外侧的有源层和位于所述第二高阻区外侧的有源层进行掺杂,从而分别形成源区和漏区。
上述方法通过在有源层的中间沟道区外侧设置第一高阻区和第二高阻区,降低了载流子的迁移率,可有效抑制薄膜晶体管的漏电流。
需要说明的是,本实施例提供的薄膜晶体管的结构既可以为NMOS结构,也可以为PMOS结构,为了便于说明,后续描述时,以NMOS为例进行详细说明。
下面结合附图3A至图3E分别对上述薄膜晶体管的制作方法进行详细说明。
步骤201中,具体包括:在衬底上利用化学汽相沉积(Microwave Plasma ChemicalVapor Deposition,简称MPCVD)方法沉积(111)面金刚石单晶,形成有源层,如图3A所示。
具体的,在所述衬底上沉积(111)面金刚石单晶,沉积温度为780-850℃,沉积压力16-18KPa,甲烷与氢气流量比为0.5%-1%,沉积功率为3-5KW,沉积速率为0.01-0.02um/min,沉积时间为10-15min。
上述衬底材料的选择主要取决于以下几个方面:结构特性、界面特性、化学稳定性、热学性能、导电性能、光学性能以及机械性能,选择衬底以及相应的外延层时需要考虑上述几个方面。由于硅是热的良导体,器件的导热性能较好,从而达到延长器件寿命的目的,因此本实施例中以单晶硅衬底为例进行说明,但是需要说明的是,衬底材料除了可以是硅(Si)以外,还可以是碳化硅(SiC)、氮化镓(GaN)或者是砷化镓(GaAS)等。
上述步骤202具体包括:利用干刻工艺在有源层的(111)面金刚石单晶刻蚀出轻掺杂漏极区(Lightly Drain Doping,简称LDD)即预定第一高阻区和预定第二高阻区的(111)面金刚石单晶,并在该区域沉积(100)面金刚石单晶,如图3B所示。由于采用不同晶体取向的金刚石单晶,减缓了载流子的迁移,从而抑制了薄膜晶体管的漏电流。
具体的,在预定第一高阻区和第二高阻区沉积(100)面金刚石单晶,沉积温度为900-1000℃,沉积压力21-23KPa,甲烷与氢气流量比为3%-4%,沉积功率为5-7KW,沉积速率为0.1-0.2um/min,沉积时间为2-3min。
在上述步骤202之后,为了提高金刚石薄膜的稳定性,本实施例首先采用氧气等离子体对金刚石基体进行处理,在其表面形成C-O键,随后在OVEN腔室中通入极性气体如N2或NH3等使氮或氢原子与氧结合,而此时在金刚石表面的下方会形成稳定的P沟道区,提高器件的稳定性,如图3C所示。
在上述步骤203中,对位于所述第一高阻区外侧的有源层和位于所述第二高阻区外侧的有源层进行掺杂,使其导电能力更强。举例来说,可以通过离子注入的方法,若该薄膜晶体管为N型,则在第一高阻区外侧的有源层和位于所述第二高阻区外侧的有源层掺入五价杂质元素,例如磷、砷等分别形成源区和漏区。
在另一个可实现的方式中,若该薄膜晶体管为P型,则在第一高阻区外侧的有源层和位于所述第二高阻区外侧的有源层掺入三价杂质元素,例如硼、镓等分别形成源区和漏区。
在本发明的一个优选的实施例中,上述方法还包括图2中未示出的步骤204:
步骤204、在经过等离子体和极性气体处理后的有源层上形成栅绝缘层,在所述栅绝缘层上形成栅电极;同时在源区和漏区进行B原子注入,沉积ILD层,并在所述源区和所述漏区分别刻蚀第一过孔和第二过孔,如图3D所示。
在本发明的一个优选的实施例中,上述方法还包括图2中未示出的步骤205:
步骤205、利用自对准工艺在第一过孔9的源区表面和第二过孔10的漏区表面上分别沉积金属形成源极和漏极,对所述源极和漏极进行快速热退火处理(RTA),以分别在所述源极与所述源区之间和所述漏极与所述漏区之间形成碳化金属层,如图3E所示。
具体的,上述在源区表面和漏区表面沉积的金属可以是W、Ti、Mo等金属中的一种或多种;上述快速热退火处理(RTA)的温度为450-500℃,处理时间为1-2h。
在实施过程中,该步骤205还包括:在ILD层上方进行加氢气处理,从而获得更好的电学特性的稳定性。
上述步骤通过在所述源极与所述源区之间和所述漏极与所述漏区之间形成碳化金属层,使源极与源区和漏极与漏区之间形成良好的欧姆接触,提高了该薄膜晶体管的稳定性。
本发明实施例还提供了一种阵列基板,包括上述实施例中的薄膜晶体管。
本发明的说明书中,说明了大量具体细节。然而,能够理解,本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中,并未详细示出公知的方法、结构和技术,以便不模糊对本说明书的理解。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围,其均应涵盖在本发明的权利要求和说明书的范围当中。

Claims (10)

1.一种薄膜晶体管,其特征在于,包括:设置在衬底上的有源层,所述有源层包括中间沟道区,分别设置在所述中间沟道区外侧的第一高阻区和第二高阻区,以及设置在所述第一高阻区外侧的源区和设置在所述第二高阻区外侧的漏区;
其中,所述有源层的基体材料为金刚石单晶;
其中,所述中间沟道区、源区和漏区的基体材料为(111)面金刚石单晶,所述第一高阻区和第二高阻区的基体材料为(100)面金刚石单晶。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述有源层经过等离子体和极性气体处理。
3.根据权利要求1所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括:设置在所述源区上的源极和设置在所述漏区上的漏极,并且所述源极与所述源区之间和所述漏极与所述漏区之间还包括碳化金属层。
4.根据权利要求3所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括:栅绝缘层和栅电极;
所述栅绝缘层设置在所述有源区上,所述栅电极设置在所述栅绝缘层上;所述栅绝缘层还设置有暴露所述源区的第一过孔和所述漏区第二过孔,所述源极和所述漏极分别形成在所述源区的第一过孔中和所述漏区第二过孔中。
5.一种阵列基板,其特征在于,包括:如权利要求1-4中任一项所述的薄膜晶体管。
6.一种薄膜晶体管的制作方法,其特征在于,包括:
在衬底上沉积金刚石单晶,形成有源层;
分别在所述有源层的中间沟道区外侧设置第一高阻区和第二高阻区;
对位于所述第一高阻区外侧的有源层和位于所述第二高阻区外侧的有源层进行掺杂,从而分别形成源区和漏区;
其中,所述沉积的金刚石单晶为(111)面金刚石单晶;
所述分别在所述有源层的中间沟道区外侧设置第一高阻区和第二高阻区包括:
刻蚀掉预定第一高阻区和预定第二高阻区的(111)面金刚石单晶,沉积(100)面金刚石单晶。
7.根据权利要求6所述的方法,其特征在于,所述方法还包括:
在所述有源层上形成栅绝缘层,在所述栅绝缘层上形成栅电极;
在所述源区和所述漏区分别刻蚀第一过孔和第二过孔,分别沉积金属形成源极和漏极。
8.根据权利要求7所述的方法,其特征在于,所述方法还包括:
对所述源极和漏极进行快速热退火处理,以分别在所述源极与所述源区之间和所述漏极与所述漏区之间形成碳化金属层。
9.根据权利要求6所述的方法,其特征在于,所述在衬底上沉积金刚石单晶,包括:
在所述衬底上沉积(111)面金刚石单晶,沉积温度为780-850℃,沉积压力16-18KPa,甲烷与氢气流量比为0.5%-1%,沉积功率为3-5KW,沉积速率为0.01-0.02um/min,沉积时间为10-15min。
10.根据权利要求6所述的薄膜晶体管的制作方法,其特征在于,所述刻蚀掉预定第一高阻区和预定第二高阻区的(111)面金刚石单晶,沉积(100)面金刚石单晶,包括:
在预定第一高阻区和第二高阻区沉积(100)面金刚石单晶,沉积温度为900-1000℃,沉积压力21-23KPa,甲烷与氢气流量比为3%-4%,沉积功率为5-7KW,沉积速率为0.1-0.2um/min,沉积时间为2-3min。
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