CN105097450B - 多晶硅薄膜及制作方法、tft及制作方法、显示面板 - Google Patents

多晶硅薄膜及制作方法、tft及制作方法、显示面板 Download PDF

Info

Publication number
CN105097450B
CN105097450B CN201510350269.7A CN201510350269A CN105097450B CN 105097450 B CN105097450 B CN 105097450B CN 201510350269 A CN201510350269 A CN 201510350269A CN 105097450 B CN105097450 B CN 105097450B
Authority
CN
China
Prior art keywords
polysilicon
production method
polysilicon membrane
layer
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510350269.7A
Other languages
English (en)
Other versions
CN105097450A (zh
Inventor
李小龙
刘政
陆小勇
李栋
龙春平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510350269.7A priority Critical patent/CN105097450B/zh
Priority to US15/116,980 priority patent/US10431669B2/en
Priority to PCT/CN2015/092080 priority patent/WO2016206244A1/zh
Publication of CN105097450A publication Critical patent/CN105097450A/zh
Application granted granted Critical
Publication of CN105097450B publication Critical patent/CN105097450B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明公开了一种多晶硅薄膜及制作方法、TFT及制作方法、显示面板，所述制作方法包括：形成多晶硅层；对所述多晶硅层的表面进行处理，以使得所述多晶硅层的表面呈电负性；向工艺腔内通入极性气体，使极性气体中的极性分子吸附在表面呈电负性的多晶硅层的表面，以获得表面的空穴密度大于电子密度的所述多晶硅薄膜。本发明制作的多晶硅薄膜表面形成有向上的电场，从而使空穴积累在多晶硅薄膜表面，宏观上表现为在多晶硅薄膜表面形成稳定的空穴导电沟道，由于空穴的移动速度较慢，能够有效降低光致漏电效应和高温、应力导致的漏电效应，从而减小了漏电流。

Description

多晶硅薄膜及制作方法、TFT及制作方法、显示面板
技术领域
本发明涉及显示技术领域，尤其涉及一种多晶硅薄膜及该多晶硅薄膜的制作方法、包括该多晶硅薄膜的TFT及该TFT的制作方法、以及包括该TFT的显示面板。
背景技术
低温多晶硅(LTPS)薄膜晶体管(TFT)由于迁移率高、耗电量低、产品轻薄等优点被广泛应用于液晶显示面板(LCD)和发光二极管显示面板(OLED)中。然而，低温多晶硅薄膜晶体管器件在施加光照、高温或者应力时，漏电流明显增加，这一问题在一定程度上阻碍了低温多晶硅显示面板的发展。
现有技术中主要采用设置轻掺杂漏区(Lightly Doped Drain，LDD)的方法来减少低温多晶硅器件的漏电流。如图1所示，薄膜晶体管器件在沟道区1的靠近两侧源漏极的位置设置了轻掺杂漏区2，让轻掺杂漏区2也承受部分电压，以减轻漏电流。但是该方法会增加一道掩膜工艺，从而提高了生产成本。另外，光刻胶掩模的精度大约在2μm左右，难以满足沟道小尺寸的要求。
发明内容
本发明的目的在于提供一种多晶硅薄膜及其制作方法、TFT及其制作方法、显示面板，以减小漏电流。
为解决上述技术问题，作为本发明的第一个方面，提供一种多晶硅薄膜的制作方法，包括以下步骤：
形成多晶硅层；
对所述多晶硅层的表面进行处理，以使得所述多晶硅层的表面呈电负性；
向工艺腔内通入极性气体，使极性气体中的极性分子吸附在表面呈电负性的多晶硅层的表面，以获得表面的空穴密度大于电子密度的所述多晶硅薄膜。
优选地，对所述多晶硅层的表面进行处理的步骤包括：向工艺腔内通入氧气，对所述多晶硅层的表面进行氧气等离子化处理。
优选地，对所述多晶硅层的表面进行氧气等离子化处理的步骤中，所述工艺腔内的气压为1100-1300mTorr，处理时间为250-350s。
优选地，所述制作方法还包括向工艺腔内通入极性气体之前进行的：
对所述工艺腔抽真空。
优选地，向工艺腔内通入极性气体的步骤中，所述工艺腔内的气压为50-150mTorr，处理时间为30-50min。
优选地，所述极性气体包括N2、SiH4、NO2和NH3中的任意一种或多种。
优选地，对所述多晶硅层的表面进行处理的步骤包括：向工艺腔内通入氢气，对所述多晶硅层的表面进行氢气等离子化处理。
优选地，所述制作方法还包括在形成多晶硅层之前进行的：
在衬底基板上方形成非晶硅层；
对所述非晶硅层进行准分子激光退火处理，得到所述多晶硅层。
作为本发明的第二个方面，还提供一种TFT的制作方法，所述TFT的制作方法包括形成多晶硅薄膜的步骤，其中，所述多晶硅薄膜采用本发明所提供的上述制作方法形成。
优选地，所述TFT的制作方法还包括在形成所述多晶硅薄膜之后进行的：
在所述多晶硅薄膜上依次形成第一绝缘层和栅极；
在所述栅极上形成第二绝缘层；
形成贯穿所述第二绝缘层和所述第一绝缘层的两个过孔；
在所述第二绝缘层上形成源极和漏极，所述源极和所述漏极分别通过两个所述过孔与所述多晶硅薄膜相连。
作为本发明的第三个方面，还提供一种多晶硅薄膜，所述多晶硅薄膜表面的空穴密度大于电子密度。
优选地，所述多晶硅薄膜的表面形成有Si-O偶极子，所述Si-O偶极子的位于所述多晶硅薄膜外侧的部分吸附有极性分子。
优选地，所述多晶硅薄膜的表面形成有Si-H偶极子，所述Si-H偶极子的位于所述多晶硅薄膜外侧的部分吸附有极性分子。
作为本发明的第四个方面，还提供一种TFT，所述TFT包括本发明所提供的上述多晶硅薄膜。
作为本发明的第五个方面，还提供一种显示面板，所述显示面板包括本发明所提供的上述TFT。
本发明制作的多晶硅薄膜表面积累了大量的空穴，从而形成了稳定的空穴导电沟道，由于空穴的移动速度较慢，能够有效改善光照、高温、应力所导致的漏电效应，从而有效减小TFT器件的漏电流。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。
图1是现有技术中改善漏电流的沟道区结构；
图2a-图2b是本发明实施例中多晶硅薄膜的制作流程示意图；
图3a-图3d是本发明实施例中TFT的制作流程示意图。
在附图中，1-沟道区；2-轻掺杂漏区；3-多晶硅层；4-极性分子；5-空穴；6-衬底基板；7-缓冲层；8-第一绝缘层；9-栅极；10-第二绝缘层；11-源极；12-漏极。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
本发明首先提供了一种多晶硅薄膜的制作方法，所述制作方法包括以下步骤：
形成多晶硅层；
对所述多晶硅层的表面进行处理，以使得所述多晶硅层的表面呈电负性；
向工艺腔内通入极性气体，使极性气体中的极性分子吸附在表面呈电负性的多晶硅层的表面，以获得表面的空穴密度大于电子密度的所述多晶硅薄膜。
现有的多晶硅薄膜的表面是电中性的，即空穴密度与电子密度相同，由于电子的迁移速率较快，容易形成表面漏电流。本发明中所述的多晶硅层即相当于现有的多晶硅薄膜，其表面是电中性的，对所述多晶硅层的表面进行处理之后，使得多晶硅层的表面呈电负性，从而能够吸引极性分子。吸附极性分子之后，由于极性分子端的化学势较低，电子向极性分子端迁移，使空穴大量积累在多晶硅薄膜的表面，宏观上表现为在多晶硅薄膜表面形成稳定的空穴导电沟道。由于空穴的移动速度较慢，能够有效改善光照、高温、应力所导致的漏电效应，从而能够有效减小TFT器件的漏电流。
优选地，如图2a所示，对多晶硅层3的表面进行处理的步骤包括：向工艺腔内通入氧气，对多晶硅层3的表面进行氧气等离子化处理，在多晶硅层3的表面形成Si-O偶极子，即，处理后的多晶硅层3的表面形成稳定的氧端基，从而使得多晶硅层3的表面呈电负性。
在上述处理步骤中：工艺腔内的气压控制在1100-1300mTorr，优选为1200mTorr；处理时间控制在250-350s之间，优选为300s；通入氧气的流量约为2000sccm。
在本发明中，对多晶硅层3的表面进行处理的步骤还可以采用以下方式：向工艺腔内通入氢气，对多晶硅层3的表面进行氢气等离子化处理，通过形成Si-H偶极子以获得呈电负性的表面。
进一步地，所述制作方法还包括向工艺腔内通入极性气体之前进行的：
对所述工艺腔抽真空，以去除所述工艺腔中原有的气体，然后再通入极性气体，以确保极性气体中的极性分子的吸附效率和吸附稳定性。
图2b是通入极性气体后多晶硅层3表面的示意图。具有氧端基的表面暴露在极性气体中时会吸附其中的极性分子4，从而形成一个电化学系统。此系统中Si-O偶极子的能量价带高于极性分子4的化学势，导致电子向极性分子4迁移，从而使空穴5积累在多晶硅层3的表面，形成稳定的空穴导电沟道。
在上述步骤中：所述工艺腔内的气压控制在50-150mTorr，优选为100mTorr；处理时间控制在30-50min之间，优选为40min，以达到理想的吸附效果。
本发明中所述的极性气体包括N2、SiH4、NO2、NH3等气体中的任意一种或多种，相应的，极性分子4可以是N2分子、SiH4分子、NO2分子、NH3分子等。
进一步地，如图3a所示，所述多晶硅薄膜的制作方法还包括在形成多晶硅层之前进行的：
在衬底基板6上方形成非晶硅层(a-Si层)；
对所述非晶硅层进行准分子激光退火处理，得到多晶硅层3(相当于现有技术中的P-Si层)。
进一步地，衬底基板6和多晶硅层3之间还设置有缓冲层7，缓冲层7包括与衬底基板6相接触的氮化硅层和与多晶硅层3相接触的氧化硅层，其中，氮化硅层起到隔离衬底基板6和多晶硅层3的作用，氧化硅层起到与多晶硅层3进行晶格匹配作用。
本发明还提供了一种薄膜晶体管(TFT)的制作方法，所述TFT的制作方法包括形成多晶硅薄膜的步骤，其中，所述多晶硅薄膜采用本发明所提供的上述制作方法形成。
如上所述，采用本发明方法制作的TFT能够有效减小漏电流。
如图3a-图3d所示，所述制作方法还包括在形成所述多晶硅薄膜之后进行的：
在所述多晶硅薄膜上依次形成第一绝缘层8和栅极9；
在栅极9上形成第二绝缘层10以及贯穿第二绝缘层10和第一绝缘层8的两个过孔；
在第二绝缘层10上形成源极11和漏极12，源极11和漏极12分别通过两个所述过孔与所述多晶硅薄膜相连。
本发明还提供了一种多晶硅薄膜，所述多晶硅薄膜表面的空穴密度大于电子密度。如图3d所示，所述多晶硅薄膜的表面聚集有大量的空穴5，由于空穴的移动速度较慢，能够有效降低光致漏电效应和高温、应力导致的漏电效应，从而减小了TFT的漏电流。
作为本发明的一种实施方式，所述多晶硅薄膜的表面形成有Si-O偶极子，所述Si-O偶极子的位于所述多晶硅薄膜外侧的部分吸附有极性分子。Si-O偶极子的能量价带高于极性分子的化学势，导致电子向极性分子迁移，空穴大量积累在多晶硅薄膜的表面，使多晶硅薄膜表面的空穴密度大于电子密度。
作为本发明的另一种实施方式，所述多晶硅薄膜的表面形成有Si-H偶极子，所述Si-H偶极子的位于所述多晶硅薄膜外侧的部分吸附有极性分子。相应地，Si-H偶极子的能量价带高于极性分子的化学势，导致电子向极性分子迁移，空穴大量积累在多晶硅薄膜的表面，从而使多晶硅薄膜表面的空穴密度大于电子密度。
本发明还提供了一种薄膜晶体管(TFT)，所述TFT包括本发明所提供的上述多晶硅薄膜。所述TFT可用于显示面板中(例如：用于显示面板的阵列基板中)，能够有效降低显示面板中的漏电流，提升显示品质。
相应地，本发明还提供了一种显示面板，所述显示面板包括本发明所提供的上述TFT。如上所述，本发明所提供的显示面板由于改善了漏电流，具有较好的显示品质。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

1.一种多晶硅薄膜的制作方法，其特征在于，包括以下步骤：
形成多晶硅层；
对所述多晶硅层的表面进行处理，以使得所述多晶硅层的表面呈电负性；
向工艺腔内通入极性气体，使极性气体中的极性分子吸附在表面呈电负性的多晶硅层的表面，以获得表面的空穴密度大于电子密度的所述多晶硅薄膜；
对所述多晶硅层的表面进行处理的步骤包括：向工艺腔内通入氧气，对所述多晶硅层的表面进行氧气等离子化处理。
2.根据权利要求1所述的多晶硅薄膜的制作方法，其特征在于，对所述多晶硅层的表面进行氧气等离子化处理的步骤中，所述工艺腔内的气压为1100-1300mTorr，处理时间为250-350s。
3.根据权利要求1所述的多晶硅薄膜的制作方法，其特征在于，所述制作方法还包括向工艺腔内通入极性气体之前进行的：
对所述工艺腔抽真空。
4.根据权利要求1所述的多晶硅薄膜的制作方法，其特征在于，向工艺腔内通入极性气体的步骤中，所述工艺腔内的气压为50-150mTorr，处理时间为30-50min。
5.根据权利要求1至4中任意一项所述的多晶硅薄膜的制作方法，其特征在于，所述极性气体包括NO2和NH3中的任意一种或多种。
6.根据权利要求1至4中任意一项所述的多晶硅薄膜的制作方法，其特征在于，所述制作方法还包括在形成多晶硅层之前进行的：
在衬底基板上方形成非晶硅层；
对所述非晶硅层进行准分子激光退火处理，得到所述多晶硅层。
7.一种TFT的制作方法，其特征在于，包括形成多晶硅薄膜的步骤，其中，所述多晶硅薄膜采用权利要求1至6中任意一项所述的制作方法形成。
8.根据权利要求7所述的TFT的制作方法，其特征在于，所述制作方法还包括在形成所述多晶硅薄膜之后进行的：
在所述多晶硅薄膜上依次形成第一绝缘层和栅极；
在所述栅极上形成第二绝缘层；
形成贯穿所述第二绝缘层和所述第一绝缘层的两个过孔；
在所述第二绝缘层上形成源极和漏极，所述源极和所述漏极分别通过两个所述过孔与所述多晶硅薄膜相连。
9.一种权利要求1-6任一项所述方法制作的多晶硅薄膜，其特征在于，所述多晶硅薄膜表面的空穴密度大于电子密度。
10.根据权利要求9所述的多晶硅薄膜，其特征在于，所述多晶硅薄膜的表面形成有Si-O偶极子，所述Si-O偶极子的位于所述多晶硅薄膜外侧的部分吸附有极性分子。
11.一种TFT，其特征在于，所述TFT包括权利要求9或10所述的多晶硅薄膜。
12.一种显示面板，其特征在于，所述显示面板包括权利要求11所述的TFT。
CN201510350269.7A 2015-06-23 2015-06-23 多晶硅薄膜及制作方法、tft及制作方法、显示面板 Active CN105097450B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510350269.7A CN105097450B (zh) 2015-06-23 2015-06-23 多晶硅薄膜及制作方法、tft及制作方法、显示面板
US15/116,980 US10431669B2 (en) 2015-06-23 2015-10-16 Polysilicon thin film and manufacturing method thereof, TFT and manufacturing method thereof, and display panel
PCT/CN2015/092080 WO2016206244A1 (zh) 2015-06-23 2015-10-16 多晶硅薄膜及制作方法、tft及制作方法、显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510350269.7A CN105097450B (zh) 2015-06-23 2015-06-23 多晶硅薄膜及制作方法、tft及制作方法、显示面板

Publications (2)

Publication Number Publication Date
CN105097450A CN105097450A (zh) 2015-11-25
CN105097450B true CN105097450B (zh) 2019-11-01

Family

ID=54577623

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510350269.7A Active CN105097450B (zh) 2015-06-23 2015-06-23 多晶硅薄膜及制作方法、tft及制作方法、显示面板

Country Status (3)

Country Link
US (1) US10431669B2 (zh)
CN (1) CN105097450B (zh)
WO (1) WO2016206244A1 (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740387A (zh) * 2008-11-27 2010-06-16 上海华虹Nec电子有限公司 具有多晶硅化物的表面沟道pmos器件制作工艺
CN103779404A (zh) * 2014-01-24 2014-05-07 东南大学 P沟道注入效率增强型绝缘栅双极型晶体管

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136926A (ja) * 1983-01-25 1984-08-06 Seiko Epson Corp 半導体装置の製法
JPH01241175A (ja) * 1988-03-23 1989-09-26 Seikosha Co Ltd 非晶質シリコン薄膜トランジスタの製造方法
JPH08181317A (ja) * 1994-12-22 1996-07-12 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5907008A (en) * 1996-03-18 1999-05-25 Kabushiki Kaisha Toshiba Black coloring composition, high heat resistance light-shielding component, array substrate, liquid crystal and method of manufacturing array substrate
JPH11233776A (ja) * 1998-02-09 1999-08-27 Sharp Corp 薄膜半導体装置およびその製造方法
KR100297719B1 (ko) * 1998-10-16 2001-08-07 윤종용 박막제조방법
JP2003218350A (ja) * 2002-01-22 2003-07-31 Hitachi Ltd 半導体装置及びその製造方法
DE10234488B4 (de) * 2002-07-29 2007-03-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer lokalisierten Implantationsbarriere in einer Polysiliziumleitung
JP2004265603A (ja) * 2003-01-14 2004-09-24 Sharp Corp 電子放出装置および電子放出素子クリーニング装置および電子放出素子クリーニング方法
EP1636853A4 (en) * 2003-06-12 2007-04-04 Sirica Corp STATIONARY NON-BALANCE DISTRIBUTION FREE CARRIER AND PHOTOENENERGY UPGRADING THEREFORE
US7115449B2 (en) * 2003-06-24 2006-10-03 National Chiao Tung University Method for fabrication of polycrystalline silicon thin film transistors
CN1567550A (zh) * 2003-07-04 2005-01-19 统宝光电股份有限公司 低温多晶硅薄膜晶体管的制作方法
JP2006332172A (ja) * 2005-05-24 2006-12-07 Mitsubishi Electric Corp 半導体装置及び半導体装置の製造方法
CN102646593A (zh) 2011-05-16 2012-08-22 京东方科技集团股份有限公司 一种tft及tft的制造方法
US20140261666A1 (en) * 2013-03-13 2014-09-18 Applied Materials, Inc. Methods of manufacturing a low cost solar cell device
CN103531595B (zh) * 2013-10-31 2016-09-14 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管阵列基板及其制作方法、显示装置
CN104659109B (zh) * 2015-03-20 2017-07-14 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740387A (zh) * 2008-11-27 2010-06-16 上海华虹Nec电子有限公司 具有多晶硅化物的表面沟道pmos器件制作工艺
CN103779404A (zh) * 2014-01-24 2014-05-07 东南大学 P沟道注入效率增强型绝缘栅双极型晶体管

Also Published As

Publication number Publication date
US20180108757A1 (en) 2018-04-19
CN105097450A (zh) 2015-11-25
WO2016206244A1 (zh) 2016-12-29
US20180337262A9 (en) 2018-11-22
US10431669B2 (en) 2019-10-01

Similar Documents

Publication Publication Date Title
CN106558538B (zh) 阵列基板、显示装置及阵列基板的制备方法
US9502448B2 (en) Method for fabricating an array substrate with improved driving ability
CN102983176B (zh) 包括纳米导体层的薄膜晶体管
CN103985637A (zh) 低温多晶硅薄膜晶体管及其制作方法和显示装置
CN106128944A (zh) 金属氧化物薄膜晶体管阵列基板的制作方法
CN104037090B (zh) 氧化物薄膜晶体管结构制作方法及氧化物薄膜晶体管结构
CN103887344A (zh) Igzo薄膜晶体管及改善igzo薄膜晶体管电学性能的方法
TWI508183B (zh) 形成含氧半導體薄膜電晶體之方法
CN104576399A (zh) 一种薄膜晶体管及其制造方法
Hsieh et al. Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors
CN104505404A (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN109148597A (zh) 薄膜晶体管及其制备方法
CN105551967B (zh) N型薄膜晶体管的制作方法
CN104538455A (zh) 一种轻掺杂漏极区的制作方法、薄膜晶体管及阵列基板
CN105097450B (zh) 多晶硅薄膜及制作方法、tft及制作方法、显示面板
Cheong et al. Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors
CN106057677B (zh) 低温多晶硅薄膜晶体管的制作方法
CN107910378A (zh) Ltps薄膜晶体管、阵列基板及其制作方法、显示装置
CN103500711B (zh) 薄膜晶体管的制造方法
CN207425865U (zh) 一种含超薄金属氧化物薄膜介电层的晶体管
CN105185715B (zh) 一种tft基板、tft开关管及其制造方法
CN110120349A (zh) InGaZnO薄膜晶体管的源漏电极及晶体管制备方法
CN107230681A (zh) 阵列基板及其制备方法和显示装置
CN102610520A (zh) 一种多晶硅薄膜晶体管的制备方法
CN105097925A (zh) 一种新型功率器件结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant