WO2018157319A1 - 隧穿场效应晶体管及其制造方法 - Google Patents

隧穿场效应晶体管及其制造方法 Download PDF

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WO2018157319A1
WO2018157319A1 PCT/CN2017/075275 CN2017075275W WO2018157319A1 WO 2018157319 A1 WO2018157319 A1 WO 2018157319A1 CN 2017075275 W CN2017075275 W CN 2017075275W WO 2018157319 A1 WO2018157319 A1 WO 2018157319A1
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conductive portion
layer
conductive
region electrode
source region
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PCT/CN2017/075275
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English (en)
French (fr)
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徐慧龙
李伟
张臣雄
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华为技术有限公司
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Priority to CN201780080089.9A priority Critical patent/CN110088912B/zh
Priority to PCT/CN2017/075275 priority patent/WO2018157319A1/zh
Publication of WO2018157319A1 publication Critical patent/WO2018157319A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the embodiments of the present application relate to communication technologies, and in particular, to a tunnel field effect transistor (TFET) and a method for fabricating the same.
  • TFET tunnel field effect transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • CMOS technology has a working voltage due to the limitation of its transistor operating principle.
  • ultra-low operating voltage such as 0.3V
  • TFET is one of the more promising technologies.
  • the transition between the on-state and the off-state of the TFET is achieved by whether or not inter-band tunneling occurs.
  • the subthreshold swing can theoretically be less than 60 mV/dec, which can be small. Normally open and close under voltage.
  • FIG. 1 is a black phosphorus TFET having a heterojunction effect in the prior art, as shown in FIG. 1, where 11 represents a source region, 13 represents a drain region, 12 represents a channel, 16 is a gate dielectric, and 17 is a gate metal.
  • 14 and 15 denote channel materials, wherein the channel material is black phosphorus, and as shown in FIG. 1, the TFET has a double gate structure, that is, the channel 12 has a gate dielectric 16 and a gate metal 17 on both sides.
  • the black phosphorus material is thicker on the left side and thinner on the right side, and there is a step between the two, and there is a step on each of the upper and lower surfaces, wherein the gate structure forms a cover for the step. Since the thickness of the black phosphorus on the left and right sides is different, a large on-state current can be achieved.
  • the step structure in the above TFET is not precisely controlled due to the limitation of the process precision in actual fabrication. Therefore, the position of the step in the different devices may fluctuate somewhat, which may affect the performance of the device. Uniformity and repeatability.
  • Embodiments of the present application provide a tunneling field effect transistor and a manufacturing method thereof for solving the problem of uniformity and reproducibility of device performance of different devices.
  • a first aspect of the present application provides a tunneling field effect transistor, including: a substrate layer;
  • a conductive layer comprising a first conductive portion and a second conductive portion, the first conductive portion and the second conductive portion covering a portion of a surface of the substrate layer, the first conductive portion having a thickness greater than the second portion a thickness of the conductive portion, and a stepped shape is formed between the first conductive portion and the upper surface of the second conductive portion;
  • a source region electrode covering an outer surface of the first conductive portion, and a vertical surface where the step is located is a boundary of the source region electrode
  • drain region electrode covering the outer surface of the second conductive portion away from the first conductive portion
  • the first insulating layer is located on an upper surface of the substrate layer, and covers an outer surface of the source region electrode, the conductive layer, and the drain region electrode;
  • the gate covering the surface of the first insulating layer away from the conductive layer, and located in a gap between the source region electrode and the drain region electrode, the gate includes a plurality of a surface, wherein the two surfaces are in contact with a first insulating layer overlying the source region electrode and a first insulating layer overlying the drain region electrode;
  • a second insulating layer covering the surface of the first insulating layer and the gate away from the first insulating layer.
  • the conductive layer includes a first conductive portion and a second conductive portion.
  • the first conductive portion and the second conductive portion cover a portion of the surface of the substrate layer.
  • the thickness of the first conductive portion is greater than the thickness of the second conductive portion, and the first conductive portion Forming a step between the portion and the upper surface of the second conductive portion.
  • the TFET of the structure has a larger on-state current due to the thickness of the first conductive portion being greater than the thickness of the second conductive portion.
  • the switch ratio is better, the structure process is simple, the preparation is easy, and the controllability is strong, so that the uniformity and repeatability of the device performance can be effectively improved.
  • the material of the conductive layer comprises black phosphorus.
  • the source region electrode is a high work function metal material
  • the drain region electrode is a low work function metal material
  • the source region electrode may be a high work function metal material, for example, metal palladium may be used, and the drain region electrode may be a low work function metal material such as metal aluminum.
  • the metal palladium may form a P type to the source region black phosphorus. Doping, improve hole injection efficiency, metal aluminum can form N-type doping of black phosphorus in the drain region, improve electron collection efficiency, and thus obtain a high-performance N-type TFET.
  • the source region electrode is a low work function metal material
  • the drain region electrode is a high work function metal material
  • the source region electrode may be a low work function metal material, for example, metal aluminum may be used, and the drain region electrode may be a high work function metal material such as metal palladium, thereby obtaining a high performance P-type TFET.
  • the first conductive portion has a thickness of not less than 3 nm
  • the second conductive portion has a thickness of not more than 10 nm
  • a step formed between the first conductive portion and the upper surface of the second conductive portion The height is not less than 1 nm.
  • a second aspect of the present application provides a method of fabricating a tunneling field effect transistor, including:
  • a second insulating layer is formed on the first insulating layer and the gate.
  • the tunneling field effect transistor formed by the method forms a source region electrode at one end of the substrate layer and the conductive layer, and the conductive layer covered by the source region electrode serves as the first conductive portion, and the conductive layer is other than the first conductive portion Forming a second conductive portion on the portion, wherein the thickness of the first conductive portion is greater than the thickness of the second conductive portion, and a stepped shape is formed between the first conductive portion and the upper surface of the second conductive portion, because the source region is thicker
  • the black phosphorus, while the channel and drain regions use thinner black phosphorus, so the TFET has a larger on-state current and a better switching ratio.
  • the above process is simple and makes TFET easy
  • the preparation has strong controllability, so that the uniformity and repeatability of the device performance can be effectively improved.
  • the forming the source region electrode at one end of the substrate layer and the conductive layer comprises:
  • a source region electrode made of a high work function metal or a low work function metal is formed on the exposed substrate layer and the conductive layer.
  • the forming the second conductive portion on the portion of the conductive layer other than the first conductive portion comprises:
  • the oxidized conductive layer is hydrolyzed, and the remaining portion after the hydrolysis is used as the second conductive portion.
  • forming a drain electrode on the second conductive portion away from the first conductive portion comprising:
  • a drain region electrode made of a high work function metal or a low work function metal is formed, wherein materials of the source region electrode and the drain region electrode are different.
  • the forming a first insulating layer on the outer side of the substrate layer, the source region electrode, the conductive layer, and the drain region electrode comprises:
  • a first insulating layer is formed on the outer side of the substrate layer, the source region electrode, the conductive layer, and the drain region electrode by atomic layer deposition.
  • the forming a second insulating layer on the first insulating layer and the gate includes:
  • a second insulating layer is formed on the first insulating layer and the gate by a chemical vapor deposition or a doping technique.
  • the material of the conductive layer comprises black phosphorus.
  • the conductive layer includes a first conductive portion and a second conductive portion, and the first conductive portion and the second conductive portion cover a portion of the surface of the substrate layer,
  • the thickness of the first conductive portion is greater than the thickness of the second conductive portion, and a step shape is formed between the first conductive portion and the upper surface of the second conductive portion.
  • the TFET of the structure is due to the first conductive portion.
  • the thickness is greater than the thickness of the second conductive portion, and therefore has a large on-state current and a good switching ratio, and the structure process is simple, easy to prepare, and has strong controllability, thereby effectively improving uniformity and repeatability of device performance. Sex.
  • Figure 1 is a prior art black phosphorus TFET having a heterojunction effect
  • Embodiment 1 of a tunneling field effect transistor according to an embodiment of the present disclosure
  • Embodiment 3 is a flowchart of Embodiment 1 of a method for manufacturing a tunneling field effect transistor according to an embodiment of the present disclosure
  • 4( a ) to 4 ( g ) are schematic diagrams illustrating a manufacturing process of an example of a method for fabricating a tunneling field effect transistor according to an embodiment of the present application.
  • the present application provides a TFET with a simple preparation process, which can effectively improve the uniformity and repeatability of device performance.
  • TFET thin film transistor
  • the tunneling field effect transistor includes:
  • the conductive layer 22 includes a first conductive portion 221 and a second conductive portion 222.
  • the first conductive portion 221 and the second conductive portion 222 cover a portion of the surface of the substrate layer 21.
  • the first conductive portion 221 has a thickness greater than the second conductive portion. a thickness of the portion 222, and a stepped shape is formed between the first conductive portion 221 and the upper surface of the second conductive portion 222;
  • a source region electrode 23 covering the outer surface of the first conductive portion 221, and the vertical surface where the step is located is a boundary of the source region electrode 23;
  • drain electrode 24 covering the outer surface of the second conductive portion 222 away from the first conductive portion 221;
  • the first insulating layer 25 is located on the upper surface of the substrate layer 21, and covers the outer surfaces of the source region electrode 23, the conductive layer 22 and the drain region electrode 24;
  • a gate electrode 26 covering the surface of the first insulating layer 25 away from the conductive layer 22 and located in a gap between the source region electrode 23 and the drain region electrode 24, the gate electrode 26 including a plurality of surfaces, two of which The surfaces are respectively in contact with the first insulating layer 25 covering the source region electrode 23 and the first insulating layer 25 covering the drain region electrode 24;
  • the second insulating layer 27 covers the surface of the first insulating layer 25 and the gate electrode 26 away from the first insulating layer 25.
  • the substrate layer 21 is an insulating substrate layer.
  • the conductive layer 22 includes a first conductive portion 221 and a second conductive portion 222, and the thickness of the first conductive portion 221 is greater than the thickness of the second conductive portion 222, and between the first conductive portion 221 and the upper surface of the second conductive portion 222
  • the stepped shape is formed, and the lower surface forms a continuous horizontal plane, that is, the conductive layer of the drain region and the channel portion is thinner, and the conductive layer of the source region is thicker.
  • the material of the conductive layer includes black phosphorus, wherein black phosphorus is formed by stacking layered phosphorus atoms, and the single layer of phosphorus atoms is usually called phosphoolefin or single layer of phosphoenene, and a few layers are stacked. Less layer of phosphone.
  • the monolayer of the phosphene has a thickness of about 0.5 nm and a band gap of about 2 eV. As the number of layers increases, the corresponding band gap will decrease accordingly. When the number of layers reaches 20 layers or more, the band gap will not continue to increase, but will stabilize at about 0.3 eV.
  • the preparation process of the TFET is simpler, and since the black phosphorus in the drain region and the channel portion is thinner, the black phosphorus in the source region is thicker, so that the TFET can be made more Large on-state current and good switching ratio.
  • the source region electrode 23 covers the outer surface of the first conductive portion 221, and the vertical surface where the step formed between the first conductive portion 221 and the upper surface of the second conductive portion 222 is located is one of the source region electrodes 23.
  • the boundary, that is, the right side surface of the source region black phosphorus is aligned with the right side surface of the source region electrode 23.
  • the first insulating layer 25 is a gate dielectric covering the outer surfaces of the source region electrode 23, the conductive layer 22 and the drain region electrode 24, that is, the TFET adopts a single gate structure, and the gate dielectric covers the upper surface and the source region of the channel black phosphorus.
  • the side surface of the black phosphorus and the upper surface and the side surface of the source region electrode and the drain region electrode, and the gate dielectric is seamlessly connected to the right side surface of the source region black phosphorus.
  • the gate electrode 26 covers the surface of the first insulating layer 25 away from the conductive layer 22, and is located in a space between the source region electrode 23 and the drain region electrode 24, and the gate electrode 26 is formed with the source region electrode 23 and the drain region electrode 24. In the self-aligned structure, the left and right sides of the gate electrode 26 are seamlessly connected to the first insulating layer 25.
  • the second insulating layer 27 covers the surface of the first insulating layer 25 and the gate electrode 26 away from the first insulating layer 25.
  • the second insulating layer 27 is an insulating medium and is an isolation layer between the devices.
  • the source region electrode 23 may adopt a high work function metal material in a specific implementation process, for example, Metal palladium is used, and the drain electrode 24 can be made of a low work function metal material, such as metal aluminum.
  • the metal palladium can form a P-type doping to the black phosphorus in the source region, the hole injection efficiency is improved, and the metal aluminum can be leaked.
  • the region black phosphorus forms an N-type doping, which improves the electron collection efficiency, thereby obtaining a high-performance N-type TFET.
  • the source region electrode 23 may also adopt a low work function metal material in a specific implementation process, for example, metal aluminum may be used, and the drain region electrode 24 may adopt a high work function metal material, such as metal palladium, thereby obtaining high.
  • Performance P-type TFET may also adopt a low work function metal material in a specific implementation process, for example, metal aluminum may be used, and the drain region electrode 24 may adopt a high work function metal material, such as metal palladium, thereby obtaining high. Performance P-type TFET.
  • the source region electrode 23 and the drain region electrode 24 need to adopt different metal materials to form asymmetric doping of the source region and the drain region.
  • the source region electrode 23 and the drain region electrode 24 are further Other materials may be used.
  • the embodiment is not limited herein.
  • the thickness of the first conductive portion 221 is not less than 3 nm, and the thickness of the second conductive portion 222 is not more than 10 nm, between the first conductive portion 221 and the upper surface of the second conductive portion 222.
  • the height of the step formed is not less than 1 nm.
  • the working principle of the above-mentioned tunneling field effect transistor is as follows: when the N-type TFET is taken as an example, when the source region electrode 23 is a high-power function electrode, the black phosphorus directly under the source region electrode 23 forms a P-type doping. When a positive voltage is applied to the pole 26, the black phosphorus under the gate 26 is N-type, and a PN junction is formed between the black phosphorus in the two regions. If the gate voltage is sufficiently strong, electrons on the left and right sides of the PN junction will undergo inter-band tunneling. Forming a strong conduction current (ie, the TFET enters the on state).
  • the gate voltage is zero or the gate voltage is weak, the transistor does not significantly tunnel, and the conduction current is weak (ie, the TFET is in the off state);
  • the type TFET the source region electrode 23 uses a low work function metal such that the black phosphorus under it is N-doped, and when the gate voltage applies a strong negative voltage, the black phosphor under the gate 26 forms a P-type doping, thereby forming a TFET. Entering the on state, if the gate voltage is zero or weak, the TFET is off.
  • the tunneling field effect transistor provided by each embodiment of the present application has a conductive layer including a first conductive portion and a second conductive portion, and the first conductive portion and the second conductive portion cover a portion of the surface of the substrate layer, and the thickness of the first conductive portion The thickness of the second conductive portion is larger than that of the second conductive portion, and the first conductive portion and the upper surface of the second conductive portion are stepped.
  • the TFET of the structure adopts a thick black phosphorus in the source region, and the trench
  • the channel and the drain region are made of thin black phosphorus, so they have a large on-state current and a good switching ratio, and the structure process is simple, easy to prepare, and the controllability is strong, so that the uniformity of device performance can be effectively improved. Repeatability.
  • FIG. 3 is a flowchart of Embodiment 1 of a method for manufacturing a tunneling field effect transistor according to an embodiment of the present disclosure. As shown in FIG. 3, the specific steps of the method for manufacturing the tunneling field effect transistor include:
  • Step 101 Place a conductive layer on the substrate layer, and form a source region electrode at one end of the substrate layer and the conductive layer, wherein the conductive layer covered by the source region electrode is the first conductive portion.
  • a suitable substrate material may be first selected to form a substrate layer according to a desired shape, and then the conductive layer is transferred onto the substrate layer, and a source region electrode is formed at one end of the substrate layer and the conductive layer, wherein the conductive layer
  • the material can be black phosphorus.
  • the specific way of forming the source region electrode is: spin-coating the photoresist on the substrate layer and the conductive layer; treating the inner region of one end edge of the photoresist by a lift-off technique to expose the substrate layer and the conductive layer; On the underlayer and the conductive layer, source electrode electrodes made of a high work function metal or a low work function metal are formed.
  • Step 102 forming a second conductive portion on a portion of the conductive layer other than the first conductive portion, wherein a thickness of the first conductive portion is greater than a thickness of the second conductive portion, and the first conductive portion and the second conductive portion are upper A stepped shape is formed between the surfaces.
  • a stepped shape is formed between the first conductive portion and the upper surface of the second conductive portion, and the lower surface forms a continuous horizontal surface.
  • the surface of the conductive layer except the first conductive portion may be subjected to oxidation treatment by oxygen plasma or ultraviolet light irradiation technology; the oxidized conductive layer is hydrolyzed, and the remaining portion after hydrolysis is used as a second conductive portion.
  • the surface of the black phosphorus not covered by the source region electrode may be oxidized by oxygen plasma or ultraviolet light irradiation to form an oxide of phosphorus, and then the obtained sample is placed in water which has been previously removed from oxygen, and the phosphorus oxide is added. Hydrolysis, thereby exposing the surface of the black phosphorus which is not oxidized, thereby obtaining a second conductive portion.
  • Step 103 forming a drain electrode on an end of the second conductive portion that is away from the first conductive portion.
  • the photoresist is spin-coated on the substrate layer and the second conductive portion; the inner region of the one end edge of the photoresist away from the source region electrode is processed by a lift-off technique to expose the substrate layer and the second conductive layer.
  • a drain region electrode made of a high work function metal or a low work function metal, wherein the source region electrode and the drain region electrode are different in material on the exposed substrate layer and the second conductive portion.
  • the specific implementation manner of forming the drain region electrode is similar to the specific implementation manner of forming the source region electrode, and details are not described herein again. It should be noted that the material of the source electrode is different from the material of the drain electrode. If the source electrode uses a high work function metal, the drain electrode will use a low work function metal, if the source electrode uses a low work function metal. The drain electrode will use a high work function metal.
  • Step 104 forming a first insulating layer on the outer side of the substrate layer, the source region electrode, the conductive layer, and the drain electrode.
  • the first insulating layer is a gate dielectric, and the first insulating layer may be formed on the outer side of the substrate layer, the source region electrode, the conductive layer, and the drain electrode by atomic layer deposition.
  • Step 105 forming a gate in an upper portion of the first insulating layer and in a gap between the source region electrode and the drain region electrode.
  • the gate is located in the gap between the source region electrode and the drain region electrode, and the left and right sides thereof are seamlessly connected to the first insulating layer.
  • Step 106 forming a second insulating layer on the first insulating layer and the gate.
  • a second insulating layer is formed on the first insulating layer and the gate by chemical vapor deposition or a leveling technique.
  • the source region electrode is formed at one end of the substrate layer and the conductive layer, and the conductive layer covered by the source region electrode is used as the first conductive portion, and the first conductive layer is removed in the conductive layer.
  • a second conductive portion is formed on a portion other than the portion, wherein a thickness of the first conductive portion is greater than a thickness of the second conductive portion, and a stepped shape is formed between the first conductive portion and the upper surface of the second conductive portion due to the source region Thicker black phosphorus is used, and the channel and drain regions are made of thinner black phosphorus, so the TFET has a larger on-state current and a better switching ratio.
  • the above process is simple, the TFET is easy to prepare, and the controllability is strong, so that the uniformity and repeatability of the device performance can be effectively improved.
  • FIG. 4(a) to FIG. 4(g) are examples of a method for fabricating a tunneling field effect transistor according to an embodiment of the present application.
  • Step 1 Transfer black phosphorus to the substrate layer and form source region electrodes at one end of the substrate layer and the conductive layer.
  • the conductive layer 32 that is, black phosphorus
  • the conductive layer 32 is first transferred onto the substrate layer 31, and then a layer of photoresist 33 is spin-coated on the substrate layer 31 and the conductive layer 32. Then, the method of optical exposure forms a pattern of the source region electrodes.
  • the source region electrode 34 made of a high work function metal or a low work function metal is formed by thermal evaporation, electron beam evaporation or sputtering, and the like.
  • the photoresist and the metal covered on the photoresist are stripped and removed by an organic solvent immersion method.
  • Step 2 Form a second conductive portion on a portion of the conductive layer other than the first conductive portion.
  • the surface of the black phosphorus 32 not covered by the source region electrode 34 is oxidized by oxygen plasma or ultraviolet light irradiation to form an oxide of phosphorus, and then the obtained sample is placed in the oxygen which has been previously removed.
  • Phosphorus The compound is hydrolyzed to expose the surface of the black phosphorus which is not oxidized, thereby obtaining black phosphorus 322, that is, the second conductive portion, and the portion covered by the source region electrode 34 forms the source region black phosphorus 321 which is the first conductive portion.
  • the thickness of the first conductive portion 321 is greater than the thickness of the second conductive portion 322, and a stepped shape is formed between the first conductive portion 321 and the upper surface of the second conductive portion 322.
  • Step 3 Form a drain electrode on an end of the second conductive portion that is away from the first conductive portion.
  • a layer of photoresist may be spin-coated on the substrate layer 31 and the second conductive portion 322, followed by exposure to form a pattern of drain electrode. Then, a drain electrode 35 made of a high work function metal or a low work function metal is formed by evaporation or sputtering, and the photoresist and the metal covered on the photoresist are stripped and removed.
  • the drain region electrode 35 and the source region electrode 34 are made of different materials.
  • Step 4 Form a first insulating layer on the outer side of the substrate layer, the source region electrode, the conductive layer, and the drain region electrode.
  • a first insulating layer 36 that is, a gate dielectric such as alumina or oxide is uniformly formed on the surface of the substrate layer, the source region electrode, the conductive layer, and the drain electrode by atomic layer deposition.
  • Step 5 Form a gate electrode in an upper portion of the first insulating layer and in a gap between the source region electrode and the drain region electrode.
  • a layer of photoresist is spin-coated on the first insulating layer 36, and then exposed to form a pattern of gate electrodes.
  • the gate electrode 37 is then formed by evaporation or sputtering, and the photoresist and the metal covered on the photoresist are stripped away.
  • Step 6 Form a second insulating layer on the first insulating layer and the gate.
  • the second insulating layer 38 of the isolation layer is obtained by chemical vapor deposition or homogenization.
  • the above process is a detailed process for fabricating the tunneling field effect transistor provided by the present application, and the tunneling field effect transistor shown in FIG. 2 can be fabricated by the above method.
  • the manufacturing method of the tunneling field effect transistor provided in this embodiment is used for manufacturing the tunneling field effect transistor described above, by forming a source region electrode at one end of the substrate layer and the conductive layer, and the conductive layer covered by the source region electrode is used as the first a conductive portion, and forming a second conductive portion on a portion of the conductive layer other than the first conductive portion, wherein a thickness of the first conductive portion is greater than a thickness of the second conductive portion, and the first conductive portion and the second conductive portion
  • the upper surface is stepped, and since the source region uses thicker black phosphorus and the channel and drain regions use thinner black phosphorus, the TFET has a larger on-state current and a better switching ratio.
  • the above process is simple, the TFET is easy to prepare, and the controllability is strong, so that the uniformity and repeatability of the device performance can be effectively improved.

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Abstract

一种隧穿场效应晶体管及其制造方法，该隧穿场效应晶体管包括：衬底层（21）；导电层（22）包括第一导电部（221）和第二导电部（222），第一导电部（221）和第二导电部（222）覆盖在衬底层（21）的部分表面，第一导电部（221）的厚度大于第二导电部（222）的厚度；源区电极（23）覆盖在第一导电部（221）的外表面上；漏区电极（24）覆盖在第二导电部（222）远离第一导电部（221）的外表面上；第一绝缘层（25）位于衬底层（21）的上表面，且覆盖在源区电极（23）、导电层（22）和漏区电极（24）的外表面；栅极（26）覆盖在第一绝缘层（25）远离导电层（22）的表面上，且位于源区电极（23）与漏区电极（24）之间的空隙中；第二绝缘层（27）覆盖在第一绝缘层（25）和栅极（26）远离第一绝缘层（25）的表面上。所述隧穿场效应晶体管在提升器件的开态电流和开关比的同时，能够有效提高器件性能的均一性和可重复性。

Description

隧穿场效应晶体管及其制造方法 技术领域
本申请实施例涉及通信技术，尤其涉及一种隧穿场效应晶体管(Tunnel field effect transistor，TFET)及其制造方法。
背景技术
目前，为了降低金氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)器件的功耗，需要降低工作电压，然而，目前CMOS技术由于其晶体管工作原理的限制，其工作电压通常在1V左右，超低工作电压(如0.3V以下)电路的实现需要从晶体管原理上进行突破。目前有不少新原理晶体管的研究，TFET是其中一种较有潜力的技术。和目前硅基MOSFET不同，TFET在开态和关态间的转变是通过是否发生带间隧穿来实现，室温下，其亚阈值摆幅理论上可以小于60mV/dec，从而可以在很小的电压下实现正常开和关。
图1为现有技术中具有异质结效应的黑磷TFET，如图1所示，图中的11表示源区，13表示漏区，12表示沟道，16为栅介质，17为栅金属，14和15表示沟道材料，其中，沟道材料为黑磷，另外，如图1所示，该TFET为双栅结构，即沟道12的两侧都有栅介质16和栅金属17，其中，黑磷材料左侧较厚，右侧较薄，两者之间存在台阶，且上下表面各有一个台阶，其中的栅结构对上述台阶形成覆盖。由于左右两侧黑磷的厚度不同，因此可以实现较大的开态电流。
然而，上述TFET中的台阶结构由于实际制备时工艺精度的限制，其在沟道中的位置并不能精确控制，因此，不同器件中台阶所出现的位置会出现一定的波动，从而会影响器件性能的均一性和可重复性。
发明内容
本申请实施例提供一种隧穿场效应晶体管及其制造方法，用于解决不同器件的器件性能的均一性和可重复性不高的问题。
本申请第一方面提供一种隧穿场效应晶体管，包括：衬底层；
导电层，包括第一导电部和第二导电部，所述第一导电部和所述第二导电部覆盖在所述衬底层的部分表面，所述第一导电部的厚度大于所述第二导电部的厚度，且所述第一导电部与所述第二导电部的上表面之间形成台阶状；
源区电极，所述源区电极覆盖在所述第一导电部的外表面上，且所述台阶所在的竖直面为所述源区电极的一个边界；
漏区电极，所述漏区电极覆盖在所述第二导电部远离所述第一导电部的外表面上；
第一绝缘层，所述第一绝缘层位于所述衬底层的上表面，且覆盖在所述源区电极、所述导电层和所述漏区电极的外表面；
栅极，所述栅极覆盖在所述第一绝缘层远离所述导电层的表面上，且位于所述源区电极与所述漏区电极之间的空隙中，所述栅极包括多个表面，其中两个表面分别与覆盖在源区电极上的第一绝缘层和覆盖在漏区电极上的第一绝缘层接触；
第二绝缘层，所述第二绝缘层覆盖在所述第一绝缘层和所述栅极远离所述第一绝缘层的表面上。
其中，导电层包括第一导电部和第二导电部，第一导电部和第二导电部覆盖在衬底层的部分表面，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状，与现有技术相比，此结构的TFET由于第一导电部的厚度大于第二导电部的厚度，因此具有较大的开态电流和较好的开关比，而且结构工艺简单，容易制备，可控性强，从而可以有效的提高器件性能的均一性和可重复性。
可选地，所述导电层的材料包括黑磷。
其中，由于本实施例中仅以黑磷作为沟道材料，使得TFET的制备工艺更为简单。
可选地，所述源区电极为高功函数金属材料，所述漏区电极为低功函数金属材料。
其中，源区电极可以采用高功函数金属材料，例如可以采用金属钯，而漏区电极可以采用低功函数金属材料，如金属铝，此时，由于金属钯可以对源区黑磷形成P型掺杂，提高空穴注入效率，金属铝可以对漏区黑磷形成N型掺杂，提高电子收集效率，从而获得高性能的N型TFET。
可选地，所述源区电极为低功函数金属材料，所述漏区电极为高功函数金属材料。
其中，源区电极可以采用低功函数金属材料，例如可以采用金属铝，而漏区电极可以采用高功函数金属材料，如金属钯，从而获得高性能的P型TFET。
可选地，所述第一导电部的厚度不小于3nm，所述第二导电部的厚度不超过10nm，所述第一导电部与所述第二导电部的上表面之间形成的台阶的高度不小于1nm。
本申请第二方面提供一种隧穿场效应晶体管的制造方法，包括：
将导电层放置在衬底层上，并在所述衬底层和所述导电层的一端形成源区电极，其中，被所述源区电极覆盖的导电层为第一导电部；
在所述导电层除所述第一导电部之外的部分上形成第二导电部，其中，所述第一导电部的厚度大于所述第二导电部的厚度，且所述第一导电部与所述第二导电部的上表面之间形成台阶状；
在所述第二导电部上远离所述第一导电部的一端形成漏区电极；
在所述衬底层、所述源区电极、所述导电层和所述漏区电极的整体外侧形成第一绝缘层；
在所述第一绝缘层上部，且位于所述源区电极与所述漏区电极之间的空隙中形成栅极；
在所述第一绝缘层和所述栅极上形成第二绝缘层。
该方法形成的隧穿场效应晶体管，通过在衬底层和导电层的一端形成源区电极，且被源区电极覆盖的导电层作为第一导电部，并在导电层除第一导电部之外的部分上形成第二导电部，其中，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状，由于源区采用较厚的黑磷，而沟道和漏区采用较薄的黑磷，因此该TFET具有较大的开态电流和较好的开关比。另外，上述工艺过程简单，使TFET容易 制备，可控性强，从而可以有效的提高器件性能的均一性和可重复性。
可选地，所述在所述衬底层和所述导电层的一端形成源区电极，包括：
在所述衬底层和所述导电层上旋涂光刻胶；
通过剥离技术对所述光刻胶一端边缘的内侧区域进行处理，以露出所述衬底层和所述导电层；
在露出的衬底层和导电层上，形成由高功函数金属或低功函数金属为材料的源区电极。
可选地，所述在所述导电层除所述第一导电部之外的部分上形成第二导电部，包括：
通过氧等离子或紫外光辐照技术将除所述第一导电部之外的导电层表面进行氧化处理；
将氧化后的导电层进行水解，将水解后的剩余部分作为所述第二导电部。
可选地，所述在所述第二导电部上远离所述第一导电部的一端形成漏区电极，包括：
在所述衬底层和所述第二导电部上旋涂光刻胶；
通过剥离技术对所述光刻胶远离源区电极的一端边缘的内侧区域进行处理，以露出所述衬底层和所述第二导电部；
在露出的衬底层和第二导电部上，形成由高功函数金属或低功函数金属为材料的漏区电极，其中，所述源区电极和所述漏区电极的材料不同。
可选地，所述在所述衬底层、所述源区电极、所述导电层和所述漏区电极的整体外侧形成第一绝缘层，包括：
通过原子层沉积在所述衬底层、所述源区电极、所述导电层和所述漏区电极的整体外侧形成第一绝缘层。
可选地，所述在所述第一绝缘层和所述栅极上形成第二绝缘层，包括：
通过化学气相沉积或匀胶技术在所述第一绝缘层和所述栅极上形成第二绝缘层。
可选地，所述导电层的材料包括黑磷。
本申请提供的隧穿场效应晶体管及其制造方法，通过采用新的结构，导电层包括第一导电部和第二导电部，第一导电部和第二导电部覆盖在衬底层的部分表面，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状，与现有技术相比，此结构的TFET由于第一导电部的厚度大于第二导电部的厚度，因此具有较大的开态电流和较好的开关比，而且结构工艺简单，容易制备，可控性强，从而可以有效的提高器件性能的均一性和可重复性。
附图说明
图1为现有技术中具有异质结效应的黑磷TFET；
图2为本申请实施例提供的隧穿场效应晶体管实施例一的结构示意图；
图3为本申请实施例提供的隧穿场效应晶体管的制造方法实施例一的流程图；
图4(a)至图4(g)为本申请实施例提供的隧穿场效应晶体管的制造方法一实例的制造过程说明示意图。
具体实施方式
本申请提供一种制备工艺简单的TFET，能够有效的提高器件性能的均一性和可重复性，具体的实现请参考下面的实施例。
图2为本申请实施例提供的隧穿场效应晶体管实施例一的结构示意图，如图2所示，该隧穿场效应晶体管，包括：
衬底层21；
导电层22，包括第一导电部221和第二导电部222，该第一导电部221和该第二导电部222覆盖在衬底层21的部分表面，第一导电部221的厚度大于第二导电部222的厚度，且第一导电部221与第二导电部222的上表面之间形成台阶状；
源区电极23，该源区电极23覆盖在第一导电部221的外表面上，且台阶所在的竖直面为源区电极23的一个边界；
漏区电极24，该漏区电极24覆盖在第二导电部222远离第一导电部221的外表面上；
第一绝缘层25，该第一绝缘层25位于衬底层21的上表面，且覆盖在源区电极23、导电层22和漏区电极24的外表面；
栅极26，该栅极26覆盖在第一绝缘层25远离导电层22的表面上，且位于源区电极23与漏区电极24之间的空隙中，栅极26包括多个表面，其中两个表面分别与覆盖在源区电极23上的第一绝缘层25和覆盖在漏区电极24上的第一绝缘层25接触；
第二绝缘层27，该第二绝缘层27覆盖在第一绝缘层25和栅极26远离第一绝缘层25的表面上。
在本实施例中，衬底层21为绝缘衬底层。导电层22包括第一导电部221和第二导电部222，且第一导电部221的厚度大于第二导电部222的厚度，且第一导电部221与第二导电部222的上表面之间形成台阶状，而下表面则形成连续的水平面，也即漏区及沟道部分的导电层较薄，源区的导电层较厚。另外，导电层的材料包括黑磷，其中，黑磷由层状的磷原子堆叠而成，单层的磷原子通常称为磷烯或单层磷烯，少数几层堆叠而成的则称为少层磷烯。单层磷烯厚度约0.5nm，带隙约2eV。随着层数增加其对应的带隙会相应减小，层数达到20层以上时其带隙基本不再继续增加而是稳定在0.3eV左右。由于本实施例中仅以黑磷作为沟道材料，使得TFET的制备工艺更为简单，而且由于漏区及沟道部分的黑磷较薄，源区的黑磷较厚，可以使得TFET具有较大的开态电流和较好的开关比。
另外，源区电极23覆盖在第一导电部221的外表面上，且第一导电部221与第二导电部222的上表面之间形成的台阶所在的竖直面为源区电极23的一个边界，也即源区黑磷的右侧表面与源区电极23的右侧表面对齐。
第一绝缘层25为栅介质，其覆盖在源区电极23、导电层22和漏区电极24的外表面，即TFET采用单栅结构，栅介质覆盖在沟道黑磷的上表面、源区黑磷的侧面及源区电极、漏区电极的上表面与侧面，且栅介质与源区黑磷的右侧面无缝连接。
栅极26覆盖在第一绝缘层25远离导电层22的表面上，且位于源区电极23与漏区电极24之间的空隙中，且栅极26与源区电极23和漏区电极24形成自对准结构，栅极26的左右侧面与第一绝缘层25无缝连接。
第二绝缘层27覆盖在第一绝缘层25和栅极26远离第一绝缘层25的表面上，其中，第二绝缘层27为绝缘介质，为器件之间的隔离层。
可选地，该源区电极23在具体实现的过程中可以采用高功函数金属材料，例如可以 采用金属钯，而漏区电极24可以采用低功函数金属材料，如金属铝，此时，由于金属钯可以对源区黑磷形成P型掺杂，提高空穴注入效率，金属铝可以对漏区黑磷形成N型掺杂，提高电子收集效率，从而获得高性能的N型TFET。
可选地，该源区电极23在具体实现的过程中还可以采用低功函数金属材料，例如可以采用金属铝，而漏区电极24可以采用高功函数金属材料，如金属钯，从而获得高性能的P型TFET。
值得注意的是，源区电极23和漏区电极24需要采用不同的金属材料从而形成源区、漏区的非对称掺杂，在具体的实现过程中，源区电极23和漏区电极24还可以采用其他的材料，对于源区电极23和漏区电极24具体的制备材料，本实施例在此不作限制。
可选地，在TFET的具体实现过程中，第一导电部221的厚度不小于3nm，第二导电部222的厚度不超过10nm，第一导电部221与第二导电部222的上表面之间形成的台阶的高度不小于1nm。
上述的隧穿场效应晶体管的工作原理为：以N型TFET为例，当源区电极23采用高功函数电极时，源区电极23正下方的黑磷形成P型掺杂，此时如果栅极26施加正电压则栅极26下方的黑磷为N型，两个区域的黑磷之间形成PN结，如果栅压足够强时，该PN结左右两侧的电子将发生带间隧穿，形成较强的导电电流(即TFET进入开启状态)，如果栅压为零或者栅压很弱时则晶体管没有明显隧穿，导电电流很微弱(即TFET处于关断状态)；相反，对于P型TFET，源区电极23采用低功函数金属以使其下方黑磷呈N型掺杂，而栅压施加较强的负电压时，栅极26下方的黑磷形成P型掺杂，从而TFET进入开启状态，如果栅压为零或者很弱时则TFET处于关断状态。本申请各个实施例提供的隧穿场效应晶体管，其导电层包括第一导电部和第二导电部，第一导电部和第二导电部覆盖在衬底层的部分表面，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状，与现有技术相比，此结构的TFET由于源区采用较厚的黑磷，而沟道和漏区采用较薄的黑磷，因此具有较大的开态电流和较好的开关比，而且结构工艺简单，容易制备，可控性强，从而可以有效的提高器件性能的均一性和可重复性。
图3为本申请实施例提供的隧穿场效应晶体管的制造方法实施例一的流程图，如图3所示，该隧穿场效应晶体管的制造方法的具体步骤包括：
步骤101、将导电层放置在衬底层上，并在衬底层和导电层的一端形成源区电极，其中，被源区电极覆盖的导电层为第一导电部。
在本实施例中，可以先选择合适的衬底材料按照需要的形状加工形成衬底层，再将导电层转移到衬底层上，在衬底层和导电层的一端形成源区电极，其中，导电层的材料可以为黑磷。具体的形成源区电极的方式是：在衬底层和导电层上旋涂光刻胶；通过剥离技术对光刻胶一端边缘的内侧区域进行处理，以露出衬底层和导电层；在露出的衬底层和导电层上，形成由高功函数金属或低功函数金属为材料的源区电极。
步骤102、在导电层除第一导电部之外的部分上形成第二导电部，其中，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状。
在本实施例中，第一导电部与第二导电部的上表面之间形成台阶状，下表面则形成连续的水平面。在具体的实现过程中，可以通过氧等离子或紫外光辐照技术将除第一导电部之外的导电层表面进行氧化处理；将氧化后的导电层进行水解，将水解后的剩余部分作为 第二导电部。具体地，可以通过氧等离子或者紫外光辐照等方法将未被源区电极覆盖的黑磷表面氧化，形成磷的氧化物，然后将所得样品放入预先已除去氧气的水中，将磷氧化物水解，从而暴露出未被氧化的黑磷表面，由此得到第二导电部。
步骤103、在第二导电部上远离第一导电部的一端形成漏区电极。
在本实施例中，通过在衬底层和第二导电部上旋涂光刻胶；通过剥离技术对光刻胶远离源区电极的一端边缘的内侧区域进行处理，以露出衬底层和第二导电部；在露出的衬底层和第二导电部上，形成由高功函数金属或低功函数金属为材料的漏区电极，其中，源区电极和所述漏区电极的材料不同。其中，形成漏区电极的具体实现方式与形成源区电极的具体实现方式类似，此处不再赘述。需要进行说明的是，源区电极的材料与漏区电极的材料不同，如若源区电极采用高功函数金属，则漏区电极则将采用低功函数金属，若源区电极采用低功函数金属，则漏区电极则将采用高功函数金属。
步骤104、在衬底层、源区电极、导电层和漏区电极的整体外侧形成第一绝缘层。
在本实施例中，第一绝缘层为栅介质，可以通过原子层沉积的方式在衬底层、源区电极、导电层和漏区电极的整体外侧形成第一绝缘层。
步骤105、在第一绝缘层上部，且位于源区电极与漏区电极之间的空隙中形成栅极。
在本实施例中，栅极位于源区电极与漏区电极之间的空隙中，且其左右侧面与第一绝缘层无缝连接。
步骤106、在第一绝缘层和栅极上形成第二绝缘层。
在本实施例中，通过化学气相沉积或匀胶技术在第一绝缘层和栅极上形成第二绝缘层。
本实施例提供的隧穿场效应晶体管的制造方法，在衬底层和导电层的一端形成源区电极，且被源区电极覆盖的导电层作为第一导电部，并在导电层除第一导电部之外的部分上形成第二导电部，其中，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状，由于源区采用较厚的黑磷，而沟道和漏区采用较薄的黑磷，因此该TFET具有较大的开态电流和较好的开关比。另外，上述工艺过程简单，使TFET容易制备，可控性强，从而可以有效的提高器件性能的均一性和可重复性。
在上述实施例的基础上，下面举一实例详细说明本制造方法的具体实现步骤：图4(a)至图4(g)为本申请实施例提供的隧穿场效应晶体管的制造方法一实例的制造过程说明示意图。
步骤1、将黑磷转移到衬底层上，并在衬底层和导电层的一端形成源区电极。
如图4(a)所示，在形成衬底层31之后，首先将导电层32，即黑磷转移到衬底层31上，然后在衬底层31和导电层32上旋涂一层光刻胶33，之后进行光学曝光的方法形成源区电极的图形。
如图4(b)所示，在形成源区电极的图形之后，通过热蒸发、电子束蒸发或溅射等方法形成以高功函数金属或低功函数金属为材料的源区电极34，并通过有机溶剂浸泡的方法剥离去除光刻胶及光刻胶上覆盖的金属。
步骤2、在导电层除第一导电部之外的部分上形成第二导电部。
如图4(c)所示，通过氧等离子或者紫外光辐照等方法将未被源区电极34覆盖的黑磷32表面氧化，形成磷的氧化物，然后将所得样品放入预先已除去氧气的水中，将磷氧 化物水解，从而暴露出未被氧化的黑磷表面，由此得到黑磷322，即第二导电部，被源区电极34覆盖的部分形成源区黑磷321，即第一导电部。其中，第一导电部321的厚度大于第二导电部322的厚度，且第一导电部321与第二导电部322的上表面之间形成台阶状。
步骤3、在第二导电部上远离第一导电部的一端形成漏区电极。
如图4(d)所示，与步骤1类似，可以在衬底层31和第二导电部322上旋涂一层光刻胶，之后进行曝光，形成漏区电极的图形。然后通过蒸发或溅射等方法形成以高功函数金属或低功函数金属为材料的漏区电极35，并剥离去除光刻胶及光刻胶上覆盖的金属。其中，漏区电极35与源区电极34采用不同的材料。
步骤4、在衬底层、源区电极、导电层和漏区电极的整体外侧形成第一绝缘层。
如图4(e)所示，通过原子层沉积的方式在衬底层、源区电极、导电层和漏区电极的表面均匀形成一层第一绝缘层36，即栅介质，如氧化铝或氧化铪等。
步骤5、在第一绝缘层上部，且位于源区电极与漏区电极之间的空隙中形成栅极。
如图4(f)所示，在第一绝缘层36上旋涂一层光刻胶，之后进行曝光，形成栅极的图形。然后通过蒸发或溅射等方法形成栅极37，并剥离去除光刻胶及光刻胶上覆盖的金属。
步骤6、在第一绝缘层和栅极上形成第二绝缘层。
如图4(g)所示，通过化学气相沉积或者匀胶的方法得到隔离层第二绝缘层38。
上述过程为制作本申请提供的隧穿场效应晶体管的详细工艺过程，图2所示的隧穿场效应晶体管可采用上述方法制造。
本实施例提供的隧穿场效应晶体管的制造方法，用于制造前述的隧穿场效应晶体管，通过在衬底层和导电层的一端形成源区电极，且被源区电极覆盖的导电层作为第一导电部，并在导电层除第一导电部之外的部分上形成第二导电部，其中，第一导电部的厚度大于第二导电部的厚度，且第一导电部与第二导电部的上表面之间形成台阶状，由于源区采用较厚的黑磷，而沟道和漏区采用较薄的黑磷，因此该TFET具有较大的开态电流和较好的开关比。另外，上述工艺过程简单，使TFET容易制备，可控性强，从而可以有效的提高器件性能的均一性和可重复性。

Claims (12)

  1. 一种隧穿场效应晶体管，其特征在于，包括：
    衬底层；
    导电层，包括第一导电部和第二导电部，所述第一导电部和所述第二导电部覆盖在所述衬底层的部分表面，所述第一导电部的厚度大于所述第二导电部的厚度，且所述第一导电部与所述第二导电部的上表面之间形成台阶状；
    源区电极，所述源区电极覆盖在所述第一导电部的外表面上，且所述台阶所在的竖直面为所述源区电极的一个边界；
    漏区电极，所述漏区电极覆盖在所述第二导电部远离所述第一导电部的外表面上；
    第一绝缘层，所述第一绝缘层位于所述衬底层的上表面，且覆盖在所述源区电极、所述导电层和所述漏区电极的外表面；
    栅极，所述栅极覆盖在所述第一绝缘层远离所述导电层的表面上，且位于所述源区电极与所述漏区电极之间的空隙中，所述栅极包括多个表面，其中两个表面分别与覆盖在源区电极上的第一绝缘层和覆盖在漏区电极上的第一绝缘层接触；
    第二绝缘层，所述第二绝缘层覆盖在所述第一绝缘层和所述栅极远离所述第一绝缘层的表面上。
  2. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述导电层的材料包括黑磷。
  3. 根据权利要求1或2所述的隧穿场效应晶体管，其特征在于，所述源区电极为高功函数金属材料，所述漏区电极为低功函数金属材料。
  4. 根据权利要求1或2所述的隧穿场效应晶体管，其特征在于，所述源区电极为低功函数金属材料，所述漏区电极为高功函数金属材料。
  5. 根据权利要求1-4任一项所述的隧穿场效应晶体管，其特征在于，所述第一导电部的厚度不小于3nm，所述第二导电部的厚度不超过10nm，所述第一导电部与所述第二导电部的上表面之间形成的台阶的高度不小于1nm。
  6. 一种隧穿场效应晶体管的制造方法，其特征在于，包括：
    将导电层放置在衬底层上，并在所述衬底层和所述导电层的一端形成源区电极，其中，被所述源区电极覆盖的导电层为第一导电部；
    在所述导电层除所述第一导电部之外的部分上形成第二导电部，其中，所述第一导电部的厚度大于所述第二导电部的厚度，且所述第一导电部与所述第二导电部的上表面之间形成台阶状；
    在所述第二导电部上远离所述第一导电部的一端形成漏区电极；
    在所述衬底层、所述源区电极、所述导电层和所述漏区电极的整体外侧形成第一绝缘层；
    在所述第一绝缘层上部，且位于所述源区电极与所述漏区电极之间的空隙中形成栅极；
    在所述第一绝缘层和所述栅极上形成第二绝缘层。
  7. 根据权利要求6所述的方法，其特征在于，所述在所述衬底层和所述导电层的一端形成源区电极，包括：
    在所述衬底层和所述导电层上旋涂光刻胶；
    通过剥离技术对所述光刻胶一端边缘的内侧区域进行处理，以露出所述衬底层和所述导电层；
    在露出的衬底层和导电层上，形成由高功函数金属或低功函数金属为材料的源区电极。
  8. 根据权利要求6或7所述的方法，其特征在于，所述在所述导电层除所述第一导电部之外的部分上形成第二导电部，包括：
    通过氧等离子或紫外光辐照技术将除所述第一导电部之外的导电层表面进行氧化处理；
    将氧化后的导电层进行水解，将水解后的剩余部分作为所述第二导电部。
  9. 根据权利要求6-8任一项所述的方法，其特征在于，所述在所述第二导电部上远离所述第一导电部的一端形成漏区电极，包括：
    在所述衬底层和所述第二导电部上旋涂光刻胶；
    通过剥离技术对所述光刻胶远离源区电极的一端边缘的内侧区域进行处理，以露出所述衬底层和所述第二导电部；
    在露出的衬底层和第二导电部上，形成由高功函数金属或低功函数金属为材料的漏区电极，其中，所述源区电极和所述漏区电极的材料不同。
  10. 根据权利要求6-9任一项所述的方法，其特征在于，所述在所述衬底层、所述源区电极、所述导电层和所述漏区电极的整体外侧形成第一绝缘层，包括：
    通过原子层沉积在所述衬底层、所述源区电极、所述导电层和所述漏区电极的整体外侧形成第一绝缘层。
  11. 根据权利要求6-10任一项所述的方法，其特征在于，所述在所述第一绝缘层和所述栅极上形成第二绝缘层，包括：
    通过化学气相沉积或匀胶技术在所述第一绝缘层和所述栅极上形成第二绝缘层。
  12. 根据权利要求6-11任一项所述的方法，其特征在于，所述导电层的材料包括黑磷。
PCT/CN2017/075275 2017-02-28 2017-02-28 隧穿场效应晶体管及其制造方法 WO2018157319A1 (zh)

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