WO2017008331A1 - Tft基板结构及其制作方法 - Google Patents

Tft基板结构及其制作方法 Download PDF

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Publication number
WO2017008331A1
WO2017008331A1 PCT/CN2015/085157 CN2015085157W WO2017008331A1 WO 2017008331 A1 WO2017008331 A1 WO 2017008331A1 CN 2015085157 W CN2015085157 W CN 2015085157W WO 2017008331 A1 WO2017008331 A1 WO 2017008331A1
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amorphous silicon
layer
doped amorphous
silicon layer
heavily doped
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PCT/CN2015/085157
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English (en)
French (fr)
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吕晓文
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深圳市华星光电技术有限公司
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Priority to US14/778,087 priority Critical patent/US9553198B1/en
Publication of WO2017008331A1 publication Critical patent/WO2017008331A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT substrate structure and a method of fabricating the same.
  • Amorphous silicon is currently the most widely used active layer material in the semiconductor industry.
  • A-Si materials are in contact with metals, it is difficult to form ohmic contacts because of the large potential difference.
  • the ohmic contact between the semiconductors in order to obtain metal and The ohmic contact between the semiconductors generally super-does the P element on the semiconductor surface, reduces the contact resistance between the metal and the semiconductor, and improves the current efficiency.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional TFT substrate.
  • the TFT substrate structure includes a substrate 100, a gate electrode 200 disposed on the substrate 100, a gate insulating layer 300 disposed on the substrate 100 and covering the gate electrode 200, and corresponding to the gate electrode 200.
  • a channel region 450 is formed on the amorphous silicon layer 400 corresponding to the gate electrode 200; the first and second N are respectively formed on the surface of the amorphous silicon layer 400 corresponding to the two sides of the channel region 450.
  • the source 500 and the drain 600 are in contact with the surfaces of the first and second N-type heavily doped regions 410, 420, respectively.
  • FIG. 2 is a graph showing leakage current Ioff of the A-Si device having the TFT substrate structure of FIG. 1 as a function of the gate voltage Vg.
  • the TFT substrate structure of FIG. 1 is increasing the operating current ( At the same time, Ion) also has certain problems.
  • Ioff leakage current
  • Another object of the present invention is to provide a method for fabricating a TFT substrate structure, which can effectively reduce the energy barrier between the metal layer and the amorphous silicon layer, make electron injection easier, and reduce leakage without reducing the operating current. Current improves the electrical properties of the TFT.
  • the present invention provides a TFT substrate structure including a substrate, a gate electrode disposed on the substrate, and a gate insulating layer disposed on the substrate to cover the gate electrode, corresponding to the An island-shaped semiconductor layer disposed on the gate insulating layer above the gate; and a source and a drain respectively disposed on the gate insulating layer and contacting the two sides of the island-shaped semiconductor layer;
  • the island-shaped semiconductor layer includes an amorphous silicon layer, an N-type lightly doped amorphous silicon layer, and an N-type heavily doped amorphous silicon layer stacked in this order from bottom to top, and the island-shaped semiconductor layer is provided with a U a groove, the U-shaped groove penetrating the N-type lightly doped amorphous silicon layer and the N-type heavily doped amorphous silicon layer, and dividing the N-type heavily doped amorphous silicon layer into two U-shaped grooves
  • the first and second N-type heavily doped amorphous silicon layers on the side, the N-type lightly doped amorphous silicon layer is divided into first and second N-type lightly doped amorphous on both sides of the U-shaped groove a silicon layer on the amorphous silicon layer corresponding to a position below the U-shaped groove to form a channel;
  • the source and the drain are respectively in contact with surfaces of the first and second N-type heavily doped amorphous silicon layers.
  • the impurity incorporated in the N-type lightly doped amorphous silicon layer and the N-type heavily doped amorphous silicon layer is a P element.
  • the concentration of the P atoms doped in the N-type heavily doped amorphous silicon layer is more than twice the concentration of the P atoms doped in the N-type lightly doped amorphous silicon layer.
  • the substrate is a glass substrate or a plastic substrate
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two, and the material of the source and the drain is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the present invention also provides a TFT substrate structure, including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the substrate to cover the gate electrode, and corresponding to the gate electrode disposed above An island-shaped semiconductor layer on the gate insulating layer; and a source and a drain respectively disposed on the gate insulating layer and contacting the two sides of the island-shaped semiconductor layer;
  • the island-shaped semiconductor layer includes an amorphous silicon layer, an N-type lightly doped amorphous silicon layer, and an N-type heavily doped amorphous silicon layer stacked in this order from bottom to top, and the island-shaped semiconductor layer is provided with a U a groove, the U-shaped groove penetrating the N-type lightly doped amorphous silicon layer and the N-type heavily doped amorphous silicon layer, and dividing the N-type heavily doped amorphous silicon layer into two U-shaped grooves
  • the first and second N-type heavily doped amorphous silicon layers on the side, the N-type lightly doped amorphous silicon layer is divided into first and second N-type lightly doped amorphous on both sides of the U-shaped groove a silicon layer on the amorphous silicon layer corresponding to a position below the U-shaped groove to form a channel;
  • the source and the drain are respectively in contact with surfaces of the first and second N-type heavily doped amorphous silicon layers;
  • the impurity incorporated in the N-type lightly doped amorphous silicon layer and the N-type heavily doped amorphous silicon layer is a P element
  • the concentration of the P atoms doped in the N-type heavily doped amorphous silicon layer is more than twice the concentration of the P atoms doped in the N-type lightly doped amorphous silicon layer;
  • the substrate is a glass substrate or a plastic substrate
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum and copper.
  • the invention also provides a method for fabricating a TFT substrate structure, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate;
  • Step 2 depositing a gate insulating layer on the substrate, the gate insulating layer covering the gate;
  • Step 3 sequentially depositing an amorphous silicon layer, an N-type lightly doped amorphous silicon layer, and an N-type heavily doped amorphous silicon layer by chemical vapor deposition on the gate insulating layer;
  • Step 4 patterning the amorphous silicon layer, the N-type lightly doped amorphous silicon layer, and the N-type heavily doped amorphous silicon layer by a photolithography process to obtain an island located above the gate a semiconductor layer, the island-shaped semiconductor layer comprising an amorphous silicon layer corresponding to the gate, an N-type lightly doped amorphous silicon layer, and an N-type heavily doped amorphous silicon layer;
  • Step 5 depositing a second metal layer on the gate insulating layer and the island-shaped semiconductor layer, and then coating a photoresist layer on the second metal layer, and performing the photoresist layer on the photoresist layer by using a photomask Exposing, developing, forming a strip-shaped passage on the photoresist layer at an intermediate position and passing through the front and rear;
  • Step 6 using the photoresist layer as an occlusion, performing a wet etching process on the second metal layer to obtain a source and a drain respectively corresponding to the two sides of the strip channel;
  • Step 7 performing a dry etching process on the island-shaped semiconductor layer by using the photoresist layer and the source and the drain as an etch barrier layer, and forming a U corresponding to the strip-shaped channel on the island-shaped semiconductor layer a groove, the U-shaped groove penetrating through the N-type lightly doped amorphous silicon layer and the N-type heavily doped amorphous silicon layer, and dividing the N-type heavily doped amorphous silicon layer into a U-shaped groove
  • the first and second N-type heavily doped amorphous silicon layers on both sides divide the N-type lightly doped amorphous silicon layer into first and second N-type lightly doped non-positive sides on both sides of the U-shaped groove a crystalline silicon layer, a channel is formed on the amorphous silicon layer corresponding to a position below the U-shaped groove; the source and the drain are respectively associated with the first and second N-type heavily doped amorphous silicon layers Surface contact;
  • the photoresist layer located above the source and the drain is stripped.
  • an amorphous silicon layer is deposited by using SiH 4 gas, and an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer are deposited by using PH 3 and SiH 4 gas.
  • the gas flow ratio of PH 3 and SiH 4 is ⁇ 0.5; when the N-type heavily doped amorphous silicon layer is deposited, the gas flow ratio of PH 3 and SiH 4 is >1.
  • the substrate is a glass substrate or a plastic substrate
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two, the source
  • the material with the drain is a combination of one or more of molybdenum, titanium, aluminum, and copper.
  • an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer are formed between the amorphous silicon layer and the metal layer to form a doped layer.
  • the concentration gradient, the lower energy barrier between the metal layer and the amorphous silicon layer makes electron injection easier, while reducing the leakage current without reducing the operating current, and improving the electrical properties of the TFT.
  • an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer are formed between the amorphous silicon layer and the metal layer to form a doping concentration gradient, which is effective
  • the energy barrier between the metal layer and the amorphous silicon layer is lowered, the electron injection is made easier, and the leakage current is reduced without lowering the operating current, thereby improving the electrical properties of the TFT.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional TFT substrate
  • FIG. 2 is a graph showing leakage current of an A-Si device having the TFT substrate structure of FIG. 1;
  • FIG. 3 is a cross-sectional view showing the structure of a TFT substrate of the present invention.
  • FIG. 4 is a graph comparing curves of leakage current of an A-Si device having the TFT substrate structure of FIG. 3 and leakage current of an A-Si device having the TFT substrate structure of FIG. 1;
  • step 1 is a schematic diagram of step 1 of a method for fabricating a TFT substrate structure according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT substrate structure according to the present invention.
  • step 3 is a schematic diagram of step 3 of a method for fabricating a TFT substrate structure according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIGS 9-10 are schematic diagrams showing the fifth step of the method for fabricating the TFT substrate structure of the present invention.
  • FIG. 11 is a schematic view showing a step 6 of a method for fabricating a TFT substrate structure according to the present invention.
  • Figure 12 is a schematic view showing the seventh step of the method of fabricating the TFT substrate structure of the present invention.
  • the present invention firstly provides a TFT substrate structure, including a substrate 10, a gate electrode 20 disposed on the substrate 10, and a gate insulating layer 30 disposed on the substrate 10 to cover the gate electrode 20.
  • a source 51 and a drain 52 respectively provided on the gate insulating layer 30 in contact with both sides of the island-shaped semiconductor layer 40.
  • the island-shaped semiconductor layer 40 includes an amorphous silicon layer 41, an N-type lightly doped amorphous silicon layer 42, and an N-type heavily doped amorphous silicon layer 43, which are sequentially stacked from bottom to top, and the island-shaped semiconductor layer 40 is provided with a U-shaped groove 44 penetrating through the N-type lightly doped amorphous silicon layer 43 and the N-type heavily doped amorphous silicon layer 42, and the N-type heavily doped amorphous
  • the silicon layer 43 is divided into first and second N-type heavily doped amorphous silicon layers 431 and 432 located on both sides of the U-shaped groove 44, and the N-type lightly doped amorphous silicon layer 42 is divided into U-shaped grooves.
  • the source 51 and the drain 52 are in contact with the surfaces of the first and second N-type heavily doped amorphous silicon layers 431 and 432, respectively.
  • the substrate 10 may be a glass substrate or a plastic substrate.
  • the material of the gate 20, the source 51, and the drain 52 may be a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer 30 may be silicon oxide, silicon nitride, or a combination of the two.
  • the impurity incorporated in the N-type lightly doped amorphous silicon layer 42 and the N-type heavily doped amorphous silicon layer 43 is a P element.
  • the concentration of the P atoms doped in the N-type heavily doped amorphous silicon layer 43 is more than twice the concentration of the P atoms doped in the N-type lightly doped amorphous silicon layer 42.
  • FIG. 4 is a graph comparing curves of leakage current of an A-Si device having the TFT substrate structure of FIG. 3 and leakage current of an A-Si device having the TFT substrate structure of FIG. 1, wherein a broken line represents a TFT substrate structure having the structure of FIG.
  • the leakage current Ioff of the A-Si device changes with the gate voltage Vg, and the solid line represents the curve of the leakage current Ioff of the A-Si device having the TFT substrate structure of FIG. 3 as a function of the gate voltage Vg, which can be seen from FIG.
  • the leakage current Ioff of the A-Si device having the TFT substrate structure of FIG. 3 (present invention) is lower than that of the A-Si device having the TFT substrate structure of FIG.
  • an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer are disposed between the amorphous silicon layer and the metal layer to form a doping concentration gradient, a metal layer and an amorphous layer.
  • the lower energy barrier between the silicon layers makes electron injection easier, while reducing the leakage current without reducing the operating current, improving the electrical properties of the TFT.
  • the present invention also provides a method for fabricating the above TFT substrate structure, comprising the following steps:
  • Step 1 as shown in FIG. 5, a substrate 10 is provided, a first metal layer is deposited on the substrate 10, and the first metal layer is patterned to form a gate electrode 20.
  • the substrate 10 may be a glass substrate or a plastic substrate.
  • the material of the gate electrode 20 may be a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • Step 2 As shown in FIG. 6, a gate insulating layer 30 is deposited on the substrate 10, and the gate insulating layer 30 covers the gate 20.
  • the material of the gate insulating layer 30 may be silicon oxide, silicon nitride, or a combination of the two.
  • Step 3 sequentially depositing an amorphous silicon layer 41, an N-type lightly doped amorphous silicon layer 42, and an N-type heavily doped amorphous on the gate insulating layer 30 by a chemical vapor deposition method. Silicon layer 43.
  • the amorphous silicon layer 41 is deposited using SiH 4 gas, and the N-type lightly doped amorphous silicon layer 42 and the N-type heavily doped amorphous silicon layer 43 are deposited using PH 3 and SiH 4 gases.
  • the gas flow ratio of PH 3 and SiH 4 is ⁇ 0.5; when the N-type heavily doped amorphous silicon layer 43 is deposited, the gas flow ratio of PH 3 and SiH 4 >1; therefore, the concentration of P atoms doped in the N-type heavily doped amorphous silicon layer 43 obtained in the step 3 is the concentration of P atoms doped in the N-type lightly doped amorphous silicon layer 42. More than 2 times.
  • Step 4 as shown in FIG. 8, the amorphous silicon layer 41, the N-type lightly doped amorphous silicon layer 42, and the N-type heavily doped amorphous silicon layer 43 are patterned by a photolithography process.
  • An island-shaped semiconductor layer 40 is disposed above the gate electrode 20, and the island-shaped semiconductor layer 40 includes an amorphous silicon layer 41, an N-type lightly doped amorphous silicon layer 42, and a N corresponding to the gate electrode 20 The type is heavily doped with an amorphous silicon layer 43.
  • Step 5 depositing a second metal layer 50 on the gate insulating layer 30 and the island-shaped semiconductor layer 40, and then coating a photoresist layer on the second metal layer 50. 60.
  • the photoresist layer 60 is exposed and developed by using a photomask, and a strip-shaped channel 61 is formed on the photoresist layer 60 at an intermediate position and penetrates the front and rear.
  • Step 6 as shown in FIG. 11, the second metal layer 50 is subjected to a wet etching process by using the photoresist layer 60 as a mask, and the source 51 and the drain respectively corresponding to the two sides of the strip-shaped channel 61 are obtained. 52.
  • the material of the source 51 and the drain 52 may be a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • Step 7 as shown in FIG. 12, the photoresist layer 60 and the source and drain electrodes 51 and 52 are used as an etch barrier layer, and the island-shaped semiconductor layer 40 is subjected to a dry etching process in the island-shaped semiconductor layer.
  • the N-type heavily doped amorphous silicon layer 43 is divided into first and second N-type heavily doped amorphous silicon layers 431 located on both sides of the U-shaped groove 44, 432, dividing the N-type lightly doped amorphous silicon layer 42 into first and second N-type lightly doped amorphous silicon layers 421, 422 on both sides of the U-shaped groove 44, in the amorphous silicon layer
  • a channel 415 is formed at a position corresponding to the lower portion of the U-shaped groove 44
  • the photoresist layer 60 located above the source and drain electrodes 51, 52 is stripped to obtain a TFT substrate structure as shown in FIG.
  • the method for fabricating the TFT substrate structure described above forms an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer between the amorphous silicon layer and the metal layer to form a doping concentration gradient, thereby effectively reducing the concentration.
  • the energy barrier between the metal layer and the amorphous silicon layer makes electron injection easier, while reducing the leakage current without reducing the operating current, and improving the electrical properties of the TFT.
  • an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer are disposed between the amorphous silicon layer and the metal layer to form a doped concentration.
  • the gradient, the energy barrier between the metal layer and the amorphous silicon layer is lower, making electron injection easier, while reducing the leakage current without reducing the operating current, and improving the electrical properties of the TFT.
  • an N-type lightly doped amorphous silicon layer and an N-type heavily doped amorphous silicon layer are formed between the amorphous silicon layer and the metal layer to form a doping concentration gradient, which is effective
  • the energy barrier between the metal layer and the amorphous silicon layer is lowered, the electron injection is made easier, and the leakage current is reduced without lowering the operating current, thereby improving the electrical properties of the TFT.

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Abstract

提供了一种TFT基板结构及其制作方法。TFT基板结构包括在非晶硅层（41）与金属层之间设置的N型轻掺杂非晶硅层（42）与N型重掺杂非晶硅层（43），以形成掺杂的浓度梯度，使得金属层和非晶硅层间的能量势垒较低，使电子注入更加容易，同时在不降低工作电流的前提下降低漏电流，改善了TFT的电性。TFT基板结构的制作方法包括在非晶硅层与金属层之间形成N型轻掺杂非晶硅层与N型重掺杂非晶硅层。

Description

TFT基板结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板结构及其制作方法。
背景技术
非晶硅(A-Si)是目前半导体行业应用最广泛的有源层材料，A-Si材料与金属接触时因为有较大的势能差，难以形成欧姆接触，实际应用中，为了获得金属和半导体之间的欧姆接触，一般对半导体表面进行重掺杂P元素，降低金属和半导体的接触阻抗，提高电流效率。
图1所示为一种现有TFT基板结构的剖面示意图。该TFT基板结构包括基板100、设于所述基板100上的栅极200、设于所述基板100上覆盖所述栅极200的栅极绝缘层300、对应所述栅极200上方设于所述栅极绝缘层300上的非晶硅层400、及设于所述栅极绝缘层300上分别与所述非晶硅层400的两侧相接触的源极500与漏极600。所述非晶硅层400上对应所述栅极200的上方形成有沟道区450；所述非晶硅层400表面对应所述沟道区450的两侧分别形成有第一、第二N型重掺杂区410、420。所述源极500与漏极600分别与所述第一、第二N型重掺杂区410、420的表面相接触。
图2所示为具有图1的TFT基板结构的A-Si器件的漏电流Ioff随栅电压Vg变化的曲线图，从图2中可以看出，图1的TFT基板结构在增大工作电流(Ion)的同时，也存在一定的问题，当加负电压到一定程度时，会引出正电荷形成空穴导电通道，漏电流(Ioff)也随之增大，曲线翘曲严重，造成信赖性的问题。
因此，有必要提供一种TFT基板结构及其制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种TFT基板结构，金属层与非晶硅层间的能量势垒较低，且漏电流较低。
本发明的另一目的在于提供一种TFT基板结构的制作方法，可有效降低金属层和非晶硅层间的能量势垒，使电子注入更加容易，同时在不降低工作电流的前提下降低漏电流，改善TFT的电性。
为实现上述目的，本发明提供一种TFT基板结构，包括基板、设于所述基板上的栅极、设于所述基板上覆盖所述栅极的栅极绝缘层、对应所述 栅极上方设于所述栅极绝缘层上的岛状半导体层、及设于所述栅极绝缘层上分别与所述岛状半导体层的两侧相接触的源极与漏极；
所述岛状半导体层包括从下到上依次叠加的非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层，所述岛状半导体层上设有U型槽，所述U型槽贯穿所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层，将所述N型重掺杂非晶硅层分为位于U型槽两侧的第一、第二N型重掺杂非晶硅层，将所述N型轻掺杂非晶硅层分为位于U型槽两侧的第一、第二N型轻掺杂非晶硅层，在所述非晶硅层上对应于U型槽下方的位置形成沟道；
所述源极与漏极分别与所述第一、第二N型重掺杂非晶硅层的表面相接触。
所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层中掺入的杂质为P元素。
所述N型重掺杂非晶硅层中掺入的P原子的浓度为所述N型轻掺杂非晶硅层中掺入的P原子的浓度的2倍以上。
所述基板为玻璃基板或塑料基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
所述栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合，所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板结构，包括基板、设于所述基板上的栅极、设于所述基板上覆盖所述栅极的栅极绝缘层、对应所述栅极上方设于所述栅极绝缘层上的岛状半导体层、及设于所述栅极绝缘层上分别与所述岛状半导体层的两侧相接触的源极与漏极；
所述岛状半导体层包括从下到上依次叠加的非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层，所述岛状半导体层上设有U型槽，所述U型槽贯穿所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层，将所述N型重掺杂非晶硅层分为位于U型槽两侧的第一、第二N型重掺杂非晶硅层，将所述N型轻掺杂非晶硅层分为位于U型槽两侧的第一、第二N型轻掺杂非晶硅层，在所述非晶硅层上对应于U型槽下方的位置形成沟道；
所述源极与漏极分别与所述第一、第二N型重掺杂非晶硅层的表面相接触；
其中，所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层中掺入的杂质为P元素；
其中，所述N型重掺杂非晶硅层中掺入的P原子的浓度为所述N型轻掺杂非晶硅层中掺入的P原子的浓度的2倍以上；
其中，所述基板为玻璃基板或塑料基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
步骤3、在所述栅极绝缘层上采用化学气相沉积方法依次沉积非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层；
步骤4、采用一道光刻制程对所述非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层进行图案化处理，得到位于所述栅极上方的岛状半导体层，所述岛状半导体层包括对应所述栅极上方的非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层；
步骤5、在所述栅极绝缘层、及岛状半导体层上沉积第二金属层，然后在所述第二金属层上涂布一光阻层，采用一道光罩对所述光阻层进行曝光、显影，在所述光阻层上形成一位于中间位置且贯通前后的条形通道；
步骤6、以所述光阻层为遮挡，对所述第二金属层进行湿蚀刻制程，得到分别对应所述条形通道两侧的源极与漏极；
步骤7、以所述光阻层、及源、漏极为刻蚀阻挡层，对所述岛状半导体层进行干蚀刻制程，在所述岛状半导体层上形成一对应所述条形通道的U型槽，所述U型槽贯穿所述N型轻掺杂非晶硅层、及N型重掺杂非晶硅层，将所述N型重掺杂非晶硅层分为位于U型槽两侧的第一、第二N型重掺杂非晶硅层，将所述N型轻掺杂非晶硅层分为位于U型槽两侧的第一、第二N型轻掺杂非晶硅层，在所述非晶硅层上对应于U型槽下方的位置形成沟道；所述源极与漏极分别与所述第一、第二N型重掺杂非晶硅层的表面相接触；
完成对所述岛状半导体层的干蚀刻制程之后，剥离位于源、漏极上方的光阻层。
所述步骤3中，采用SiH4气体来沉积非晶硅层，采用PH3和SiH4气体来沉积N型轻掺杂非晶硅层与N型重掺杂非晶硅层。
沉积N型轻掺杂非晶硅层42时，PH3和SiH4的气体流量比<0.5；沉积N型重掺杂非晶硅层时，PH3和SiH4的气体流量比>1。
所述基板为玻璃基板或塑料基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
所述栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合，所述源极 与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明的TFT基板结构，在非晶硅层与金属层之间设有N型轻掺杂非晶硅层与N型重掺杂非晶硅层，形成了掺杂的浓度梯度，金属层和非晶硅层间的能量势垒较低，使电子注入更加容易，同时在不降低工作电流的前提下降低了漏电流，改善了TFT的电性。本发明的TFT基板结构的制作方法，通过在非晶硅层与金属层之间形成N型轻掺杂非晶硅层与N型重掺杂非晶硅层，形成掺杂的浓度梯度，有效降低了金属层和非晶硅层间的能量势垒，使电子注入更加容易，同时在不降低工作电流的前提下降低了漏电流，改善了TFT的电性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的TFT基板结构的剖面示意图；
图2为具有图1的TFT基板结构的A-Si器件的漏电流的曲线图；
图3为本发明的TFT基板结构的剖面示意图；
图4为具有图3的TFT基板结构的A-Si器件的漏电流与具有图1的TFT基板结构的A-Si器件的漏电流的曲线对比图；
图5为本发明的TFT基板结构的制作方法的步骤1的示意图；
图6为本发明的TFT基板结构的制作方法的步骤2的示意图；
图7为本发明的TFT基板结构的制作方法的步骤3的示意图；
图8为本发明的TFT基板结构的制作方法的步骤4的示意图；
图9-10为本发明的TFT基板结构的制作方法的步骤5的示意图；
图11为本发明的TFT基板结构的制作方法的步骤6的示意图；
图12为本发明的TFT基板结构的制作方法的步骤7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明首先提供一种TFT基板结构，包括基板10、设于所述基板10上的栅极20、设于所述基板10上覆盖所述栅极20的栅极绝缘层30、对应所述栅极20上方设于所述栅极绝缘层30上的岛状半导体层40、 及设于所述栅极绝缘层30上分别与所述岛状半导体层40的两侧相接触的源极51与漏极52。
所述岛状半导体层40包括从下到上依次叠加的非晶硅层41、N型轻掺杂非晶硅层42、及N型重掺杂非晶硅层43，所述岛状半导体层40上设有U型槽44，所述U型槽44贯穿所述N型轻掺杂非晶硅层43与N型重掺杂非晶硅层42，将所述N型重掺杂非晶硅层43分为位于U型槽44两侧的第一、第二N型重掺杂非晶硅层431、432，将所述N型轻掺杂非晶硅层42分为位于U型槽44两侧的第一、第二N型轻掺杂非晶硅层421、422，在所述非晶硅层41上对应于U型槽44下方的位置形成沟道415；
所述源极51与漏极52分别与所述第一、第二N型重掺杂非晶硅层431、432的表面相接触。
具体的，所述基板10可以是玻璃基板或塑料基板。
具体的，所述栅极20、源极51、及漏极52的材料可以是钼、钛、铝和铜中的一种或多种的堆栈组合。
具体的，所述栅极绝缘层30的材料可以是氧化硅、氮化硅、或二者的组合。
具体的，所述N型轻掺杂非晶硅层42与N型重掺杂非晶硅层43中掺入的杂质为P元素。优选的，所述N型重掺杂非晶硅层43中掺入的P原子的浓度为所述N型轻掺杂非晶硅层42中掺入的P原子的浓度的2倍以上。
图4为具有图3的TFT基板结构的A-Si器件的漏电流与具有图1的TFT基板结构的A-Si器件的漏电流的曲线对比图，其中，虚线代表具有图1的TFT基板结构的A-Si器件的漏电流Ioff随栅电压Vg变化的曲线，实线代表具有图3的TFT基板结构的A-Si器件的漏电流Ioff随栅电压Vg变化的曲线，从图4中可以看出，与具有图1(现有技术)的TFT基板结构的A-Si器件相比，具有图3(本发明)的TFT基板结构的A-Si器件的漏电流Ioff降低，曲线的翘曲变缓，提高了A-Si器件的信赖性。上述TFT基板结构，在非晶硅层与金属层之间设有N型轻掺杂非晶硅层与N型重掺杂非晶硅层，形成了掺杂的浓度梯度，金属层和非晶硅层间的能量势垒较低，使电子注入更加容易，同时在不降低工作电流的前提下降低了漏电流，改善了TFT的电性。
本发明还提供一种上述TFT基板结构的制作方法，包括如下步骤：
步骤1、如图5所示，提供基板10，在所述基板10上沉积第一金属层，并所述第一金属层进行图案化处理，形成栅极20。
具体的，所述基板10可以是玻璃基板或塑料基板。
具体的，所述栅极20的材料可以是钼、钛、铝和铜中的一种或多种的堆栈组合。
步骤2、如图6所示，在所述基板10上沉积栅极绝缘层30，所述栅极绝缘层30覆盖所述栅极20。
具体的，所述栅极绝缘层30的材料可以是氧化硅、氮化硅、或二者的组合。
步骤3、如图7所示，在所述栅极绝缘层30上采用化学气相沉积方法依次沉积非晶硅层41、N型轻掺杂非晶硅层42、及N型重掺杂非晶硅层43。
具体的，采用SiH4气体来沉积非晶硅层41，采用PH3和SiH4气体来沉积N型轻掺杂非晶硅层42与N型重掺杂非晶硅层43。
优选的，沉积N型轻掺杂非晶硅层42时，PH3和SiH4的气体流量比<0.5；沉积N型重掺杂非晶硅层43时，PH3和SiH4的气体流量比>1；因此，所述步骤3得到的N型重掺杂非晶硅层43中掺入的P原子的浓度为所述N型轻掺杂非晶硅层42中掺入的P原子的浓度的2倍以上。
步骤4、如图8所示，采用一道光刻制程对所述非晶硅层41、N型轻掺杂非晶硅层42、及N型重掺杂非晶硅层43进行图案化处理，得到位于所述栅极20上方的岛状半导体层40，所述岛状半导体层40包括对应所述栅极20上方的非晶硅层41、N型轻掺杂非晶硅层42、及N型重掺杂非晶硅层43。
步骤5、如图9-10所示，在所述栅极绝缘层30、及岛状半导体层40上沉积第二金属层50，然后在所述第二金属层50上涂布一光阻层60，采用一道光罩对所述光阻层60进行曝光、显影，在所述光阻层60上形成一位于中间位置且贯通前后的条形通道61。
步骤6、如图11所示，以所述光阻层60为遮挡，对所述第二金属层50进行湿蚀刻制程，得到分别对应所述条形通道61两侧的源极51与漏极52。
具体的，所述源极51与漏极52的材料可以是钼、钛、铝和铜中的一种或多种的堆栈组合。
步骤7、如图12所示，以所述光阻层60与源、漏极51、52为刻蚀阻挡层，对所述岛状半导体层40进行干蚀刻制程，在所述岛状半导体层40上形成一对应所述条形通道61的U型槽44，所述U型槽44贯穿所述N型轻掺杂非晶硅层42、及N型重掺杂非晶硅层43，将所述N型重掺杂非晶硅层43分为位于U型槽44两侧的第一、第二N型重掺杂非晶硅层431、 432，将所述N型轻掺杂非晶硅层42分为位于U型槽44两侧的第一、第二N型轻掺杂非晶硅层421、422，在所述非晶硅层41上对应于U型槽44下方的位置形成沟道415；所述源极51与漏极52分别与所述第一、第二N型重掺杂非晶硅层43、44的表面相接触；
完成对所述岛状半导体层40的干蚀刻制程之后，剥离位于源、漏极51、52上方的光阻层60，得到如图3所示的TFT基板结构。
上述TFT基板结构的制作方法，通过在非晶硅层与金属层之间形成N型轻掺杂非晶硅层与N型重掺杂非晶硅层，形成掺杂的浓度梯度，有效降低了金属层和非晶硅层间的能量势垒，使电子注入更加容易，同时在不降低工作电流的前提下降低了漏电流，改善了TFT的电性。
综上所述，本发明的TFT基板结构，在非晶硅层与金属层之间设有N型轻掺杂非晶硅层与N型重掺杂非晶硅层，形成了掺杂的浓度梯度，金属层和非晶硅层间的能量势垒较低，使电子注入更加容易，同时在不降低工作电流的前提下降低了漏电流，改善了TFT的电性。本发明的TFT基板结构的制作方法，通过在非晶硅层与金属层之间形成N型轻掺杂非晶硅层与N型重掺杂非晶硅层，形成掺杂的浓度梯度，有效降低了金属层和非晶硅层间的能量势垒，使电子注入更加容易，同时在不降低工作电流的前提下降低了漏电流，改善了TFT的电性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (12)

  1. 一种TFT基板结构，包括基板、设于所述基板上的栅极、设于所述基板上覆盖所述栅极的栅极绝缘层、对应所述栅极上方设于所述栅极绝缘层上的岛状半导体层、及设于所述栅极绝缘层上分别与所述岛状半导体层的两侧相接触的源极与漏极；
    所述岛状半导体层包括从下到上依次叠加的非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层，所述岛状半导体层上设有U型槽，所述U型槽贯穿所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层，将所述N型重掺杂非晶硅层分为位于U型槽两侧的第一、第二N型重掺杂非晶硅层，将所述N型轻掺杂非晶硅层分为位于U型槽两侧的第一、第二N型轻掺杂非晶硅层，在所述非晶硅层上对应于U型槽下方的位置形成沟道；
    所述源极与漏极分别与所述第一、第二N型重掺杂非晶硅层的表面相接触。
  2. 如权利要求1所述的TFT基板结构，其中，所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层中掺入的杂质为P元素。
  3. 如权利要求1所述的TFT基板结构，其中，所述N型重掺杂非晶硅层中掺入的P原子的浓度为所述N型轻掺杂非晶硅层中掺入的P原子的浓度的2倍以上。
  4. 如权利要求1所述的TFT基板结构，其中，所述基板为玻璃基板或塑料基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  5. 如权利要求1所述的TFT基板结构，其中，所述栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合，所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  6. 一种TFT基板结构，包括基板、设于所述基板上的栅极、设于所述基板上覆盖所述栅极的栅极绝缘层、对应所述栅极上方设于所述栅极绝缘层上的岛状半导体层、及设于所述栅极绝缘层上分别与所述岛状半导体层的两侧相接触的源极与漏极；
    所述岛状半导体层包括从下到上依次叠加的非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层，所述岛状半导体层上设有U型槽，所述U型槽贯穿所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层，将所述N型重掺杂非晶硅层分为位于U型槽两侧的第一、第二N型重掺杂非晶硅层， 将所述N型轻掺杂非晶硅层分为位于U型槽两侧的第一、第二N型轻掺杂非晶硅层，在所述非晶硅层上对应于U型槽下方的位置形成沟道；
    所述源极与漏极分别与所述第一、第二N型重掺杂非晶硅层的表面相接触；
    其中，所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层中掺入的杂质为P元素；
    其中，所述N型重掺杂非晶硅层中掺入的P原子的浓度为所述N型轻掺杂非晶硅层中掺入的P原子的浓度的2倍以上；
    其中，所述基板为玻璃基板或塑料基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  7. 如权利要求6所述的TFT基板结构，其中，所述栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合，所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  8. 一种TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    步骤2、在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
    步骤3、在所述栅极绝缘层上采用化学气相沉积方法依次沉积非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层；
    步骤4、采用一道光刻制程对所述非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层进行图案化处理，得到位于所述栅极上方的岛状半导体层，所述岛状半导体层包括对应所述栅极上方的非晶硅层、N型轻掺杂非晶硅层、及N型重掺杂非晶硅层；
    步骤5、在所述栅极绝缘层、及岛状半导体层上沉积第二金属层，然后所述第二金属层上涂布一光阻层，采用一道光罩对所述光阻层进行曝光、显影，在所述光阻层上形成一位于中间位置且贯通前后的条形通道；
    步骤6、以所述光阻层为遮挡，对所述第二金属层进行湿蚀刻制程，得到分别对应所述条形通道两侧的源极与漏极；
    步骤7、以所述光阻层、及源、漏极为刻蚀阻挡层，对所述岛状半导体层进行干蚀刻制程，在所述岛状半导体层上形成一对应所述条形通道的U型槽，所述U型槽贯穿所述N型轻掺杂非晶硅层、及N型重掺杂非晶硅层，将所述N型重掺杂非晶硅层分为位于U型槽两侧的第一、第二N型重掺杂非晶硅层，将所述N型轻掺杂非晶硅层分为位于U型槽两侧的第一、第二N型轻掺杂非晶硅层，在所述非晶硅层上对应于U型槽下方的位置形成沟 道；所述源极与漏极分别与所述第一、第二N型重掺杂非晶硅层的表面相接触；
    完成对所述岛状半导体层的干蚀刻制程之后，剥离位于源、漏极上方的光阻层。
  9. 如权利要求8所述的TFT基板结构的制作方法，其中，所述步骤3中，采用SiH4气体来沉积非晶硅层，采用PH3和SiH4气体来沉积N型轻掺杂非晶硅层与N型重掺杂非晶硅层。
  10. 如权利要求9所述的TFT基板结构的制作方法，其中，沉积N型轻掺杂非晶硅层时，PH3和SiH4的气体流量比<0.5；沉积N型重掺杂非晶硅层时，PH3和SiH4的气体流量比>1。
  11. 如权利要求8所述的TFT基板结构的制作方法，其中，所述基板为玻璃基板或塑料基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  12. 如权利要求8所述的TFT基板结构的制作方法，其中，所述栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合，所述源极与漏极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
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