WO2018137548A1 - 一种时钟同步装置及方法 - Google Patents

一种时钟同步装置及方法 Download PDF

Info

Publication number
WO2018137548A1
WO2018137548A1 PCT/CN2018/073241 CN2018073241W WO2018137548A1 WO 2018137548 A1 WO2018137548 A1 WO 2018137548A1 CN 2018073241 W CN2018073241 W CN 2018073241W WO 2018137548 A1 WO2018137548 A1 WO 2018137548A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
compensation value
reference clock
clock signal
processor
Prior art date
Application number
PCT/CN2018/073241
Other languages
English (en)
French (fr)
Inventor
蔡院玲
孟凡顺
吕京飞
徐川
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2018137548A1 publication Critical patent/WO2018137548A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network

Definitions

  • the present invention relates to the field of communications, and in particular, to a clock synchronization apparatus and method.
  • the system clock of the clock synchronization device supports multiple reference clock sources. At any time, the clock synchronization device selects only one of the reference clock sources for clock synchronization.
  • FIG. 1 exemplarily shows the structure of a clock synchronization circuit.
  • the clock synchronization circuit includes a frequency divider 101, a phase detector 102, a filter 103, and a voltage controlled oscillator 104.
  • the clock synchronization circuit supports four reference clock sources.
  • the reference clock signals provided by the four reference clock sources include: a reference clock signal RefClkA provided by the reference clock source A, a reference clock signal RefClkB provided by the reference clock source B, a reference clock signal RefClkC provided by the reference clock source C, and a reference clock source.
  • D provides the reference clock signal RefClkD.
  • the frequency divider 101 divides the reference clock signal RefClkA and outputs it to the phase frequency detector 102.
  • the frequency of the frequency-divided clock signal is 1/X of the frequency of the reference clock signal RefClkA.
  • X is an integer greater than one.
  • the phase frequency detector 102 converts the frequency deviation of the system clock signal SysClk and the clock signal supplied from the frequency divider 101 into a voltage signal, and outputs the voltage signal to the filter 103.
  • the voltage signal is filtered by the filter 103 and used as a control signal of a Voltage Controlled Oscillator (VCO).
  • VCO Voltage Controlled Oscillator
  • the control signal is used to control the frequency of the system clock signal output by the VCO 104.
  • the VCO 104 outputs a system clock signal SysClk according to the input control signal.
  • the system clock signal SysClk is divided by the frequency divider 105 and output to the phase frequency detector 102.
  • the system clock signal generated by the clock synchronization circuit may be abnormal.
  • the embodiment of the present application provides a clock synchronization apparatus and method.
  • an embodiment of the present application provides a clock synchronization apparatus, where the apparatus includes:
  • N phase frequency detectors for determining N frequency deviations, the N phase frequency detectors corresponding to the N frequency deviations, the N phase frequency detectors and N reference clocks
  • the signals are in one-to-one correspondence, wherein the N frequency deviations are frequency deviations between the system clock signal and the N reference clock signals, and the frequency deviation of the system clock signal and each reference clock signal is determined by a corresponding frequency discrimination Determines that N is an integer greater than one;
  • a processor configured to determine a compensation value according to the N frequency deviations determined by the N phase frequency detectors, the compensation value being equal to a weighted average of the N frequency deviations, and the N frequency deviations Each frequency deviation in the corresponding one weight;
  • the processor includes:
  • a weight determining unit configured to determine, according to synchronization performance information of the N reference clock signals, a weight of each of the N frequency offsets determined by the N phase frequency detectors;
  • a compensation value determining unit configured to perform weighted summation on the N frequency deviations according to a weight corresponding to each of the N frequency deviations determined by the weight determining unit, where the compensation value is equal to the weighting The result of the summation.
  • the synchronization performance information of the N reference clock signals includes one or more of the following information:
  • each of the N frequency deviations corresponding to the N reference clock signals is determined by A corresponding reference clock signal is determined from a plurality of phase deviations of the system clock signal.
  • the processor further includes: an abnormality detecting unit, configured to detect whether the N reference clock signals are abnormal, and instruct the processor to only correspond to a normal reference clock signal The frequency deviation determined by the phase frequency detector determines the compensation value.
  • an abnormality detecting unit configured to detect whether the N reference clock signals are abnormal, and instruct the processor to only correspond to a normal reference clock signal The frequency deviation determined by the phase frequency detector determines the compensation value.
  • the processor is further configured to: determine first correspondence relationship information of the frequency deviation and the time according to the frequency compensation value, and save the first correspondence relationship information, and/or determine the frequency deviation and the temperature Corresponding to the second correspondence information, and saving the second correspondence information;
  • the processor is further configured to: when determining that the N reference clock signals are lost, determine a frequency compensation value according to the saved first correspondence relationship information and/or the second correspondence relationship information, and determine the determined value The frequency compensation value is output to the oscillator.
  • the first correspondence corresponds to a first linear polynomial with time as a variable
  • the saved first correspondence information includes coefficients of the first linear polynomial
  • the second correspondence is consistent with temperature as a variable a second linear polynomial, the saved second correspondence information including coefficients of the second linear polynomial;
  • the processor is specifically configured to:
  • an embodiment of the present application provides a clock synchronization method, where the method includes:
  • N frequency discriminators determine N frequency deviations
  • the N phase frequency detectors are in one-to-one correspondence with the N frequency deviations
  • the N phase frequency detectors and the N reference clock signals are one by one
  • the N frequency deviations are frequency deviations between the system clock signal and the N reference clock signals
  • the frequency deviation of the system clock signal and each reference clock signal is determined by a corresponding phase frequency detector.
  • N is an integer greater than one;
  • the compensation value Determining, by the processor, the compensation value according to the N frequency deviations determined by the N phase frequency detectors, the compensation value being equal to a weighted average of the N frequency deviations, each of the N frequency deviations The frequency deviations respectively correspond to one weight;
  • the oscillator generates a new system clock signal based on the compensation value.
  • the determining, by the processor, the compensation value according to the N frequency deviations determined by the N phase frequency detectors including:
  • the processor weights and sums the N frequency offsets according to weights corresponding to each of the N frequency offsets, and the compensation value is equal to a result of the weighted summation.
  • the synchronization performance information of the N reference clock signals includes one or more of the following information:
  • each of the N frequency deviations corresponding to the N reference clock signals is determined by A corresponding reference clock signal is determined from a plurality of phase deviations of the system clock signal.
  • the method further includes: detecting, by the abnormality detecting unit in the processor, whether the N reference clock signals are abnormal, and instructing the processor to determine only according to a phase frequency detector corresponding to a normal reference clock signal.
  • the frequency deviation determines the compensation value.
  • it also includes:
  • the processor determines that the N reference clock signals are lost, determining the frequency compensation value according to the saved first correspondence relationship information and/or the second correspondence relationship information.
  • the first correspondence corresponds to a first linear polynomial with time as a variable
  • the saved first correspondence information includes coefficients of the first linear polynomial
  • the second correspondence is consistent with temperature as a variable a second linear polynomial, the saved second correspondence information including coefficients of the second linear polynomial;
  • Determining, by the processor, the frequency compensation value according to the saved first correspondence relationship information and/or the second correspondence relationship information including:
  • the processor determines, according to the saved coefficient of the first linear polynomial and the time counter value corresponding to the current compensation period, a first frequency compensation value corresponding to the current compensation period, where the time counter value is incremented according to the compensation period; or,
  • the time counter value is incremented according to the compensation period.
  • the embodiment of the present application further provides one or more computer readable media, where the readable medium stores instructions, when the instructions are executed by one or more processors, causing the communication device to perform the second aspect The method provided.
  • the clock synchronization device only tracks one reference clock signal, and generates a new system clock signal according to the frequency deviation of the channel reference clock signal and the system clock signal generated by the clock synchronization device, thereby calibrating the clock of the clock synchronization device. If the reference clock signal is abnormal, the effect on clock synchronization is large.
  • the multiple reference clock signals are tracked to obtain a compensation value. A new system clock signal is obtained based on the compensation value. That is to say, when determining the compensation value, it is based on the multi-reference clock signal. If one of the multiple reference clock signals is abnormal, the reference clock signal that has an abnormality has less influence on the clock synchronization than when the clock synchronization device only tracks one reference clock signal, and the tracked reference clock signal is abnormally The effect of clock synchronization.
  • FIG. 1 is a schematic structural diagram of a clock synchronization circuit in the prior art
  • FIGS. 2a and 2b are respectively schematic structural diagrams of a clock synchronization apparatus 200 in the embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of a processor in a clock synchronization apparatus 200 in an embodiment of the present application;
  • FIG. 4 is a schematic diagram of a principle of a phase frequency detector in a clock synchronization apparatus 200 according to an embodiment of the present application;
  • FIG. 5 is a schematic flowchart of a clock synchronization method according to an embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a clock synchronization method according to another embodiment of the present application.
  • FIG. 2a exemplarily shows the structure of a clock synchronization apparatus 200 provided by an embodiment of the present application.
  • the clock synchronization device 200 may include: N Phase Discriminating Detectors (PFDs), which are identified in the figure as the first phase frequency detectors 201 to N
  • the phase frequency detector 201 (N is an integer greater than 1).
  • the clock synchronization device 200 further includes a processor 202 and an oscillator 203.
  • the first to Nth phase frequency detectors 201 can be a dual D digital phase frequency detector or a time to digital convertor (TDC).
  • the processor 202 can be a CPU, a Complex Programmable Logic Device (CPLD), a Digital Signal Process (DSP), or a Field-Programmable Gate Array (FPGA). ).
  • the oscillator 203 may be a Voltage-Controlled Oscillator (VCO), or a Digitally Controlled Oscillator (DCO), or a Numerical Controlled Oscillator (NCO). It can also be a Direct Digital Synthesizer (DDS).
  • the first through Nth phase frequency detectors 201, the processor 202, and the oscillator 203 are connected by a data bus.
  • the data bus is used to transfer digital information.
  • each of the first phase detectors 201 of the first to Nth phase frequency detectors 201 can determine the frequency deviation of the input two clock signals.
  • the frequency deviation is output to the processor 202.
  • the two clock signals of the input of each phase frequency detector 201 are a reference clock signal and a system clock signal, respectively.
  • the N phase frequency detectors are in one-to-one correspondence with the N frequency deviations, and the N frequency discrimination phase detectors are in one-to-one correspondence with N reference clock signals, wherein the N frequency deviations are system clocks
  • the signal is offset from the frequency of the N reference clock signals.
  • the N phase frequency detectors correspond to the same system clock signal
  • the different phase frequency detectors correspond to different reference clock signals.
  • the frequency deviation of the system clock signal from each reference clock signal is determined by a corresponding phase frequency detector.
  • the corresponding phase frequency detector is a phase frequency detector corresponding to the reference clock signal.
  • the processor 202 determines a compensation value according to a frequency deviation corresponding to each of the phase detectors in the first to Nth phase frequency detectors, and outputs the compensation value to the oscillator 203.
  • Oscillator 203 generates a new system clock signal based on the compensation value determined by processor 202.
  • the reference clock signal may be sent by a master clock device.
  • the master clock device can be the master clock defined by IEEE 1588-2008.
  • the master clock device can transmit a reference clock signal to the clock synchronization device via Ethernet.
  • the clock synchronization device may be a slave clock defined by IEEE 1588-2008.
  • the reference clock signal can be a continuous pulse signal.
  • the data bus can be interfaced to an Ethernet standard.
  • the Ethernet-compliant interface can be a Fast Ethernet (FE) interface or a Gigabit Ethernet (GE) interface.
  • the frequency offset and the compensation value can be carried in an Ethernet frame.
  • Ethernet frames can be transmitted via the data bus.
  • the data bus can also use a bus that conforms to other interface standards, such as a Localbus bus, an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, or an advanced data link. High-Level Data Link Control (HDLC) bus.
  • I2C Inter-Integrated Circuit
  • SPI Serial Peripheral Interface
  • HDLC High-Level Data Link Control
  • the clock synchronization device 200 can be a clock board in a network device that can be placed on the backplane of the network device.
  • the network device can be a router or a switch.
  • the clock board can receive reference clock signals provided by other boards of the network device.
  • the board that provides the reference clock signal can carry its own Media Access Control (MAC) address as the source MAC address to the Ethernet frame and send it to the clock board to distinguish the board from which the reference clock signal originates.
  • the system clock signal generated by the clock board can also be sent to other boards.
  • the clock board can carry the MAC address of the board for receiving the system clock signal as the destination MAC address to the Ethernet frame and send the card to the board for receiving the system clock signal.
  • MAC Media Access Control
  • the frequency deviation of the system clock signal from all or a portion of the N reference clock signals may be stored in a module that is accessible by the processor 203 to cause the processor 203 Get the frequency deviation stored in this module.
  • the N phase frequency detectors are in one-to-one correspondence with the N reference clock signals.
  • the frequency deviation of the reference clock signal For example, the first phase frequency detector 201 receives the first reference clock signal RefClk1 and the system clock signal SysClk, and outputs a first frequency difference offset PD_Err1 between the system clock signal SysClk and the first reference clock signal RefClk1.
  • the second phase frequency detector 201 receives the second reference clock signal RefClk2 and the system clock signal SysClk, and outputs a second frequency difference PD_Err2 between the system clock signal SysClk and the second reference clock signal RefClk2. And so on.
  • the processor 202 may determine the compensation value ⁇ f according to the N frequency deviations output by the first to Nth phase frequency detectors 201, and output the compensation value ⁇ f to the oscillator 203.
  • the compensation value is equal to a weighted average of the N frequency deviations, and each of the N frequency deviations corresponds to a weight.
  • the weighted average may be determined as follows: First, the N frequency deviations are multiplied by corresponding weights, and then the multiplied result values are added. Optionally, for the frequency deviations participating in the weighted summation operation, the sum of the respective weights is equal to one.
  • Oscillator 203 can generate a new system clock signal based on the compensation value determined by processor 202.
  • the oscillator 203 can generate a new system clock signal SysClk based on the local clock signal LocClk and the compensation value ⁇ f output by the processor 202, and output the system clock signal SysClk.
  • the local clock signal LocClk is a continuous pulse signal generated by a crystal oscillator.
  • the continuous pulse signal can be a continuous square wave.
  • the local clock signal LocClk may be an input signal from outside the clock synchronization device 200 (as shown in Figure 2a).
  • a crystal oscillator 205 can be included in the clock synchronization device 200 for generating a local clock signal LocClk and providing it to the oscillator 203 (as shown in Figure 2b).
  • the processor 202 in the clock synchronization apparatus 200 can include a weight determination unit 2022, a compensation value determination unit 2023, and optionally, an anomaly detection unit 2021.
  • the abnormality detecting unit 2021, the weight determining unit 2022, and the compensation value determining unit 2023 may be implemented by software (i.e., these modules are logical functional modules in the processor 202).
  • the abnormality detecting unit 2021 is configured to detect whether the N reference clock signals are abnormal, and instruct the processor 202 to use only the phase frequency detector corresponding to the normal reference clock signal.
  • the determined frequency deviation determines the compensation value.
  • the normal reference clock signal refers to the reference clock signal that the abnormality detecting unit 2021 detects as normal
  • the abnormal reference clock signal refers to the reference clock signal that the abnormality detecting unit 2021 detects as abnormal. Detecting whether the reference clock signal is abnormal may include one or more of the following: detecting whether the frequency offset range of the reference clock signal is normal, whether the noise is excessive, and whether the frequency change trend is consistent with the frequency change trend of other reference clock signals.
  • the frequency deviation determined by the Nth phase frequency detector 201 is prevented from being supplied to the processor 202.
  • the frequency offset range of the Nth reference clock signal is significantly beyond the spectrum range of other reference clock signals or exceeds the preset. The frequency offset range avoids providing the processor 202 with the frequency offset determined by the Nth phase frequency detector 201.
  • the frequency discriminator 201 determines the frequency deviation.
  • the weight determining unit 2022 may determine the weight of the corresponding frequency offset only for the reference clock signal in which the abnormality detecting unit 2021 does not detect the occurrence of the abnormality, and instruct the processor 202 to determine only according to the phase frequency detector corresponding to the normal reference clock signal.
  • the frequency deviation determines the compensation value. That is, for the reference clock signal detected to be abnormal, it is determined that the weight of the corresponding frequency deviation is equal to zero.
  • the compensation value determining unit 2023 may perform weighted summation on the frequency deviation corresponding to the reference clock signal detected by the abnormality detecting unit 2021 according to the weight determined by the weight determining unit 2022 to obtain a compensation value.
  • the weight determining unit 2022 determines the weight of each frequency deviation for the N frequency deviations determined by the first to Nth phase frequency detectors 201.
  • the compensation value determining unit 2023 performs weighting and summing the frequency deviations determined by the first to Nth phase frequency detectors 201 according to the weight corresponding to each of the N frequency deviations determined by the weight determining unit 2022, Get the compensation value.
  • the weight determining unit 2022 can determine the weight of the frequency offset corresponding to the reference clock signal based on the synchronization performance information of the reference clock signal.
  • the synchronization performance information of the reference clock signal may include one or more of the following information:
  • the quality information of the reference clock signal can be configured in advance based on the clock accuracy.
  • the quality level of the reference clock source can be configured, the quality level of one reference clock source being the same as the quality level of the reference clock signal from the reference clock source.
  • These configuration information can be stored in the memory.
  • the processor 202 can obtain quality information of the reference clock signal from the memory.
  • the quality information of the reference clock signal may also be carried in the output data of the corresponding phase frequency detector.
  • the quality information of the reference clock signal may be carried in the message, and the message is transmitted by means of the data channel of the phase frequency detector 201. Sent to processor 202.
  • the processor 202 can perform weight allocation according to quality information of the reference clock signal.
  • the weight corresponding to the frequency deviation between the reference clock signal and the synchronized clock signal is relatively large. Conversely, if the quality of the reference clock signal is low, the reference clock signal is The weight corresponding to the frequency deviation between the synchronized clock signals is small.
  • the priority of the reference clock signal can be configured in advance.
  • the priority of the reference clock source can be configured, and the priority of one reference clock source is the same as the priority of the reference clock signal from the reference clock source.
  • These configuration information can be stored in the memory.
  • the processor 202 can obtain priority information of the reference clock signal from the memory.
  • the priority information of the reference clock signal can also be carried in the message, which message is sent to the processor 202 by means of the data channel of the phase frequency detector 201.
  • the processor 202 can perform weight allocation according to the priority of the reference clock signal. As an example, if the priority is higher, the weight corresponding to the frequency deviation between the reference clock signal and the synchronized clock signal is larger. Otherwise, the reference clock signal has a lower priority and the reference clock signal is synchronized. The frequency deviation between the clock signals corresponds to a smaller weight.
  • the processor 202 may extract noise information therein for the frequency deviation of the phase frequency detector output, and perform weight distribution according to the extracted noise information. As an example, if the noise extracted from the frequency deviation is small, the weight corresponding to the frequency deviation is large, and conversely, if the noise extracted from the frequency deviation is large, the weight corresponding to the frequency deviation is small.
  • Each of the N frequency offsets corresponding to the N reference clock signals may be determined by a plurality of phase deviations of the corresponding system clock signal and the reference clock signal, for example, a frequency offset PD_Err1 corresponding to the first reference clock signal.
  • the phase deviation of the system clock signal SysClk from the first reference clock signal RefClk1 at time t0 and time t1 can be determined.
  • the controller 202 may determine the weight of the corresponding reference clock signal for the phase deviation corresponding to each of the N frequency offsets determined by the first to Nth phase frequency detectors. As an example, for a frequency deviation, if the corresponding phase deviation is small, the weight corresponding to the frequency deviation is relatively large. Conversely, if the corresponding phase deviation is large, the weight corresponding to the frequency deviation is greater. small.
  • a filtering module may also be included in the clock synchronization device 200.
  • the filtering module can be implemented by one or a set of digital filters.
  • the filtering module is mainly used for filtering the frequency deviation outputted by the first to Nth phase frequency detectors 201 to filter out noise information in the frequency deviation to ensure the accuracy of clock synchronization.
  • the processor 202 may further determine the correspondence relationship between the frequency deviation and the time, and/or the correspondence relationship between the frequency deviation and the temperature, according to the determined frequency compensation value, and further combining information such as temperature and time.
  • “correspondence information of frequency deviation and time” is referred to as first correspondence relationship information
  • “correspondence information of frequency deviation and temperature” is referred to as second correspondence relationship information.
  • the first correspondence information may be represented by a linear polynomial with time as a variable (for convenience of description, the polynomial is called a first polynomial).
  • the processor 202 can obtain the coefficient of the polynomial according to the frequency compensation value determined at a plurality of time points within the set duration. For example, the frequency deviation can be sampled at a fixed time interval (per second or every ms or other time interval) and saved to memory, and then learned by polynomial according to the frequency deviation of each time point stored within a certain length of time (such as one day). Get the following polynomial:
  • t is a polynomial variable representing time
  • f(t) is the frequency deviation
  • a, b, c, and d are the coefficients of the polynomial, respectively.
  • the processor 202 may save the coefficients of the first polynomial in the memory, and may further save the frequency deviation sampled at a fixed time interval and the time counter value (for example, +1 per second) of the sampling time point.
  • the second correspondence information may be represented by a linear polynomial with temperature as a variable (for convenience of description, the polynomial is called a second polynomial).
  • the processor 202 can obtain the coefficient of the polynomial according to the frequency compensation value determined at a plurality of time points within the set duration. For example, the frequency deviation can be sampled at a fixed time interval (per second or every ms or other time interval), and the sampled frequency deviation and the temperature of the corresponding sampling time point can be saved to the memory and then according to a certain length of time (such as one day).
  • the frequency deviation and temperature at each time point stored in it are obtained by polynomial learning to obtain the following polynomial:
  • the oscillator may be the oscillator 203; f(T) represents the frequency deviation; a', b', c', d' are the coefficients of the polynomial, respectively.
  • the processor 202 may save the coefficients of the second polynomial in the memory, and may further store the frequency deviations sampled at the fixed time interval and the temperature of the sampling time point.
  • the frequency compensation value may be determined according to the first correspondence relationship information and/or the second correspondence relationship information stored in the memory 204, and the determined The frequency compensation value is output to the oscillator 203 to cause the oscillator 203 to generate a new system clock signal based on the frequency compensation value.
  • the processor 202 may determine the frequency compensation value corresponding to the current compensation period according to the saved coefficient of the first linear polynomial and the time counter value corresponding to the current compensation period.
  • the time counter value is incremented according to the compensation period.
  • the length of the compensation period is 1 ms.
  • the processor 202 determines that the N reference clock signals are lost, then the compensation value is determined to be determined by the compensation period.
  • the time counter value takes a value of 1.
  • the time counter value takes a value of 2, and so on, and the time counter value is incremented by an increment value equal to 1 according to the compensation period.
  • the nth supplemental period (n is an integer greater than or equal to 1)
  • the time counter value is equal to n, according to the coefficient of the first linear polynomial and the time counter value n
  • the frequency compensation value of the compensation period can be calculated:
  • the processor 202 may determine a frequency compensation value corresponding to the current temperature according to the saved coefficient of the second linear polynomial and the current temperature. As an example, based on the coefficients of the second linear polynomial and the current temperature m, the frequency compensation value corresponding to the temperature can be calculated:
  • the processor 202 may determine, according to the saved coefficient of the first linear polynomial and the time counter value corresponding to the current compensation period, the first frequency compensation value corresponding to the current compensation period, according to the saved second linear polynomial And a current temperature, determining a second frequency compensation value corresponding to the current temperature, and determining a frequency compensation value for outputting to the oscillator according to the first frequency compensation value and the second frequency compensation value.
  • the sum of the first frequency compensation value and the second frequency compensation value may be used as a frequency compensation value for output to the oscillator 203.
  • Fig. 4 exemplarily shows a circuit principle structure of a phase frequency detector implemented by a PFD.
  • the first phase frequency detector 201 includes two input signals for detecting (the first reference clock signal RefClk1 and The phase-frequency phase detector of the rising edge phase deviation of the system clock signal SysClk) and the phase frequency detector 2012 for detecting the phase deviation of the falling edge of the two input signals, the adder 2013 is based on the phase frequency detector 2011 and The output of the phase detector 2012 obtains the frequency deviation PD_Err1 of the two input signals (RefClk1 and SysClk).
  • the clock synchronization device 200 can operate in a tracking operation mode, a hold operation mode, or a free oscillation operation mode depending on the specific situation.
  • the clock synchronization flow of the clock synchronization apparatus will be described below with reference to FIG.
  • step S503 the clock synchronization device operates in the tracking operation mode; if the processor 202 in the clock synchronization device 200 determines that none of the first to Nth phase frequency detectors 201 outputs a valid frequency deviation, then proceeds to S505, and the clock is synchronized.
  • the device works in the keep working mode.
  • the processor 202 can determine the first to the Nth.
  • the reference signal is lost, so it enters the keep-alive mode.
  • the processor 202 determines all the phase frequency detectors. If the frequency deviation of the output is abnormal, it can be judged that the first to Nth reference signals are lost, and thus enter the hold mode.
  • the processor 202 weights and sums the frequency deviation outputted by the phase frequency detector to obtain a compensation value ⁇ f, and outputs the compensation value ⁇ f to the oscillator 203.
  • the oscillator 203 generates a new system clock signal based on the compensation value ⁇ f and outputs the generated system clock signal.
  • the processor 202 determines first correspondence information of frequency deviation and time according to the compensation value ⁇ f, and/or second correspondence relationship information of frequency deviation and temperature, and the first correspondence information and/or the first correspondence information
  • the second correspondence information is stored in the memory 204.
  • the processor 202 acquires the first correspondence relationship information and/or the second correspondence relationship information stored in the memory 204, according to the obtained first correspondence.
  • the relationship information and/or the second correspondence information may be further combined with key information such as compensation period and/or temperature to determine the frequency compensation value and output to the oscillator 203.
  • the oscillator 203 generates a new system clock signal based on the input frequency compensation value and outputs the generated system clock signal. Oscillator 203 can generate a system clock signal that is substantially immune to temperature variations and aging. If the processor 202 cannot obtain the first correspondence relationship information and/or the second correspondence relationship information from the memory 204, the process proceeds to S507 to enter a free-running operation mode.
  • the oscillator 203 in the free-running operation mode, can generate a system clock signal based on the local clock signal and output the generated system clock signal.
  • the clock synchronization device in the tracking mode, does not only track one reference clock signal, but tracks multiple reference clock signals, and frequency deviation between the system clock signal and the multiple reference clock signals. A weighted summation is performed to obtain a compensation value.
  • the selected reference clock signal if the selected reference clock signal is abnormal, the error generated by the abnormality will all be introduced into the clock synchronization process.
  • the multi-way reference clock signal is used as the basis for determining the compensation value, if some of the reference clock signals are abnormal, the error caused by the abnormality is only partially introduced. The clock synchronization process reduces the impact on clock synchronization.
  • the traffic clock is carried in the service clock signal, and the signal is abnormal due to the abnormality of the service processing, thereby affecting the clock synchronization accuracy.
  • the coupling between the service clock and the system clock isolates the interference of the service clock to the system clock.
  • the clock synchronization device determines the first correspondence relationship information of the frequency deviation and the time and/or the second correspondence relationship information of the frequency deviation and the temperature
  • the system clock signal and the multiple reference clock are used.
  • the compensation value is more accurate, which improves the performance of clock synchronization.
  • FIG. 6 is a schematic diagram of different clock processes according to another embodiment of the present application, where the process may include:
  • N frequency discriminators determine N frequency offsets, the N phase frequency detectors are in one-to-one correspondence with the N frequency offsets, the N phase frequency detectors and N reference clock signals One-to-one correspondence, wherein the N frequency deviations are frequency deviations between the system clock signal and the N reference clock signals, and the frequency deviation of the system clock signal and each reference clock signal is determined by a corresponding phase frequency detector Determine that N is an integer greater than one;
  • the processor determines, according to the N frequency deviations, a compensation value, where the compensation value is equal to a weighted average value of the N frequency deviations, and each of the N frequency deviations respectively corresponds to one weight;
  • S603 The oscillator generates a new system clock signal according to the compensation value.
  • the above process may be performed by the clock synchronization apparatus shown in FIG. 2a or 2b, wherein S601 may be performed by N phase frequency detectors in the clock synchronization apparatus, S602 may be executed by a processor in the clock synchronization apparatus, and S603 may be performed.
  • the oscillator in the above clock synchronization device is executed.
  • the embodiment of the invention further provides a computer readable storage medium for storing computer software instructions required to execute the above-mentioned processor, which comprises a program for executing the above-mentioned processor.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

本申请公开了一种时钟同步装置及方法。该时钟同步装置包括：N个鉴频鉴相器，用于确定N个频率偏差，所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差，所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定；处理器，用于根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重；振荡器，用于根据所述处理器确定的补偿值生成新的系统时钟信号。

Description

一种时钟同步装置及方法 技术领域
本发明涉及通信领域，尤其涉及一种时钟同步装置及方法。
背景技术
时钟同步设备的系统时钟支持多路参考时钟源，在任一时刻，时钟同步设备只选择其中一路参考时钟源的时钟信号进行时钟同步。
图1示例性地示出了时钟同步电路的结构。参见图1，时钟同步电路包括分频器101、鉴相器102、滤波器103以及压控振荡器104。该时钟同步电路支持4路参考时钟源。这4路参考时钟源提供的参考时钟信号分别包括：参考时钟源A提供的参考时钟信号RefClkA、参考时钟源B提供的参考时钟信号RefClkB、参考时钟源C提供的参考时钟信号RefClkC和参考时钟源D提供的参考时钟信号RefClkD。以RefClkA被时钟同步电路确定为用于进行时钟同步的参考时钟信号为例进行说明。分频器101将参考时钟信号RefClkA分频处理后输出给鉴频鉴相器102。分频处理后的时钟信号的频率是参考时钟信号RefClkA的频率的1/X。X为大于1的整数。鉴频鉴相器102将系统时钟信号SysClk与分频器101提供的时钟信号的频率偏差转换为电压信号，并将电压信号输出给滤波器103。该电压信号经过滤波器103滤波后作为压控振荡器(Voltage Controlled Oscillator，简称VCO)的控制信号。该控制信号用于对VCO 104输出的系统时钟信号的频率进行控制。具体来说，VCO 104根据输入的控制信号输出系统时钟信号SysClk。系统时钟信号SysClk经分频器105分频后输出给鉴频鉴相器102。
上述技术方案中，若时钟同步电路的参考时钟源的信号发生异常(比如低频扰动)，可能导致时钟同步电路生成的系统时钟信号发生异常。
发明内容
本申请实施例提供了一种时钟同步装置及方法。
第一方面，本申请实施例提供了一种时钟同步装置，该装置包括：
N个鉴频鉴相器，用于确定N个频率偏差，所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差，所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定，N为大于1的整数；
处理器，用于根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重；
振荡器，用于根据所述处理器确定的补偿值生成新的系统时钟信号。
可选地，所述处理器包括：
权重确定单元，用于根据所述N个参考时钟信号的同步性能信息，确定所述N个鉴频鉴相器确定的所述N个频率偏差中每个频率偏差的权重；
补偿值确定单元，用于根据所述权重确定单元确定的所述N个频率偏差中每个频率偏差对应的权重，对所述N个频率偏差进行加权求和，所述补偿值等于所述加权求和的结果。
可选地，所述N个参考时钟信号的同步性能信息包括以下信息中的一种或多种：
所述N个参考时钟信号中每个参考时钟信号的质量信息；
所述N个参考时钟信号中每个参考时钟信号的优先级信息；
所述N个鉴频鉴相器确定的N个频率偏差中每个频率偏差的噪声信息；
所述N个鉴频鉴相器确定的N个频率偏差中的每个频率偏差所对应的相位偏差，其中，所述N个参考时钟信号对应的N个频率偏差中的每个频率偏差，由对应的参考时钟信号与所述系统时钟信号的多个相位偏差确定。
可选地，所述处理器还包括：异常检测单元；所述异常检测单元，用于检测所述N个参考时钟信号是否异常，并指示所述处理器仅根据正常的参考时钟信号所对应的鉴频鉴相器确定的频率偏差确定补偿值。
可选地，所述处理器还用于：根据所述频率补偿值确定频率偏差与时间的第一对应关系信息，并保存所述第一对应关系信息，和/或，确定频率偏差与温度的第二对应关系信息，并保存所述第二对应关系信息；
所述处理器还用于：确定所述N个参考时钟信号丢失时，根据保存的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值，并将确定出的频率补偿值输出给所述振荡器。
可选地，所述第一对应关系符合以时间作为变量的第一线性多项式，所保存的第一对应关系信息包括所述第一线性多项式的系数；所述第二对应关系符合以温度作为变量的第二线性多项式，所保存的第二对应关系信息包括所述第二线性多项式的系数；
所述处理器具体用于：
根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，其中，时间计数器值根据补偿周期递增；或者，
根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值；或者，
根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值，并根据所述第一频率补偿值和所述第二频率补偿值确定用于输出给所述振荡器的频率补偿值；其中，时间计数器值根据补偿周期递增。
第二方面，本申请实施例提供了一种时钟同步方法，该方法包括：
N个鉴频鉴相器确定N个频率偏差，所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差，所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定，N为大于1的整数；
处理器根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重；
振荡器根据所述补偿值生成新的系统时钟信号。
可选地，所述处理器根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，包括：
所述处理器根据所述N个参考时钟信号的同步性能信息，确定所述N个频率偏差中每个频率偏差的权重；
所述处理器根据所述N个频率偏差中每个频率偏差对应的权重，对所述N个频率偏差进行加权求和，所述补偿值等于所述加权求和的结果。
可选地，所述N个参考时钟信号的同步性能信息包括以下信息中的一种或多种：
所述N个参考时钟信号中每个参考时钟信号的质量信息；
所述N个参考时钟信号中每个参考时钟信号的优先级信息；
所述N个鉴频鉴相器确定的N个频率偏差中每个频率偏差的噪声信息；
所述N个鉴频鉴相器确定的N个频率偏差中的每个频率偏差所对应的相位偏差，其中，所述N个参考时钟信号对应的N个频率偏差中的每个频率偏差，由对应的参考时钟信号与所述系统时钟信号的多个相位偏差确定。
可选地，还包括：所述处理器中的异常检测单元检测所述N个参考时钟信号是否异常，并指示所述处理器仅根据正常的参考时钟信号所对应的鉴频鉴相器确定的频率偏差确定补偿值。
可选地，还包括：
所述处理器根据所述频率补偿值确定频率偏差与时间的第一对应关系信息，并保存所述第一对应关系信息，和/或，确定频率偏差与温度的第二对应关系信息，并保存所述第二对应关系信息；
所述处理器确定所述N个参考时钟信号丢失时，根据保存的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值。
可选地，所述第一对应关系符合以时间作为变量的第一线性多项式，所保存的第一对应关系信息包括所述第一线性多项式的系数；所述第二对应关系符合以温度作为变量的第二线性多项式，所保存的第二对应关系信息包括所述第二线性多项式的系数；
所述处理器根据保存的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值，包括：
所述处理器根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，其中，时间计数器值根据补偿周期递增；或者，
所述处理器根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值；或者，
所述处理器根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值，并根据所述第一频率补偿值和所述第二频率补偿值确定用于输出给所述振荡器的频率补偿值；其中，时间计数器值根据补偿周期递增。
第三方面，本申请实施例还提供了一个或多个计算机可读介质，所述可读介质上存储有指令，所述指令被一个或多个处理器执行时，使得通信装置执行第二方面所提供的方法。
现有技术中，时钟同步装置仅跟踪一路参考时钟信号，并根据该路参考时钟信号与时钟同步装置生成的系统时钟信号的频率偏差生成新的系统时钟信号，从而校准时钟同步装置的时钟。如果该路参考时钟信号异常，对时钟同步的影响很大。本申请实施例提供的技术方案中，跟踪多路参考时钟信号，从而得到补偿值。根据补偿值得到新的系统时钟信号。也就是说，在确定补偿值时，以多路参考时钟信号为依据。若这多路参考时钟信号中有一个参考时钟信号异常，则发生异常的一个参考时钟信号对时钟同步的影响小于当时钟同步装置仅跟踪一个参考时钟信号时，被跟踪的参考时钟信号发生异常对时钟同步的影响。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的时钟同步电路结构示意图；
图2a、图2b分别为本申请实施例中的时钟同步装置200的结构示意图；
图3为本申请实施例中的时钟同步装置200中的处理器的结构示意图；
图4为本申请实施例中时钟同步装置200中的鉴频鉴相器的原理示意图；
图5为本申请实施例提供的时钟同步方法流程示意图；
图6为本申请另一实施例提供的时钟同步方法流程示意图。
具体实施方式
下面结合附图对本申请实施例进行详细描述。
图2a示例性地示出了本申请实施例提供的时钟同步装置200的结构。时钟同步装置200中可包括：N个鉴频鉴相器(Phase and Frequence Detector，简称PFD)，该N个鉴频鉴相器201在图中标识为第一鉴频鉴相器201至第N鉴频鉴相器201(N为大于1的整数)。该时钟同步装置200中还包括处理器202、振荡器203。
在一些实施例中，第一至第N鉴频鉴相器201可以是双D数字鉴频鉴相器或时间数字转换器(Time to Digital Convertor，简称TDC)。处理器202可以是CPU、复杂可编程逻辑器件(Complex Programmable Logic Device，简称CPLD)、数字信号处理器(Digital Signal Process，简称DSP)或是现场可编程门阵列(Field－Programmable Gate Array，简称FPGA)。振荡器203可以是压控振荡器(Voltage-Controlled Oscillator，简称VCO)，或者是数字控制振荡器(Digitally Controlled Oscillator，简称DCO)，或者是数字控制振荡器(Numerical-Controlled Oscillator，简称NCO)，还可以是直接数字式频率合成器(Direct digital synthesizer，简称DDS)。
在一些实施例中，第一至第N鉴频鉴相器201、处理器202以及振荡器203之间通过数据总线连接。数据总线用于传输数字信息。比如，第一至第N鉴频鉴相器201中的每个鉴 频鉴相器201都可以确定出输入的两路时钟信号的频率偏差。并将频率偏差输出给处理器202。每个鉴频鉴相器201的输入的两路时钟信号分别是参考时钟信号以及系统时钟信号。所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差。具体来说，所述N个鉴频鉴相器对应同一个系统时钟信号，不同的鉴频鉴相器对应不同的参考时钟信号。所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定。所述对应的鉴频鉴相器是指与参考时钟信号对应的鉴频鉴相器。处理器202根据第一至第N鉴频鉴相器中的每个鉴频鉴相器对应的频率偏差确定出补偿值并将补偿值输出给振荡器203。振荡器203根据处理器202确定的补偿值生成新的系统时钟信号。
所述参考时钟信号可以是主时钟设备发送的。例如，主时钟设备可以是IEEE1588-2008定义的主时钟。主时钟设备可以通过以太网向时钟同步装置发送参考时钟信号。时钟同步装置可以是IEEE1588-2008定义的从时钟。参考时钟信号可以是连续的脉冲信号。
数据总线可以采用符合以太网标准的接口。符合以太网标准的接口可以是快速以太网(Fast Ethernet，简称FE)接口或千兆以太网(Gigabit Ethernet，简称GE)接口。频率偏差以及补偿值可以携带在以太网帧中。以太网帧可以经由数据总线传输。当然，数据总线也可以采用符合其他接口标准的总线，比如Localbus总线、集成电路(Inter-Integrated Circuit，简称I2C)总线、串行外设接口(Serial Peripheral Interface，简称SPI)总线或者高级数据链路控制(High-Level Data Link Control，简称HDLC)总线。
在一些实施例中，时钟同步装置200可以是网络设备中的时钟板，该时钟板可设置在所述网络设备的背板上。所述网络设备可以是路由器或交换机。时钟板可以接收所述网络设备的其他板卡提供的参考时钟信号。提供参考时钟信号的板卡可将自身的媒体接入控制(Media Access Control，简称MAC)地址作为源MAC地址携带于以太网帧发送给时钟板，以区分参考时钟信号所来源于的板卡。时钟板所生成的系统时钟信号也可发送至其他的板卡。时钟板可将用于接收系统时钟信号的板卡的MAC地址作为目的MAC地址携带于以太网帧发送给所述用于接收系统时钟信号的板卡。
在另外一些实施例中，可以将系统时钟信号与所述N路参考时钟信号中的所有或部分参考时钟信号的频率偏差存在一个模块中，该模块可被处理器203访问，以使处理器203获取该模块中存储的频率偏差。
所述N个鉴频鉴相器与N个参考时钟信号一一对应。第一至第N鉴频鉴相器201中，第n(1<＝n<＝N)鉴频鉴相器用于接收第n路参考时钟信号与系统时钟信号，输出系统时钟信号与第n路参考时钟信号的频率偏差。例如，第一鉴频鉴相器201接收第一参考时钟信号RefClk1和系统时钟信号SysClk，输出系统时钟信号SysClk与第一参考时钟信号RefClk1之间的第一频率差偏PD_Err1。再例如，第二鉴频鉴相器201接收第二参考时钟信号RefClk2和系统时钟信号SysClk，输出系统时钟信号SysClk与第二参考时钟信号RefClk2之间的第二频率差偏PD_Err2。以此类推。
处理器202可根据第一至第N鉴频鉴相器201输出的N个频率偏差确定补偿值Δf，并输出补偿值Δf到振荡器203。所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重。所述加权平均值可以按照如下方式确定： 先将所述N个频率偏差与对应的权重相乘，再对各相乘结果值进行相加。可选地，对于参与加权求和运算的频率偏差，各自对应的权值之和等于1。
振荡器203可根据处理器202确定的补偿值生成新的系统时钟信号。在一些实施例中，振荡器203可根据本地时钟信号LocClk以及处理器202输出的补偿值Δf，生成新的系统时钟信号SysClk，并输出该系统时钟信号SysClk。所述本地时钟信号LocClk是晶振生成的连续的脉冲信号。所述连续的脉冲信号可以是连续的方波。
可选地，本地时钟信号LocClk可以是来自于时钟同步装置200外部的输入信号(如图2a所示)。在另外的例子中，时钟同步装置200中可包括晶振205，用于生成本地时钟信号LocClk并提供给振荡器203(如图2b所示)。
在一些实施例中，如图3所示，时钟同步装置200中的处理器202可包括权重确定单元2022、补偿值确定单元2023，可选地，还可包括异常检测单元2021。异常检测单元2021、权重确定单元2022和补偿值确定单元2023，可以由软件实现(即这些模块是处理器202中的逻辑功能模块)。
以处理器202中包含异常检测单元2021为例，异常检测单元2021用于检测所述N个参考时钟信号是否异常，并指示处理器202仅根据正常的参考时钟信号所对应的鉴频鉴相器确定的频率偏差确定补偿值。其中，正常的参考时钟信号是指异常检测单元2021检测为正常的参考时钟信号，异常的参考时钟信号是指异常检测单元2021检测为异常的参考时钟信号。检测参考时钟信号是否异常可包括以下中的一种或多种：检测参考时钟信号的频偏范围是否正常、噪声是否超标、频率变化趋势与其它参考时钟信号的频率变化趋势是否一致。作为一个例子，若在设定的时间段内，第一至第N-1参考时钟信号的频率变化趋势相同(比如频率提高)，而第N参考时钟信号的变化趋势与之不同(比如频率降低)，则避免向处理器202提供第N鉴频鉴相器201确定出的频率偏差。作为另一个例子，若在设定时间段内，第一至第N参考时钟信号的频率变化趋势相同，但第N参考时钟信号的频偏范围明显超出其它参考时钟信号的频谱范围或者超出预设的频偏范围，则避免向处理器202提供第N鉴频鉴相器201确定出的频率偏差。作为另一个例子，若第一至第N-1参考时钟信号中的噪声低于设定阈值，而第N参考时钟信号中的噪声显著高于设定阈值，则避免向处理器202提供第N鉴频鉴相器201确定出的频率偏差。
权重确定单元2022可仅为异常检测单元2021没有检测到发生异常的参考时钟信号确定所对应的频率偏差的权重，并指示处理器202仅根据正常的参考时钟信号所对应的鉴频鉴相器确定的频率偏差确定补偿值。也就是说，针对被检测为发生异常的参考时钟信号，确定所对应的频率偏差的权重等于0。以上使得处理器202确定补偿值时，不考虑发生异常的时钟参考信号所对应的频率偏差。补偿值确定单元2023可根据权重确定单元2022确定的权重，对异常检测单元2021检测为正常的参考时钟信号所对应的频率偏差进行加权求和，得到补偿值。
作为另一个例子，若时钟同步装置200中不包括异常检测单元2021，则权重确定单元2022为第一至第N鉴频鉴相器201确定的所述N个频率偏差确定每个频率偏差的权重；补偿值确定单元2023根据权重确定单元2022确定的所述N个频率偏差中每个频率偏差对应的权重，对第一至第N鉴频鉴相器201确定出的频率偏差进行加权求和，得到补偿值。
在一些实施例中，权重确定单元2022可根据参考时钟信号的同步性能信息确定参考时 钟信号所对应的频率偏差的权重。可选地，所述参考时钟信号的同步性能信息可包括以下信息中的一种或多种：
-参考时钟信号的质量信息
可预先根据时钟精度对参考时钟信号的质量信息进行配置。可选地，可对参考时钟源的质量等级进行配置，一个参考时钟源的质量等级与来自于该参考时钟源的参考时钟信号的质量等级相同。这些配置信息可存储于存储器中。处理器202可从存储器获取参考时钟信号的质量信息。参考时钟信号的质量信息也可携带在相应鉴频鉴相器的输出数据中，比如，参考时钟信号的质量信息可携带在报文中，该报文借助于鉴频鉴相器201的数据通道发送到处理器202。处理器202可根据参考时钟信号的质量信息进行权重分配。作为一个例子，参考时钟信号的质量较高，则该参考时钟信号与同步后的时钟信号之间的频率偏差所对应的权重较大，反之，参考时钟信号的质量较低，则该参考时钟信号与同步后的时钟信号之间的频率偏差所对应的权重较小。
-参考时钟信号的优先级信息
可预先对参考时钟信号的优先级进行配置。可选地，可对参考时钟源的优先级进行配置，一个参考时钟源的优先级与来自于该参考时钟源的参考时钟信号的优先级相同。这些配置信息可存储于存储器中。处理器202可从存储器获取参考时钟信号的优先级信息。参考时钟信号的优先级信息也可携带在报文中，该报文借助于鉴频鉴相器201的数据通道发送到处理器202。处理器202可根据参考时钟信号的优先级进行权重分配。作为一个例子，优先级较高则该参考时钟信号与同步后的时钟信号之间的频率偏差所对应的权重则较大，反之，参考时钟信号的优先级较低则该参考时钟信号与同步后的时钟信号之间的频率偏差所对应的权重则较小。
-第一至第N鉴频鉴相器201输出的频率偏差中的噪声信息
处理器202可针对鉴频鉴相器输出的频率偏差，提取其中的噪声信息，根据提取到的噪声信息进行权重分配。作为一个例子，从频率偏差中提取到的噪声较小，则该频率偏差所对应的权重较大，反之，从频率偏差中提取到的噪声较大，则该频率偏差所对应的权重较小。
-第一至第N鉴频鉴相器201输出的频率偏差所对应的相位偏差
所述N个参考时钟信号对应的N个频率偏差中的每个频率偏差，可由对应的系统时钟信号与参考时钟信号的多个相位偏差确定，比如，第一参考时钟信号对应的一个频率偏差PD_Err1可由系统时钟信号SysClk与第一参考时钟信号RefClk1在t0时刻和t1时刻的相位偏差确定。针对第一至第N鉴频鉴相器确定的N个频率偏差中的每个频率偏差所对应的相位偏差，控制器202可确定对应的参考时钟信号的权重。作为一个例子，对于一个频率偏差，如果所对应的相位偏差较小，则该该频率偏差所对应的权重较大，反之，如果所对应的相位偏差较大，则该频率偏差所对应的权重较小。
进一步地，在一些实施例中，时钟同步装置200中还可包括滤波模块(未在图中示出)。滤波模块可由一个或一组数字滤波器实现。滤波模块主要用于对第一至第N鉴频鉴相器201输出的频率偏差进行滤波，以滤除频率偏差中的噪声信息，以保证时钟同步的精度。
进一步地，处理器202还可根据确定出的频率补偿值，并进一步结合温度、时间等信息，确定频率偏差与时间的对应关系信息，和/或，频率偏差与温度的对应关系信息。以下 为描述方便，将“频率偏差与时间的对应关系信息”称为第一对应关系信息，将“频率偏差与温度的对应关系信息”称为第二对应关系信息。当处理器202确定所述N个参考时钟信号丢失时，根据保存的所述第一对应关系信息和/或第二对应关系信息，确定频率补偿值，并将确定出的频率补偿值输出给振荡器203。
可选地，所述第一对应关系信息可用一个以时间作为变量的线性多项式表示(为描述方便，该多项式称为第一多项式)。处理器202可根据设定时长内在多个时间点确定出的频率补偿值，统计得到该多项式的系数。比如，可按照固定时间间隔(每秒或每ms或其它时间间隔)采样得到频率偏差并保存至存储器中，然后根据一定时间长度(比如一天)内存储的各个时间点的频率偏差，通过多项式学习得到以下多项式：
f(t)＝a×t 3+b×t 2+c×t+d
其中，t为多项式的变量，表示时间；f(t)表示频率偏差；a、b、c、d分别为该多项式的系数。
处理器202可将该第一多项式的系数保存在存储器中，还可以进一步保存上述按照固定时间间隔采样到的频率偏差以及采样时刻点的时间计数器值(例如每秒+1)。
可选地，所述第二对应关系信息可用一个以温度作为变量的线性多项式表示(为描述方便，该多项式称为第二多项式)。处理器202可根据设定时长内在多个时间点确定出的频率补偿值，统计得到该多项式的系数。比如，可按照固定时间间隔(每秒或每ms或其它时间间隔)采样得到频率偏差，并将采样得到的频率偏差以及相应采样时间点的温度保存至存储器中，然后根据一定时间长度(比如一天)内存储的各个时间点的频率偏差以及温度，通过多项式学习得到以下多项式：
f(T)＝a’×T 3+b’×T 2+c’×T+d’
其中，T为多项式的变量，表示振荡器内部的温度，该振荡器可以是振荡器203；f(T)表示频率偏差；a’、b’、c’、d’分别为该多项式的系数。
处理器202可将该第二多项式的系数保存在存储器中，还可以进一步保存上述按照固定时间间隔采样到的频率偏差以及采样时刻点的温度。
当处理器202确定第一至第N参考时钟信号丢失时，可根据存储器204中存储的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值，并将确定出的频率补偿值输出给振荡器203，以使振荡器203根据该频率补偿值生成新的系统时钟信号。
具体来说，处理器202可根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定当前补偿周期对应的频率补偿值。其中，时间计数器值按照补偿周期递增。作为一个例子，补偿周期的长度为1ms，当处理器202确定所述N个参考时钟信号丢失时，则开始以该补偿周期确定补偿值。在第一个补偿周期，时间计数器数值取值为1，在第二个补偿周期，时间计数器数值取值为2，以此类推，时间计数器数值按照补偿周期以增量值等于1进行递增。当在第n个补充周期(n为大于等于1的整数)，时间计数器数值等于n，根据第一线性多项式的系数以及时间计数器数值n，可计算得到该补偿周期的频率补偿值：
a×n 3+b×n 2+c×n+d
具体来说，处理器202可根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的频率补偿值。作为一个例子，根据第二线性多项式的系数以及当前温 度m，可计算得到该温度对应的频率补偿值：
a’×m 3+b’×m 2+c’×m+d’
具体来说，处理器202可根据保存的第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，根据保存的第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值，并根据所述第一频率补偿值和所述第二频率补偿值确定用于输出给所述振荡器的频率补偿值。比如，可将第一频率补偿值与第二频率补偿值的和，作为用于输出给振荡器203的频率补偿值。
图4示例性地示出了一种由PFD实现的鉴频鉴相器的电路原理结构。以时钟同步装置200中的第一鉴频鉴相器201为例，如图4所示，该第一鉴频鉴相器201中包括用于检测两路输入信号(第一参考时钟信号RefClk1和系统时钟信号SysClk)的上升沿相位偏差的鉴频鉴相器2011和用于检测两路输入信号的下降沿相位偏差的鉴频鉴相器2012，加法器2013根据鉴频鉴相器2011和鉴频鉴相器2012的输出，得到这两路输入信号(RefClk1和SysClk)的频率偏差PD_Err1。
时钟同步装置200可根据具体情况工作在跟踪工作模式、保持工作模式或者自由振荡工作模式。下面结合图5对时钟同步装置的时钟同步流程进行描述。
在图5所示的S501～S502中，若时钟同步装置200中的处理器202确定第一至第N鉴频鉴相器201中的至少一个鉴频鉴相器输出有效的频率偏差，则转入S503，时钟同步装置工作在跟踪工作模式下；若时钟同步装置200中的处理器202确定第一至第N鉴频鉴相器201均未输出有效的频率偏差，则转入S505，时钟同步装置工作在保持工作模式下。
具体地，在一个例子中，若S501中，第一至第N鉴频鉴相器201均未接收到参考时钟信号，则无法输出有效的频率偏差，则处理器202可判断第一至第N参考信号丢失，因此进入保持工作模式。在另一个例子中，若S501中，第一至第N鉴频鉴相器201中的至少一个接收到参考时钟信号并输出频率偏差，但在S502中，处理器202判断所有鉴频鉴相器输出的频率偏差均异常，则可判断第一至第N参考信号丢失，因此进入保持工作模式。
在图5所示的S503～S504中，在跟踪工作模式下，处理器202对鉴频鉴相器输出的频率偏差进行加权求和，得到补偿值Δf，输出该补偿值Δf给振荡器203，振荡器203根据该补偿值Δf生成新的系统时钟信号，并输出生成的系统时钟信号。进一步地，处理器202根据该补偿值Δf确定频率偏差与时间的第一对应关系信息，和/或，频率偏差与温度的第二对应关系信息，将所述第一对应关系信息和/或第二对应关系信息存储于存储器204。跟踪工作模式的具体实现过程，可参见前述实施例的描述，在此不再重复。
在图5所示的S505～S506中，在保持工作模式下，处理器202获取存储器204中存储的所述第一对应关系信息和/或第二对应关系信息，根据获取的所述第一对应关系信息和/或第二对应关系信息，并可进一步结合补偿周期和/或温度等关键信息，确定频率补偿值，并输出给振荡器203。振荡器203根据输入的频率补偿值生成新的系统时钟信号，并输出生成的系统时钟信号。振荡器203可生成基本不受温度变化和老化影响的系统时钟信号。若处理器202无法从存储器204获取到所述第一对应关系信息和/或第二对应关系信息，则转入S507，进入自由振荡工作模式。
在图5所示的S507中，在自由振荡工作模式下，振荡器203可基于本地时钟信号生成系统时钟信号，并输出生成的系统时钟信号。
本申请的实施例中，一方面，在跟踪工作模式下，时钟同步装置不是仅跟踪一路参考时钟信号，而是跟踪多路参考时钟信号，并对系统时钟信号与多路参考时钟信号的频率偏差进行加权求和，从而得到补偿值。在现有技术中，若所选择的参考时钟信号异常，则该异常所产生的误差会全部引入时钟同步过程。而本申请实施例中，由于在确定补偿值时，以多路参考时钟信号为依据，因此，若这多路参考时钟信号中有一部分参考时钟信号异常，则该异常所产生的误差仅部分引入时钟同步过程，降低了对时钟同步的影响。尤其在使用业务时钟信号作为参考时钟信号的情况下，由于业务时钟信号中承载有业务数据，容易因业务处理异常等原因产生信号异常，从而影响时钟同步精度，而采用本申请实施例，可降低业务时钟与系统时钟间的耦合性，隔离业务时钟对系统时钟的干扰。
另一方面，在跟踪工作模式下，时钟同步装置确定频率偏差与时间的第一对应关系信息和/或频率偏差与温度的第二对应关系信息时，依据的是系统时钟信号与多路参考时钟信号的频率偏差的加权平均值，而非单个参考时钟信号与时钟信号的频率偏差，相比之下降低了单路参考时钟信号对系统时钟性能的影响。由于上述第一对应关系信息和第二对应关系信息可反映振荡器的频率特性，因此使得通过这种方法得到的振荡器的频率特性更加稳定，因而在保持工作模式下，基于该频率特性所得到的补偿值更加准确，从而提高了时钟同步的性能。
参见图6，为本申请另一实施例提供的时钟不同流程示意图，该流程可包括：
S601：N个鉴频鉴相器确定N个频率偏差，所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差，所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定，N为大于1的整数；
S602：处理器根据所述N个频率偏差，确定补偿值，所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重；
S603：振荡器根据所述补偿值生成新的系统时钟信号。
上述流程可采用图2a或图2b所示的时钟同步装置执行，其中，S601可由上述时钟同步装置中的N个鉴频鉴相器执行，S602可由上述时钟同步装置中的处理器执行，S603可由上述时钟同步装置中的振荡器执行。上述各步骤的具体实现过程，可参见前述实施例，在此不再详述。
本发明实施例还提供了一种计算机可读存储介质，用于存储为执行上述处理器所需执行的计算机软件指令，其包含用于执行上述处理器所需执行的程序。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一 个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。

Claims (12)

  1. 一种时钟同步装置，其特征在于，包括：
    N个鉴频鉴相器，用于确定N个频率偏差，所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差，所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定，N为大于1的整数；
    处理器，用于根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重；
    振荡器，用于根据所述处理器确定的补偿值生成新的系统时钟信号。
  2. 如权利要求1所述的装置，其特征在于，所述处理器包括：
    权重确定单元，用于根据所述N个参考时钟信号的同步性能信息，确定所述N个鉴频鉴相器确定的所述N个频率偏差中每个频率偏差的权重；
    补偿值确定单元，用于根据所述权重确定单元确定的所述N个频率偏差中每个频率偏差对应的权重，对所述N个频率偏差进行加权求和，所述补偿值等于所述加权求和的结果。
  3. 如权利要求2所述的装置，其特征在于，所述N个参考时钟信号的同步性能信息包括以下信息中的一种或多种：
    所述N个参考时钟信号中每个参考时钟信号的质量信息；
    所述N个参考时钟信号中每个参考时钟信号的优先级信息；
    所述N个鉴频鉴相器确定的N个频率偏差中每个频率偏差的噪声信息；
    所述N个鉴频鉴相器确定的N个频率偏差中的每个频率偏差所对应的相位偏差，其中，所述N个参考时钟信号对应的N个频率偏差中的每个频率偏差，由对应的参考时钟信号与所述系统时钟信号的多个相位偏差确定。
  4. 如权利要求1至3中任一项所述的装置，其特征在于，所述处理器还包括：异常检测单元；
    所述异常检测单元，用于检测所述N个参考时钟信号是否异常，并指示所述处理器仅根据正常的参考时钟信号所对应的鉴频鉴相器确定的频率偏差确定补偿值。
  5. 如权利要求1至4中任一所述的装置，其特征在于，所述处理器还用于：
    根据所述频率补偿值确定频率偏差与时间的第一对应关系信息，并保存所述第一对应关系信息，和/或，确定频率偏差与温度的第二对应关系信息，并保存所述第二对应关系信息；
    所述处理器还用于：
    确定所述N个参考时钟信号丢失时，根据保存的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值，并将确定出的频率补偿值输出给所述振荡器。
  6. 如权利要求5所述的装置，其特征在于，所述第一对应关系符合以时间作为变量的第一线性多项式，所保存的第一对应关系信息包括所述第一线性多项式的系数；所述第二对应关系符合以温度作为变量的第二线性多项式，所保存的第二对应关系信息包括所述第二线性多项式的系数；
    所述处理器具体用于：
    根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，其中，时间计数器值根据补偿周期递增；或者，
    根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值；或者，
    根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值，并根据所述第一频率补偿值和所述第二频率补偿值确定用于输出给所述振荡器的频率补偿值；其中，时间计数器值根据补偿周期递增。
  7. 一种时钟同步方法，其特征在于，包括：
    N个鉴频鉴相器确定N个频率偏差，所述N个鉴频鉴相器与所述N个频率偏差一一对应，所述N个鉴频鉴相器与N个参考时钟信号一一对应，其中，所述N个频率偏差是系统时钟信号与所述N个参考时钟信号的频率偏差，所述系统时钟信号与每个参考时钟信号的频率偏差由对应的鉴频鉴相器确定，N为大于1的整数；
    处理器根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，所述补偿值等于所述N个频率偏差的加权平均值，所述N个频率偏差中的每个频率偏差分别对应一个权重；
    振荡器根据所述补偿值生成新的系统时钟信号。
  8. 如权利要求7所述的方法，其特征在于，所述处理器根据所述N个鉴频鉴相器确定的所述N个频率偏差，确定补偿值，包括：
    所述处理器根据所述N个参考时钟信号的同步性能信息，确定所述N个频率偏差中每个频率偏差的权重；
    所述处理器根据所述N个频率偏差中每个频率偏差对应的权重，对所述N个频率偏差进行加权求和，所述补偿值等于所述加权求和的结果。
  9. 如权利要求8所述的方法，其特征在于，所述N个参考时钟信号的同步性能信息包括以下信息中的一种或多种：
    所述N个参考时钟信号中每个参考时钟信号的质量信息；
    所述N个参考时钟信号中每个参考时钟信号的优先级信息；
    所述N个鉴频鉴相器确定的N个频率偏差中每个频率偏差的噪声信息；
    所述N个鉴频鉴相器确定的N个频率偏差中的每个频率偏差所对应的相位偏差，其中，所述N个参考时钟信号对应的N个频率偏差中的每个频率偏差，由对应的参考时钟信号与所述系统时钟信号的多个相位偏差确定。
  10. 如权利要求7至9中任一项所述的方法，其特征在于，还包括：
    所述处理器检测所述N个参考时钟信号是否异常，并仅根据正常的参考时钟信号所对应的鉴频鉴相器确定的频率偏差确定补偿值。
  11. 如权利要求7至10中任一所述的方法，其特征在于，还包括：
    所述处理器根据所述频率补偿值确定频率偏差与时间的第一对应关系信息，并保存所述第一对应关系信息，和/或，确定频率偏差与温度的第二对应关系信息，并保存所述第二 对应关系信息；
    所述处理器确定所述N个参考时钟信号丢失时，根据保存的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值。
  12. 如权利要求11所述的方法，其特征在于，所述第一对应关系符合以时间作为变量的第一线性多项式，所保存的第一对应关系信息包括所述第一线性多项式的系数；所述第二对应关系符合以温度作为变量的第二线性多项式，所保存的第二对应关系信息包括所述第二线性多项式的系数；
    所述处理器根据保存的所述第一对应关系信息和/或所述第二对应关系信息，确定频率补偿值，包括：
    所述处理器根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，其中，时间计数器值根据补偿周期递增；或者，
    所述处理器根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值；或者，
    所述处理器根据保存的所述第一线性多项式的系数以及当前补偿周期所对应的时间计数器值，确定所述当前补偿周期对应的第一频率补偿值，根据保存的所述第二线性多项式的系数以及当前温度，确定所述当前温度对应的第二频率补偿值，并根据所述第一频率补偿值和所述第二频率补偿值确定用于输出给所述振荡器的频率补偿值；其中，时间计数器值根据补偿周期递增。
PCT/CN2018/073241 2017-01-26 2018-01-18 一种时钟同步装置及方法 WO2018137548A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710064282.5 2017-01-26
CN201710064282.5A CN106788853B (zh) 2017-01-26 2017-01-26 一种时钟同步装置及方法

Publications (1)

Publication Number Publication Date
WO2018137548A1 true WO2018137548A1 (zh) 2018-08-02

Family

ID=58956071

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/073241 WO2018137548A1 (zh) 2017-01-26 2018-01-18 一种时钟同步装置及方法

Country Status (2)

Country Link
CN (1) CN106788853B (zh)
WO (1) WO2018137548A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106788853B (zh) * 2017-01-26 2018-12-07 华为技术有限公司 一种时钟同步装置及方法
CN107144343A (zh) * 2017-07-10 2017-09-08 薛天 低频振动位移传感器组网方法、系统及装置
CN109586715A (zh) * 2018-11-20 2019-04-05 中国电子科技集团公司第五十四研究所 一种多源综合时钟产生装置
WO2020237648A1 (zh) * 2019-05-31 2020-12-03 京东方科技集团股份有限公司 信号频率调整方法及装置、显示装置、存储介质
CN111355551A (zh) * 2020-02-11 2020-06-30 西安电子科技大学 一种适用于半稳态链路的网络时钟同步方法及装置
CN114126027B (zh) * 2020-08-26 2024-04-09 上海华为技术有限公司 一种获取累计偏差的方法，装置以及相关设备
CN112350718B (zh) * 2020-09-25 2023-06-27 苏州华兴源创科技股份有限公司 时钟源电路、机箱及多机箱级联系统
CN113541913B (zh) * 2020-11-05 2022-08-02 中兴通讯股份有限公司 时钟校准方法、时钟校准装置、电子设备和可读介质
CN112383498B (zh) * 2020-11-17 2022-11-04 紫光展锐(重庆)科技有限公司 低频时钟的补偿方法及装置、存储介质、终端
CN114528998B (zh) * 2022-01-26 2023-05-12 山东浪潮科学研究院有限公司 用于量子测控系统的多板卡信号同步方法、设备及介质
CN114785341B (zh) * 2022-06-16 2022-10-11 成都金诺信高科技有限公司 一种用于多输入的锁相环参考源切换方法及锁相环

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000224059A (ja) * 1999-01-29 2000-08-11 Nec Eng Ltd 干渉波除去方法
WO2005078935A1 (de) * 2004-02-12 2005-08-25 Infineon Technologies Ag Digitaler phasenregelkreis mit schnellem einschwingverhalten
CN101398474A (zh) * 2007-09-30 2009-04-01 郑州威科姆技术开发有限公司 北斗与gps双系统秒时差切换方法
CN101753134A (zh) * 2008-11-28 2010-06-23 卓联半导体有限公司 用于锁相环的软基准切换
CN106788853A (zh) * 2017-01-26 2017-05-31 华为技术有限公司 一种时钟同步装置及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008010536A1 (de) * 2008-02-22 2009-08-27 Symeo Gmbh Schaltungsanordnung und Verfahren zur Synchronisation von Uhren in einem Netz
CN101651456B (zh) * 2008-08-12 2012-03-21 博通集成电路（上海）有限公司 时钟信号恢复的电路
CN104683088B (zh) * 2014-12-01 2017-02-15 国家电网公司 多基准同步方法、装置及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000224059A (ja) * 1999-01-29 2000-08-11 Nec Eng Ltd 干渉波除去方法
WO2005078935A1 (de) * 2004-02-12 2005-08-25 Infineon Technologies Ag Digitaler phasenregelkreis mit schnellem einschwingverhalten
CN101398474A (zh) * 2007-09-30 2009-04-01 郑州威科姆技术开发有限公司 北斗与gps双系统秒时差切换方法
CN101753134A (zh) * 2008-11-28 2010-06-23 卓联半导体有限公司 用于锁相环的软基准切换
CN106788853A (zh) * 2017-01-26 2017-05-31 华为技术有限公司 一种时钟同步装置及方法

Also Published As

Publication number Publication date
CN106788853B (zh) 2018-12-07
CN106788853A (zh) 2017-05-31

Similar Documents

Publication Publication Date Title
WO2018137548A1 (zh) 一种时钟同步装置及方法
US7439816B1 (en) Phase-locked loop fast lock circuit and method
US6297702B1 (en) Phase lock loop system and method
US20090296869A1 (en) Communication systems, clock generation circuits thereof, and method for generating clock signal
CN106209084A (zh) 双路定时抖动或漂移消除
US9660797B2 (en) Method and apparatus for implementing clock holdover
US7555089B2 (en) Data edge-to-clock edge phase detector for high speed circuits
JP2518148B2 (ja) クロック従属同期方法
US11144088B2 (en) Clocking synchronization method and apparatus
CN106656392A (zh) 一种时钟参考无缝切换的方法及装置
CN108183708B (zh) 相位锁定检测方法及其电路、锁相环
CN109787620B (zh) 一种基于数字分频器的校准频率的方法及装置
TW201631897A (zh) 具有時序自我檢測的四相位時脈產生器
US10110371B2 (en) Phase difference estimation device and communication device having the phase difference estimation device
JP5270524B2 (ja) クロック位相同期回路
JPH09502594A (ja) デジタル位相ロック・ループ
US10116435B2 (en) Control circuit and control method of communication device
JPH0779366B2 (ja) 通信ネットワークに接続される端末装置
JP5323977B1 (ja) クロック再生装置及び方法
JPH0349319A (ja) 同期検出方式
JP2015171002A (ja) 電気・電子機器、回路、及び通信システム
JP2010124295A (ja) 制御装置、クロック同期方法
JPH06140928A (ja) ドリフト検出回路
CN114116581A (zh) 提高高速串行总线突发传输响应性能的方法及装置
JP2011176611A (ja) アンロック検出回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18744824

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18744824

Country of ref document: EP

Kind code of ref document: A1