WO2018086380A1 - Procédé de préparation d'un substrat hétérogène iii-v de grande taille - Google Patents

Procédé de préparation d'un substrat hétérogène iii-v de grande taille Download PDF

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WO2018086380A1
WO2018086380A1 PCT/CN2017/094041 CN2017094041W WO2018086380A1 WO 2018086380 A1 WO2018086380 A1 WO 2018086380A1 CN 2017094041 W CN2017094041 W CN 2017094041W WO 2018086380 A1 WO2018086380 A1 WO 2018086380A1
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iii
substrate
layer
ion implantation
preparing
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PCT/CN2017/094041
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English (en)
Chinese (zh)
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欧欣
龚谦
游天桂
黄凯
林家杰
张润春
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中国科学院上海微系统与信息技术研究所
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Publication of WO2018086380A1 publication Critical patent/WO2018086380A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
    • C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment

Definitions

  • the invention belongs to the technical field of semiconductor fabrication, and in particular relates to a preparation method of a large-sized III-V heterogeneous substrate by using an ion implantation stripping technique in combination with an epitaxial growth technique.
  • CMOS Complementary Metal Oxide Semiconductor
  • III-V hetero-substrate materials which can not only prepare high-speed and low-power devices in CMOS circuits, but also overcome the size reduction limit faced by silicon-based CMOS technology, and integrate III -V semiconductor materials and silicon-based materials will provide material assurance for integration of optical components (such as lasers, photoemitters, and photodetectors) in silicon-based COMS circuits for chip system integration (SoC).
  • optical components such as lasers, photoemitters, and photodetectors
  • silicon-based III-V hetero-substrate materials there are mainly two ways to realize silicon-based III-V hetero-substrate materials: (1) epitaxial growth technology; (2) ion implantation-based thin film transfer technology (referred to as ion implantation stripping technology).
  • Large-scale silicon-based III-V hetero-substrate materials can be prepared by epitaxial growth techniques. Common epitaxial growth methods include molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • the heteroepitaxial III-V layer has problems such as reverse domain, lattice mismatch, and thermal expansion coefficient.
  • the dislocation density is above 10 6 cm -2 , and the high dislocation density will reduce the electron mobility and cause Poor device reliability, high power consumption and other issues.
  • III-V layer requires introduction of a buffer layer (generally Ge and a low-mass III-V layer having a thickness of 1 to 2 ⁇ m). Due to the light absorption of the buffer layer, its application to silicon photonic devices is limited, and the thick buffer layer also makes it impossible to implement fully depleted microelectronic devices. Ion implantation stripping technology can be used to directly strip the III-V film from the III-V wafer to prepare a silicon-based III-V hetero-substrate material, which can overcome the reverse domains, lattice mismatch and heat loss in epitaxial growth. Matching issues, and no buffer layer is required.
  • a buffer layer generally Ge and a low-mass III-V layer having a thickness of 1 to 2 ⁇ m. Due to the light absorption of the buffer layer, its application to silicon photonic devices is limited, and the thick buffer layer also makes it impossible to implement fully depleted microelectronic devices. Ion implantation stripping technology can be used to directly strip the III-V film from the III-
  • III-V wafers are limited in size (up to 6 inches), making it impossible to prepare large-sized silicon-based III-V hetero-substrate; on the other hand, the ion implantation dose required to directly strip III-V wafers is very large, and III -V chips are expensive and costly. Therefore, there is an urgent need to develop a technique for efficiently preparing a large-sized high-quality silicon-based III-V hetero-substrate.
  • the object of the present invention is to provide a method for preparing a large-sized III-V hetero-substrate for solving the difficulty of preparing a large-sized III-V hetero-substrate in the prior art.
  • the present invention provides a method for preparing a large-sized III-V hetero-substrate, characterized in that the preparation method comprises the following steps: S1: providing a III-V epitaxial structure, The III-V epitaxial structure has an implantation surface; S2: performing ion implantation on the implantation surface, forming a defect layer at a predetermined depth of the III-V epitaxial structure; S3: providing a support substrate, and the implanted surface The support substrate is bonded; S4: peeling off a portion of the III-V epitaxial structure along the defect layer, transferring a portion of the III-V epitaxial structure onto the support substrate to be on the support liner A III-V film was formed on the bottom to obtain a III-V hetero substrate.
  • the method for preparing the III-V epitaxial structure comprises the following steps: S1-1: providing an epitaxial substrate; S1-2: forming a buffer layer on the epitaxial substrate; S1-3: A III-V layer is formed on the buffer layer, and an upper surface of the III-V layer is an injection surface.
  • the preset depth is the III-V layer, the buffer layer or the interface of the III-V layer and the buffer layer.
  • the epitaxial substrate has a size of 50 mm to 500 mm.
  • the epitaxial substrate is a silicon substrate, a SiO 2 /Si substrate or a Ge substrate; in step S3, the support substrate is a silicon substrate or a SiO 2 /Si substrate. .
  • step S1-1 and step S1-2 the step of cleaning the epitaxial substrate is further included.
  • the ion implantation performed on the III-V epitaxial structure is a single ion implantation of H ions, a single ion implantation of He ions, or a common ion implantation of H ions and He ions.
  • the ion implantation energy is 5 keV to 5000 keV
  • the ion implantation dose is 1 ⁇ 10 16 ions/cm 2 to 5 ⁇ 10 17 ions/cm 2
  • the ion implantation temperature is -50 ° C to 700 ° C.
  • step S4 the structure obtained in step S3 is annealed to peel off part of the III-V epitaxial structure along the defect layer, and a part of the III-V epitaxial structure is transferred onto the support substrate.
  • a III-V film on the support substrate to obtain a III-V hetero substrate.
  • the annealing treatment is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one of nitrogen, oxygen and an inert gas, the annealing temperature is 50 ° C to 1200 ° C, and the annealing time is 2 minutes to 24 hours.
  • step S3 before step S4, further comprising the step of performing a surface planarization process on the injection surface; and after step S4, further comprising the step of performing a surface planarization process on the III-V heterogeneous substrate.
  • the method for preparing a large-sized III-V hetero-substrate of the present invention has the following beneficial effects:
  • the invention utilizes ion implantation stripping technology combined with epitaxial growth technology to prepare large-sized III-V hetero-substrate, breaks through the limitation of the existing III-V wafer size, and successfully prepares a large-sized silicon-based III-V hetero-substrate and reduces The cost of preparation.
  • the present invention obtains a large-sized III-V epitaxial structure by epitaxial growth technique, and then peels off part of the III-V epitaxial structure, transferring a part of the III-V epitaxial structure onto the support substrate to be on the support
  • a III-V film is formed on the substrate, and the III-V film is integrated with the supporting substrate by bonding, so that there is almost no requirement for lattice matching, and the selection of the III-V film and the supporting substrate material is more flexible.
  • the crystal quality and properties of the obtained III-V film are comparable to those of the direct epitaxially grown III-V film.
  • the present invention adopts a bonding method to control the defect within a very small thickness range near the interface, and the internal lattice quality of the III-V film is not Affected, even if the thickness of the stripped III-V film is small, material properties can be guaranteed; and different types of III-V films and other semiconductor film materials can be simultaneously integrated on the same silicon-based substrate, and the properties of each film material It is not affected by the preparation process, which greatly improves the integration of the device and the flexibility of the design.
  • the depth of ion implantation in the present invention may be determined by ion implantation energy, and a defect layer may be formed at the interface of the III-V layer, the buffer layer or the III-V layer and the buffer layer, which can effectively reduce the peeling and transfer III
  • the total ion implantation dose required for the -V film which shortens the preparation cycle and saves production costs.
  • the common ion implantation used in the invention can effectively reduce the total ion implantation dose required for stripping and transferring the III-V film, thereby shortening the preparation cycle and saving the production cost; meanwhile, the method can also solve the use of some materials. Single ion implantation cannot achieve the problem of peeling.
  • FIG. 1 is a flow chart showing a method of preparing a large-sized III-V hetero-substrate of the present invention.
  • 2 to 15 are schematic views showing the structures corresponding to the steps of the preparation method of the large-size III-V hetero-substrate of the present invention.
  • the present invention provides a method for preparing a large-sized III-V hetero-substrate using an ion implantation stripping technique in combination with an epitaxial growth technique, the preparation method comprising the following steps:
  • step S1 providing a III-V epitaxial structure having an implantation surface 31.
  • the method for preparing the III-V epitaxial structure in step S1 includes the following steps:
  • step S1-1 epitaxial substrate 1 is provided.
  • the epitaxial substrate 1 may be, but not limited to, a silicon substrate, a SiO 2 /Si substrate, or a Ge substrate, the epitaxial substrate 1 having a size of 50 mm to 500 mm, for example, the epitaxial substrate
  • the circular substrate has a diameter of 50 mm to 500 mm.
  • the epitaxial substrate has a rectangular shape and a length and a width of 50 mm to 500 mm, respectively.
  • other shapes of the epitaxial substrate are also applicable, and are not limited to the examples listed herein. Example.
  • step S1-2 epitaxial growth on the epitaxial substrate 1 to form a buffer layer 2;
  • step S1-3 epitaxial growth on the buffer layer 2 forms a high quality III-V layer 3, and the upper surface of the III-V layer 3 is an implantation surface 31.
  • the material of the buffer layer 2 may be, but not limited to, a crucible or a low temperature grown III-V material.
  • the growth method of the buffer layer 2 may be, but not limited to, molecular beam epitaxy or organometallic vapor phase growth.
  • the thickness of the buffer layer 2 may be, but not limited to, 10 nm to 50 ⁇ m.
  • the material of the III-V layer 3 may be, but not limited to, GaAs, InGaAs, or InP.
  • the growth method of the III-V layer 3 may be, but not limited to, molecular beam epitaxy or organometallic vapor phase growth.
  • the thickness of the III-V layer 3 may be, but not limited to, 10 nm to 50 ⁇ m.
  • step S1-1 and step S1-2 in this embodiment the step of cleaning the epitaxial substrate 1 is further included.
  • the epitaxial substrate 1 is cleaned.
  • the method of cleaning the epitaxial substrate 1 may be a substrate cleaning method commonly used in the semiconductor field, which is not limited herein.
  • the epitaxial substrate 1 is cleaned to remove impurities located on the surface of the epitaxial substrate 1 to improve the quality of the epitaxial growth of the III-V layer 3 on the epitaxial substrate 1.
  • the epitaxial growth method on the epitaxial substrate and the buffer layer may also be a conventional material epitaxial growth method such as chemical vapor deposition, physical vapor deposition or magnetron sputtering.
  • step S2 performing ion implantation on the implantation surface 31 to form a defect layer 4 at a predetermined depth of the III-V epitaxial structure.
  • the preset depth is set at the interface of the III-V layer 3, the buffer layer 2 or the III-V layer 3 and the buffer layer 2. That is, the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth of the III-V epitaxial structure and form the defect layer 4.
  • the preset depth is set according to actual needs.
  • the arrows shown in Figs. 4 to 6 perpendicular to the injection face 31 of the III-V layer 3 indicate the direction of ion implantation.
  • the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth within the III-V layer 3, i.e., the defect layer 4 is formed within the III-V layer 3.
  • the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth at the interface of the buffer layer 2 and the III-V layer 3, ie, at the buffer layers 2 and III-
  • the defect layer 4 is formed at the interface of the V layer 3, that is, the defect layer 4 is simultaneously formed on the buffer layer 2 and the III-V layer 3.
  • the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth within the buffer layer 2, i.e., the defect layer 4 is formed within the buffer layer 2.
  • the ion implantation performed on the III-V epitaxial structure on the implantation surface 31 is a single ion implantation of H ions, a single ion implantation of He ions, or a common ion implantation of H ions and He ions.
  • the ion implantation energy is 5 keV to 5000 keV
  • the ion implantation dose is 1 ⁇ 10 16 ions/cm 2 to 5 ⁇ 10 17 ions/cm 2
  • the ion implantation temperature is -50 ° C to 700 ° C.
  • a single type of ion implantation is performed on the implanted surface 31, the implanted ions being H ions.
  • the principle that the H ions can strip the III-V layer 3, the buffer layer 2, or the interface between the buffer layer 2 and the III-V layer 3 is to utilize the lattice of H ions at the peeling depth (ie, at the defect layer 4). It is achieved by the formation of a destructive effect.
  • the depth at which the defect layer 4 is formed is determined by the energy of ion implantation, and the defect density required for separation can be determined by the dose of ion implantation, a suitable ion implantation dose and ion are selected during ion implantation. Inject energy.
  • the ion implantation energy of the H ion is 5 keV to 1000 keV
  • the ion implantation dose is 1 ⁇ 10 16 ions/cm 2 to 6 ⁇ 10 17 ions/cm 2
  • the ion implantation temperature is ⁇ 50° C. 700 ° C.
  • a single type of ion implantation is also performed on the implanted surface 31, but in this example, the implanted ions are He ions.
  • the implanted ions are He ions.
  • a defect is generated at the interface of the III-V layer 3, the buffer layer 2, or the buffer layer 2 and the III-V layer 3, and the He ions are accumulated in the defect and generate a pressure.
  • the defect has a Gaussian distribution in the defect layer 4, and in the subsequent processing, part of the III-V epitaxial structure can be peeled off from the maximum defect concentration.
  • the ion implantation energy of the He ion is 5 keV to 1000 keV
  • the ion implantation dose is 1 ⁇ 10 16 ions/cm 2 to 6 ⁇ 10 17 ions/cm 2
  • the ion implantation temperature is ⁇ 50° C. 700 ° C.
  • co-injection of two types of ions is performed within the III-V semiconductor material 3, the implanted ions being H ions and He ions.
  • the H ion is used to form a defect as described above, the defect having a Gaussian distribution in the defect layer 4; and He being an inert element, and the III-V layer 3, the buffer layer 2, or the buffer layer 2
  • the III-V layer 3 the buffer layer 2, or the buffer layer 2
  • they can be trapped by the platform defects formed by H ions and physically expand and combine these platform-type defects to form a crack that can separate the III-V epitaxial structure. Promoting part of the III-V epitaxial structure to achieve peeling from the maximum defect concentration.
  • Co-injection of H ions and He ions is performed on the injection surface 31, and He ions can be trapped by defects formed by H ions, and then enter the atomic gap and apply pressure, which is equivalent to applying an extra inside the defects generated by the H ions.
  • the force can effectively promote the peeling of some of the III-V epitaxial structures at a low ion implantation dose, that is, the total dose of ion implantation can be effectively reduced, thereby shortening the preparation cycle and saving the production cost.
  • the manner in which the H ions and the He ions are co-implanted may be sequentially performed, or may be simultaneously performed, that is, the implantation of the H ions may be performed before the implantation of the He ions, also in the The implantation of He ions is followed by simultaneous injection with the He ions.
  • the depth of He ion implantation needs to be the same or similar to the depth of H ion implantation, that is, the range (R p ) of He ions needs to be ensured.
  • the energy of co-injection of H ions and He ions is 5 keV to 1000 keV
  • the total implantation dose of H ions and He ions is 1 ⁇ 10 16 ions/cm 2 to 6 ⁇ 10 17 ions/cm 2 , H ions and
  • the temperature at which He ion is implanted is -50 ° C to 700 ° C.
  • step S3 providing a support substrate 5, and bonding the injection surface 31 to the support substrate 5.
  • the support substrate 5 is a silicon-based substrate, and may be, for example, a hetero-substrate such as silicon.
  • a III-V epitaxial structure in which the defect layer 4 is formed is bonded to the support substrate 5, and an implantation surface 31 of the III-V epitaxial structure is a bonding surface, that is, the III-V
  • the injection face 31 of the epitaxial layer 3 is in close contact with the surface of the bonded substrate.
  • step S3 a step of performing a surface planarization process on the bonding surface of the III-V epitaxial structure is further included to obtain a high quality bonding.
  • the structure obtained in step S2 may be bonded to the support substrate 5 by direct bonding, dielectric layer bonding, metal bonding or anodic bonding indirect bonding.
  • the dielectric layer bonding process includes a growth dielectric layer bonding process, a polymer bonding process, a molten glass bonding process, and a spin-on glass bonding process.
  • step S4 stripping a portion of the III-V epitaxial structure along the defect layer 4, and transferring a portion of the III-V epitaxial structure onto the support substrate 5, A III-V thin film is formed on the support substrate 5 to obtain a III-V hetero substrate.
  • the structure obtained in step S3 is annealed to peel off part of the III-V epitaxial structure from the epitaxial substrate 1 along the defect layer 4 to obtain a high quality III-V film 6. And transferring the obtained III-V film 6 onto a silicon-based substrate to obtain a silicon-based III-V heterogeneous integrated substrate.
  • the defect layer 4 is at the interface of the III-V layer 3, the buffer layer 2 or the III-V layer 3 and the buffer layer 2.
  • the annealing treatment is carried out under a vacuum atmosphere or under a protective atmosphere formed by at least one of nitrogen, oxygen and an inert gas, the annealing temperature is 50 ° C to 1200 ° C, and the annealing time is 2 minutes to 24 hours.
  • the III-V epitaxial structure in which the defect layer 4 is formed is annealed to achieve partial peeling of the III-V epitaxial structure along the defect layer 4.
  • the annealing process is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one gas of nitrogen and an inert gas, the annealing temperature is 150 ° C to 1200 ° C, and the annealing time is 5 minutes to 24 hours.
  • the implanted ions ie, H ions, He ions
  • the III-V epitaxial structure formed with the defect layer 4 is annealed, and the annealing process is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one gas of nitrogen and an inert gas, and the annealing temperature is performed.
  • the annealing time is from 5 minutes to 24 hours from 150 ° C to 1200 ° C.
  • a transverse layer is applied to the defect layer 4 To the mechanical force, a part of the III-V epitaxial structure is peeled off along the defect layer 4 to obtain the III-V film 6.
  • the defect density required for forming part of the III-V epitaxial structure to be separated is determined by the dose of ion implantation, if only part of the III-V epitaxial structure is separated from the defect layer 4 by annealing, It is necessary to inject a relatively large amount or a specific dose of ions into the injection surface 31; and apply a transverse mechanical force at the defect layer 4, even if the dose of ion implantation to the injection surface 31 is small or biased, separation cannot be formed.
  • the required defect density under the action of an external force, can also achieve partial separation of the III-V epitaxial structure from the defect layer 4, that is, applying a transverse mechanical force at the defect layer 4 can reduce the total ion implantation dose.
  • the portion of the III-V epitaxial structure is stripped from the defect layer 4 to obtain the III-V film 6, thereby shortening the preparation cycle and saving production costs.
  • the III-V epitaxial structure in which the defect layer 4 is formed is annealed, and the annealing process is performed under a vacuum atmosphere or a protective atmosphere formed by at least one gas of nitrogen and an inert gas.
  • the annealing temperature is from 150 ° C to 1200 ° C, and the annealing time is from 5 minutes to 24 hours.
  • the annealing temperature is maintained, and the auxiliary material layer is deposited on the injection surface 31 of the III-V layer 3 and then rapidly cooled;
  • the auxiliary material layer and the III-V layer 3 have different coefficients of thermal expansion.
  • the auxiliary material may be any one different from the coefficient of thermal expansion of the III-V layer 3.
  • the auxiliary material is a high polymer. Since the auxiliary material has a different thermal expansion coefficient from the III-V layer 3, especially when the thermal expansion coefficients of the two have a large difference, thermal stress is generated in the structure composed of the two in the process of rapid cooling. The thermal stress causes some of the III-V epitaxial structure to achieve peeling at the maximum concentration of the implant defect.
  • the means of rapid cooling can be, but is not limited to, cooling with the furnace.
  • the defect density required for the formation of the III-V epitaxial structure is determined by the dose of ion implantation, if only part of the III-V epitaxial structure is separated from the defect layer 4 by annealing, it is required A specific dose of ions is implanted into the injection surface 31; and the auxiliary material layer is rapidly cooled after the deposition surface 31 is deposited, so that thermal stress is generated in the structure formed by the two, even if the dose of ion implantation is performed on the injection surface 31. It is relatively small, and the defect density required for separation cannot be formed. Under the action of the thermal stress, part of the III-V epitaxial structure can be separated from the defect layer 4, that is, deposition auxiliary on the injection surface 31. The material layer and rapid cooling can reduce the total ion implantation dose, and promote part of the III-V epitaxial structure to be peeled off from the defect layer 4 to obtain the III-V film 6, thereby shortening the preparation cycle and saving production cost. .
  • step S4 further comprising the step of performing a surface planarization process on the III-V hetero-substrate to remove the buffer layer 2 remaining on the surface and/or the low-quality III-V layer damaged by the implanted ions 3, to obtain a high quality silicon-based III-V hetero substrate.
  • the method of the above planarization treatment may be, but not limited to, a chemical etching method or a chemical mechanical polishing method.
  • the present invention utilizes an ion implantation stripping technique in combination with an epitaxial growth technique to prepare a large-sized III-V hetero-substrate, breaks through the limitations of the existing III-V wafer size, and successfully prepares a large-sized silicon-based III-V.
  • the substrate reduces the cost of preparation.
  • the present invention obtains a large-sized III-V epitaxial structure by epitaxial growth technique, and then peels off part of the III-V epitaxial structure, transferring a part of the III-V epitaxial structure onto the support substrate to be on the support
  • a III-V film is formed on the substrate, and the III-V film is integrated with the supporting substrate by bonding, so that there is almost no requirement for lattice matching, and the selection of the III-V film and the supporting substrate material is more flexible.
  • the crystal quality and properties of the obtained III-V film are comparable to those of the direct epitaxially grown III-V film.
  • the present invention adopts a bonding method to control the defect within a very small thickness range near the interface, and the internal lattice quality of the III-V film is not Affected, even if the thickness of the stripped III-V film is small, material properties can be guaranteed; and different types of III-V films and other semiconductor film materials can be simultaneously integrated on the same silicon-based substrate, and the properties of each film material It is not affected by the preparation process, which greatly improves the integration of the device and the flexibility of the design.
  • the depth of ion implantation in the present invention may be determined by ion implantation energy, and a defect layer may be formed at the interface of the III-V layer, the buffer layer or the III-V layer and the buffer layer, which can effectively reduce the peeling and transfer III
  • the total ion implantation dose required for the -V film which shortens the preparation cycle and saves production costs.
  • the common ion implantation used in the invention can effectively reduce the total ion implantation dose required for stripping and transferring the III-V film, thereby shortening the preparation cycle and saving the production cost; meanwhile, the method can also solve the use of some materials. Single ion implantation cannot achieve the problem of peeling.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

La présente invention concerne un procédé qui permet de préparer un substrat hétérogène III-V de grande taille et qui consiste : S1 : à utiliser une structure épitaxiale III-V (1) qui comporte une surface d'injection (31); S2 : à effectuer une implantation ionique sur la surface d'injection, et à former une couche de défaut (4) à un emplacement d'une profondeur préétablie sur la structure épitaxiale III-V; S3 : à utiliser un substrat de support (5), et à lier la surface d'injection au substrat de support; S4 : à décoller une partie de la structure épitaxiale III-V le long de la couche de défaut, de telle sorte qu'une partie de la structure épitaxiale III-V est transférée au substrat de support afin de former un film III-V (6) sur le substrat de support, et à obtenir le substrat hétérogène III-V. Le procédé de préparation d'un substrat hétérogène III-V de grande taille résout les problèmes de difficulté de traitement élevée, de faible efficacité et de coûts importants dans la préparation de substrats hétérogènes III-V de grande taille.
PCT/CN2017/094041 2016-11-11 2017-07-24 Procédé de préparation d'un substrat hétérogène iii-v de grande taille WO2018086380A1 (fr)

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CN201611005213.9A CN106653583A (zh) 2016-11-11 2016-11-11 一种大尺寸iii‑v异质衬底的制备方法
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CN110838463A (zh) * 2018-08-17 2020-02-25 胡兵 一种半导体衬底、将衬底层与其上功能层分离的方法
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CN109427538B (zh) * 2017-08-24 2021-04-02 中国科学院上海微系统与信息技术研究所 一种异质结构的制备方法
CN109671618B (zh) * 2018-11-13 2020-10-02 中国科学院上海微系统与信息技术研究所 一种高平坦度异质集成薄膜结构的制备方法
CN111262127B (zh) * 2020-02-04 2022-06-10 中国科学院上海微系统与信息技术研究所 一种硅基InGaAs激光器衬底的制备方法、衬底和激光器
CN111799365B (zh) * 2020-06-29 2022-03-25 上海新硅聚合半导体有限公司 基于同一衬底制备不同厚度薄膜的方法及其结构、及应用器件
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