WO2018086380A1

WO2018086380A1 - Method for preparing large-sized iii-v heterogeneous substrate

Info

Publication number: WO2018086380A1
Application number: PCT/CN2017/094041
Authority: WO
Inventors: 欧欣; 龚谦; 游天桂; 黄凯; 林家杰; 张润春
Original assignee: 中国科学院上海微系统与信息技术研究所
Priority date: 2016-11-11
Filing date: 2017-07-24
Publication date: 2018-05-17
Also published as: CN106653583A

Abstract

A method for preparing a large-sized III-V heterogeneous substrate, comprising the following steps: S1: providing a III-V epitaxial structure (1) which comprises an injection surface (31); S2: performing ion implantation on the injection surface, and forming a defect layer (4) at a position of a preset depth on the III-V epitaxial structure; S3: providing a support substrate (5), and bonding the injection surface to the support substrate; and S4: peeling a part of the III-V epitaxial structure along the defect layer, so that a part of the III-V epitaxial structure is transferred to the support substrate to form an III-V film (6) on the support substrate, and the III-V heterogeneous substrate is obtained. The method for preparing a large-sized III-V heterogeneous substrate solves the problems of high process difficulty, low efficiency, and high costs in preparation of large-size III-V heterogeneous substrates.

Description

Method for preparing large-size III-V heterogeneous substrate

Technical field

The invention belongs to the technical field of semiconductor fabrication, and in particular relates to a preparation method of a large-sized III-V heterogeneous substrate by using an ion implantation stripping technique in combination with an epitaxial growth technique.

Background technique

Microelectronics based on silicon-based CMOS (Complementary Metal Oxide Semiconductor) integrated circuits has experienced rapid development for more than half a century along "Moore's Law." After entering the 14nm technology node, the development of microelectronics technology will no longer follow the law of scaling down, and turn to the post-Moore era integration with devices such as non-silicon based CMOS devices, non-digital functional devices, and non-CMOS operating mode devices. development of. The III-V semiconductor material has higher carrier mobility than the silicon material, and the III-V semiconductor material having a direct band gap exhibits excellent optical properties. Silicon-based III-V hetero-substrate materials have become an emerging research direction in the international semiconductor technology field. Developed an efficient process for preparing large-size silicon-based III-V hetero-substrate materials, which can not only prepare high-speed and low-power devices in CMOS circuits, but also overcome the size reduction limit faced by silicon-based CMOS technology, and integrate III -V semiconductor materials and silicon-based materials will provide material assurance for integration of optical components (such as lasers, photoemitters, and photodetectors) in silicon-based COMS circuits for chip system integration (SoC).

At present, there are mainly two ways to realize silicon-based III-V hetero-substrate materials: (1) epitaxial growth technology; (2) ion implantation-based thin film transfer technology (referred to as ion implantation stripping technology). Large-scale silicon-based III-V hetero-substrate materials can be prepared by epitaxial growth techniques. Common epitaxial growth methods include molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD). However, the heteroepitaxial III-V layer has problems such as reverse domain, lattice mismatch, and thermal expansion coefficient. The dislocation density is above 10 ⁶ cm ^-2 , and the high dislocation density will reduce the electron mobility and cause Poor device reliability, high power consumption and other issues. Further, epitaxially growing the III-V layer requires introduction of a buffer layer (generally Ge and a low-mass III-V layer having a thickness of 1 to 2 μm). Due to the light absorption of the buffer layer, its application to silicon photonic devices is limited, and the thick buffer layer also makes it impossible to implement fully depleted microelectronic devices. Ion implantation stripping technology can be used to directly strip the III-V film from the III-V wafer to prepare a silicon-based III-V hetero-substrate material, which can overcome the reverse domains, lattice mismatch and heat loss in epitaxial growth. Matching issues, and no buffer layer is required. However, III-V wafers are limited in size (up to 6 inches), making it impossible to prepare large-sized silicon-based III-V hetero-substrate; on the other hand, the ion implantation dose required to directly strip III-V wafers is very large, and III -V chips are expensive and costly. Therefore, there is an urgent need to develop a technique for efficiently preparing a large-sized high-quality silicon-based III-V hetero-substrate.

Summary of the invention

In view of the above disadvantages of the prior art, the object of the present invention is to provide a method for preparing a large-sized III-V hetero-substrate for solving the difficulty of preparing a large-sized III-V hetero-substrate in the prior art. Large, inefficient, and costly issues.

To achieve the above and other related objects, the present invention provides a method for preparing a large-sized III-V hetero-substrate, characterized in that the preparation method comprises the following steps: S1: providing a III-V epitaxial structure, The III-V epitaxial structure has an implantation surface; S2: performing ion implantation on the implantation surface, forming a defect layer at a predetermined depth of the III-V epitaxial structure; S3: providing a support substrate, and the implanted surface The support substrate is bonded; S4: peeling off a portion of the III-V epitaxial structure along the defect layer, transferring a portion of the III-V epitaxial structure onto the support substrate to be on the support liner A III-V film was formed on the bottom to obtain a III-V hetero substrate.

Preferably, in the step S1, the method for preparing the III-V epitaxial structure comprises the following steps: S1-1: providing an epitaxial substrate; S1-2: forming a buffer layer on the epitaxial substrate; S1-3: A III-V layer is formed on the buffer layer, and an upper surface of the III-V layer is an injection surface.

Preferably, in step S2, the preset depth is the III-V layer, the buffer layer or the interface of the III-V layer and the buffer layer.

Preferably, in step S1-1, the epitaxial substrate has a size of 50 mm to 500 mm.

Preferably, in step S1-1, the epitaxial substrate is a silicon substrate, a SiO ₂ /Si substrate or a Ge substrate; in step S3, the support substrate is a silicon substrate or a SiO ₂ /Si substrate. .

Preferably, between step S1-1 and step S1-2, the step of cleaning the epitaxial substrate is further included.

Preferably, in step S2, the ion implantation performed on the III-V epitaxial structure is a single ion implantation of H ions, a single ion implantation of He ions, or a common ion implantation of H ions and He ions.

Preferably, the ion implantation energy is 5 keV to 5000 keV, the ion implantation dose is 1 × 10 ¹⁶ ions/cm ² to 5 × 10 ¹⁷ ions/cm ² , and the ion implantation temperature is -50 ° C to 700 ° C.

Preferably, in step S4, the structure obtained in step S3 is annealed to peel off part of the III-V epitaxial structure along the defect layer, and a part of the III-V epitaxial structure is transferred onto the support substrate. To form a III-V film on the support substrate to obtain a III-V hetero substrate.

Preferably, the annealing treatment is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one of nitrogen, oxygen and an inert gas, the annealing temperature is 50 ° C to 1200 ° C, and the annealing time is 2 minutes to 24 hours.

Preferably, after step S3, before step S4, further comprising the step of performing a surface planarization process on the injection surface; and after step S4, further comprising the step of performing a surface planarization process on the III-V heterogeneous substrate.

As described above, the method for preparing a large-sized III-V hetero-substrate of the present invention has the following beneficial effects:

The invention utilizes ion implantation stripping technology combined with epitaxial growth technology to prepare large-sized III-V hetero-substrate, breaks through the limitation of the existing III-V wafer size, and successfully prepares a large-sized silicon-based III-V hetero-substrate and reduces The cost of preparation.

The present invention obtains a large-sized III-V epitaxial structure by epitaxial growth technique, and then peels off part of the III-V epitaxial structure, transferring a part of the III-V epitaxial structure onto the support substrate to be on the support A III-V film is formed on the substrate, and the III-V film is integrated with the supporting substrate by bonding, so that there is almost no requirement for lattice matching, and the selection of the III-V film and the supporting substrate material is more flexible. The crystal quality and properties of the obtained III-V film are comparable to those of the direct epitaxially grown III-V film.

Different from the conventional thin film material obtained by epitaxially growing a III-V film directly on a supporting substrate, the present invention adopts a bonding method to control the defect within a very small thickness range near the interface, and the internal lattice quality of the III-V film is not Affected, even if the thickness of the stripped III-V film is small, material properties can be guaranteed; and different types of III-V films and other semiconductor film materials can be simultaneously integrated on the same silicon-based substrate, and the properties of each film material It is not affected by the preparation process, which greatly improves the integration of the device and the flexibility of the design.

The depth of ion implantation in the present invention may be determined by ion implantation energy, and a defect layer may be formed at the interface of the III-V layer, the buffer layer or the III-V layer and the buffer layer, which can effectively reduce the peeling and transfer III The total ion implantation dose required for the -V film, which shortens the preparation cycle and saves production costs.

The common ion implantation used in the invention can effectively reduce the total ion implantation dose required for stripping and transferring the III-V film, thereby shortening the preparation cycle and saving the production cost; meanwhile, the method can also solve the use of some materials. Single ion implantation cannot achieve the problem of peeling.

DRAWINGS

1 is a flow chart showing a method of preparing a large-sized III-V hetero-substrate of the present invention.

2 to 15 are schematic views showing the structures corresponding to the steps of the preparation method of the large-size III-V hetero-substrate of the present invention.

Component label description

1 epitaxial substrate

2 buffer layer

3 III-V layer

31 injection surface

4 defect layer

5 support substrate

6 III-V film

detailed description

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 15. It should be noted that the illustrations provided in the embodiments merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, rather than the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

Referring to FIG. 1 , the present invention provides a method for preparing a large-sized III-V hetero-substrate using an ion implantation stripping technique in combination with an epitaxial growth technique, the preparation method comprising the following steps:

S1: providing a III-V epitaxial structure, the III-V epitaxial structure having an implantation surface;

S2: performing ion implantation on the implanted surface to form a defect layer at a predetermined depth of the III-V epitaxial structure;

S3: providing a supporting substrate, bonding the injection surface to the supporting substrate;

S4: stripping a portion of the III-V epitaxial structure along the defect layer, transferring a portion of the III-V epitaxial structure onto the support substrate to form a III-V film on the support substrate, A III-V heterogeneous substrate was obtained.

Specifically, as shown in FIG. 1 and FIG. 3, step S1: providing a III-V epitaxial structure having an implantation surface 31.

As shown in FIG. 2 to FIG. 3, specifically, the method for preparing the III-V epitaxial structure in step S1 includes the following steps:

As shown in FIG. 2, step S1-1: epitaxial substrate 1 is provided.

As an example, the epitaxial substrate 1 may be, but not limited to, a silicon substrate, a SiO ₂ /Si substrate, or a Ge substrate, the epitaxial substrate 1 having a size of 50 mm to 500 mm, for example, the epitaxial substrate The circular substrate has a diameter of 50 mm to 500 mm. For example, the epitaxial substrate has a rectangular shape and a length and a width of 50 mm to 500 mm, respectively. Of course, other shapes of the epitaxial substrate are also applicable, and are not limited to the examples listed herein. Example.

As shown in Figure 3, step S1-2: epitaxial growth on the epitaxial substrate 1 to form a buffer layer 2;

As shown in FIG. 3, step S1-3: epitaxial growth on the buffer layer 2 forms a high quality III-V layer 3, and the upper surface of the III-V layer 3 is an implantation surface 31.

As an example, the material of the buffer layer 2 may be, but not limited to, a crucible or a low temperature grown III-V material. The growth method of the buffer layer 2 may be, but not limited to, molecular beam epitaxy or organometallic vapor phase growth. The thickness of the buffer layer 2 may be, but not limited to, 10 nm to 50 μm.

As an example, the material of the III-V layer 3 may be, but not limited to, GaAs, InGaAs, or InP. The growth method of the III-V layer 3 may be, but not limited to, molecular beam epitaxy or organometallic vapor phase growth. The thickness of the III-V layer 3 may be, but not limited to, 10 nm to 50 μm.

Between step S1-1 and step S1-2 in this embodiment, the step of cleaning the epitaxial substrate 1 is further included.

As an example, after the epitaxial substrate 1 is provided, the epitaxial substrate 1 is cleaned. The method of cleaning the epitaxial substrate 1 may be a substrate cleaning method commonly used in the semiconductor field, which is not limited herein. The epitaxial substrate 1 is cleaned to remove impurities located on the surface of the epitaxial substrate 1 to improve the quality of the epitaxial growth of the III-V layer 3 on the epitaxial substrate 1.

In other embodiments, the epitaxial growth method on the epitaxial substrate and the buffer layer may also be a conventional material epitaxial growth method such as chemical vapor deposition, physical vapor deposition or magnetron sputtering.

As shown in FIG. 1 and FIG. 4 to FIG. 6 , step S2: performing ion implantation on the implantation surface 31 to form a defect layer 4 at a predetermined depth of the III-V epitaxial structure.

Specifically, the preset depth is set at the interface of the III-V layer 3, the buffer layer 2 or the III-V layer 3 and the buffer layer 2. That is, the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth of the III-V epitaxial structure and form the defect layer 4. The preset depth is set according to actual needs. The arrows shown in Figs. 4 to 6 perpendicular to the injection face 31 of the III-V layer 3 indicate the direction of ion implantation.

In an example, as shown in FIG. 4, the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth within the III-V layer 3, i.e., the defect layer 4 is formed within the III-V layer 3.

In another example, as shown in FIG. 5, the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth at the interface of the buffer layer 2 and the III-V layer 3, ie, at the buffer layers 2 and III- The defect layer 4 is formed at the interface of the V layer 3, that is, the defect layer 4 is simultaneously formed on the buffer layer 2 and the III-V layer 3.

In another example, as shown in FIG. 6, the energy of the ion implantation is sufficient to cause the implanted ions to reach any predetermined depth within the buffer layer 2, i.e., the defect layer 4 is formed within the buffer layer 2.

Specifically, the ion implantation performed on the III-V epitaxial structure on the implantation surface 31 is a single ion implantation of H ions, a single ion implantation of He ions, or a common ion implantation of H ions and He ions. The ion implantation energy is 5 keV to 5000 keV, the ion implantation dose is 1 × 10 ¹⁶ ions/cm ² to 5 × 10 ¹⁷ ions/cm ² , and the ion implantation temperature is -50 ° C to 700 ° C.

In an example, a single type of ion implantation is performed on the implanted surface 31, the implanted ions being H ions. The principle that the H ions can strip the III-V layer 3, the buffer layer 2, or the interface between the buffer layer 2 and the III-V layer 3 is to utilize the lattice of H ions at the peeling depth (ie, at the defect layer 4). It is achieved by the formation of a destructive effect.

Since the depth at which the defect layer 4 is formed is determined by the energy of ion implantation, and the defect density required for separation can be determined by the dose of ion implantation, a suitable ion implantation dose and ion are selected during ion implantation. Inject energy. In this example, the ion implantation energy of the H ion is 5 keV to 1000 keV, the ion implantation dose is 1×10 ¹⁶ ions/cm ² to 6×10 ¹⁷ ions/cm ² , and the ion implantation temperature is −50° C. 700 ° C.

In another example, a single type of ion implantation is also performed on the implanted surface 31, but in this example, the implanted ions are He ions. After the He ion is implanted into the III-V epitaxial structure, a defect is generated at the interface of the III-V layer 3, the buffer layer 2, or the buffer layer 2 and the III-V layer 3, and the He ions are accumulated in the defect and generate a pressure. The defect has a Gaussian distribution in the defect layer 4, and in the subsequent processing, part of the III-V epitaxial structure can be peeled off from the maximum defect concentration. In this example, the ion implantation energy of the He ion is 5 keV to 1000 keV, the ion implantation dose is 1×10 ¹⁶ ions/cm ² to 6×10 ¹⁷ ions/cm ² , and the ion implantation temperature is −50° C. 700 ° C.

In another example, co-injection of two types of ions is performed within the III-V semiconductor material 3, the implanted ions being H ions and He ions. Wherein the H ion is used to form a defect as described above, the defect having a Gaussian distribution in the defect layer 4; and He being an inert element, and the III-V layer 3, the buffer layer 2, or the buffer layer 2 There is no chemical action at the interface of III-V layer 3, but they can be trapped by the platform defects formed by H ions and physically expand and combine these platform-type defects to form a crack that can separate the III-V epitaxial structure. Promoting part of the III-V epitaxial structure to achieve peeling from the maximum defect concentration. Co-injection of H ions and He ions is performed on the injection surface 31, and He ions can be trapped by defects formed by H ions, and then enter the atomic gap and apply pressure, which is equivalent to applying an extra inside the defects generated by the H ions. The force can effectively promote the peeling of some of the III-V epitaxial structures at a low ion implantation dose, that is, the total dose of ion implantation can be effectively reduced, thereby shortening the preparation cycle and saving the production cost.

In this example, the manner in which the H ions and the He ions are co-implanted may be sequentially performed, or may be simultaneously performed, that is, the implantation of the H ions may be performed before the implantation of the He ions, also in the The implantation of He ions is followed by simultaneous injection with the He ions.

It should be noted that in order to make the implanted He ions easily trapped by the defects formed by H ions, the depth of He ion implantation needs to be the same or similar to the depth of H ion implantation, that is, the range (R _p ) of He ions needs to be ensured. The vicinity of the range of H ion implantation. In this example, the energy of co-injection of H ions and He ions is 5 keV to 1000 keV, and the total implantation dose of H ions and He ions is 1×10 ¹⁶ ions/cm ² to 6×10 ¹⁷ ions/cm ² , H ions and The temperature at which He ion is implanted is -50 ° C to 700 ° C.

As shown in FIGS. 1 and 7 to 9, step S3: providing a support substrate 5, and bonding the injection surface 31 to the support substrate 5.

As an example, the support substrate 5 is a silicon-based substrate, and may be, for example, a hetero-substrate such as silicon.

As an example, a III-V epitaxial structure in which the defect layer 4 is formed is bonded to the support substrate 5, and an implantation surface 31 of the III-V epitaxial structure is a bonding surface, that is, the III-V The injection face 31 of the epitaxial layer 3 is in close contact with the surface of the bonded substrate.

As an example, after performing step S3, a step of performing a surface planarization process on the bonding surface of the III-V epitaxial structure is further included to obtain a high quality bonding.

As an example, the structure obtained in step S2 may be bonded to the support substrate 5 by direct bonding, dielectric layer bonding, metal bonding or anodic bonding indirect bonding. The dielectric layer bonding process includes a growth dielectric layer bonding process, a polymer bonding process, a molten glass bonding process, and a spin-on glass bonding process.

As shown in FIG. 1 and FIGS. 10-15, step S4: stripping a portion of the III-V epitaxial structure along the defect layer 4, and transferring a portion of the III-V epitaxial structure onto the support substrate 5, A III-V thin film is formed on the support substrate 5 to obtain a III-V hetero substrate.

Specifically, as shown in FIGS. 10-15, the structure obtained in step S3 is annealed to peel off part of the III-V epitaxial structure from the epitaxial substrate 1 along the defect layer 4 to obtain a high quality III-V film 6. And transferring the obtained III-V film 6 onto a silicon-based substrate to obtain a silicon-based III-V heterogeneous integrated substrate. The defect layer 4 is at the interface of the III-V layer 3, the buffer layer 2 or the III-V layer 3 and the buffer layer 2. The annealing treatment is carried out under a vacuum atmosphere or under a protective atmosphere formed by at least one of nitrogen, oxygen and an inert gas, the annealing temperature is 50 ° C to 1200 ° C, and the annealing time is 2 minutes to 24 hours.

In an example, the III-V epitaxial structure in which the defect layer 4 is formed is annealed to achieve partial peeling of the III-V epitaxial structure along the defect layer 4. Specifically, the annealing process is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one gas of nitrogen and an inert gas, the annealing temperature is 150 ° C to 1200 ° C, and the annealing time is 5 minutes to 24 hours. During the annealing process from 150 °C to 1200 °C, the implanted ions (ie, H ions, He ions) will be thermally expanded, increasing the pressure applied to the atoms, thereby promoting the realization of part of the III-V epitaxial structure from the maximum defect concentration. Peeling to obtain the III-V film 6.

In another example, first, the III-V epitaxial structure formed with the defect layer 4 is annealed, and the annealing process is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one gas of nitrogen and an inert gas, and the annealing temperature is performed. The annealing time is from 5 minutes to 24 hours from 150 ° C to 1200 ° C. Secondly, after the annealing treatment, a transverse layer is applied to the defect layer 4 To the mechanical force, a part of the III-V epitaxial structure is peeled off along the defect layer 4 to obtain the III-V film 6. Since the defect density required for forming part of the III-V epitaxial structure to be separated is determined by the dose of ion implantation, if only part of the III-V epitaxial structure is separated from the defect layer 4 by annealing, It is necessary to inject a relatively large amount or a specific dose of ions into the injection surface 31; and apply a transverse mechanical force at the defect layer 4, even if the dose of ion implantation to the injection surface 31 is small or biased, separation cannot be formed. The required defect density, under the action of an external force, can also achieve partial separation of the III-V epitaxial structure from the defect layer 4, that is, applying a transverse mechanical force at the defect layer 4 can reduce the total ion implantation dose. The portion of the III-V epitaxial structure is stripped from the defect layer 4 to obtain the III-V film 6, thereby shortening the preparation cycle and saving production costs.

In another example, first, the III-V epitaxial structure in which the defect layer 4 is formed is annealed, and the annealing process is performed under a vacuum atmosphere or a protective atmosphere formed by at least one gas of nitrogen and an inert gas. The annealing temperature is from 150 ° C to 1200 ° C, and the annealing time is from 5 minutes to 24 hours. Secondly, after the annealing treatment, the annealing temperature is maintained, and the auxiliary material layer is deposited on the injection surface 31 of the III-V layer 3 and then rapidly cooled; The auxiliary material layer and the III-V layer 3 have different coefficients of thermal expansion.

Wherein, the auxiliary material may be any one different from the coefficient of thermal expansion of the III-V layer 3. Preferably, in the embodiment, the auxiliary material is a high polymer. Since the auxiliary material has a different thermal expansion coefficient from the III-V layer 3, especially when the thermal expansion coefficients of the two have a large difference, thermal stress is generated in the structure composed of the two in the process of rapid cooling. The thermal stress causes some of the III-V epitaxial structure to achieve peeling at the maximum concentration of the implant defect. The means of rapid cooling can be, but is not limited to, cooling with the furnace.

Since the defect density required for the formation of the III-V epitaxial structure is determined by the dose of ion implantation, if only part of the III-V epitaxial structure is separated from the defect layer 4 by annealing, it is required A specific dose of ions is implanted into the injection surface 31; and the auxiliary material layer is rapidly cooled after the deposition surface 31 is deposited, so that thermal stress is generated in the structure formed by the two, even if the dose of ion implantation is performed on the injection surface 31. It is relatively small, and the defect density required for separation cannot be formed. Under the action of the thermal stress, part of the III-V epitaxial structure can be separated from the defect layer 4, that is, deposition auxiliary on the injection surface 31. The material layer and rapid cooling can reduce the total ion implantation dose, and promote part of the III-V epitaxial structure to be peeled off from the defect layer 4 to obtain the III-V film 6, thereby shortening the preparation cycle and saving production cost. .

As an example, after performing step S4, further comprising the step of performing a surface planarization process on the III-V hetero-substrate to remove the buffer layer 2 remaining on the surface and/or the low-quality III-V layer damaged by the implanted ions 3, to obtain a high quality silicon-based III-V hetero substrate.

As an example, the method of the above planarization treatment may be, but not limited to, a chemical etching method or a chemical mechanical polishing method.

In summary, the present invention utilizes an ion implantation stripping technique in combination with an epitaxial growth technique to prepare a large-sized III-V hetero-substrate, breaks through the limitations of the existing III-V wafer size, and successfully prepares a large-sized silicon-based III-V. The substrate reduces the cost of preparation. The present invention obtains a large-sized III-V epitaxial structure by epitaxial growth technique, and then peels off part of the III-V epitaxial structure, transferring a part of the III-V epitaxial structure onto the support substrate to be on the support A III-V film is formed on the substrate, and the III-V film is integrated with the supporting substrate by bonding, so that there is almost no requirement for lattice matching, and the selection of the III-V film and the supporting substrate material is more flexible. The crystal quality and properties of the obtained III-V film are comparable to those of the direct epitaxially grown III-V film. Different from the conventional thin film material obtained by epitaxially growing a III-V film directly on a supporting substrate, the present invention adopts a bonding method to control the defect within a very small thickness range near the interface, and the internal lattice quality of the III-V film is not Affected, even if the thickness of the stripped III-V film is small, material properties can be guaranteed; and different types of III-V films and other semiconductor film materials can be simultaneously integrated on the same silicon-based substrate, and the properties of each film material It is not affected by the preparation process, which greatly improves the integration of the device and the flexibility of the design. The depth of ion implantation in the present invention may be determined by ion implantation energy, and a defect layer may be formed at the interface of the III-V layer, the buffer layer or the III-V layer and the buffer layer, which can effectively reduce the peeling and transfer III The total ion implantation dose required for the -V film, which shortens the preparation cycle and saves production costs. The common ion implantation used in the invention can effectively reduce the total ion implantation dose required for stripping and transferring the III-V film, thereby shortening the preparation cycle and saving the production cost; meanwhile, the method can also solve the use of some materials. Single ion implantation cannot achieve the problem of peeling.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims

A method for preparing a large-sized III-V heterogeneous substrate, characterized in that the method comprises the following steps:

S1: providing a III-V epitaxial structure, the III-V epitaxial structure having an implantation surface;

S2: performing ion implantation on the implanted surface to form a defect layer at a predetermined depth of the III-V epitaxial structure;

S3: providing a supporting substrate, bonding the injection surface to the supporting substrate;

S4: stripping a portion of the III-V epitaxial structure along the defect layer, transferring a portion of the III-V epitaxial structure onto the support substrate to form a III-V film on the support substrate, A III-V heterogeneous substrate was obtained.
The method for preparing a large-sized III-V hetero-substrate according to claim 1, wherein in the step S1, the method for preparing the III-V epitaxial structure comprises the following steps:

S1-1: providing an epitaxial substrate;

S1-2: forming a buffer layer on the epitaxial substrate;

S1-3: forming a III-V layer on the buffer layer, and an upper surface of the III-V layer is an injection surface.
The method for preparing a large-sized III-V hetero-substrate according to claim 1, wherein in the step S2, the predetermined depth is the III-V layer, the buffer layer or the III- At the interface of the V layer and the buffer layer.
The method for preparing a large-sized III-V hetero-substrate according to claim 2, wherein in step S1-1, the epitaxial substrate has a size of 50 mm to 500 mm.
The method for preparing a large-sized III-V hetero-substrate according to claim 2, wherein in the step S1-1, the epitaxial substrate is a silicon substrate, a SiO 2 /Si substrate or a Ge substrate. In step S3, the support substrate is a silicon substrate or a SiO 2 /Si substrate.
The method for preparing a large-sized III-V hetero-substrate according to claim 2, further comprising the step of cleaning the epitaxial substrate between step S1-1 and step S1-2.
The method for preparing a large-sized III-V hetero-substrate according to claim 1, wherein in the step S2, the ion implantation performed on the III-V epitaxial structure is a single ion implantation of H ions. , He ion single ion implantation, or H ion and He ion common ion implantation.
The method for preparing a large-sized III-V hetero-substrate according to claim 7, wherein the ion implantation energy is 5 keV to 5000 keV, and the ion implantation dose is 1 × 10 16 ions/cm 2 ～ 5 × 10 17 ions/cm 2 , the temperature of ion implantation is -50 ° C to 700 ° C.
The method for preparing a large-sized III-V hetero-substrate according to claim 1, wherein in step S4, the structure obtained in step S3 is annealed to peel the portion of the III-V along the defect layer. An epitaxial structure is formed by transferring a portion of the III-V epitaxial structure onto the support substrate to form a III-V film on the support substrate to obtain a III-V hetero-substrate.
The method for preparing a large-sized III-V heterogeneous substrate according to claim 9, wherein the annealing treatment is performed under a vacuum atmosphere or under a protective atmosphere formed by at least one of nitrogen, oxygen and an inert gas. The annealing temperature is 50 ° C to 1200 ° C, and the annealing time is 2 minutes to 24 hours.
The method for preparing a large-sized III-V hetero-substrate according to claim 1, wherein after step S3, before step S4, further comprising the step of surface flattening the implantation surface; after step S4 And a step of performing a surface planarization treatment on the III-V heterogeneous substrate.