CN112382559A - Heterogeneous thin film structure and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Abstract
The invention discloses a heterogeneous thin film structure and a preparation method thereof, wherein the method comprises the following steps: providing a III-V compound substrate, and depositing a protective layer on the injection surface of the III-V compound substrate; depositing an auxiliary stripping layer on the back surface of the III-V compound substrate, wherein the back surface is opposite to the injection surface, and the thermal expansion coefficient of the auxiliary stripping layer is smaller than that of the III-V compound substrate; performing ion implantation from the implantation surface to form a defect layer in the III-V group compound substrate; removing the protective layer on the injection surface; providing a silicon substrate, and bonding the silicon substrate and the injection surface of the III-V group compound substrate to obtain a bonding structure; heating and annealing the bonding structure, and stripping part of the bonding structure along the defect layer to obtain a heterostructure; and carrying out post-treatment on the heterostructure to obtain the heterostructure. The invention can solve the technical problem of poor quality of the transfer film caused by overlarge ion implantation dosage in the ion beam stripping technology in the prior art.
Description
Technical Field
The invention relates to the technical field of semiconductor substrate preparation, in particular to a heterogeneous thin film structure and a preparation method thereof.
Background
With the continuous emergence of new technologies such as artificial intelligence and 5G communication, the Moore's law is gradually ending, and the traditional chip preparation technology cannot meet the current requirements on high performance, low power consumption, multiplied calculation amount and the like. Therefore, the development of communication technology is no longer limited to the continuous reduction of device size, but the diversity of functions is achieved by a heterogeneous integration method.
The III-V group compound semiconductor mostly has advantages of high electron mobility, good frequency characteristics, and the like, and is widely applied to semiconductor devices such as MOSFET (metal-oxide semiconductor field effect transistor), HBT (heterojunction bipolar transistor), HEMT (high electron mobility transistor), and the like. In addition, compared with the indirect band gap of silicon, the III-V group compound semiconductor can be used as an effective on-chip light source due to the direct band gap, so that the III-V group compound semiconductor optical device and the silicon-based integrated circuit are integrated to replace a waveguide to couple an external light source, and the research on semiconductor optical devices such as a laser, a detector, an amplifier and the like is greatly promoted.
The methods currently used to realize the III-V/Si heterogeneous integration are mainly divided into two methods, namely a heteroepitaxy method and an ion beam stripping and transferring method. Although heteroepitaxy is the most cost effective method, heteroepitaxy of high quality III-V compound semiconductor films on silicon substrates still presents a great challenge due to the problems of large lattice mismatch, crystal mismatch, and difference in thermal expansion coefficient between the III-V compound semiconductor and the Si substrate. The ion beam stripping and transferring method is one relatively new single crystal film transferring technology, and includes implanting light ion in certain energy and dosage in certain depth inside the material to form ion-rich layer in certain thickness in the position far from the surface of the material, introducing great amount of defect into the ion-rich layer, and subsequent bonding, annealing stripping, surface treatment, quality recovery and other steps to obtain high quality single crystal film. The method can control the thickness of the film, and the film has higher uniformity, in addition, the peeled substrate can be repeatedly utilized after chemical mechanical polishing, and the cost is greatly saved.
However, when the ion beam stripping and transferring method is used to realize the III-V/Si heterogeneous integration, a certain amount of ions need to be implanted, which will damage the crystal lattice to a certain extent, and the larger the ion implantation amount is, the more serious the damage is, and it is difficult to recover, how to reduce the crystal lattice damage caused by the higher implantation amount when the ion beam stripping and transferring technology is used to realize the III-V/Si heterogeneous integration, which becomes a problem to be solved in the art.
Disclosure of Invention
The invention aims to provide a heterogeneous thin film structure and a preparation method thereof, wherein an auxiliary stripping layer is formed on one surface of a III-V group compound substrate opposite to an injection surface of the III-V group compound substrate, so that sufficient defect evolution driving force can be ensured while the ion injection dosage is reduced, the occurrence of stripping of the III-V group compound substrate thin film is promoted, and the technical problem of poor quality of a transferred thin film caused by overlarge ion injection dosage in the ion beam stripping technology in the prior art is solved.
The invention is realized by the following technical scheme:
in one aspect, the present invention provides a method for preparing a heterogeneous thin film structure, comprising:
providing a III-V compound substrate, and depositing a protective layer on the injection surface of the III-V compound substrate;
depositing an auxiliary release layer on a back surface of the III-V compound substrate, the back surface being opposite to the implantation surface, the auxiliary release layer having a coefficient of thermal expansion less than a coefficient of thermal expansion of the III-V compound substrate;
performing ion implantation from the implantation surface to form a defect layer inside the III-V compound substrate;
removing the protective layer on the injection surface;
providing a silicon substrate, and bonding the silicon substrate and the injection surface of the III-V group compound substrate to obtain a bonding structure;
heating and annealing the bonding structure, and peeling part of the bonding structure along the defect layer to obtain a heterostructure;
and carrying out post-treatment on the heterogeneous structure to obtain the heterogeneous thin film structure.
Further, in the step of providing a III-V compound substrate and depositing a protective layer on the injection surface of the III-V compound substrate, the deposition method is chemical vapor deposition or electron beam evaporation; the protective layer is any one of silicon oxide, silicon nitride and aluminum oxide.
Further, in the step of depositing an auxiliary peeling layer on the back surface of the III-V compound substrate, the auxiliary peeling layer has a composition of silicon oxide or metal.
Further, in the step of depositing an auxiliary peeling layer on the back surface of the III-V group compound substrate, the auxiliary peeling layer has a thickness of 50-500 um.
Further, the performing ion implantation from the implantation surface to form a defect layer inside the III-V compound substrate specifically includes:
the temperature of the ion implantation is room temperature; the ion implantation mode comprises any one of hydrogen ion implantation, helium ion implantation and hydrogen helium ion co-implantation; the energy of the ion implantation is 1-1000 KeV; the dosage of the ion implantation is 5 multiplied by 1015～1×1016cm-2。
Further, in the step of removing the protective layer on the implantation surface, the removing method includes any one of chemical etching, inductive coupling, plasma etching, and reactive ion etching.
Further, the providing a silicon substrate, and bonding the silicon substrate and the implantation surface of the III-V group compound substrate to obtain a bonded structure specifically includes: bonding the silicon substrate and the implantation surface of the III-V compound substrate at room temperature.
Further, in the step of heating and annealing the bonding structure, and peeling part of the bonding structure along the defect layer to obtain the heterostructure, the annealing temperature is 150-400 ℃, and the heating rate in the annealing process is 1-5 ℃/min.
Further, in the step of performing post-treatment on the heterostructure to obtain the heterogeneous thin film structure, the post-treatment process is post-annealing treatment or surface treatment.
In another aspect, the invention provides a heterogeneous thin film structure, which is prepared by the preparation method of the heterogeneous thin film structure.
The implementation of the technical scheme of the invention has the following beneficial effects:
the heterogeneous thin film structure and the preparation method thereof of the invention form an auxiliary stripping layer on one surface of a III-V group compound substrate opposite to an injection surface, in the formed bonding structure, since the thermal expansion coefficients of the auxiliary peeling layer and the silicon substrate are both smaller than that of the group III-V compound substrate, therefore, in the process of annealing the bonded structure, in-plane compressive stress is simultaneously introduced into the III-V compound substrate, the distribution of the pressure stress can be adjusted through the auxiliary stripping layer, the pressure stress of the stripping area is consistent with the stress introduced under the condition of larger implantation dosage, namely, the thermal stress of the auxiliary peeling layer is used to compensate the stress drop caused by the reduction of the implantation dosage, thereby realizing the same peeling effect as that under the condition of larger implantation dosage, thereby realizing the purpose of stripping and transferring the III-V compound substrate film under lower implantation dosage. Compared with the prior art, the heterogeneous thin film structure has the advantages of low damage and high quality.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart of a heterogeneous thin film structure and a method for fabricating the same according to an embodiment of the present invention;
FIG. 2 is a schematic view of a structure corresponding to FIG. 1;
FIG. 3 is a graph of thermal mismatch stress simulation results provided by an embodiment of the present invention;
wherein the reference numerals in the figures correspond to: a 1-III-V group compound substrate, a 2-protective layer, a 3-auxiliary stripping layer, a 4-defect layer, a 5-bonding structure, a 6-heterostructure and a 7-heterostructure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following examples. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," "third," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Examples
In the prior art, when the ion beam stripping and transferring method is adopted to realize the heterogeneous integration of the III-V group compound substrate/the silicon substrate, a certain amount of ions need to be implanted, so that crystal lattices are damaged to a certain extent, and the larger the ion implantation amount is, the more serious the damage is, namely, when the ion beam amount is too large, the poorer the quality of a transferred film is caused.
Therefore, the specification provides a technical scheme capable of realizing the stripping and transfer of the III-V compound substrate film under the condition of reducing the ion implantation dosage; specifically, the method comprises the following steps:
embodiments of the present invention provide a method for fabricating a heterogeneous thin film structure, such as the flow chart shown in fig. 1, and the present specification provides the method steps as described in the embodiments or the flow chart, but may include more or less steps based on conventional or non-inventive labor. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. As shown in fig. 1 and 2, the method may include:
s101, providing a III-V compound substrate 1, and depositing a protective layer 2 on the injection surface of the III-V compound substrate 1.
In a particular embodiment, the III-V compound substrate 1 may include a GaAs substrate, an InP substrate, a GaSb substrate, an InAs substrate, an InSb substrate, or the like.
In a specific embodiment, the deposition method may include chemical vapor deposition and physical vapor deposition, wherein the physical vapor deposition may include magnetron sputtering, electron beam evaporation, and the like.
In this embodiment, a protective layer 2 is deposited on the implantation surface of the III-V compound substrate for protecting the implantation surface during the subsequent ion implantation. In a specific embodiment, the protective layer 2 on the implantation surface may be any one of a silicon oxide protective layer, a silicon nitride protective layer, an aluminum oxide protective layer, and the like.
In a specific embodiment, when the protective layer 2 is removed at a later stage, it may be removed by etching. The thickness of the deposited protective layer 2 is less than 100nm to facilitate later removal.
S102, depositing an auxiliary stripping layer 3 on the back surface of the III-V compound substrate 1, wherein the back surface is opposite to the injection surface, and the thermal expansion coefficient of the auxiliary stripping layer 3 is smaller than that of the III-V compound substrate 1.
In ion beam stripping and transfer, the evolution of defects is a prerequisite for stripping to occur, and the driving force for defect evolution is the ion implantation induced stress. On the premise of ensuring that an amorphous layer is not formed, the larger the ion implantation dosage is, the larger the induced stress is, and the easier the film is to strip. Therefore, in order to reduce the ion implantation dose, it is necessary to ensure that the stress is not changed, so that the defect evolution is promoted and the film peeling occurs. Therefore, in the present embodiment, the auxiliary peeling layer 3 is introduced while the ion implantation dose is reduced, and the auxiliary peeling layer 3 is formed on the back surface of the III-V compound substrate 1, so that a sufficient defect evolution driving force can be ensured, which is advantageous for promoting the occurrence of film peeling.
In this embodiment, the auxiliary peeling layer 3 is introduced before ion implantation to prevent peeling of the film during deposition of the auxiliary peeling layer 3.
In a specific embodiment, the auxiliary peeling layer 3 has a composition of silicon oxide or metal, i.e., the auxiliary peeling layer 3 is a silicon oxide layer or a metal layer.
Further, the metal forming the auxiliary peeling layer 3 may include tungsten, molybdenum, or the like.
In a specific embodiment, the thickness of the auxiliary peeling layer 3 is 50 to 500um, and the thickness of the auxiliary peeling layer 3 is determined based on the magnitude of the compressive stress of the peeling region in accordance with the stress introduced by the larger ion implantation dose, so that the same peeling effect as in the case of the larger ion implantation dose can be achieved.
It is understood that in practical applications, one skilled in the art can select other suitable auxiliary peeling layers and auxiliary peeling layer thicknesses according to practical situations.
S103, ion implantation is carried out from the implantation surface, and the defect layer 4 is formed inside the III-V compound substrate 1.
In one embodiment, the ion implantation is performed at room temperature.
In one embodiment, the ion implantation is performed by any one of hydrogen ion implantation, helium ion implantation, and hydrogen-helium ion co-implantation.
In one embodiment, the energy for performing the ion implantation is 1 to 1000 KeV.
In one embodiment, the ion implantation is performed at a dose of 5 × 1015c～1×1016cm-2. Compared with the prior art, the method has the advantages that the auxiliary stripping layer is formed on the surface, opposite to the injection surface, of the III-V group compound substrate, the dosage of ion injection can be reduced by 60-70%, so that the crystal lattice damage caused by overlarge dosage of ion injection is reduced, and the quality of the III-V group compound substrate/silicon substrate heterogeneous film structure can be improved.
And S104, removing the protective layer 2 on the injection surface.
In one embodiment, the removal process may include chemical etching, inductive coupling, plasma etching, reactive ion etching, and the like.
And S105, providing a silicon substrate, and bonding the silicon substrate and the injection surface of the III-V group compound substrate 1 to obtain a bonding structure 5.
In a specific embodiment, bonding is performed at room temperature at the implantation surface of the silicon substrate and the III-V compound substrate 1 to yield the bonded structure 5.
And S106, carrying out heating annealing treatment on the bonding structure 5, and stripping part of the bonding structure 5 along the defect layer 4 to obtain the heterostructure 6.
In a specific embodiment, the annealing temperature is 150 to 400 ℃.
In a specific embodiment, in order to ensure that the stress is fully released, the temperature rise rate in the annealing process is 1-5 ℃/min.
In this embodiment, in the formed bonding structure, since the thermal expansion coefficients of the auxiliary peeling layer and the silicon substrate are both smaller than the thermal expansion coefficient of the III-V group compound substrate, in the annealing process of the bonding structure, an in-plane compressive stress is introduced into the III-V group compound substrate at the same time, and the distribution of the compressive stress can be adjusted by the auxiliary peeling layer, so that the magnitude of the compressive stress in the peeling region is consistent with the stress introduced under the condition of a large implantation dose, that is, the thermal stress of the auxiliary peeling layer is used to compensate for the stress reduction caused by the reduction of the implantation dose, and further, the same peeling effect as that under the condition of a large implantation dose can be achieved, thereby achieving the purpose of peeling and transferring the III-V group compound substrate film under the low ion implantation dose. Compared with the ion beam stripping and transferring method adopting larger ion implantation dosage in the prior art, the III-V group compound substrate/silicon substrate heterogeneous thin film structure prepared by the method in the embodiment has the advantages of low damage and high quality.
S107, post-processing is carried out on the heterostructure 6, and the heterogeneous thin film structure 7 is obtained.
In a specific embodiment, the post-treatment process of the thin-film heterostructure 6 includes at least one of a post-annealing treatment and a surface treatment.
In a specific embodiment, the post-annealing temperature of the post-annealing treatment is 300-600 ℃, the post-annealing time is 1-10 h, and the post-annealing atmosphere comprises any one of nitrogen, oxygen, vacuum and argon.
In a specific embodiment, the surface treatment is performed by at least one of chemical mechanical polishing, chemical etching, and low energy ion irradiation.
In the present embodiment, it is considered that in the process of peeling and transferring a substrate using an ion beam, the evolution of defects is a necessary condition for peeling to occur, and the driving force for the defect evolution is the stress introduced by ion implantation. On the premise of ensuring that an amorphous layer is not formed, the larger the ion implantation dosage is, the larger the induced stress is, and the easier the substrate film is stripped. Therefore, in order to reduce the ion implantation dose and reduce the damage to the crystal lattice, it is necessary to ensure that the stress level is not changed, so that the defect evolution is promoted and the film peeling occurs. Therefore, the method in the embodiment introduces the auxiliary stripping layer with a certain thickness while reducing the ion implantation dosage, so as to ensure enough defect evolution driving force and promote the occurrence of film stripping. After the ions with smaller dose are implanted and bonded, because the thermal expansion coefficients of the auxiliary stripping layer and the silicon substrate are both smaller than those of the III-V group compound substrate, in the annealing treatment process, in-plane pressure stress can be simultaneously introduced into the III-V group compound substrate, the distribution of the pressure stress is adjusted by controlling the thickness of the auxiliary layer, the pressure stress of a stripping region is ensured to be consistent with the attraction introduced by larger ion implantation dose, the thermal stress of the auxiliary stripping layer is used for making up the stress reduction caused by the reduction of the implantation dose, the stripping effect consistent with the larger ion implantation dose can be realized, and the purpose of stripping and transferring the III-V group compound substrate film under the lower ion implantation dose is achieved. Compared with the prior art, the heterogeneous thin film structure prepared by the method in the embodiment of the invention has the advantages of low damage and high quality.
To further illustrate the beneficial effects of the preparation method of the heterogeneous thin film structure in the embodiment of the present invention, taking the GaAs substrate as an example, before ion implantation of the 350um GaAs substrate, Wu and SiO are respectively used2Forming an auxiliary peeling layer, a Wu auxiliary peeling layer and SiO2The thickness of the auxiliary stripping layer is 100um, the 350um GaAs substrate is used as blank contrast, the bonding structures are respectively formed with the 500um Si substrate, and the thermal mismatch stress simulation analysis is carried out on the bonding structures, the result is shown in figure 3, the three bonding structures in the figure are respectively 500um Si +350um GaAs, 500um Si +350um GaAs +100um Wu, 500um Si +350um GaAs +100um SiO2(ii) a The horizontal axis represents the distance from the plane of the bonded structure to the bottom surface of the silicon substrate, the vertical axis represents the stress induced at the defect layer due to thermal stress at the time of ion implantation, and the dotted line in the figure represents the position where the defect layer is located. In a bonding structure 500um Si +350um GaAs without an auxiliary peeling layer under a heating condition of 150 c, stress induced by thermal stress at a defect layer by ion implantation is about 23MPa, in contrast, when there is a 100um Wu auxiliary peeling layer, thermal stress at the same defect layer increases to about 30MPa, and 100um Wu auxiliary peeling layer is replaced with 100umSiO of um2When the auxiliary stripping layer is used, the thermal stress at the same position is increased to 35MPa, which shows that the existence of the auxiliary stripping layer can effectively improve the stress at the stripping position, thereby realizing that the extremely large stress can still be generated under the condition of smaller dosage of ion implantation.
The embodiment of the invention also provides a heterogeneous thin film structure, which is prepared by adopting the preparation method of the heterogeneous thin film structure in the embodiment. Since the preparation method of the heterogeneous thin film structure has the above technical effects, the heterogeneous thin film structure in this embodiment should also have the same technical effects, and will not be described herein again.
The above embodiment of the invention has the following beneficial effects:
the heterogeneous thin film structure and the preparation method thereof in the embodiment of the invention form an auxiliary stripping layer on one surface of a III-V group compound substrate opposite to an injection surface, in the formed bonding structure, since the thermal expansion coefficients of the auxiliary peeling layer and the silicon substrate are both smaller than that of the group III-V compound substrate, therefore, in the process of annealing the bonded structure, in-plane compressive stress is simultaneously introduced into the III-V compound substrate, the distribution of the pressure stress can be adjusted through the auxiliary stripping layer, the pressure stress of the stripping area is consistent with the stress introduced under the condition of larger implantation dosage, namely, the thermal stress of the auxiliary peeling layer is used to compensate the stress drop caused by the reduction of the implantation dosage, thereby realizing the same peeling effect as that under the condition of larger implantation dosage, thereby realizing the purpose of stripping and transferring the III-V compound substrate film under lower implantation dosage. Compared with the prior art, the heterogeneous thin film structure in the embodiment of the invention has the advantages of low damage and high quality.
It should be noted that: the precedence order of the above embodiments of the present invention is only for description, and does not represent the merits of the embodiments. And specific embodiments of the present invention have been described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the above claims.
Claims (10)
1. A method of fabricating a heterogeneous thin film structure, comprising:
providing a III-V compound substrate, and depositing a protective layer on the injection surface of the III-V compound substrate;
depositing an auxiliary release layer on a back surface of the III-V compound substrate, the back surface being opposite to the implantation surface, the auxiliary release layer having a coefficient of thermal expansion less than a coefficient of thermal expansion of the III-V compound substrate;
performing ion implantation from the implantation surface to form a defect layer inside the III-V compound substrate;
removing the protective layer on the injection surface;
providing a silicon substrate, and bonding the silicon substrate and the injection surface of the III-V group compound substrate to obtain a bonding structure;
heating and annealing the bonding structure, and peeling part of the bonding structure along the defect layer to obtain a heterostructure;
and carrying out post-treatment on the heterogeneous structure to obtain the heterogeneous thin film structure.
2. The method of claim 1, wherein in the step of providing a III-V compound substrate and depositing a passivation layer on the implantation surface of the III-V compound substrate, the deposition method is chemical vapor deposition or electron beam evaporation; the protective layer is any one of silicon oxide, silicon nitride and aluminum oxide.
3. The method of claim 1, wherein in the step of depositing an auxiliary release layer on the backside of the III-V compound substrate, the auxiliary release layer comprises silicon oxide or a metal.
4. The method of claim 1, wherein in the step of depositing an auxiliary release layer on the backside of the III-V compound substrate, the auxiliary release layer has a thickness of 50-500 μm.
5. The method for preparing a heterogeneous thin film structure according to claim 1, wherein the ion implantation is performed from the implantation surface to form a defect layer inside the III-V compound substrate, and specifically comprises:
the temperature of the ion implantation is room temperature; the ion implantation mode comprises any one of hydrogen ion implantation, helium ion implantation and hydrogen helium ion co-implantation; the energy of the ion implantation is 1-1000 KeV; the dosage of the ion implantation is 5 multiplied by 1015～1×1016cm-2。
6. The method for preparing a hetero-thin film structure according to claim 1, wherein in the step of removing the protective layer on the implantation surface, the removing method comprises any one of chemical etching, inductive coupling, plasma etching and reactive ion etching.
7. The method according to claim 1, wherein the step of providing a silicon substrate and bonding the silicon substrate to the implantation surface of the III-V compound substrate to obtain a bonded structure comprises: bonding the silicon substrate and the implantation surface of the III-V compound substrate at room temperature.
8. The method for preparing a heterogeneous thin film structure according to claim 1, wherein in the step of heating and annealing the bonded structure and peeling part of the bonded structure along the defect layer to obtain the heterogeneous structure, the annealing temperature is 150-400 ℃, and the heating rate in the annealing process is 1-5 ℃/min.
9. The method of claim 1, wherein the post-treatment process is post-annealing or surface treatment in the step of post-treating the heterostructure to obtain a heterostructure.
10. A heterogeneous thin film structure prepared by the method of any one of claims 1 to 9.
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