WO2018045625A1 - 平面显示装置及其扫描驱动电路 - Google Patents

平面显示装置及其扫描驱动电路 Download PDF

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Publication number
WO2018045625A1
WO2018045625A1 PCT/CN2016/104629 CN2016104629W WO2018045625A1 WO 2018045625 A1 WO2018045625 A1 WO 2018045625A1 CN 2016104629 W CN2016104629 W CN 2016104629W WO 2018045625 A1 WO2018045625 A1 WO 2018045625A1
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Prior art keywords
controllable switch
control
scan
capacitor
signal
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Application number
PCT/CN2016/104629
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English (en)
French (fr)
Inventor
赵莽
Original Assignee
武汉华星光电技术有限公司
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Priority to PL16915559T priority Critical patent/PL3511925T3/pl
Priority to US15/316,155 priority patent/US10089916B2/en
Priority to EP16915559.5A priority patent/EP3511925B1/en
Priority to KR1020197010564A priority patent/KR102301545B1/ko
Priority to JP2019513963A priority patent/JP2019529993A/ja
Publication of WO2018045625A1 publication Critical patent/WO2018045625A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
    • H03K4/023—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform by repetitive charge or discharge of a capacitor, analogue generators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a flat display device and a scan driving circuit thereof.
  • a scan driving circuit is used, that is, a scan driving circuit is fabricated on an array substrate by using a conventional thin film transistor planar display array process to realize a driving method for progressive scanning.
  • each scan driving unit drives only one scan line, and each scan drive unit needs a complete circuit to generate a drive signal.
  • a plurality of scan lines are arranged in the flat display device, which will require design.
  • Many scanning drive units cannot be shared, which inevitably makes the circuit design complicated and takes up space, which is not conducive to the narrow frame design of the flat display device.
  • the technical problem to be solved by the present invention is to provide a flat display device and a scan driving circuit thereof to solve the above problems.
  • a technical solution adopted by the present invention is to provide a scan driving circuit including a plurality of cascaded scan driving units, each of which includes:
  • a forward/reverse scan circuit for receiving a first scan control signal, a second scan control signal, a drive signal, and a next-stage scan signal, and outputting a forward-reverse control signal for controlling the scan driving unit to perform positive Scanning or reverse scanning;
  • An output circuit connected to the forward and reverse scan circuit, for receiving the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, and receiving the forward and reverse control signals from the forward and reverse scan circuits, and outputting the first scan a signal, a second scan signal, and a third scan signal;
  • a pull-down circuit connected to the output circuit for pulling up or discharging the first node
  • the pull-down control circuit is connected to the pull-down circuit for receiving the first clock signal and the first reference voltage for controlling the first node to perform pull-down control on the first scan signal, the second scan signal, and the third scan signal.
  • the output circuit includes a first output circuit, a second output circuit, and a third output circuit.
  • the first output circuit outputs a first scan signal according to the forward and reverse control signals, the first clock signal, and the second clock signal.
  • the second output circuit And outputting a second scan signal according to the second clock signal, the third clock signal, and the first scan signal; the third output circuit outputs the third scan signal according to the third clock signal, the fourth clock signal, and the second scan signal.
  • the front and back scanning circuit includes a first controllable switch and a second controllable switch.
  • the control end of the first controllable switch receives the first scan control signal, and the first end of the first controllable switch receives the drive signal, the first The second end of the control switch and the second end of the second controllable switch are connected to the output circuit, and the control end of the second controllable switch receives the second scan control signal, and the first end of the second controllable switch receives the next scan signal .
  • the first output circuit includes a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a first capacitor, and the control end of the third controllable switch receives the first clock signal, and the third controllable switch One end is connected to the second end of the second controllable switch and the second end of the first controllable switch, and the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the fourth controllable switch is controlled Receiving a first reference voltage, the second end of the fourth controllable switch is connected to the first end of the first capacitor and the control end of the fifth controllable switch, and the first end of the fifth controllable switch receives the second clock signal, The second end of the five controllable switch is connected to the second end of the first capacitor, and outputs a first scan signal;
  • the second output circuit includes a sixth controllable switch, a seventh controllable switch, an eighth controllable switch, and a second capacitor, wherein the first end of the sixth controllable switch is connected to the second end of the first capacitor and the fifth controllable switch
  • the second end of the sixth controllable switch receives the second clock signal
  • the second end of the sixth controllable switch is connected to the first end of the seventh controllable switch
  • the control end of the seventh controllable switch receives the first a reference voltage
  • a second end of the seventh controllable switch is connected to the first end of the second capacitor and the control end of the eighth controllable switch
  • the first end of the eighth controllable switch receives the third clock signal
  • the eighth controllable switch The second end is connected to the second end of the second capacitor, and outputs a second scan signal
  • the third output circuit includes a ninth controllable switch, a tenth controllable switch, an eleventh controllable switch, and a third capacitor, wherein the first end of the ninth controllable switch is connected to the second end of the second capacitor, and the ninth controllable
  • the control end of the switch receives the third clock signal, the second end of the ninth controllable switch and the first end of the tenth controllable switch, the control end of the tenth controllable switch receives the first reference voltage, and the tenth controllable switch
  • the second end is connected to the first end of the third capacitor and the control end of the eleventh controllable switch, the first end of the eleventh controllable switch receives the fourth clock signal, and the second end of the eleventh controllable switch
  • the second end of the three capacitors is connected and outputs a third scan signal.
  • the pull-down circuit includes a twelfth controllable switch, a thirteenth controllable switch, a fourteenth controllable switch, a fifteenth controllable switch, a sixteen controllable switch, a seventeenth controllable switch, and a fourth capacitor
  • the control end of the twelfth controllable switch, the control end of the thirteenth controllable switch, the control end of the fourteenth controllable switch, the control end of the fifteenth controllable switch, and the control end of the sixteen controllable switch a control end of the seventeenth controllable switch, and a first end of the fourth capacitor connected to the pull-down control circuit, a second end of the twelfth controllable switch, a second end of the thirteenth controllable switch, and a fourteenth
  • the second end of the controllable switch, the second end of the fifteenth controllable switch, the second end of the sixteenth controllable switch, the second end of the seventeenth controllable switch, and the second end of the fourth capacitor receive
  • the pull-down control circuit comprises an eighteenth controllable switch, a nineteenth controllable switch, a twentieth controllable switch and a fifth capacitor, a control end of the eighteenth controllable switch and a control end of the nineteenth controllable switch Connecting the second end of the third controllable switch, the second end of the eighteenth controllable switch and the second end of the nineteenth controllable switch receive the second reference voltage, and the first end of the eighteenth controllable switch is connected a second end of the fifth capacitor and a control end of the twentieth controllable switch, the first end of the fifth capacitor receives the first clock signal, and the first end of the twentieth controllable switch receives the first reference voltage, and the twentieth The second end of the control switch and the first end of the nineteenth controllable switch are connected to the control end of the twelfth controllable switch.
  • the first reference voltage is a high level
  • the second reference voltage is a low level
  • the first to twentieth controllable switches are N-type thin film transistors, and the control ends, the first ends and the second ends of the first to twentieth controllable switches respectively correspond to gates and sources of the N-type thin film transistors and Drain.
  • the first to twentieth controllable switches are P-type thin film transistors, and the control ends, the first ends and the second ends of the first to twentieth controllable switches respectively correspond to gates and sources of the P-type thin film transistors and Drain.
  • a flat display device including a scan driving circuit including a plurality of cascaded scan driving units, each of which includes:
  • a forward/reverse scan circuit for receiving a first scan control signal, a second scan control signal, a drive signal, and a next-stage scan signal, and outputting a forward-reverse control signal for controlling the scan driving unit to perform positive Scanning or reverse scanning;
  • An output circuit connected to the forward and reverse scan circuit, for receiving the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, and receiving the forward and reverse control signals from the forward and reverse scan circuits, and outputting the first scan a signal, a second scan signal, and a third scan signal;
  • a pull-down circuit connected to the output circuit for pulling up or discharging the first node
  • the pull-down control circuit is connected to the pull-down circuit for receiving the first clock signal and the first reference voltage for controlling the first node to perform pull-down control on the first scan signal, the second scan signal, and the third scan signal.
  • the output circuit includes a first output circuit, a second output circuit, and a third output circuit.
  • the first output circuit outputs a first scan signal according to the forward and reverse control signals, the first clock signal, and the second clock signal.
  • the second output circuit And outputting a second scan signal according to the second clock signal, the third clock signal, and the first scan signal; the third output circuit outputs the third scan signal according to the third clock signal, the fourth clock signal, and the second scan signal.
  • the front and back scanning circuit includes a first controllable switch and a second controllable switch.
  • the control end of the first controllable switch receives the first scan control signal, and the first end of the first controllable switch receives the drive signal, the first The second end of the control switch and the second end of the second controllable switch are connected to the output circuit, and the control end of the second controllable switch receives the second scan control signal, and the first end of the second controllable switch receives the next scan signal .
  • the first output circuit includes a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a first capacitor, and the control end of the third controllable switch receives the first clock signal, and the third controllable switch One end is connected to the second end of the second controllable switch and the second end of the first controllable switch, and the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the fourth controllable switch is controlled Receiving a first reference voltage, the second end of the fourth controllable switch is connected to the first end of the first capacitor and the control end of the fifth controllable switch, and the first end of the fifth controllable switch receives the second clock signal, The second end of the five controllable switch is connected to the second end of the first capacitor, and outputs a first scan signal;
  • the second output circuit includes a sixth controllable switch, a seventh controllable switch, an eighth controllable switch, and a second capacitor, wherein the first end of the sixth controllable switch is connected to the second end of the first capacitor and the fifth controllable switch
  • the second end of the sixth controllable switch receives the second clock signal
  • the second end of the sixth controllable switch is connected to the first end of the seventh controllable switch
  • the control end of the seventh controllable switch receives the first a reference voltage
  • a second end of the seventh controllable switch is connected to the first end of the second capacitor and the control end of the eighth controllable switch
  • the first end of the eighth controllable switch receives the third clock signal
  • the eighth controllable switch The second end is connected to the second end of the second capacitor, and outputs a second scan signal
  • the third output circuit includes a ninth controllable switch, a tenth controllable switch, an eleventh controllable switch, and a third capacitor, wherein the first end of the ninth controllable switch is connected to the second end of the second capacitor, and the ninth controllable
  • the control end of the switch receives the third clock signal, the second end of the ninth controllable switch and the first end of the tenth controllable switch, the control end of the tenth controllable switch receives the first reference voltage, and the tenth controllable switch
  • the second end is connected to the first end of the third capacitor and the control end of the eleventh controllable switch, the first end of the eleventh controllable switch receives the fourth clock signal, and the second end of the eleventh controllable switch
  • the second end of the three capacitors is connected and outputs a third scan signal.
  • the pull-down circuit includes a twelfth controllable switch, a thirteenth controllable switch, a fourteenth controllable switch, a fifteenth controllable switch, a sixteen controllable switch, a seventeenth controllable switch, and a fourth capacitor
  • the control end of the twelfth controllable switch, the control end of the thirteenth controllable switch, the control end of the fourteenth controllable switch, the control end of the fifteenth controllable switch, and the control end of the sixteen controllable switch a control end of the seventeenth controllable switch, and a first end of the fourth capacitor connected to the pull-down control circuit, a second end of the twelfth controllable switch, a second end of the thirteenth controllable switch, and a fourteenth
  • the second end of the controllable switch, the second end of the fifteenth controllable switch, the second end of the sixteenth controllable switch, the second end of the seventeenth controllable switch, and the second end of the fourth capacitor receive
  • the pull-down control circuit comprises an eighteenth controllable switch, a nineteenth controllable switch, a twentieth controllable switch and a fifth capacitor, a control end of the eighteenth controllable switch and a control end of the nineteenth controllable switch Connecting the second end of the third controllable switch, the second end of the eighteenth controllable switch and the second end of the nineteenth controllable switch receive the second reference voltage, and the first end of the eighteenth controllable switch is connected a second end of the fifth capacitor and a control end of the twentieth controllable switch, the first end of the fifth capacitor receives the first clock signal, and the first end of the twentieth controllable switch receives the first reference voltage, and the twentieth The second end of the control switch and the first end of the nineteenth controllable switch are connected to the control end of the twelfth controllable switch.
  • the first reference voltage is a high level
  • the second reference voltage is a low level
  • the first to twentieth controllable switches are N-type thin film transistors, and the control ends, the first ends and the second ends of the first to twentieth controllable switches respectively correspond to gates and sources of the N-type thin film transistors and Drain.
  • the first to twentieth controllable switches are P-type thin film transistors, and the control ends, the first ends and the second ends of the first to twentieth controllable switches respectively correspond to gates and sources of the P-type thin film transistors and Drain.
  • the scan driving unit of the present invention comprises a forward and reverse scanning circuit, an output circuit, a pull-down circuit and a pull-down control circuit, and the forward and reverse scanning circuit is used to control the scan driving unit to perform the forward direction.
  • the output circuit outputs a first scan signal, a second scan signal, and a third scan signal;
  • the present invention outputs the first scan signal, the second scan signal, and the common forward/reverse scan circuit, the pull-down circuit, and the pull-down control circuit.
  • the third scan signal reduces the number of thin film transistors of the scan driving circuit, saves space, and thus facilitates narrow frame design.
  • FIG. 1 is a schematic structural view of a scan driving circuit according to a first embodiment of the present invention
  • Figure 2 is a circuit diagram of the scan driving unit of Figure 1;
  • FIG. 3 is a timing chart of forward scanning of the scan driving circuit of FIG. 1;
  • FIG. 4 is a timing chart of reverse scanning of the scan driving circuit of FIG. 1;
  • Figure 5 is an analog timing diagram of the scan driving circuit of Figure 1;
  • Figure 6 is a circuit diagram of a scan driving unit of a second embodiment of the present invention.
  • Fig. 7 is a schematic structural view of a flat display device according to a first embodiment of the present invention.
  • FIG. 1-2 is a schematic structural view of a scan driving circuit according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram of the scan driving unit of FIG.
  • the scan driving circuit 10 disclosed in this embodiment includes a plurality of cascaded scan driving units 11, wherein each scan driving unit 11 outputs three scan signals, for example, the first scan driving unit 11 outputs a scan signal.
  • Gate1, Gate2, and Gate3 Each of the scan driving units 11 is connected to the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4.
  • each scan driving unit 11 includes a forward/reverse scan circuit 12, an output circuit 13, a pull-down circuit 14, and a pull-down control circuit 15.
  • the forward/reverse scan circuit 11 is configured to receive the first scan control signal U2D (Up to Dowm), second scan control signal D2U (Down to Up), the drive signal STV, and the next-stage scan signal Gaten+6.
  • the forward/reverse scan circuit 11 outputs a forward/reverse control signal CLn according to the first scan control signal U2D, the second scan control signal D2U, the drive signal STV, and the next-stage scan signal Gaten+6, and the forward-backward control signal CLn is used to control the scan.
  • the drive unit 11 performs a forward scan or a reverse scan.
  • the output circuit 13 is connected to the forward and reverse scan circuit 12, and the output circuit 13 is configured to receive the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, and receive positive and negative signals from the forward/reverse scan circuit 12.
  • the control signal CLn The control signal CLn.
  • the output circuit 13 outputs a first scan signal Gaten, a second scan signal Gaten+1 and a third scan signal Gaten+3;
  • the pull-down circuit 14 is connected to the output circuit 13, and the pull-down circuit 14 is used for pull-up or pull-down discharge of the first node Pn.
  • the pull-down control circuit 15 is connected to the pull-down circuit 14 for receiving the first clock signal CK1 and the first reference voltage V1, and the pull-down control circuit 15 is configured to control the first according to the first clock signal CK1 and the first reference voltage V1.
  • the node Pn performs pull-down control on the first scan signal Gaten, the second scan signal Gaten+1, and the third scan signal Gaten+3.
  • the output circuit 13 includes a first output circuit 131, a second output circuit 132, and a third output circuit 133.
  • the first output circuit 131 outputs a first scan according to the forward and reverse control signal CL1, the first clock signal CK1, and the second clock signal CK2.
  • the second output circuit 132 outputs a second scan signal Gate2 according to the second clock signal CK2, the third clock signal CK3, and the first scan signal Gate1;
  • the third output circuit 133 is based on the third clock signal CK3, the fourth clock signal, and
  • the second scan signal Gate2 outputs a third scan signal Gate3.
  • the front and back scanning circuit 12 includes a first controllable switch T1 and a second controllable switch T2.
  • the control end of the first controllable switch T1 receives the first scan control signal U2D, and the first end of the first controllable switch T1 receives the drive signal.
  • the second end of the first controllable switch T1 and the second end of the second controllable switch T2 are connected to the output circuit 13, and the control end of the second controllable switch T2 receives the second scan control signal D2T, the second controllable switch The first end of T2 receives the next level scan signal Gate6.
  • the first output circuit 131 includes a third controllable switch T3, a fourth controllable switch T4, a fifth controllable switch T5, and a first capacitor C1.
  • the control end of the third controllable switch T3 receives the first clock signal CK1, and the third
  • the first end of the controllable switch T3 is connected to the second end of the second controllable switch T2 and the second end of the first controllable switch T1, and the second end of the third controllable switch T3 is connected to the fourth controllable switch T4
  • One end, the control end of the fourth controllable switch T4 receives the first reference voltage V1
  • the second end of the fourth controllable switch T4 is connected to the first end of the first capacitor C1 and the control end of the fifth controllable switch T5,
  • the first end of the five controllable switch T5 receives the second clock signal CK2, and the second end of the fifth controllable switch T5 is connected to the second end of the first capacitor C1, and outputs the first scan signal Gate1.
  • connection between the second end of the third controllable switch T3 and the first end of the fourth controllable switch T4 is the second node H1, the first end of the first capacitor C1 and the control end of the fifth controllable switch T5
  • the connection is the third node Q1.
  • the second output circuit 132 includes a sixth controllable switch T6, a seventh controllable switch T7, an eighth controllable switch T8, and a second capacitor C2.
  • the first end of the sixth controllable switch T6 is connected to the second capacitor C1.
  • the second end of the sixth controllable switch T6 receives the second clock signal CK2, and the second end of the sixth controllable switch T6 is connected to the first end of the seventh controllable switch T7.
  • the control end of the seventh controllable switch T7 receives the first reference voltage V1, and the second end of the seventh controllable switch T7 is connected to the first end of the second capacitor C2 and the control end of the eighth controllable switch T8, and the eighth The first end of the control switch T8 receives the third clock signal CK3, the second end of the eighth controllable switch T8 is connected to the second end of the second capacitor C2, and the second scan signal Gate2 is output.
  • the junction of the first end of the second capacitor C2 and the control end of the eighth controllable switch T8 is the fourth node Q2.
  • the third output circuit 133 includes a ninth controllable switch T9, a tenth controllable switch T10, an eleventh controllable switch T11, and a third capacitor C3.
  • the first end of the ninth controllable switch T9 is connected to the second capacitor C2.
  • the second end, the control end of the ninth controllable switch T9 receives the third clock signal CK3, the second end of the ninth controllable switch T9 and the first end of the tenth controllable switch T10, and the control end of the tenth controllable switch T10
  • Receiving the first reference voltage V1 the second end of the tenth controllable switch T10 is connected to the first end of the third capacitor C3 and the control end of the eleventh controllable switch T11, and the first end of the eleventh controllable switch T11 is received
  • the fourth clock signal, the second end of the eleventh controllable switch T11 is connected to the second end of the third capacitor C3, and outputs a third scan signal Gate3.
  • the junction of the first end of the third capacitor C3 and the control end of the eleventh controllable switch T11 is the fifth node Q3.
  • the pull-down circuit includes a twelfth controllable switch T12, a thirteenth controllable switch T13, a fourteen controllable switch T14, a fifteenth controllable switch T15, a sixteen controllable switch T16, and a seventeen controllable switch T17 And a fourth capacitor C4, a control end of the twelfth controllable switch T12, a control end of the thirteenth controllable switch T13, a control end of the fourteen controllable switch T14, a control end of the fifteenth controllable switch T15,
  • the control end of the sixteen controllable switch T16, the control end of the seventeenth controllable switch T17, and the first end of the fourth capacitor C4 are connected to the pull-down control circuit, and the second end of the twelfth controllable switch T12 a second end of the thirteen controllable switch T13, a second end of the fourteenth controllable switch T14, a second end of the fifteenth controllable switch T15, a second
  • the first end of the seventeenth controllable switch T17 is connected to the second end of the third capacitor C3.
  • the connection between the control end of the twelfth controllable switch T12, the control end of the thirteenth controllable switch T13, and the first end of the fourth capacitor C4 is the first node P1.
  • the pull-down control circuit includes an eighteen controllable switch T18, a nineteenth controllable switch T19, a twentieth controllable switch T20 and a fifth capacitor C5, a control end of the eighteenth controllable switch T18 and a nineteenth controllable switch
  • the control end of the T19 is connected to the second end of the third controllable switch T3, the second end of the eighteenth controllable switch T18 and the second end of the nineteenth controllable switch T19 receive the second reference voltage V2, the eighteenth
  • the first end of the control switch T18 is connected to the second end of the fifth capacitor C5 and the control end of the twentieth controllable switch T20.
  • the first end of the fifth capacitor C5 receives the first clock signal CK1, and the twentieth controllable switch T20
  • the first end receives the first reference voltage V1
  • the second end of the twentieth controllable switch T20 and the first end of the nineteenth controllable switch T19 are connected to the control end of the twelfth controllable switch T12.
  • the junction of the first end of the eighteenth controllable switch T18, the second end of the fifth capacitor C5, and the control end of the twentieth controllable switch T20 is a sixth node M1.
  • the first reference voltage V1 is at a high level
  • the second reference voltage V2 is at a low level.
  • the first controllable switch T1 to the twentieth controllable switch T20 are N-type thin film transistors, and the control end, the first end and the second end of the first controllable switch T1 to the twentieth controllable switch T20 respectively correspond to The gate, source and drain of the N-type thin film transistor.
  • the first scan control signal U2D is at a high level
  • the second scan control signal D2U is at a low level
  • the first controllable switch T1 is turned on
  • the second controllable switch T2 is turned off.
  • the second node H1 and the third node Q1 are charged high to the high level, and the fifth controllable switch T5 at this time
  • the nineteenth controllable switch T19 and the eighteenth controllable switch T18 are turned on, the sixth node M1 and the first node P1 are discharged to a low level, the twentieth controllable switch T20, the twelfth controllable
  • the switch T12, the thirteenth controllable switch T13, the fourteenth controllable switch T14, the fifteenth controllable switch T15, the sixteenth controllable switch T16, and the seventeenth controllable switch T17 are disconnected.
  • the first scan signal Gate1 is a high-level pulse signal, that is, the first-stage gate drive signal is generated.
  • the sixth controllable switch T6 is turned on, the fourth node Q2 is charged to a high level, and the eighth controllable switch T8 is turned on.
  • the second scan signal Gate2 is a high-level pulse signal, that is, a second-stage gate drive signal is generated.
  • the ninth controllable switch T9 is turned on, the fifth node Q3 is charged to a high level, and the eleventh controllable switch T11 is turned on.
  • the third scan signal Gate3 is a high-level pulse signal, that is, a third-stage gate drive signal is generated.
  • the second node H1 and the third node Q1 are discharged to a low level, and the eighteen controllable switch T18 and the nineteenth controllable switch T19 are disconnected.
  • the sixth node M1 is in a floating state, the high-level pulse signal of the first clock signal CK1 causes the sixth node M1 to be bootstrapped to a high level, and the twentieth controllable switch T20 is turned on, first Node P1 is pulled up to a high level, a twelfth controllable switch T12, a thirteenth controllable switch T13, a fourteen controllable switch T14, a fifteenth controllable switch T15, a sixteen controllable switch T16, and The seventeenth controllable switch T17 is turned on, and the third node Q1, the fourth node Q2, the fifth node Q3, the first scan signal Gate1, the second scan signal Gate2, and the third scan signal Gate3 are stably outputted to a low
  • the working principle of the reverse scan of the scan driving unit 11 disclosed in this embodiment is similar to the working principle of the forward scan of the scan driving unit 11, and details are not described herein again.
  • the function of the scan driving circuit 10 of the present invention is consistent with the description and can be performed well between stages.
  • the first scan signal Gaten, the second scan signal Gaten+1, and the third scan signal Gaten+3 are outputted by the common forward/reverse scan circuit 12, the pull-down circuit 14, and the pull-down control circuit 15, thereby reducing the thin film transistor of the scan driving circuit 10.
  • the number of spaces saves space and thus contributes to the narrow bezel design.
  • the present invention further provides a scan driving unit of the second embodiment, which is different from the scan driving unit 10 disclosed in the first embodiment in that the first to twentieth controllable switches are P-type films.
  • the control terminals, the first end and the second end of the first to twentieth controllable switches respectively correspond to a gate, a source and a drain of the P-type thin film transistor.
  • the first through twentieth controllable switches can also be other types of switches as long as the objectives of the present invention are achieved.
  • the present invention also provides a flat display device of the first embodiment.
  • the flat display device includes the aforementioned scan driving circuit, and the scan driving circuit is disposed on both sides of the flat display device.
  • Other devices and functions in the flat display device are the same as those of the existing flat display device, and are not described herein again.
  • the flat display device is an LCD or an OLED.
  • the scan driving unit of the present invention comprises a forward and reverse scan circuit, an output circuit, a pull-down circuit and a pull-down control circuit, and the forward and reverse scan circuit is configured to control the scan drive unit to perform forward scan or reverse scan, and output circuit output a scan signal, a second scan signal, and a third scan signal; the present invention reduces the scan drive circuit by sharing the first scan signal, the pull-down circuit, and the pull-down control circuit to output the first scan signal, the second scan signal, and the third scan signal.
  • the number of thin film transistors saves space and thus facilitates narrow bezel design.

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Abstract

一种平面显示装置及其扫描驱动电路(10)。扫描驱动电路(10)包括级联的多个扫描驱动单元(11)，每一扫描驱动单元(11)包括正反扫描电路(12)、输出电路(13)、下拉电路(14)以及下拉控制电路(15)，正反扫描电路(12)用于控制扫描驱动单元(11)进行正向扫描或者反向扫描，输出电路(13)输出第一扫描信号(Gaten)、第二扫描信号(Gaten+1)以及第三扫描信号(Gaten+3)；通过共用正反扫描电路(12)、下拉电路(14)以及下拉控制电路(15)输出第一扫描信号(Gaten)、第二扫描信号(Gaten+1)以及第三扫描信号(Gaten+3)，减少扫描驱动电路(10)的薄膜晶体管的数目，节省空间，进而利于窄边框设计。

Description

平面显示装置及其扫描驱动电路
【技术领域】
本发明涉及显示技术领域，特别是涉及一种平面显示装置及其扫描驱动电路。
【背景技术】
目前的平面显示装置中采用扫描驱动电路，也就是利用现有薄膜晶体管平面显示器阵列制程将扫描驱动电路制作在阵列基板上，实现对逐行扫描的驱动方式。
现有的平面显示装置中每一扫描驱动单元仅驱动一条扫描线，而每一扫描驱动单元均需要完整的电路来实现产生驱动信号，一般平面显示装置中设置诸多条扫描线，这将需要设计诸多扫描驱动单元，无法实现共用，势必使得电路设计复杂，且占用空间，不利于平面显示装置的窄边框设计。
【发明内容】
本发明主要解决的技术问题是提供一种平面显示装置及其扫描驱动电路，以解决上述问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，其包括级联的多个扫描驱动单元，每一扫描驱动单元包括：
正反扫描电路，用于接收第一扫描控制信号、第二扫描控制信号、驱动信号以及下一级扫描信号，并且输出正反向控制信号，正反向控制信号用于控制扫描驱动单元进行正向扫描或者反向扫描；
输出电路，与正反扫描电路连接，用于接收第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和从正反扫描电路接收正反向控制信号，并且输出第一扫描信号、第二扫描信号以及第三扫描信号；
下拉电路，与输出电路连接，用于对第一节点进行上拉充电或者下拉放电；
下拉控制电路，与下拉电路连接，用于接收第一时钟信号和第一参考电压，用于控制第一节点，以对第一扫描信号、第二扫描信号以及第三扫描信号进行下拉控制。
其中，输出电路包括第一输出电路、第二输出电路以及第三输出电路，第一输出电路根据正反向控制信号、第一时钟信号以及第二时钟信号输出第一扫描信号；第二输出电路根据第二时钟信号、第三时钟信号以及第一扫描信号输出第二扫描信号；第三输出电路根据第三时钟信号、第四时钟信号以及第二扫描信号输出第三扫描信号。
其中，正反扫描电路包括第一可控开关以及第二可控开关，第一可控开关的控制端接收第一扫描控制信号，第一可控开关的第一端接收驱动信号，第一可控开关的第二端和第二可控开关的第二端连接输出电路，第二可控开关的控制端接收第二扫描控制信号，第二可控开关的第一端接收下一级扫描信号。
其中，第一输出电路包括第三可控开关、第四可控开关、第五可控开关以及第一电容，第三可控开关的控制端接收第一时钟信号，第三可控开关的第一端连接第二可控开关的第二端和第一可控开关的第二端，第三可控开关的第二端连接第四可控开关的第一端，第四可控开关的控制端接收第一参考电压，第四可控开关的第二端连接第一电容的第一端和第五可控开关的控制端，第五可控开关的第一端接收第二时钟信号，第五可控开关的第二端与第一电容的第二端连接，并且输出第一扫描信号；
第二输出电路包括第六可控开关、第七可控开关、第八可控开关以及第二电容，第六可控开关的第一端连接第一电容的第二端和第五可控开关的第二端，第六可控开关的控制端接收第二时钟信号，第六可控开关的第二端连接第七可控开关的第一端，第七可控开关的控制端接收第一参考电压，第七可控开关的第二端连接第二电容的第一端和第八可控开关的控制端，第八可控开关的第一端接收第三时钟信号，第八可控开关的第二端连接第二电容的第二端，并且输出第二扫描信号；
第三输出电路包括第九可控开关、第十可控开关、第十一可控开关以及第三电容，第九可控开关的第一端连接第二电容的第二端，第九可控开关的控制端接收第三时钟信号，第九可控开关的第二端与第十可控开关的第一端，第十可控开关的控制端接收第一参考电压，第十可控开关的第二端连接第三电容的第一端和第十一可控开关的控制端，第十一可控开关的第一端接收第四时钟信号，第十一可控开关的第二端与第三电容的第二端连接，并且输出第三扫描信号。
其中，下拉电路包括第十二可控开关、第十三可控开关、第十四可控开关、第十五可控开关、第十六可控开关、第十七可控开关以及第四电容，第十二可控开关的控制端、第十三可控开关的控制端、第十四可控开关的控制端、第十五可控开关的控制端、第十六可控开关的控制端、第十七可控开关的控制端、以及第四电容的第一端与下拉控制电路连接，第十二可控开关的第二端、第十三可控开关的第二端、第十四可控开关的第二端、第十五可控开关的第二端、第十六可控开关的第二端、第十七可控开关的第二端、以及第四电容的第二端接收第二参考电压，第十二可控开关的第一端连接第三可控开关的第二端，第十三可控开关的第一端连接第一电容的第二端，第十四可控开关的第一端连接第六可控开关的第二端，第十五可控开关的第一端连接第二电容的第二端，第十六可控开关的第一端连接第九可控开关的第二端，第十七可控开关的第一端连接第三电容的第二端。
其中，下拉控制电路包括第十八可控开关、第十九可控开关、第二十可控开关以及第五电容，第十八可控开关的控制端和第十九可控开关的控制端连接第三可控开关的第二端，第十八可控开关的第二端和第十九可控开关的第二端接收第二参考电压，第十八可控开关的第一端连接第五电容的第二端和第二十可控开关的控制端，第五电容的第一端接收第一时钟信号，第二十可控开关的第一端接收第一参考电压，第二十可控开关的第二端和第十九可控开关的第一端连接第十二可控开关的控制端。
其中，第一参考电压为高电平，第二参考电压为低电平。
其中，第一至第二十可控开关为N型薄膜晶体管，第一至第二十可控开关的控制端、第一端及第二端分别对应N型薄膜晶体管的栅极、源极及漏极。
其中，第一至第二十可控开关为P型薄膜晶体管，第一至第二十可控开关的控制端、第一端及第二端分别对应P型薄膜晶体管的栅极、源极及漏极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种平面显示装置，平面显示装置包括扫描驱动电路，其包括级联的多个扫描驱动单元，每一扫描驱动单元包括：
正反扫描电路，用于接收第一扫描控制信号、第二扫描控制信号、驱动信号以及下一级扫描信号，并且输出正反向控制信号，正反向控制信号用于控制扫描驱动单元进行正向扫描或者反向扫描；
输出电路，与正反扫描电路连接，用于接收第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和从正反扫描电路接收正反向控制信号，并且输出第一扫描信号、第二扫描信号以及第三扫描信号；
下拉电路，与输出电路连接，用于对第一节点进行上拉充电或者下拉放电；
下拉控制电路，与下拉电路连接，用于接收第一时钟信号和第一参考电压，用于控制第一节点，以对第一扫描信号、第二扫描信号以及第三扫描信号进行下拉控制。
其中，输出电路包括第一输出电路、第二输出电路以及第三输出电路，第一输出电路根据正反向控制信号、第一时钟信号以及第二时钟信号输出第一扫描信号；第二输出电路根据第二时钟信号、第三时钟信号以及第一扫描信号输出第二扫描信号；第三输出电路根据第三时钟信号、第四时钟信号以及第二扫描信号输出第三扫描信号。
其中，正反扫描电路包括第一可控开关以及第二可控开关，第一可控开关的控制端接收第一扫描控制信号，第一可控开关的第一端接收驱动信号，第一可控开关的第二端和第二可控开关的第二端连接输出电路，第二可控开关的控制端接收第二扫描控制信号，第二可控开关的第一端接收下一级扫描信号。
其中，第一输出电路包括第三可控开关、第四可控开关、第五可控开关以及第一电容，第三可控开关的控制端接收第一时钟信号，第三可控开关的第一端连接第二可控开关的第二端和第一可控开关的第二端，第三可控开关的第二端连接第四可控开关的第一端，第四可控开关的控制端接收第一参考电压，第四可控开关的第二端连接第一电容的第一端和第五可控开关的控制端，第五可控开关的第一端接收第二时钟信号，第五可控开关的第二端与第一电容的第二端连接，并且输出第一扫描信号；
第二输出电路包括第六可控开关、第七可控开关、第八可控开关以及第二电容，第六可控开关的第一端连接第一电容的第二端和第五可控开关的第二端，第六可控开关的控制端接收第二时钟信号，第六可控开关的第二端连接第七可控开关的第一端，第七可控开关的控制端接收第一参考电压，第七可控开关的第二端连接第二电容的第一端和第八可控开关的控制端，第八可控开关的第一端接收第三时钟信号，第八可控开关的第二端连接第二电容的第二端，并且输出第二扫描信号；
第三输出电路包括第九可控开关、第十可控开关、第十一可控开关以及第三电容，第九可控开关的第一端连接第二电容的第二端，第九可控开关的控制端接收第三时钟信号，第九可控开关的第二端与第十可控开关的第一端，第十可控开关的控制端接收第一参考电压，第十可控开关的第二端连接第三电容的第一端和第十一可控开关的控制端，第十一可控开关的第一端接收第四时钟信号，第十一可控开关的第二端与第三电容的第二端连接，并且输出第三扫描信号。
其中，下拉电路包括第十二可控开关、第十三可控开关、第十四可控开关、第十五可控开关、第十六可控开关、第十七可控开关以及第四电容，第十二可控开关的控制端、第十三可控开关的控制端、第十四可控开关的控制端、第十五可控开关的控制端、第十六可控开关的控制端、第十七可控开关的控制端、以及第四电容的第一端与下拉控制电路连接，第十二可控开关的第二端、第十三可控开关的第二端、第十四可控开关的第二端、第十五可控开关的第二端、第十六可控开关的第二端、第十七可控开关的第二端、以及第四电容的第二端接收第二参考电压，第十二可控开关的第一端连接第三可控开关的第二端，第十三可控开关的第一端连接第一电容的第二端，第十四可控开关的第一端连接第六可控开关的第二端，第十五可控开关的第一端连接第二电容的第二端，第十六可控开关的第一端连接第九可控开关的第二端，第十七可控开关的第一端连接第三电容的第二端。
其中，下拉控制电路包括第十八可控开关、第十九可控开关、第二十可控开关以及第五电容，第十八可控开关的控制端和第十九可控开关的控制端连接第三可控开关的第二端，第十八可控开关的第二端和第十九可控开关的第二端接收第二参考电压，第十八可控开关的第一端连接第五电容的第二端和第二十可控开关的控制端，第五电容的第一端接收第一时钟信号，第二十可控开关的第一端接收第一参考电压，第二十可控开关的第二端和第十九可控开关的第一端连接第十二可控开关的控制端。
其中，第一参考电压为高电平，第二参考电压为低电平。
其中，第一至第二十可控开关为N型薄膜晶体管，第一至第二十可控开关的控制端、第一端及第二端分别对应N型薄膜晶体管的栅极、源极及漏极。
其中，第一至第二十可控开关为P型薄膜晶体管，第一至第二十可控开关的控制端、第一端及第二端分别对应P型薄膜晶体管的栅极、源极及漏极。
本发明的有益效果是：区别于现有技术的情况，本发明的扫描驱动单元包括正反扫描电路、输出电路、下拉电路以及下拉控制电路，正反扫描电路用于控制扫描驱动单元进行正向扫描或者反向扫描，输出电路输出第一扫描信号、第二扫描信号以及第三扫描信号；本发明通过共用正反扫描电路、下拉电路以及下拉控制电路输出第一扫描信号、第二扫描信号以及第三扫描信号，减少扫描驱动电路的薄膜晶体管的数目，节省空间，进而利于窄边框设计。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的扫描驱动电路结构示意图；
图2是图1中扫描驱动单元的电路图；
图3是图1中的扫描驱动电路正向扫描的时序图；
图4是图1中的扫描驱动电路反向扫描的时序图；
图5是图1中的扫描驱动电路的模拟时序图；
图6是本发明第二实施例的扫描驱动单元的电路图；
图7是本发明第一实施例的平面显示装置的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1-2所示，图1是本发明第一实施例的扫描驱动电路结构示意图；图2是图1中扫描驱动单元的电路图。如图1所示，本实施例所揭示的扫描驱动电路10包括级联的多个扫描驱动单元11，其中每个扫描驱动单元11输出三个扫描信号，例如第一扫描驱动单元11输出扫描信号Gate1、Gate2以及Gate3。每一的扫描驱动单元11均连接第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3以及第四时钟信号CK4。
如图2所示，每一扫描驱动单元11包括正反扫描电路12、输出电路13、下拉电路14以及下拉控制电路15。
其中，正反扫描电路11用于接收第一扫描控制信号U2D（Up to Dowm）、第二扫描控制信号D2U（Down to Up）、驱动信号STV以及下一级扫描信号Gaten+6。正反扫描电路11根据第一扫描控制信号U2D、第二扫描控制信号D2U、驱动信号STV以及下一级扫描信号Gaten+6输出正反向控制信号CLn，正反向控制信号CLn用于控制扫描驱动单元11进行正向扫描或者反向扫描。
输出电路13与正反扫描电路12连接，输出电路13用于接收第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4和从正反扫描电路12接收正反向控制信号CLn。并且输出电路13输出第一扫描信号Gaten、第二扫描信号Gaten+1以及第三扫描信号Gaten+3；
下拉电路14与输出电路13连接，下拉电路14用于对第一节点Pn进行上拉充电或者下拉放电。
下拉控制电路15与下拉电路14连接，下拉控制电路15用于接收第一时钟信号CK1和第一参考电压V1，下拉控制电路15用于根据第一时钟信号CK1和第一参考电压V1控制第一节点Pn，以对第一扫描信号Gaten、第二扫描信号Gaten+1以及第三扫描信号Gaten+3进行下拉控制。
以下以第一级扫描驱动单元11描述扫描驱动单元11的电路图。
输出电路13包括第一输出电路131、第二输出电路132以及第三输出电路133，第一输出电路131根据正反向控制信号CL1、第一时钟信号CK1以及第二时钟信号CK2输出第一扫描信号Gate1；第二输出电路132根据第二时钟信号CK2、第三时钟信号CK3以及第一扫描信号Gate1输出第二扫描信号Gate2；第三输出电路133根据第三时钟信号CK3、第四时钟信号以及第二扫描信号Gate2输出第三扫描信号Gate3。
正反扫描电路12包括第一可控开关T1以及第二可控开关T2，第一可控开关T1的控制端接收第一扫描控制信号U2D，第一可控开关T1的第一端接收驱动信号STV，第一可控开关T1的第二端和第二可控开关T2的第二端连接输出电路13，第二可控开关T2的控制端接收第二扫描控制信号D2T，第二可控开关T2的第一端接收下一级扫描信号Gate6。
第一输出电路131包括第三可控开关T3、第四可控开关T4、第五可控开关T5以及第一电容C1，第三可控开关T3的控制端接收第一时钟信号CK1，第三可控开关T3的第一端连接第二可控开关T2的第二端和第一可控开关T1的第二端，第三可控开关T3的第二端连接第四可控开关T4的第一端，第四可控开关T4的控制端接收第一参考电压V1，第四可控开关T4的第二端连接第一电容C1的第一端和第五可控开关T5的控制端，第五可控开关T5的第一端接收第二时钟信号CK2，第五可控开关T5的第二端与第一电容C1的第二端连接，并且输出第一扫描信号Gate1。其中，第三可控开关T3的第二端和第四可控开关T4的第一端的连接处为第二节点H1，第一电容C1的第一端和第五可控开关T5的控制端的连接处为第三节点Q1。
第二输出电路132包括第六可控开关T6、第七可控开关T7、第八可控开关T8以及第二电容C2，第六可控开关T6的第一端连接第一电容C1的第二端和第五可控开关T5的第二端，第六可控开关T6的控制端接收第二时钟信号CK2，第六可控开关T6的第二端连接第七可控开关T7的第一端，第七可控开关T7的控制端接收第一参考电压V1，第七可控开关T7的第二端连接第二电容C2的第一端和第八可控开关T8的控制端，第八可控开关T8的第一端接收第三时钟信号CK3，第八可控开关T8的第二端连接第二电容C2的第二端，并且输出第二扫描信号Gate2。其中，第二电容C2的第一端和第八可控开关T8的控制端的连接处为第四节点Q2。
第三输出电路133包括第九可控开关T9、第十可控开关T10、第十一可控开关T11以及第三电容C3，第九可控开关T9的第一端连接第二电容C2的第二端，第九可控开关T9的控制端接收第三时钟信号CK3，第九可控开关T9的第二端与第十可控开关T10的第一端，第十可控开关T10的控制端接收第一参考电压V1，第十可控开关T10的第二端连接第三电容C3的第一端和第十一可控开关T11的控制端，第十一可控开关T11的第一端接收第四时钟信号，第十一可控开关T11的第二端与第三电容C3的第二端连接，并且输出第三扫描信号Gate3。其中，第三电容C3的第一端和第十一可控开关T11的控制端的连接处为第五节点Q3。
下拉电路包括第十二可控开关T12、第十三可控开关T13、第十四可控开关T14、第十五可控开关T15、第十六可控开关T16、第十七可控开关T17以及第四电容C4，第十二可控开关T12的控制端、第十三可控开关T13的控制端、第十四可控开关T14的控制端、第十五可控开关T15的控制端、第十六可控开关T16的控制端、第十七可控开关T17的控制端、以及第四电容C4的第一端与下拉控制电路连接，第十二可控开关T12的第二端、第十三可控开关T13的第二端、第十四可控开关T14的第二端、第十五可控开关T15的第二端、第十六可控开关T16的第二端、第十七可控开关T17的第二端、以及第四电容C4的第二端接收第二参考电压V2，第十二可控开关T12的第一端连接第三可控开关T3的第二端，第十三可控开关T13的第一端连接第一电容C1的第二端，第十四可控开关T14的第一端连接第六可控开关T6的第二端，第十五可控开关T15的第一端连接第二电容C2的第二端，第十六可控开关T16的第一端连接第九可控开关T9的第二端，第十七可控开关T17的第一端连接第三电容C3的第二端。其中，第十二可控开关T12的控制端、第十三可控开关T13的控制端以及第四电容C4的第一端的连接处为第一节点P1。
下拉控制电路包括第十八可控开关T18、第十九可控开关T19、第二十可控开关T20以及第五电容C5，第十八可控开关T18的控制端和第十九可控开关T19的控制端连接第三可控开关T3的第二端，第十八可控开关T18的第二端和第十九可控开关T19的第二端接收第二参考电压V2，第十八可控开关T18的第一端连接第五电容C5的第二端和第二十可控开关T20的控制端，第五电容C5的第一端接收第一时钟信号CK1，第二十可控开关T20的第一端接收第一参考电压V1，第二十可控开关T20的第二端和第十九可控开关T19的第一端连接第十二可控开关T12的控制端。其中，第十八可控开关T18的第一端、第五电容C5的第二端以及第二十可控开关T20的控制端的连接处为第六节点M1。
优选地，第一参考电压V1为高电平，第二参考电压V2为低电平。
优选地，第一可控开关T1至第二十可控开关T20为N型薄膜晶体管，第一可控开关T1至第二十可控开关T20的控制端、第一端及第二端分别对应N型薄膜晶体管的栅极、源极及漏极。
以下结合图3详细描述本实施例所揭示的扫描驱动单元11正向扫描的工作原理。
扫描驱动单元11进行正向扫描时，第一扫描控制信号U2D为高电平，第二扫描控制信号D2U为低电平，第一可控开关T1导通，第二可控开关T2断开。在驱动信号STV的高电平脉冲信号和第一时钟信号CK1的高电平脉冲信号来临时，第二节点H1和第三节点Q1被充电拉高至高电平，此时第五可控开关T5、第十九可控开关T19以及第十八可控开关T18导通，第六节点M1和第一节点P1被放电拉低至低电平，第二十可控开关T20、第十二可控开关T12、第十三可控开关T13、第十四可控开关T14、第十五可控开关T15、第十六可控开关T16以及第十七可控开关T17断开。
当第二时钟信号CK2的高电平脉冲信号来临时，第一扫描信号Gate1为高电平脉冲信号，即产生第一级栅极驱动信号。此时，第六可控开关T6导通，第四节点Q2被充电至高电平，第八可控开关T8导通。
当第三时钟信号CK3的高电平脉冲信号来临时，第二扫描信号Gate2为高电平脉冲信号，即产生第二级栅极驱动信号。此时，第九可控开关T9导通，第五节点Q3被充电至高电平，第十一可控开关T11导通。
当第四时钟信号CK4的高电平脉冲信号来临时，第三扫描信号Gate3为高电平脉冲信号，即产生第三级栅极驱动信号。
当第一时钟信号CK1的高电平脉冲信号再次来临时，第二节点H1和第三节点Q1被放电拉低至低电平，第十八可控开关T18和第十九可控开关T19断开，第六节点M1处于浮充状态（Floatingate），第一时钟信号CK1的高电平脉冲信号会造成第六节点M1被自举至高电平，第二十可控开关T20导通，第一节点P1被充电上拉至高电平，第十二可控开关T12、第十三可控开关T13、第十四可控开关T14、第十五可控开关T15、第十六可控开关T16以及第十七可控开关T17导通，第三节点Q1、第四节点Q2、第五节点Q3、第一扫描信号Gate1、第二扫描信号Gate2以及第三扫描信号Gate3稳定输出低电平。
如图4所示，本实施例所揭示的扫描驱动单元11反向扫描的工作原理与上述扫描驱动单元11正向扫描的工作原理类似，在此不再赘述。
如图5所示，本发明的扫描驱动电路10的功能与描述的一致且在多级之间级传也能进行很好的工作。
本实施例通过共用正反扫描电路12、下拉电路14以及下拉控制电路15输出第一扫描信号Gaten、第二扫描信号Gaten+1以及第三扫描信号Gaten+3，减少扫描驱动电路10的薄膜晶体管的数目，节省空间，进而利于窄边框设计。
如图6所示，本发明还提供第二实施例的扫描驱动单元，其与第一实施例所揭示的扫描驱动单元10不同之处在于：第一至第二十可控开关为P型薄膜晶体管，第一至第二十可控开关的控制端、第一端及第二端分别对应P型薄膜晶体管的栅极、源极及漏极。在其他实施例中，第一至第二十可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
如图7所示，本发明还提供第一实施例的平面显示装置。如图7所示，平面显示装置包括前述的扫描驱动电路，扫描驱动电路设置在平面显示装置的两侧。平面显示装置中的其他器件及功能与现有平面显示装置的器件及功能相同，在此不再赘述。其中，平面显示装置为LCD或OLED。
综上所述，本发明的扫描驱动单元包括正反扫描电路、输出电路、下拉电路以及下拉控制电路，正反扫描电路用于控制扫描驱动单元进行正向扫描或者反向扫描，输出电路输出第一扫描信号、第二扫描信号以及第三扫描信号；本发明通过共用正反扫描电路、下拉电路以及下拉控制电路输出第一扫描信号、第二扫描信号以及第三扫描信号，减少扫描驱动电路的薄膜晶体管的数目，节省空间，进而利于窄边框设计。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫描电路，用于接收第一扫描控制信号、第二扫描控制信号、驱动信号以及下一级扫描信号，并且输出正反向控制信号，所述正反向控制信号用于控制所述扫描驱动单元进行正向扫描或者反向扫描；
    输出电路，与所述正反扫描电路连接，用于接收第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和从所述正反扫描电路接收所述正反向控制信号，并且输出第一扫描信号、第二扫描信号以及第三扫描信号；
    下拉电路，与所述输出电路连接，用于对第一节点进行上拉充电或者下拉放电；
    下拉控制电路，与所述下拉电路连接，用于接收所述第一时钟信号和第一参考电压，用于控制所述第一节点，以对所述第一扫描信号、所述第二扫描信号以及所述第三扫描信号进行下拉控制。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述输出电路包括第一输出电路、第二输出电路以及第三输出电路，所述第一输出电路根据所述正反向控制信号、所述第一时钟信号以及所述第二时钟信号输出所述第一扫描信号；所述第二输出电路根据所述第二时钟信号、所述第三时钟信号以及所述第一扫描信号输出所述第二扫描信号；所述第三输出电路根据所述第三时钟信号、所述第四时钟信号以及所述第二扫描信号输出所述第三扫描信号。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述正反扫描电路包括第一可控开关以及第二可控开关，所述第一可控开关的控制端接收所述第一扫描控制信号，所述第一可控开关的第一端接收所述驱动信号，所述第一可控开关的第二端和所述第二可控开关的第二端连接所述输出电路，所述第二可控开关的控制端接收所述第二扫描控制信号，所述第二可控开关的第一端接收所述下一级扫描信号。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述第一输出电路包括第三可控开关、第四可控开关、第五可控开关以及第一电容，所述第三可控开关的控制端接收所述第一时钟信号，所述第三可控开关的第一端连接所述第二可控开关的第二端和所述第一可控开关的第二端，所述第三可控开关的第二端连接所述第四可控开关的第一端，所述第四可控开关的控制端接收所述第一参考电压，所述第四可控开关的第二端连接所述第一电容的第一端和所述第五可控开关的控制端，所述第五可控开关的第一端接收所述第二时钟信号，所述第五可控开关的第二端与所述第一电容的第二端连接，并且输出所述第一扫描信号；
    所述第二输出电路包括第六可控开关、第七可控开关、第八可控开关以及第二电容，所述第六可控开关的第一端连接所述第一电容的第二端和所述第五可控开关的第二端，所述第六可控开关的控制端接收所述第二时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收所述第一参考电压，所述第七可控开关的第二端连接所述第二电容的第一端和所述第八可控开关的控制端，所述第八可控开关的第一端接收所述第三时钟信号，所述第八可控开关的第二端连接所述第二电容的第二端，并且输出所述第二扫描信号；
    所述第三输出电路包括第九可控开关、第十可控开关、第十一可控开关以及第三电容，所述第九可控开关的第一端连接所述第二电容的第二端，所述第九可控开关的控制端接收所述第三时钟信号，所述第九可控开关的第二端与所述第十可控开关的第一端，所述第十可控开关的控制端接收所述第一参考电压，所述第十可控开关的第二端连接所述第三电容的第一端和所述第十一可控开关的控制端，所述第十一可控开关的第一端接收所述第四时钟信号，所述第十一可控开关的第二端与所述第三电容的第二端连接，并且输出所述第三扫描信号。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述下拉电路包括第十二可控开关、第十三可控开关、第十四可控开关、第十五可控开关、第十六可控开关、第十七可控开关以及第四电容，所述第十二可控开关的控制端、所述第十三可控开关的控制端、所述第十四可控开关的控制端、所述第十五可控开关的控制端、所述第十六可控开关的控制端、所述第十七可控开关的控制端、以及所述第四电容的第一端与所述下拉控制电路连接，所述第十二可控开关的第二端、所述第十三可控开关的第二端、所述第十四可控开关的第二端、所述第十五可控开关的第二端、所述第十六可控开关的第二端、所述第十七可控开关的第二端、以及所述第四电容的第二端接收第二参考电压，所述第十二可控开关的第一端连接所述第三可控开关的第二端，所述第十三可控开关的第一端连接所述第一电容的第二端，所述第十四可控开关的第一端连接所述第六可控开关的第二端，所述第十五可控开关的第一端连接所述第二电容的第二端，所述第十六可控开关的第一端连接所述第九可控开关的第二端，所述第十七可控开关的第一端连接所述第三电容的第二端。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述下拉控制电路包括第十八可控开关、第十九可控开关、第二十可控开关以及第五电容，所述第十八可控开关的控制端和所述第十九可控开关的控制端连接所述第三可控开关的第二端，所述第十八可控开关的第二端和所述第十九可控开关的第二端接收所述第二参考电压，所述第十八可控开关的第一端连接所述第五电容的第二端和所述第二十可控开关的控制端，所述第五电容的第一端接收所述第一时钟信号，所述第二十可控开关的第一端接收所述第一参考电压，所述第二十可控开关的第二端和所述第十九可控开关的第一端连接所述第十二可控开关的控制端。
  7. 根据权利要求6所述的扫描驱动电路，其中，所述第一参考电压为高电平，所述第二参考电压为低电平。
  8. 根据权利要求6所述的扫描驱动电路，其中，所述第一至第二十可控开关为N型薄膜晶体管，所述第一至第二十可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。
  9. 根据权利要求6所述的扫描驱动电路，其中，所述第一至第二十可控开关为P型薄膜晶体管，所述第一至第二十可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、源极及漏极。
  10. 一种平面显示装置，其中，所述平面显示装置包括扫描驱动电路，
    所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫描电路，用于接收第一扫描控制信号、第二扫描控制信号、驱动信号以及下一级扫描信号，并且输出正反向控制信号，所述正反向控制信号用于控制所述扫描驱动单元进行正向扫描或者反向扫描；
    输出电路，与所述正反扫描电路连接，用于接收第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和从所述正反扫描电路接收所述正反向控制信号，并且输出第一扫描信号、第二扫描信号以及第三扫描信号；
    下拉电路，与所述输出电路连接，用于对第一节点进行上拉充电或者下拉放电；
    下拉控制电路，与所述下拉电路连接，用于接收所述第一时钟信号和第一参考电压，用于控制所述第一节点，以对所述第一扫描信号、所述第二扫描信号以及所述第三扫描信号进行下拉控制。
  11. 根据权利要求10所述的平面显示装置，其中，所述输出电路包括第一输出电路、第二输出电路以及第三输出电路，所述第一输出电路根据所述正反向控制信号、所述第一时钟信号以及所述第二时钟信号输出所述第一扫描信号；所述第二输出电路根据所述第二时钟信号、所述第三时钟信号以及所述第一扫描信号输出所述第二扫描信号；所述第三输出电路根据所述第三时钟信号、所述第四时钟信号以及所述第二扫描信号输出所述第三扫描信号。
  12. 根据权利要求11所述的平面显示装置，其中，所述正反扫描电路包括第一可控开关以及第二可控开关，所述第一可控开关的控制端接收所述第一扫描控制信号，所述第一可控开关的第一端接收所述驱动信号，所述第一可控开关的第二端和所述第二可控开关的第二端连接所述输出电路，所述第二可控开关的控制端接收所述第二扫描控制信号，所述第二可控开关的第一端接收所述下一级扫描信号。
  13. 根据权利要求12所述的平面显示装置，其中，所述第一输出电路包括第三可控开关、第四可控开关、第五可控开关以及第一电容，所述第三可控开关的控制端接收所述第一时钟信号，所述第三可控开关的第一端连接所述第二可控开关的第二端和所述第一可控开关的第二端，所述第三可控开关的第二端连接所述第四可控开关的第一端，所述第四可控开关的控制端接收所述第一参考电压，所述第四可控开关的第二端连接所述第一电容的第一端和所述第五可控开关的控制端，所述第五可控开关的第一端接收所述第二时钟信号，所述第五可控开关的第二端与所述第一电容的第二端连接，并且输出所述第一扫描信号；
    所述第二输出电路包括第六可控开关、第七可控开关、第八可控开关以及第二电容，所述第六可控开关的第一端连接所述第一电容的第二端和所述第五可控开关的第二端，所述第六可控开关的控制端接收所述第二时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收所述第一参考电压，所述第七可控开关的第二端连接所述第二电容的第一端和所述第八可控开关的控制端，所述第八可控开关的第一端接收所述第三时钟信号，所述第八可控开关的第二端连接所述第二电容的第二端，并且输出所述第二扫描信号；
    所述第三输出电路包括第九可控开关、第十可控开关、第十一可控开关以及第三电容，所述第九可控开关的第一端连接所述第二电容的第二端，所述第九可控开关的控制端接收所述第三时钟信号，所述第九可控开关的第二端与所述第十可控开关的第一端，所述第十可控开关的控制端接收所述第一参考电压，所述第十可控开关的第二端连接所述第三电容的第一端和所述第十一可控开关的控制端，所述第十一可控开关的第一端接收所述第四时钟信号，所述第十一可控开关的第二端与所述第三电容的第二端连接，并且输出所述第三扫描信号。
  14. 根据权利要求13所述的平面显示装置，其中，所述下拉电路包括第十二可控开关、第十三可控开关、第十四可控开关、第十五可控开关、第十六可控开关、第十七可控开关以及第四电容，所述第十二可控开关的控制端、所述第十三可控开关的控制端、所述第十四可控开关的控制端、所述第十五可控开关的控制端、所述第十六可控开关的控制端、所述第十七可控开关的控制端、以及所述第四电容的第一端与所述下拉控制电路连接，所述第十二可控开关的第二端、所述第十三可控开关的第二端、所述第十四可控开关的第二端、所述第十五可控开关的第二端、所述第十六可控开关的第二端、所述第十七可控开关的第二端、以及所述第四电容的第二端接收第二参考电压，所述第十二可控开关的第一端连接所述第三可控开关的第二端，所述第十三可控开关的第一端连接所述第一电容的第二端，所述第十四可控开关的第一端连接所述第六可控开关的第二端，所述第十五可控开关的第一端连接所述第二电容的第二端，所述第十六可控开关的第一端连接所述第九可控开关的第二端，所述第十七可控开关的第一端连接所述第三电容的第二端。
  15. 根据权利要求14所述的平面显示装置，其中，所述下拉控制电路包括第十八可控开关、第十九可控开关、第二十可控开关以及第五电容，所述第十八可控开关的控制端和所述第十九可控开关的控制端连接所述第三可控开关的第二端，所述第十八可控开关的第二端和所述第十九可控开关的第二端接收所述第二参考电压，所述第十八可控开关的第一端连接所述第五电容的第二端和所述第二十可控开关的控制端，所述第五电容的第一端接收所述第一时钟信号，所述第二十可控开关的第一端接收所述第一参考电压，所述第二十可控开关的第二端和所述第十九可控开关的第一端连接所述第十二可控开关的控制端。
  16. 根据权利要求15所述的平面显示装置，其中，所述第一参考电压为高电平，所述第二参考电压为低电平。
  17. 根据权利要求15所述的平面显示装置，其中，所述第一至第二十可控开关为N型薄膜晶体管，所述第一至第二十可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。
  18. 根据权利要求15所述的平面显示装置，其中，所述第一至第二十可控开关为P型薄膜晶体管，所述第一至第二十可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、源极及漏极。
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