WO2018023859A1 - 扫描驱动电路及具有该电路的平面显示装置 - Google Patents

扫描驱动电路及具有该电路的平面显示装置 Download PDF

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Publication number
WO2018023859A1
WO2018023859A1 PCT/CN2016/099221 CN2016099221W WO2018023859A1 WO 2018023859 A1 WO2018023859 A1 WO 2018023859A1 CN 2016099221 W CN2016099221 W CN 2016099221W WO 2018023859 A1 WO2018023859 A1 WO 2018023859A1
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Prior art keywords
controllable switch
control
circuit
signal
controllable
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PCT/CN2016/099221
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English (en)
French (fr)
Inventor
李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/308,557 priority Critical patent/US10297203B2/en
Publication of WO2018023859A1 publication Critical patent/WO2018023859A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a flat display device having the same.
  • a scan driving circuit is used, that is, a scan driving circuit is fabricated on an array substrate by using a conventional thin film transistor planar display array process to realize a driving method for progressive scanning.
  • the pull-up control signal point is set.
  • Q shown in FIG. 1 to FIG. 3, wherein FIG. 1 is a circuit diagram of a scan driving unit of the conventional scan driving circuit, and FIGS. 2 and 3 are front and back scanning waveform diagrams and reverse scanning waveform diagrams of FIG.
  • the capacitor C1 causes the thin film transistor T6 to be seriously affected when the pull-up control signal point Q is lifted to a higher level, and the thin film transistor T5 is provided.
  • the thin film transistor T5 is always in an open state, then the pull-up control signal point Q is also pre-charged.
  • the clock signal CKV2 changes from a low level to a high level, the bootstrap of the capacitor C1 The action recharges the pull-up control signal point Q, and at this time, the voltage Vgs between the gate and the source of the thin film transistor T5 is equal to 0V.
  • the H point will continue to maintain the precharge.
  • the pull-up control signal point Q will also continue to maintain the high potential of the capacitor C1 after bootstrap, and the thin film transistor T6 will not be seriously affected by the capacitor C1 lifting the pull-up control signal point Q to a higher potential.
  • the thin film transistor T5 is in a serious leakage state, and then the pull-up control signal point Q is pulled low by the H point after the bootstrap of the capacitor C1, thereby causing the scan line.
  • the output signal of Gn is unstable, which in turn affects the display effect of the panel.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a flat display device having the same to effectively solve the problem that the output signal of the scan line is unstable due to leakage of the thin film transistor, so as to improve the display effect of the panel.
  • the present invention adopts a technical solution to provide a scan driving circuit
  • the scan driving circuit includes a plurality of cascaded scan driving units, and each scan driving unit includes:
  • a positive sweep circuit for receiving the upper scan signal and the first clock signal and outputting the first control signal to control the scan drive circuit to perform forward scan, or for receiving the lower scan signal and the second clock signal and outputting the second control signal Performing a reverse scan by controlling the scan driving circuit;
  • An input circuit connected to the forward and reverse sweep circuit, for receiving the third clock signal and receiving the first and second control signals from the forward and reverse sweep circuit, and pulling up the control signal point according to the third clock signal, the first and second control signals And pull down the control signal point for charging;
  • a leakage prevention circuit connected to the input circuit for receiving the first clock signal and the second clock signal and processing the leakage of the input circuit according to the first and second clock signals;
  • the output circuit is connected to the input circuit for processing the received fourth control signal and the data received from the input circuit, and generating a scan drive signal output to the scan line of the current stage to drive the pixel unit.
  • the positive and negative scanning circuit includes first and second controllable switches, and the control end of the first controllable switch receives the first clock signal, and the first end of the first controllable switch receives the upper scanning signal, and the first controllable switch The second end is connected to the first end of the second controllable switch and the input circuit, the control end of the second controllable switch receives the second clock signal, and the second end of the second controllable switch receives the lower level scan signal.
  • the input circuit includes third to seventh controllable switches, first and second capacitors, and the control end of the third controllable switch is connected to the leakage prevention circuit, and the first end of the third controllable switch is connected to the fourth controllable switch a control end, a second end of the first controllable switch, and a first end of the second controllable switch, the second end of the third controllable switch is connected to the first end of the fifth controllable switch and the output circuit, and the fifth controllable
  • the second end of the switch is connected to the second end of the fourth controllable switch, the second end of the sixth controllable switch, and the second end of the seventh controllable switch, and receives the signal of the closed voltage end, and the control end of the fifth controllable switch Connecting the first end of the fourth controllable switch and the control end of the sixth controllable switch, the first end of the sixth controllable switch is connected to the first end of the seventh controllable switch and the output circuit, and the control of the seventh controllable switch The terminal receive
  • the leakage prevention circuit includes eighth to tenth controllable switches, and the control end of the eighth controllable switch receives the first clock signal, and the first end of the eighth controllable switch is connected to the first end of the ninth controllable switch and receives Turning on the voltage end signal, the second end of the eighth controllable switch is connected to the second end of the ninth controllable switch, the second end of the tenth controllable switch, and the control end of the third controllable switch, and the ninth controllable switch
  • the control terminal receives the second clock signal, and the first end of the tenth controllable switch receives the signal of the closed voltage end, and the control end of the tenth controllable switch is connected to the second end of the first capacitor and the output circuit.
  • the output circuit includes an eleventh controllable switch and a third capacitor, and the control end of the eleventh controllable switch is connected to the second end of the third controllable switch and the first end of the fifth controllable switch, the eleventh The first end of the control switch is connected to the control end of the tenth controllable switch and the second end of the first capacitor and receives the fourth clock signal, and the second end of the eleventh controllable switch is connected to the sixth and seventh controllable switches The first end is connected to the scanning line of the first stage, and the third capacitor is connected between the control end and the second end of the eleventh controllable switch.
  • the first to the eleventh controllable switches are N-type thin film transistors, and the control ends, the first ends and the second ends of the first to eleventh controllable switches respectively correspond to gates and drains of the N-type thin film transistors and Source.
  • a flat display device including a scan driving circuit, the scan driving circuit including a plurality of cascaded scan driving units, each of which includes :
  • a positive sweep circuit for receiving the upper scan signal and the first clock signal and outputting the first control signal to control the scan drive circuit to perform forward scan, or for receiving the lower scan signal and the second clock signal and outputting the second control signal Performing a reverse scan by controlling the scan driving circuit;
  • An input circuit connected to the forward and reverse sweep circuit, for receiving the third clock signal and receiving the first and second control signals from the forward and reverse sweep circuit, and pulling up the control signal point according to the third clock signal, the first and second control signals And pull down the control signal point for charging;
  • a leakage prevention circuit connected to the input circuit for receiving the first clock signal and the second clock signal and processing the leakage of the input circuit according to the first and second clock signals;
  • the output circuit is connected to the input circuit for processing the received fourth control signal and the data received from the input circuit, and generating a scan drive signal output to the scan line of the current stage to drive the pixel unit.
  • the positive and negative scanning circuit includes first and second controllable switches, and the control end of the first controllable switch receives the first clock signal, and the first end of the first controllable switch receives the upper scanning signal, and the first controllable switch The second end is connected to the first end of the second controllable switch and the input circuit, the control end of the second controllable switch receives the second clock signal, and the second end of the second controllable switch receives the lower level scan signal.
  • the input circuit includes third to seventh controllable switches, first and second capacitors, and the control end of the third controllable switch is connected to the leakage prevention circuit, and the first end of the third controllable switch is connected to the fourth controllable switch a control end, a second end of the first controllable switch, and a first end of the second controllable switch, the second end of the third controllable switch is connected to the first end of the fifth controllable switch and the output circuit, and the fifth controllable
  • the second end of the switch is connected to the second end of the fourth controllable switch, the second end of the sixth controllable switch, and the second end of the seventh controllable switch, and receives the signal of the closed voltage end, and the control end of the fifth controllable switch Connecting the first end of the fourth controllable switch and the control end of the sixth controllable switch, the first end of the sixth controllable switch is connected to the first end of the seventh controllable switch and the output circuit, and the control of the seventh controllable switch The terminal receive
  • the leakage prevention circuit includes eighth to tenth controllable switches, and the control end of the eighth controllable switch receives the first clock signal, and the first end of the eighth controllable switch is connected to the first end of the ninth controllable switch and receives Turning on the voltage end signal, the second end of the eighth controllable switch is connected to the second end of the ninth controllable switch, the second end of the tenth controllable switch, and the control end of the third controllable switch, and the ninth controllable switch
  • the control terminal receives the second clock signal, and the first end of the tenth controllable switch receives the signal of the closed voltage end, and the control end of the tenth controllable switch is connected to the second end of the first capacitor and the output circuit.
  • the output circuit includes an eleventh controllable switch and a third capacitor, and the control end of the eleventh controllable switch is connected to the second end of the third controllable switch and the first end of the fifth controllable switch, the eleventh The first end of the control switch is connected to the control end of the tenth controllable switch and the second end of the first capacitor and receives the fourth clock signal, and the second end of the eleventh controllable switch is connected to the sixth and seventh controllable switches The first end is connected to the scanning line of the first stage, and the third capacitor is connected between the control end and the second end of the eleventh controllable switch.
  • the scan driving circuit of the present invention controls the scan driving circuit to perform forward scanning and reverse scanning through the forward and reverse scanning circuits, and pulls up the control signal points through the input circuit. Pulling down the control signal point for charging, preventing the leakage of the thin film transistor by the leakage preventing circuit to cause the output signal of the scan line to be unstable, and generating the scan driving signal output to the scan line through the output circuit to drive the pixel unit, thereby effectively solving the scan line caused by the leakage of the thin film transistor.
  • the output signal is unstable and the panel display effect is improved.
  • FIG. 1 is a circuit diagram of a scan driving unit of a scanning drive circuit in the prior art
  • Figure 2 is a forward scan waveform diagram of Figure 1;
  • Figure 3 is a reverse scan waveform diagram of Figure 1;
  • Figure 4 is a circuit diagram of a first embodiment of a scan driving unit of the scan driving circuit of the present invention.
  • Figure 5 is a forward scan waveform diagram of Figure 4.
  • Figure 6 is a reverse scan waveform diagram of Figure 4.
  • Figure 7 is a schematic illustration of a flat display device of the present invention.
  • the working principle (forward scanning) of the scanning driving circuit in the prior art is as follows:
  • Precharge phase When the upper scan signal Gn-1 and the clock signal CKV1 are simultaneously at a high level, the thin film transistor T1 is turned on, the H point is precharged, the thin film transistor T5 is always in an on state, and the pull-up control signal point Q is charged. When the H point is at a high level, the thin film transistor T6 is in an on state, and the pull-down control signal point P is pulled low;
  • the scan line Gn outputs a high level phase: the gate receiving open voltage terminal signal VGH of the thin film transistor T5 is always in an on state.
  • the precharge phase the pull-up control signal point Q is precharged, and the capacitor C3 has a certain hold on the charge.
  • the thin film transistor T2 is in an on state, the high level of the clock signal CKV2 is output to the scan line Gn;
  • the scanning line Gn outputs a low level phase: when the clock signal CKV3 and the lower level scanning signal Gn+1 are simultaneously at a high level, the pull-up control signal point Q is maintained at a high level, and at this time, the low level of the clock signal CKV2 is scanned. The potential of the line Gn is pulled low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL: when the clock signal CKV1 goes high again, the upper-level scan signal Gn-1 is at a low level, and the thin film transistor T1 is in a conducting state, then the upper The pull control signal point Q is pulled down to the off voltage terminal VGL;
  • the low-level sustaining phase of the pull-up control signal point Q and the scan line Gn when the pull-up control signal point Q becomes a low level, the thin film transistor T6 is in an off state, and when the clock signal CKV2 becomes a high level, When the coupling of the capacitor C1 and the pull-down control signal point P become a high level, the thin film transistors T4 and T7 are both in an on state, and the low level of the pull-up control signal point Q and the scanning line Gn can be stabilized.
  • the working principle (reverse scan) of the scan driving circuit in the prior art is as follows:
  • Precharge phase When the lower scan signal Gn+1 and the clock signal CKV3 are simultaneously at a high level, the thin film transistor T3 is turned on, the H point is precharged, the thin film transistor T5 is always in an on state, and the pull-up control signal point Q is charged. When the H point is at a high level, the thin film transistor T6 is in an on state, and the pull-down control signal point P is pulled low;
  • the scan line Gn outputs a high level phase: the gate receiving open voltage terminal signal VGH of the thin film transistor T5 is always in an on state.
  • the precharge phase the pull-up control signal point Q is precharged, and the capacitor C3 has a certain hold on the charge.
  • the thin film transistor T2 is in an on state, the high level of the clock signal CKV2 is output to the scan line Gn;
  • the scanning line Gn outputs a low level phase: when the clock signal CKV1 and the upper scanning signal Gn-1 are simultaneously at a high level, the pull-up control signal point Q is maintained at a high level, and at this time, the low level of the clock signal CKV2 is scanned. The potential of the line Gn is pulled low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL stage: when the clock signal CKV3 changes to the high level again, the lower-level scan signal Gn+1 is at a low level, and the thin film transistor T3 is in an on state. Pulling control signal point Q is pulled down to turn off voltage terminal signal VGL;
  • the low-level sustaining phase of the pull-up control signal point Q and the scan line Gn when the pull-up control signal point Q becomes a low level, the thin film transistor T6 is in an off state, and when the clock signal CKV2 becomes a high level, The coupling of the capacitor C1, the pull-down control signal point P becomes a high level, and the thin film transistors T4 and T7 are both in an on state, which can ensure the stabilization of the low level of the pull-up control signal point Q and the scan line Gn.
  • the capacitor C1 lifts the pull-up control signal point Q to a higher level, causing a serious influence on the thin film transistor T6, and is set.
  • the thin film transistor T5 when the H point is precharged, the thin film transistor T5 is always in an open state, then the pull-up control signal point Q is also pre-charged, and when the clock signal CKV2 changes from a low level to a high level, the capacitor C1
  • the bootstrap action will increase the pull-up control signal point Q again, and the voltage Vgs between the gate and the source of the thin film transistor T5 is equal to 0V.
  • the H point When the switching characteristics of the thin film transistor are good, then the H point will continue to be maintained. The corresponding high potential during pre-charging, the pull-up control signal point Q will also continue to maintain the high potential of the capacitor C1 after bootstrap, and the thin film transistor T6 will not lift the pull-up control signal point Q to a higher potential due to the capacitor C1. A serious effect is caused, however, the thin film transistor T5 is deteriorated due to process factors causing the switching characteristics of the thin film transistor to deteriorate. In a severe leakage state, the pull-up control signal point Q is pulled low by the H-point potential after the capacitor C1 is bootstrapped, causing the output signal of the scanning line Gn to be unstable, thereby affecting the display effect of the panel.
  • FIG. 4 is a structural diagram of a first embodiment of a scan driving unit of the scan driving circuit of the present invention.
  • the scan driving circuit of the present invention includes a plurality of cascaded scan driving units, each of which includes a forward and reverse sweep circuit 100 for receiving an upper scan signal and a first clock signal and outputting a first control. The signal is controlled to scan the driving circuit for forward scanning, or for receiving the lower scanning signal and the second clock signal and outputting the second control signal to control the scanning driving circuit to perform reverse scanning;
  • the input circuit 200 is connected to the forward and reverse sweep circuit 100 for receiving the third clock signal and receiving the first and second control signals from the forward and reverse sweep circuits and controlling the pull-up according to the third clock signal and the first and second control signals.
  • the leakage prevention circuit 300 is connected to the input circuit 200 for receiving the first clock signal and the second clock signal and processing the leakage of the input circuit according to the first and second clock signals;
  • the output circuit 400 is connected to the input circuit 200 for processing the received fourth control signal and the data received from the input circuit 200 to generate a scan drive signal output to the scan line of the current stage to drive the pixel unit.
  • the positive scan circuit 100 includes a first controllable switch T1 and a second controllable switch T2.
  • the control end of the first controllable switch T1 receives the first clock signal, and the first end of the first controllable switch T1 receives the upper scan signal.
  • the second end of the first controllable switch T1 is connected to the first end of the second controllable switch T2 and the input circuit 200, the control end of the second controllable switch T2 receives the second clock signal, and the second controllable switch T2 is second.
  • the terminal receives the lower level scan signal.
  • the input circuit 200 includes third to seventh controllable switches T3-T7, first and second capacitors C1, C2, and the control end of the third controllable switch T3 is connected to the leakage prevention circuit 300, and the first of the third controllable switch T3
  • the terminal is connected to the control end of the fourth controllable switch T4, the second end of the first controllable switch T1 and the first end of the second controllable switch T2, and the second end of the third controllable switch T3 is connected to the fifth controllable switch
  • the first end of the T5 and the output circuit 400, the second end of the fifth controllable switch T5 is connected to the second end of the fourth controllable switch T4, the second end of the sixth controllable switch T6, and the seventh controllable switch T7
  • the second end receives the closing voltage end signal VGL
  • the control end of the fifth controllable switch T5 is connected to the first end of the fourth controllable switch T4 and the control end of the sixth controllable switch T6, and the sixth controllable switch
  • the leakage prevention circuit 300 includes eighth to tenth controllable switches T8-T10.
  • the control end of the eighth controllable switch T8 receives the first clock signal, and the first end of the eighth controllable switch T8 is connected to the ninth controllable switch T9.
  • the first end receives the turn-on voltage terminal signal VGH
  • the second end of the eighth controllable switch T8 is connected to the second end of the ninth controllable switch T9, the second end of the tenth controllable switch T10, and the third controllable switch T3
  • the control end of the ninth controllable switch T9 receives the second clock signal
  • the first end of the tenth controllable switch T10 receives the closed voltage end signal VGL
  • the control end of the tenth controllable switch T10 is connected to the first capacitor C1 The second end and the output circuit 400.
  • the output circuit 400 includes an eleventh controllable switch T11 and a third capacitor C3.
  • the control end of the eleventh controllable switch T11 is connected to the second end of the third controllable switch T3 and the first end of the fifth controllable switch T5.
  • the first end of the eleventh controllable switch T11 is connected to the control end of the tenth controllable switch T10 and the second end of the first capacitor C1 and receives the fourth clock signal, and the second end of the eleventh controllable switch T11 is connected.
  • the first end of the sixth and seventh controllable switches T6 and T7 and the scanning line of the current stage, and the third capacitor C3 is connected between the control end and the second end of the eleventh controllable switch T11.
  • the first to eleventh controllable switches T1-T11 are N-type thin film transistors, and the control ends, the first ends, and the second ends of the first to eleventh controllable switches T1-T11 respectively correspond to N The gate, drain and source of the thin film transistor.
  • the first through eleventh controllable switches can also be other types of switches as long as the objectives of the present invention are achieved.
  • the upper scanning signal is the upper scanning signal Gn-1
  • the lower scanning signal is the lower scanning signal Gn+1
  • the first clock signal is the clock signal CKV1
  • the second clock signal is the clock signal CKV3
  • the third clock signal is
  • the fourth clock signal is the clock signal CKV2
  • the pull-up control signal point is the pull-up control signal point Q
  • the pull-down control signal point is the pull-down control signal point P.
  • the working principle (forward scanning) of a scan driving unit of the scan driving circuit can be obtained as follows:
  • Precharge phase when the upper scan signal Gn-1 and the first clock signal CKV1 are simultaneously at a high level, the first controllable switch T1 is turned on, the H point is precharged, the first clock signal CKV1 is at a high level, and the eighth The control switch T8 is in the on state, the N point is the high level, the third controllable switch T3 is turned on, the pull-up control signal point Q is charged, and when the H point is the high level, the fourth controllable switch T4 is turned on. State, the pull-down control signal point P is pulled low;
  • the scan line Gn outputs a high level phase: when the fourth clock signal CKV2 changes from a low level to a high level, the pull-up control signal point Q is again raised due to the bootstrap action of the first capacitor C1, and the first time
  • the clock signal CKV1 and the second clock signal CKV3 are both low level
  • the eighth controllable switch T8 and the ninth controllable switch T9 are both in the off state
  • the tenth controllable switch T10 is in the on state
  • the N point is pulled down to
  • the voltage terminal signal VGL is turned off
  • the third controllable switch T3 is in a closed state. Since the third capacitor C3 has a certain holding effect on the electric charge, the eleven controllable switch T11 is in an on state, and the fourth clock signal CKV2 is in a high level output.
  • the scanning line Gn outputs a low level phase: when the second clock signal CKV3 and the lower level scanning signal Gn+1 are simultaneously at a high level, the H point is maintained at a high potential, the second clock signal CKV3 is at a high level, and the ninth controllable switch T9 is in the on state, N is high level, the third controllable switch T3 is turned on, the pull-up control signal point Q is charged, and at this time, the low level of the fourth clock signal CKV2 pulls the potential of the scan line Gn low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL: when the first clock signal CKV1 goes high again, the lower level scan signal Gn-1 is at a low level, the first controllable switch T1 and the first The eight controllable switch T8 is in an on state, then the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL;
  • a low-level sustaining phase of the pull-up control signal point Q and the scan line Gn when the pull-up control signal point Q becomes a low level, the fourth controllable switch T4 is in an off state, when the fourth clock signal CKV2 becomes high After the level, due to the coupling of the first capacitor C1, the pull-down control signal point P becomes a high level, then the sixth controllable switch T6 and the fifth controllable switch T5 are both in an on state, which can ensure the pull-up control signal point The low level of Q and scan line Gn is stable.
  • the working principle (reverse scan) of a scan driving unit of the scan driving circuit can be obtained as follows:
  • Precharge phase when the lower scan signal Gn+1 and the second clock signal CKV3 are simultaneously at a high level, the second controllable switch T2 is turned on, the H point is precharged, and the second clock signal CKV3 is high level, the ninth The control switch T9 is in the on state, the N point is the high level, the third controllable switch T3 is turned on, the pull-up control signal point Q is charged, and when the H point is the high level, the fourth controllable switch T4 is turned on. State, the pull-down control signal point P is pulled low;
  • the scan line Gn outputs a high level phase: when the fourth clock signal CKV2 changes from a low level to a high level, the pull-up control signal point Q is recharged due to the bootstrap action of the first capacitor C1, and the first time
  • the clock signal CKV1 and the second clock signal CKV3 are both at a low level
  • the eighth controllable switch T8 and the ninth controllable switch T9 are both in a closed state, and at this time, the tenth controllable switch T10 is in an on state, and the N point is Pulling down to the closed voltage terminal signal VGL
  • the third controllable switch T3 is in a closed state
  • the third capacitor C3 has a certain holding effect on the charge
  • the eleventh controllable switch T11 is in an on state
  • the scanning line Gn outputs a low level phase: when the first clock signal CKV1 and the upper level scanning signal Gn-1 are simultaneously at a high level, the H point is maintained at a high potential, and the first clock signal CKV1 is at a high level, the eighth controllable switch T8 is in the on state, N is high level, the third controllable switch T3 is turned on, the pull-up control signal point Q is charged, and at this time, the low level of the fourth clock signal CKV2 pulls the potential of the scan line Gn low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL: when the second clock signal CKV3 becomes high again, the lower level scan signal Gn+1 is at a low level, the second controllable switch T2 and the The nine controllable switch T9 is in an on state, then the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL;
  • a low-level sustaining phase of the pull-up control signal point Q and the scan line Gn when the pull-up control signal point Q becomes a low level, the fourth controllable switch T4 is in an off state, when the fourth clock signal CKV2 becomes high After the level, due to the coupling of the first capacitor C1, the pull-down control signal point P becomes a high level, then the sixth controllable switch T6 and the fifth controllable switch T5 are both in an on state, which can ensure the pull-up control signal point The low level of Q and scan line Gn is stable.
  • the H point is pre-charged, and at this time, the eighth controllable switch T8 is also in an on state, and N is a high level, then the third controllable The switch T3 is also in an on state, and the pull-up control signal point Q is charged by the H point.
  • the pull-up control signal is acted upon by the bootstrap action of the first capacitor C1.
  • the point Q will be recharged, and at this time, the first clock signal CKV1 and the second clock signal CKV3 are both low, and the eighth controllable switch T8 and the ninth controllable switch T9 are both in the off state, and at this time, the tenth
  • the controllable switch T10 is in an on state, the N point is pulled down to the off voltage end signal VGL, and the third controllable switch T3 is in a closed state, so that the high potential of the pull-up control signal point Q is not affected by the H point. At the same time, the high potential of the pull-up control signal point Q does not affect the fourth controllable switch T4.
  • FIG. 7 is a schematic diagram of a flat display device according to the present invention.
  • the flat display device includes the aforementioned scan driving circuit, and the scan driving circuit is disposed at both ends of the flat display device.
  • the flat display device is an LCD or an OLED. Other devices and functions of the flat display device are the same as those of the existing flat display device, and will not be described herein.
  • the scan driving circuit of the invention controls the scan driving circuit to perform forward scanning and reverse scanning through the forward and reverse scanning circuit, and charges the pull-up control signal point and the pull-down control signal point through the input circuit, and prevents the thin film transistor from leaking through the leakage preventing circuit.
  • the output signal of the scan line is unstable, and the output of the scan drive signal is output to the scan line to drive the pixel unit, so as to effectively solve the problem that the output signal of the scan line is unstable due to leakage of the thin film transistor, so as to improve the display effect of the panel.

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Abstract

一种扫描驱动电路及平面显示装置，其中扫描驱动电路包括级联的多个扫描驱动单元，每一扫描驱动单元包括正反扫电路（100），控制正向或反向扫描；输入电路（200），对上拉控制信号点（Q）及下拉控制信号点（P）进行充电；防漏电电路（300），对输入电路的漏电进行处理；输出电路（400），产生扫描驱动信号输出给本级扫描线来驱动像素单元。

Description

扫描驱动电路及具有该电路的平面显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及具有该电路的平面显示装置。
【背景技术】
目前的平面显示装置中采用扫描驱动电路，也就是利用现有薄膜晶体管平面显示器阵列制程将扫描驱动电路制作在阵列基板上，实现对逐行扫描的驱动方式。传统扫描驱动电路设计时，为了保证扫描线输出信号的稳定性，会设置上拉控制信号点 Q（如图1至图3所示，其中，图1是现有的扫描驱动电路的一个扫描驱动单元的电路图，图2及图3是图1的正反扫描波形图及反向扫描波形图），为了防止时钟信号CKV2由低电平变高电平时，电容C1将上拉控制信号点Q自举为更高电平时对薄膜晶体管T6造成严重影响，设置了薄膜晶体管T5 ，当H点被预充电时，薄膜晶体管T5一直处于打开的状态，那么上拉控制信号点Q同时也会被预充电，当时钟信号CKV2由低电平变高电平时，电容C1的自举作用会对上拉控制信号点Q再次充电，而此时薄膜晶体管T5的栅极与源极之间的电压Vgs等于0V，当薄膜晶体管的开关特性良好时，那么H点将继续维持预充电时对应的高电位，上拉控制信号点Q也将会继续保持电容C1自举后的高电位，薄膜晶体管T6不会因为电容C1将上拉控制信号点Q自举到更高电位而造成严重影响，然而由于制程原因造成薄膜晶体管的开关特性变差时，则薄膜晶体管T5处于严重的漏电状态，那么上拉控制信号点Q在电容C1自举之后会被H点拉低电位，从而造成扫描线Gn的输出信号不稳定，进而影响面板的显示效果。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及具有该电路的平面显示装置，以有效解决由于薄膜晶体管漏电造成扫描线的输出信号不稳定的问题，以提高面板显示效果。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，扫描驱动电路包括级联的多个扫描驱动单元，每一扫描驱动单元包括：
正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制扫描驱动电路进行反向扫描；
输入电路，连接正反扫电路，用于接收第三时钟信号及从正反扫电路接收第一及第二控制信号并根据第三时钟信号、第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；
防漏电电路，连接输入电路，用于接收第一时钟信号及第二时钟信号并根据第一及第二时钟信号对输入电路的漏电进行处理；及
输出电路，连接输入电路，用于对接收到的第四控制信号及从输入电路接收的数据进行处理，产生扫描驱动信号输出给本级扫描线来驱动像素单元。
其中，正反扫电路包括第一及第二可控开关，第一可控开关的控制端接收第一时钟信号，第一可控开关的第一端接收上级扫描信号，第一可控开关的第二端连接第二可控开关的第一端及输入电路，第二可控开关的控制端接收第二时钟信号，第二可控开关的第二端接收下级扫描信号。
其中，输入电路包括第三至第七可控开关、第一及第二电容，第三可控开关的控制端连接防漏电电路，第三可控开关的第一端连接第四可控开关的控制端、第一可控开关的第二端及第二可控开关的第一端，第三可控开关的第二端连接第五可控开关的第一端及输出电路，第五可控开关的第二端连接第四可控开关的第二端、第六可控开关的第二端及第七可控开关的第二端并接收关闭电压端信号，第五可控开关的控制端连接第四可控开关的第一端及第六可控开关的控制端，第六可控开关的第一端连接第七可控开关的第一端及输出电路，第七可控开关的控制端接收第三时钟信号，第一电容的第一端连接第五可控开关的控制端，第一电容的第二端连接输出电路，第二电容连接在第六可控开关的控制端与第二端之间。
其中，防漏电电路包括第八至第十可控开关，第八可控开关的控制端接收第一时钟信号，第八可控开关的第一端连接第九可控开关的第一端并接收开启电压端信号，第八可控开关的第二端连接第九可控开关的第二端、第十可控开关的第二端及第三可控开关的控制端，第九可控开关的控制端接收第二时钟信号，第十可控开关的第一端接收关闭电压端信号，第十可控开关的控制端连接第一电容的第二端及输出电路。
其中，输出电路包括第十一可控开关及第三电容，第十一可控开关的控制端连接第三可控开关的第二端及第五可控开关的第一端，第十一可控开关的第一端连接第十可控开关的控制端及第一电容的第二端并接收第四时钟信号，第十一可控开关的第二端连接第六及第七可控开关的第一端及本级扫描线，第三电容连接在第十一可控开关的控制端与第二端之间。
其中，第一至第十一可控开关为N型薄膜晶体管，第一至第十一可控开关的控制端、第一端及第二端分别对应N型薄膜晶体管的栅极、漏极及源极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种平面显示装置，平面显示装置包括扫描驱动电路，扫描驱动电路包括级联的多个扫描驱动单元，每一扫描驱动单元包括：
正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制扫描驱动电路进行反向扫描；
输入电路，连接正反扫电路，用于接收第三时钟信号及从正反扫电路接收第一及第二控制信号并根据第三时钟信号、第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；
防漏电电路，连接输入电路，用于接收第一时钟信号及第二时钟信号并根据第一及第二时钟信号对输入电路的漏电进行处理；及
输出电路，连接输入电路，用于对接收到的第四控制信号及从输入电路接收的数据进行处理，产生扫描驱动信号输出给本级扫描线来驱动像素单元。
其中，正反扫电路包括第一及第二可控开关，第一可控开关的控制端接收第一时钟信号，第一可控开关的第一端接收上级扫描信号，第一可控开关的第二端连接第二可控开关的第一端及输入电路，第二可控开关的控制端接收第二时钟信号，第二可控开关的第二端接收下级扫描信号。
其中，输入电路包括第三至第七可控开关、第一及第二电容，第三可控开关的控制端连接防漏电电路，第三可控开关的第一端连接第四可控开关的控制端、第一可控开关的第二端及第二可控开关的第一端，第三可控开关的第二端连接第五可控开关的第一端及输出电路，第五可控开关的第二端连接第四可控开关的第二端、第六可控开关的第二端及第七可控开关的第二端并接收关闭电压端信号，第五可控开关的控制端连接第四可控开关的第一端及第六可控开关的控制端，第六可控开关的第一端连接第七可控开关的第一端及输出电路，第七可控开关的控制端接收第三时钟信号，第一电容的第一端连接第五可控开关的控制端，第一电容的第二端连接输出电路，第二电容连接在第六可控开关的控制端与第二端之间。
其中，防漏电电路包括第八至第十可控开关，第八可控开关的控制端接收第一时钟信号，第八可控开关的第一端连接第九可控开关的第一端并接收开启电压端信号，第八可控开关的第二端连接第九可控开关的第二端、第十可控开关的第二端及第三可控开关的控制端，第九可控开关的控制端接收第二时钟信号，第十可控开关的第一端接收关闭电压端信号，第十可控开关的控制端连接第一电容的第二端及输出电路。
其中，输出电路包括第十一可控开关及第三电容，第十一可控开关的控制端连接第三可控开关的第二端及第五可控开关的第一端，第十一可控开关的第一端连接第十可控开关的控制端及第一电容的第二端并接收第四时钟信号，第十一可控开关的第二端连接第六及第七可控开关的第一端及本级扫描线，第三电容连接在第十一可控开关的控制端与第二端之间。
本发明的有益效果是：区别于现有技术的情况，本发明的扫描驱动电路通过正反扫电路控制扫描驱动电路进行正向扫描及反向扫描，并通过输入电路对上拉控制信号点及下拉控制信号点进行充电，通过防漏电电路防止薄膜晶体管漏电造成扫描线输出信号不稳定，通过输出电路产生扫描驱动信号输出给扫描线来驱动像素单元，以有效解决由于薄膜晶体管漏电造成扫描线的输出信号不稳定的问题，以提高面板显示效果。
【附图说明】
图1是现有技术中扫描驱动电路的一个扫描驱动单元的电路图；
图2是图1的正向扫描波形图；
图3是图1的反向扫描波形图；
图4是本发明的扫描驱动电路的一个扫描驱动单元的第一实施例的电路图；
图5是图4的正向扫描波形图；
图6是图4的反向扫描波形图；
图7是本发明的平面显示装置的示意图。
【具体实施方式】
请参阅图1及图2，现有技术中扫描驱动电路的工作原理（正向扫描）如下：
预充电阶段：上级扫描信号Gn-1与时钟信号CKV1同时为高电平时，薄膜晶体管T1导通，H点被预充电，薄膜晶体管T5一直处于导通状态，上拉控制信号点Q被充电，当H点为高电平时，薄膜晶体管T6处于导通状态，下拉控制信号点P被拉低；
扫描线Gn输出高电平阶段：薄膜晶体管T5的栅极接收开启电压端信号VGH一直处于导通状态，在预充电阶段，上拉控制信号点Q被预充电，电容C3对电荷具有一定的保持作用，薄膜晶体管T2处于导通状态，时钟信号CKV2的高电平输出到扫描线Gn；
扫描线Gn输出低电平阶段：时钟信号CKV3与下级扫描信号Gn+1同时为高电平时，上拉控制信号点Q被保持在高电平，而此时时钟信号CKV2的低电平将扫描线Gn的电位拉低；
上拉控制信号点Q被拉低到关闭电压端信号VGL：当时钟信号CKV1再次变为高电平时，此时上级扫描信号Gn-1为低电平，薄膜晶体管T1处于导通状态，那么上拉控制信号点Q被拉低到关闭电压端VGL；
上拉控制信号点Q及扫描线Gn的低电平维持阶段：当上拉控制信号点Q变为低电平后，薄膜晶体管T6处于截止状态，当时钟信号CKV2变为高电平后，由于电容C1的耦合，下拉控制信号点P变为高电平，那么薄膜晶体管T4和T7均处于导通状态，可以保证上拉控制信号点Q及扫描线Gn的低电平的稳定。
请参阅图1及图3，现有技术中扫描驱动电路的工作原理（反向扫描）如下：
预充电阶段：下级扫描信号Gn+1与时钟信号CKV3同时为高电平时，薄膜晶体管T3导通，H点被预充电，薄膜晶体管T5一直处于导通状态，上拉控制信号点Q被充电，当H点为高电平时，薄膜晶体管T6处于导通状态，下拉控制信号点P被拉低；
扫描线Gn输出高电平阶段：薄膜晶体管T5的栅极接收开启电压端信号VGH一直处于导通状态，在预充电阶段，上拉控制信号点Q被预充电，电容C3对电荷具有一定的保持作用，薄膜晶体管T2处于导通状态，时钟信号CKV2的高电平输出到扫描线Gn；
扫描线Gn输出低电平阶段：时钟信号CKV1与上级扫描信号Gn-1同时为高电平时，上拉控制信号点Q被保持在高电平，而此时时钟信号CKV2的低电平将扫描线Gn的电位拉低；
上拉控制信号点Q被拉低到关闭电压端信号VGL阶段：当时钟信号CKV3再次变为高电平时，此时下级扫描信号Gn+1为低电平，薄膜晶体管T3处于导通状态，上拉控制信号点Q被拉低到关闭电压端信号VGL；
上拉控制信号点Q及扫描线Gn的低电平维持阶段：当上拉控制信号点Q变为低电平后，薄膜晶体管T6处于截止状态，当时钟信号CKV2变为高电平后，由于电容C1的耦合，下拉控制信号点P变为高电平，薄膜晶体管T4和T7均处于导通状态，可以保证上拉控制信号点Q及扫描线Gn的低电平的稳定。
在现有的扫描驱动电路中，为了防止时钟信号CKV2由低电平变高电平时，电容C1将上拉控制信号点Q自举为更高电平时对薄膜晶体管T6造成严重影响，而设置了薄膜晶体管T5，当H点被预充电时，薄膜晶体管T5一直处于打开的状态，那么上拉控制信号点Q同时也会被预充电，当时钟信号CKV2由低电平变高电平时，电容C1的自举作用会将上拉控制信号点Q再次提高，而此时薄膜晶体管T5的栅极与源极之间的电压Vgs等于0V，当薄膜晶体管的开关特性良好时，那么H点将继续维持预充电时对应的高电位，上拉控制信号点Q也将会继续保持电容C1自举后的高电位，薄膜晶体管T6不会因为电容C1将上拉控制信号点Q自举到更高电位而造成严重影响，然而由于制程原因造成薄膜晶体管的开关特性变差时，薄膜晶体管T5 处于严重的漏电状态，那么上拉控制信号点Q在电容C1自举之后会被H点电位拉低，造成扫描线Gn的输出信号不稳定，进而影响面板的显示效果。
请参阅图4，是本发明的扫描驱动电路的一个扫描驱动单元的第一实施例的结构示意图。在本实施方式中，仅以一个扫描驱动单元为例进行说明。如图4所示，本发明的扫描驱动电路包括级联的多个扫描驱动单元，每一扫描驱动单元包括正反扫电路100，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制扫描驱动电路进行反向扫描；
输入电路200，连接正反扫电路100，用于接收第三时钟信号及从正反扫电路接收第一及第二控制信号并根据第三时钟信号、第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；
防漏电电路300，连接输入电路200，用于接收第一时钟信号及第二时钟信号并根据第一及第二时钟信号对输入电路的漏电进行处理；及
输出电路400，连接输入电路200，用于对接收到的第四控制信号及从输入电路200接收的数据进行处理，产生扫描驱动信号输出给本级扫描线来驱动像素单元。
正反扫电路100包括第一可控开关T1及第二可控开关T2，第一可控开关T1的控制端接收第一时钟信号，第一可控开关T1的第一端接收上级扫描信号，第一可控开关T1的第二端连接第二可控开关T2的第一端及输入电路200，第二可控开关T2的控制端接收第二时钟信号，第二可控开关T2的第二端接收下级扫描信号。
输入电路200包括第三至第七可控开关T3-T7、第一及第二电容C1、C2，第三可控开关T3的控制端连接防漏电电路300，第三可控开关T3的第一端连接第四可控开关T4的控制端、第一可控开关T1的第二端及第二可控开关T2的第一端，第三可控开关T3的第二端连接第五可控开关T5的第一端及输出电路400，第五可控开关T5的第二端连接第四可控开关T4的第二端、第六可控开关T6的第二端及第七可控开关T7的第二端并接收关闭电压端信号VGL，第五可控开关T5的控制端连接第四可控开关T4的第一端及第六可控开关T6的控制端，第六可控开关T6的第一端连接第七可控开关T7的第一端及输出电路400，第七可控开关T7的控制端接收第三时钟信号，第一电容C1的第一端连接第五可控开关T5的控制端，第一电容C1的第二端连接输出电路400，第二电容C2连接在第六可控开关T6的控制端与第二端之间。
防漏电电路300包括第八至第十可控开关T8-T10，第八可控开关T8的控制端接收第一时钟信号，第八可控开关T8的第一端连接第九可控开关T9的第一端并接收开启电压端信号VGH，第八可控开关T8的第二端连接第九可控开关T9的第二端、第十可控开关T10的第二端及第三可控开关T3的控制端，第九可控开关T9的控制端接收第二时钟信号，第十可控开关T10的第一端接收关闭电压端信号VGL，第十可控开关T10的控制端连接第一电容C1的第二端及输出电路400。
输出电路400包括第十一可控开关T11及第三电容C3，第十一可控开关T11的控制端连接第三可控开关T3的第二端及第五可控开关T5的第一端，第十一可控开关T11的第一端连接第十可控开关T10的控制端及第一电容C1的第二端并接收第四时钟信号，第十一可控开关T11的第二端连接第六及第七可控开关T6、T7的第一端及本级扫描线，第三电容C3连接在第十一可控开关T11的控制端与第二端之间。
在本实施例中，第一至第十一可控开关T1-T11为N型薄膜晶体管，第一至第十一可控开关T1-T11的控制端、第一端及第二端分别对应N型薄膜晶体管的栅极、漏极及源极。在其他实施例中，第一至第十一可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
在本实施例中，上级扫描信号为上级扫描信号Gn-1，下级扫描信号为下级扫描信号Gn+1，第一时钟信号为时钟信号CKV1，第二时钟信号为时钟信号CKV3，第三时钟信号为时钟信号CKV4，第四时钟信号为时钟信号CKV2，上拉控制信号点为上拉控制信号点Q，下拉控制信号点为下拉控制信号点P。
请参阅图4及图5，可以得到扫描驱动电路的一个扫描驱动单元的工作原理（正向扫描）如下：
预充电阶段：上级扫描信号Gn-1与第一时钟信号CKV1同时为高电平时，第一可控开关T1导通，H点被预充电，第一时钟信号CKV1为高电平，第八可控开关T8处于导通状态，N点为高电平，第三可控开关T3导通，上拉控制信号点Q被充电，当H点为高电平时，第四可控开关T4处于导通状态，下拉控制信号点P被拉低；
扫描线Gn输出高电平阶段：当第四时钟信号CKV2由低电平变为高电平时，由于第一电容C1的自举作用上拉控制信号点Q会被再次提高，而此时第一时钟信号CKV1与第二时钟信号CKV3均为低电平，第八可控开关T8和第九可控开关T9均处于关闭状态，第十可控开关T10处于导通状态，N点被拉低到关闭电压端信号VGL，第三可控开关T3处于关闭状态，由于第三电容C3对电荷具有一定的保持作用，十一可控开关T11处于导通状态，第四时钟信号CKV2的高电平输出到扫描线Gn；
扫描线Gn输出低电平阶段：第二时钟信号CKV3与下级扫描信号Gn+1同时为高电平时，H点被保持在高电位，第二时钟信号CKV3为高电平，第九可控开关T9处于导通状态，N点为高电平，第三可控开关T3导通，上拉控制信号点Q被充电，而此时第四时钟信号CKV2的低电平将扫描线Gn的电位拉低；
上拉控制信号点Q被拉低到关闭电压端信号VGL：当第一时钟信号CKV1再次变为高电平时，此时下级扫描信号Gn-1为低电平，第一可控开关T1及第八可控开关T8处于导通状态，那么上拉控制信号点Q被拉低到关闭电压端信号VGL；
上拉控制信号点Q及扫描线Gn的低电平维持阶段：当上拉控制信号点Q变为低电平后，第四可控开关T4处于截止状态，当第四时钟信号CKV2变为高电平后，由于第一电容C1的耦合，下拉控制信号点P变为高电平，那么第六可控开关T6和第五可控开关T5均处于导通状态，可以保证上拉控制信号点Q及扫描线Gn的低电平的稳定。
请参阅图4及图6，可以得到扫描驱动电路的一个扫描驱动单元的工作原理（反向扫描）如下：
预充电阶段：下级扫描信号Gn+1与第二时钟信号CKV3同时为高电平时，第二可控开关T2导通，H点被预充电，第二时钟信号CKV3为高电平，第九可控开关T9处于导通状态，N点为高电平，第三可控开关T3导通，上拉控制信号点Q被充电，当H点为高电平时，第四可控开关T4处于导通状态，下拉控制信号点P被拉低；
扫描线Gn输出高电平阶段：当第四时钟信号CKV2由低电平变为高电平时，由于第一电容C1的自举作用使得上拉控制信号点Q被再次充电，而此时第一时钟信号CKV1与第二时钟信号CKV3均为低电平，第八可控开关T8和第九可控开关T9均处于关闭状态，而此时第十可控开关T10处于导通状态，N点被拉低到关闭的电压端信号VGL，第三可控开关T3处于关闭状态，第三电容C3对电荷具有一定的保持作用，第十一可控开关T11处于导通状态，第四时钟信号CKV2的高电平输出到扫描线Gn；
扫描线Gn输出低电平阶段：第一时钟信号CKV1与上级扫描信号Gn-1同时为高电平时，H点被保持在高电位，第一时钟信号CKV1为高电平时，第八可控开关T8处于导通状态，N点为高电平，第三可控开关T3导通，上拉控制信号点Q被充电，而此时第四时钟信号CKV2的低电平将扫描线Gn的电位拉低；
上拉控制信号点Q被拉低到关闭电压端信号VGL：当第二时钟信号CKV3再次变为高电平时，此时下级扫描信号Gn+1为低电平，第二可控开关T2及第九可控开关T9处于导通状态，那么上拉控制信号点Q被拉低到关闭电压端信号VGL；
上拉控制信号点Q及扫描线Gn的低电平维持阶段：当上拉控制信号点Q变为低电平后，第四可控开关T4处于截止状态，当第四时钟信号CKV2变为高电平后，由于第一电容C1的耦合，下拉控制信号点P变为高电平，那么第六可控开关T6和第五可控开关T5均处于导通状态，可以保证上拉控制信号点Q及扫描线Gn的低电平的稳定。
当第一时钟信号CKV1与下级扫描信号Gn-1同时为高电平时，H点被预充电，此时第八可控开关T8也处于导通状态，N为高电平，那么第三可控开关T3也会处于导通状态，上拉控制信号点Q会被H点充电，当第四时钟信号CKV2由低电平变为高电平时，由于第一电容C1的自举作用上拉控制信号点Q会被再次充电，而此时第一时钟信号CKV1与第二时钟信号CKV3均为低电平，第八可控开关T8和第九可控开关T9均处于关闭状态，而此时第十可控开关T10处于导通状态，N点被拉低到关闭电压端信号VGL，第三可控开关T3处于关闭状态，这样可以保证上拉控制信号点Q的高电位不会受H点的影响，同时上拉控制信号点Q的高电位也不会对第四可控开关T4造成影响，当第二时钟信号CKV3与下级扫描信号Gn+1同时为高电平时，H点再次被充电，而此时第九可控开关T9处于导通状态，N点被拉高，第三可控开关T3处于导通状态，上拉控制信号点Q的高电平继续维持，以有效解决当第三可控开关T3存在漏电时造成上拉控制信号点Q电位降低，进而造成扫描线Gn输出信号不稳定的问题，以提高面板显示效果。
请参阅图7，为本发明一种平面显示装置的示意图。平面显示装置包括前述的扫描驱动电路，扫描驱动电路设置在平面显示装置的两端。其中，平面显示装置为LCD或OLED。平面显示装置的其他器件及功能与现有平面显示装置的器件及功能相同，在此不再赘述。
本发明的扫描驱动电路通过正反扫电路控制扫描驱动电路进行正向扫描及反向扫描，并通过输入电路对上拉控制信号点及下拉控制信号点进行充电，通过防漏电电路防止薄膜晶体管漏电造成扫描线输出信号不稳定，通过输出电路产生扫描驱动信号输出给扫描线来驱动像素单元，以有效解决由于薄膜晶体管漏电造成扫描线的输出信号不稳定的问题，以提高面板显示效果。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
    输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；
    防漏电电路，连接所述输入电路，用于接收所述第一时钟信号及所述第二时钟信号并根据所述第一及第二时钟信号对所述输入电路的漏电进行处理；及
    输出电路，连接所述输入电路，用于对接收到的第四控制信号及从所述输入电路接收的数据进行处理，产生扫描驱动信号输出给本级扫描线来驱动像素单元。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述输入电路包括第三至第七可控开关、第一及第二电容，所述第三可控开关的控制端连接所述防漏电电路，所述第三可控开关的第一端连接所述第四可控开关的控制端、所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述第五可控开关的第一端及所述输出电路，所述第五可控开关的第二端连接所述第四可控开关的第二端、所述第六可控开关的第二端及所述第七可控开关的第二端并接收关闭电压端信号，所述第五可控开关的控制端连接所述第四可控开关的第一端及所述第六可控开关的控制端，所述第六可控开关的第一端连接所述第七可控开关的第一端及所述输出电路，所述第七可控开关的控制端接收所述第三时钟信号，所述第一电容的第一端连接所述第五可控开关的控制端，所述第一电容的第二端连接所述输出电路，所述第二电容连接在所述第六可控开关的控制端与第二端之间。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述防漏电电路包括第八至第十可控开关，所述第八可控开关的控制端接收所述第一时钟信号，所述第八可控开关的第一端连接所述第九可控开关的第一端并接收开启电压端信号，所述第八可控开关的第二端连接所述第九可控开关的第二端、所述第十可控开关的第二端及所述第三可控开关的控制端，所述第九可控开关的控制端接收所述第二时钟信号，所述第十可控开关的第一端接收关闭电压端信号，所述第十可控开关的控制端连接所述第一电容的第二端及所述输出电路。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述输出电路包括第十一可控开关及第三电容，所述第十一可控开关的控制端连接所述第三可控开关的第二端及所述第五可控开关的第一端，所述第十一可控开关的第一端连接所述第十可控开关的控制端及所述第一电容的第二端并接收所述第四时钟信号，所述第十一可控开关的第二端连接所述第六及第七可控开关的第一端及本级扫描线，所述第三电容连接在所述第十一可控开关的控制端与第二端之间。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述第一至第十一可控开关为N型薄膜晶体管，所述第一至第十一可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  7. 一种平面显示装置，其中，所述平面显示装置包括扫描驱动电路，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
    输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；
    防漏电电路，连接所述输入电路，用于接收所述第一时钟信号及所述第二时钟信号并根据所述第一及第二时钟信号对所述输入电路的漏电进行处理；及
    输出电路，连接所述输入电路，用于对接收到的第四控制信号及从所述输入电路接收的数据进行处理，产生扫描驱动信号输出给本级扫描线来驱动像素单元。
  8. 根据权利要求7所述的平面显示装置，其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
  9. 根据权利要求8述的平面显示装置，其中，所述输入电路包括第三至第七可控开关、第一及第二电容，所述第三可控开关的控制端连接所述防漏电电路，所述第三可控开关的第一端连接所述第四可控开关的控制端、所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述第五可控开关的第一端及所述输出电路，所述第五可控开关的第二端连接所述第四可控开关的第二端、所述第六可控开关的第二端及所述第七可控开关的第二端并接收关闭电压端信号，所述第五可控开关的控制端连接所述第四可控开关的第一端及所述第六可控开关的控制端，所述第六可控开关的第一端连接所述第七可控开关的第一端及所述输出电路，所述第七可控开关的控制端接收所述第三时钟信号，所述第一电容的第一端连接所述第五可控开关的控制端，所述第一电容的第二端连接所述输出电路，所述第二电容连接在所述第六可控开关的控制端与第二端之间。
  10. 根据权利要求9所述的平面显示装置，其中，所述防漏电电路包括第八至第十可控开关，所述第八可控开关的控制端接收所述第一时钟信号，所述第八可控开关的第一端连接所述第九可控开关的第一端并接收开启电压端信号，所述第八可控开关的第二端连接所述第九可控开关的第二端、所述第十可控开关的第二端及所述第三可控开关的控制端，所述第九可控开关的控制端接收所述第二时钟信号，所述第十可控开关的第一端接收关闭电压端信号，所述第十可控开关的控制端连接所述第一电容的第二端及所述输出电路。
  11. 根据权利要求10所述的平面显示装置，其中，所述输出电路包括第十一可控开关及第三电容，所述第十一可控开关的控制端连接所述第三可控开关的第二端及所述第五可控开关的第一端，所述第十一可控开关的第一端连接所述第十可控开关的控制端及所述第一电容的第二端并接收所述第四时钟信号，所述第十一可控开关的第二端连接所述第六及第七可控开关的第一端及本级扫描线，所述第三电容连接在所述第十一可控开关的控制端与第二端之间。
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