WO2016095262A1 - 一种扫描驱动电路 - Google Patents

一种扫描驱动电路 Download PDF

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Publication number
WO2016095262A1
WO2016095262A1 PCT/CN2014/095318 CN2014095318W WO2016095262A1 WO 2016095262 A1 WO2016095262 A1 WO 2016095262A1 CN 2014095318 W CN2014095318 W CN 2014095318W WO 2016095262 A1 WO2016095262 A1 WO 2016095262A1
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WO
WIPO (PCT)
Prior art keywords
switch tube
pull
scan
signal
module
Prior art date
Application number
PCT/CN2014/095318
Other languages
English (en)
French (fr)
Inventor
肖军城
Original Assignee
深圳市华星光电技术有限公司
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Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/416,558 priority Critical patent/US9501990B2/en
Publication of WO2016095262A1 publication Critical patent/WO2016095262A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display driving, and more particularly to a scan driving circuit.
  • Gate Driver On Array is a driving circuit for forming a scan driving circuit on an array substrate of an existing thin film transistor liquid crystal display to realize progressive scanning of a scanning line.
  • a schematic diagram of a conventional scan driving circuit is shown in FIG. 1.
  • the scan driving circuit 10 includes a pull-up control module 101, a pull-up module 102, a downlink module 103, a pull-down module 104, a bootstrap capacitor 105, and a pull-down maintaining module 106.
  • the above-mentioned scan driving circuit generally uses an NMOS (N-Mental-Oxide-Semiconductor) type transistor, but the NMOS transistor used in the lithography operation has a high manufacturing cost. Moreover, the overall circuit structure of the scan driving circuit is relatively complicated and consumes a large amount of energy.
  • NMOS N-Mental-Oxide-Semiconductor
  • the object of the present invention is to provide a scan driving circuit with a simple structure and low power consumption, so as to solve the technical problem that the structure of the conventional scan driving circuit is complicated and consumes a large amount of energy.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of a previous stage, and generate a scan level signal of a low level of the scan line according to the scan signal of the previous stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal and the first clock signal
  • a pull-up module configured to pull up a scan signal of the corresponding scan line according to the low level signal and the high level signal
  • a pull-up maintaining module configured to maintain a high level of a scan level signal of the corresponding scan line according to the low level signal and the high level signal
  • a bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • the scan driving circuit controls the pull-down control module, the pull-down module, the pull-up module, and the pull-up maintaining module using a P-type metal oxide semiconductor type transistor;
  • the pull-down control module includes a first switch tube, a control end of the first switch tube inputs a scan signal of the upper stage, and an input end of the first switch tube inputs a scan signal of a low level; An output end of the first switch tube is respectively connected to the pull-down module, the pull-up maintaining module, and the bootstrap capacitor;
  • the pull-up maintaining module includes a second potential maintaining capacitor, one end of the second potential maintaining capacitor is connected to the constant voltage high level source, and the other end of the second potential maintaining capacitor is opposite to the first switch The output of the tube is connected.
  • the pull-down module includes a second switch tube, and a control end of the second switch tube is connected to an output end of the first switch tube of the pull-down control module, the second The input end of the switch tube inputs a first clock signal, and the output end of the second switch tube outputs a scan signal of the current stage.
  • the pull-up module includes a third switch tube, and a control end of the third switch tube is connected to the constant voltage low level source, and an input of the third switch tube The terminal is connected to the constant voltage high level source, and the output end of the third switch tube is connected to the output end of the second switch tube.
  • the pull-up maintaining module further includes a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor;
  • a control end of the fourth switch tube is connected to an input end of the second switch tube, an input end of the fourth switch tube is connected to an output end of the fifth switch tube, and an output of the fourth switch tube The end is connected to the output end of the first switch tube;
  • a control end of the fifth switch tube is connected to an output end of the seventh switch tube, and an input end of the fifth switch tube is connected to the constant voltage high level source;
  • a control end of the sixth switch tube is connected to an output end of the first switch tube, an input end of the sixth switch tube is connected to the constant voltage high level source, and an output end of the sixth switch tube Connected to an output end of the seventh switch tube;
  • the control end of the seventh switch tube inputs a second clock signal, the input end of the seventh switch tube is connected to the constant voltage low level source, and the output end of the seventh switch tube and the third switch The control end of the tube is connected.
  • the second clock signal and the first clock signal are inverted clock signals.
  • the pull-down control module further includes an eighth switch tube, wherein the control end of the eighth switch tube inputs a scan signal of the next stage, and the input end of the eighth switch tube inputs a low level scan signal, the output end of the eighth switch tube being respectively connected to the pull-down module, the pull-up maintaining module, and the bootstrap capacitor.
  • the pull-up maintaining module further includes a first potential maintaining capacitor, and one end of the first potential maintaining capacitor is connected to the constant voltage high level source, the first potential The other end of the sustain capacitor is connected to the output of the seventh switch.
  • the pull-down control module includes a first switch tube and a ninth switch tube;
  • a control signal of the first switch tube inputs a scan signal of a low level, an input end of the first switch tube inputs a scan signal of the upper stage; an output end of the first switch tube and the ninth Connecting the input end of the switch tube;
  • the control end of the ninth switch tube inputs a second clock signal; the output end of the ninth switch tube is respectively connected to the pull-down module, the pull-up maintaining module, and the bootstrap capacitor.
  • the second clock signal and the first clock signal are inverted clock signals.
  • the pull-down control module further includes an eighth switch tube
  • a control signal of the eighth switch tube inputs a scan signal of a low level, an input end of the eighth switch tube inputs a scan signal of a next stage; an output end of the eighth switch tube and the ninth switch tube The input is connected.
  • the embodiment of the present invention further provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of a previous stage, and generate a scan level signal of a low level of the scan line according to the scan signal of the previous stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal and the first clock signal
  • a pull-up module configured to pull up a scan signal of the corresponding scan line according to the low level signal and the high level signal
  • a pull-up maintaining module configured to maintain a high level of a scan level signal of the corresponding scan line according to the low level signal and the high level signal
  • a bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • the scan driving circuit controls the pull-down control module, the pull-down module, the pull-up module, and the pull-up maintaining module using a P-type metal oxide semiconductor type transistor.
  • the pull-down control module includes a first switch tube, and a control end of the first switch tube inputs a scan signal of the upper stage, and an input end of the first switch tube And inputting a scan signal of a low level; an output end of the first switch tube is respectively connected to the pull-down module, the pull-up maintaining module, and the bootstrap capacitor.
  • the pull-down module includes a second switch tube, and a control end of the second switch tube is connected to an output end of the first switch tube of the pull-down control module, the second The input end of the switch tube inputs a first clock signal, and the output end of the second switch tube outputs a scan signal of the current stage.
  • the pull-up module includes a third switch tube, and a control end of the third switch tube is connected to the constant voltage low level source, and an input of the third switch tube The terminal is connected to the constant voltage high level source, and the output end of the third switch tube is connected to the output end of the second switch tube.
  • the pull-up maintaining module includes a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor;
  • a control end of the fourth switch tube is connected to an input end of the second switch tube, an input end of the fourth switch tube is connected to an output end of the fifth switch tube, and an output of the fourth switch tube The end is connected to the output end of the first switch tube;
  • a control end of the fifth switch tube is connected to an output end of the seventh switch tube, and an input end of the fifth switch tube is connected to the constant voltage high level source;
  • a control end of the sixth switch tube is connected to an output end of the first switch tube, an input end of the sixth switch tube is connected to the constant voltage high level source, and an output end of the sixth switch tube Connected to an output end of the seventh switch tube;
  • the control end of the seventh switch tube inputs a second clock signal, the input end of the seventh switch tube is connected to the constant voltage low level source, and the output end of the seventh switch tube and the third switch The control end of the tube is connected;
  • the second clock signal and the first clock signal are reverse clock signals.
  • the pull-down control module further includes an eighth switch tube, wherein the control end of the eighth switch tube inputs a scan signal of the next stage, and the input end of the eighth switch tube inputs a low level scan signal, the output end of the eighth switch tube being respectively connected to the pull-down module, the pull-up maintaining module, and the bootstrap capacitor.
  • the pull-up maintaining module further includes a first potential maintaining capacitor, and one end of the first potential maintaining capacitor is connected to the constant voltage high level source, the first potential The other end of the sustain capacitor is connected to the output of the seventh switch.
  • the pull-up maintaining module further includes a second potential maintaining capacitor, one end of the second potential maintaining capacitor is connected to the constant voltage high level source, and the second potential The other end of the sustaining capacitor is connected to the output of the first switching transistor.
  • the pull-down control module includes a first switch tube and a ninth switch tube;
  • a control signal of the first switch tube inputs a scan signal of a low level, an input end of the first switch tube inputs a scan signal of the upper stage; an output end of the first switch tube and the ninth Connecting the input end of the switch tube;
  • the control end of the ninth switch tube inputs a second clock signal; the output end of the ninth switch tube is respectively connected to the pull-down module, the pull-up maintaining module, and the bootstrap capacitor;
  • the second clock signal and the first clock signal are reverse clock signals.
  • the pull-down control module includes an eighth switch tube and a ninth switch tube;
  • a control signal of the eighth switch tube inputs a scan signal of a low level, an input end of the eighth switch tube inputs a scan signal of a next stage; an output end of the eighth switch tube and the ninth switch tube The input is connected.
  • the scan driving circuit of the present invention controls each module by using a P-type metal oxide semiconductor type transistor, so that the overall structure of the scan driving circuit is simple and the power consumption is small; The technical problem of the structure of the scan driving circuit is complicated and the power consumption is large.
  • 1 is a schematic structural view of a conventional scan driving circuit
  • FIG. 2 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 3 is a signal waveform diagram of a first preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 4 is a schematic structural view of a second preferred embodiment of a scan driving circuit of the present invention.
  • FIG. 5 is a schematic structural view of a third preferred embodiment of a scan driving circuit of the present invention.
  • Figure 6 is a block diagram showing the structure of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 2 is a schematic structural view of a first preferred embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit 20 of the preferred embodiment is configured to perform driving operations on the cascaded scan lines, including a pull-down control module 21, a pull-down module 22, a pull-up module 23, a pull-up maintaining module 24, a bootstrap capacitor C1, and a constant voltage.
  • the pull-down control module 21 is configured to receive the scan signal G(N-1) of the previous stage, and generate a scan level signal Q of a low level of the corresponding scan line according to the scan signal G(N-1) of the previous stage.
  • the pull-down module 22 is configured to pull down the scan signal G(N) of the corresponding scan line according to the scan level signal Q(N) and the first clock signal CK;
  • the pull-up module 23 is configured to be based on the low level signal The VGL and the high level signal VGH pull up the scan signal G(N) of the corresponding scan line;
  • the pull-up maintaining module 24 is configured to maintain the scan power of the corresponding scan line according to the low level signal VGL and the high level signal VGH.
  • the high level of the flat signal Q(N); the bootstrap capacitor C1 is used to generate the low level or the high level of the scan level signal Q(N) of the scan line; the constant voltage low level source is used to provide the low level Signal VGL; a constant voltage high level source is used to provide a high level signal VGH.
  • the scan driving circuit 20 of the preferred embodiment controls the pull-down control module 21, the pull-down module 22, the pull-up module 23, and the pull-up sustaining module 24 using transistors of the P-type metal oxide semiconductor type.
  • the pull-down control module 21 includes a first switch tube T1.
  • the control end of the first switch tube T1 inputs the scan signal G(N-1) of the previous stage, and the input end of the first switch tube T1 inputs the scan signal U2D of the low level.
  • the output ends of the first switching transistor T1 are respectively connected to the pull-down module 22, the pull-up maintaining module 23, and the bootstrap capacitor C1.
  • the pull-down module 22 includes a second switch tube T2, the control end of the second switch tube T2 is connected to the output end of the first switch tube T1 of the pull-down control module 21, and the input end of the second switch tube T2 is input with the first clock signal CK.
  • the output end of the second switch T2 outputs the scan signal G(N) of the current stage.
  • the pull-up module 23 includes a third switch tube T3, the control end of the third switch tube T3 is connected to the constant voltage low level source, the input end of the third switch tube T3 is connected to the constant voltage high level source, and the third switch tube T3 The output is connected to the output of the second switching transistor T2.
  • the pull-up maintaining module 24 includes a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, a seventh switching transistor T7, and a first potential holding capacitor C2.
  • the control end of the fourth switch tube T4 is connected to the input end of the second switch tube T2, the input end of the fourth switch tube T4 is connected to the output end of the fifth switch tube T5, and the output end of the fourth switch tube T4 is connected to the first switch The output of the tube T1 is connected.
  • the control end of the fifth switch tube T5 is connected to the output end of the seventh switch tube T7, and the input end of the fifth switch tube T5 is connected to the constant voltage high level source.
  • the control end of the sixth switch tube T6 is connected to the output end of the first switch tube T1
  • the input end of the sixth switch tube T6 is connected to the constant voltage high level source
  • the output end of the sixth switch tube T6 and the seventh switch tube T7 The output is connected.
  • the control end of the seventh switch tube T7 inputs a second clock signal XCK, the input end of the seventh switch tube T7 is connected to the constant voltage low level source, and the output end of the seventh switch tube T7 is connected to the control end of the third switch tube T3. .
  • One end of the first potential maintaining capacitor C2 is connected to the constant voltage high level source, and the other end of the first potential maintaining capacitor C2 is connected to the output end of the seventh switching transistor T7.
  • the first clock signal CK and the second clock signal XCK are inverted clock signals.
  • the bootstrap capacitor C1 is disposed between the output of the first switching transistor T1 and the output of the second switching transistor T2 of the pull-down module 22.
  • the second switching transistor T2 is turned on, but since the first clock signal CK is at a high level, the scanning signal G(N) is still at a high level.
  • the sixth switch tube T6 is turned on, the third switch tube T3 and the fifth switch tube T5 are disconnected by the high level signal VGH, and the fourth switch tube T4 is turned off by the first clock signal CK.
  • the scan signal G(N-1) of the previous stage is turned to a high level
  • the first clock signal CK is turned to a low level
  • the second clock signal XCK is turned to a high level
  • the first switch tube T1 is turned off
  • the first The second switch T2 is still turned on by the bootstrap capacitor C1, so the scan signal G(N) is turned to a low level by the second switch T2 under the action of the first clock signal CK.
  • the scanning level signal Q(N) of the scanning line is pulled down to a low potential by the action of the scanning signal G(N) and the bootstrap capacitor C1, so that the potential of the scanning level signal Q(N) at this stage is lower.
  • the sixth switch tube T6 is turned on, the third switch tube T3 and the fifth switch tube T5 are still disconnected by the high level signal VGH, and the fourth switch tube T4 is guided by the first clock signal CK. through.
  • the first clock signal CK is turned to a high level
  • the second clock signal XCK is turned to a low level.
  • the seventh switch tube T7 is turned on by the second clock signal
  • the third switch tube T3 and the fifth switch are turned on.
  • the tube T5 is turned on by the low level signal VGL, so that the scan signal G(N) is pulled high by the high level signal HGL through the third switching tube T3, thereby scanning the scanning line level through the bootstrap capacitor C1.
  • the signal Q(N) is also pulled high.
  • the fourth switching transistor T4 is turned off by the first clock signal CK
  • the first switching transistor T1 is also turned off by the scanning signal G(N-1) of the previous stage, so the scanning level of the scanning line
  • the signal Q(N) can be held high, so that the scan signal G(N) also remains high.
  • the first clock signal CK is turned to a low level
  • the second clock signal XCK is turned to a high level.
  • the fourth switch tube T4 is turned on by the first clock signal CK
  • the fifth switch tube T5 is at the first stage.
  • the potential maintaining capacitor C2 is also turned on, so that the scan level signal Q(N) of the scan line can receive the high level signal VGH through the fourth switch tube T4 and the fifth switch tube T5, thereby maintaining a high level.
  • the scan signal G(N) also remains high.
  • the scan level signal Q(N) and the scan signal G(N) of the scan line are kept at a high level (through the third switch tube T3 or through the fourth switch tube T4 and the fifth switch tube T5) until the first switch
  • the tube T1 is turned on, and is turned to a low level by the low-level scan signal U2D.
  • the scan driving circuit of the present invention controls each module using a P-type metal oxide semiconductor type transistor, so that the overall structure of the scan driving circuit is simple and the power consumption is small.
  • FIG. 4 is a schematic structural view of a second preferred embodiment of the scan driving circuit of the present invention.
  • the pull-up maintaining module 44 of the scan driving circuit 40 of the preferred embodiment further includes a second potential maintaining capacitor C3, and the second potential sustaining capacitor C3 has one end and a constant voltage high level source. Connected, the other end of the second potential maintaining capacitor C3 is connected to the output end of the first switching transistor T1.
  • the design of the second potential maintaining capacitor C3 can prevent the scanning level signal Q(N) from leaking through other switching tubes, so the level signal Q(N) can be maintained by the second potential maintaining capacitor C3 and the high level signal HGL. High potential.
  • FIG. 5 is a schematic structural diagram of a third preferred embodiment of the scan driving circuit of the present invention.
  • the pull-down control module 51 of the scan driving circuit 50 of the preferred embodiment further includes an eighth switch tube T8, and the control end of the eighth switch tube T8 inputs the scan signal G of the next stage. +1), the input end of the eighth switch T8 inputs a low-level scan signal D2U, and the output end of the eighth switch T8 is connected to the pull-down module 22, the pull-up maintaining module 24, and the bootstrap capacitor C1, respectively.
  • the scan driving circuit 50 of the preferred embodiment can implement the reverse scanning function through the eighth switching transistor T8, so that the scanning signal G(N) of the current stage can be pulled down by the scanning signal G(N+1) of the next stage.
  • FIG. 6 is a schematic structural view of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • the pull-down control module 61 of the scan driving circuit 60 of the preferred embodiment includes a first switching transistor T1, a ninth switching transistor T9, and an eighth switching transistor T8.
  • the control end of the first switch tube T1 inputs a scan signal U2D of a low level
  • the input end of the first switch tube T1 inputs the scan signal G(N-1) of the previous stage
  • the input end of the switch tube T9 is connected.
  • the control terminal of the ninth switch T9 inputs a second clock signal XCK
  • the output of the ninth switch T9 is respectively connected to the pull-down module 22, the pull-up maintaining module 24, and the bootstrap capacitor C1, wherein the second clock signal XCK and the first The clock signal CK is a reverse clock pulse signal.
  • the control end of the eighth switch tube T8 inputs a low-level scan signal D2U, the input end of the eighth switch tube T8 inputs the scan signal G(N+1) of the next stage, and the output end of the eighth switch tube T8 and the ninth The input end of the switch tube T9 is connected.
  • the first switching tube and the ninth switching tube of the preferred embodiment implement the function of the first switching tube in the first preferred embodiment, and the eighth switching tube and the ninth switching tube implement the eighth in the third preferred embodiment The role of the switch tube.
  • the specific working principle of the scan driving circuit of the preferred embodiment is the same as or similar to that of the scanning operation circuit of the first preferred embodiment and the third preferred embodiment described above.
  • the first switch tube and the eighth switch tube in the scan driving circuit of the preferred embodiment are always in an on state, and the stability of the low level of the output of the pull-down control module can be ensured.
  • the scan driving circuit of the invention uses P-type metal oxide semiconductor type transistors to control each module, so that the overall structure of the scan driving circuit is simple, and the energy consumption is small, so that the narrow frame design of the corresponding liquid crystal display device can be better realized.
  • the invention solves the technical problem that the structure of the existing scan driving circuit is complicated and consumes a large amount of energy.

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Abstract

一种扫描驱动电路（20），用于对级联的扫描线进行驱动操作，其整体结构简单，且能耗较小，包括下拉控制模块（21）、下拉模块（22）、上拉模块（23）、上拉维持模块（24）、自举电容（C1）、恒压低电平源以及恒压高电平源；其中扫描驱动电路（20）使用P型金属氧化物半导体类型的晶体管控制下拉控制模块（21）、下拉模块（22）、上拉模块（23）以及上拉维持模块（24）。

Description

一种扫描驱动电路 技术领域
本发明涉及显示驱动领域，特别是涉及一种扫描驱动电路。
 背景技术
Gate Driver On Array，简称GOA，即在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。现有扫描驱动电路的结构示意图如图1所示，该扫描驱动电路10包括上拉控制模块101、上拉模块102、下传模块103、下拉模块104、自举电容105以及下拉维持模块106。
上述扫描驱动电路一般使用NMOS（N型金属-氧化物-半导体，N-Mental-Oxide-Semiconductor）类型的晶体管，但是NMOS的晶体管在制作时，光刻操作使用的光罩的制作成本较高，且扫描驱动电路的总体电路结构较为复杂，能耗较大。
故，有必要提供一种扫描驱动电路，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种结构简单且能耗较小的扫描驱动电路，以解决现有的扫描驱动电路的结构复杂且能耗较大的技术问题。
 技术解决方案
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号以及第一时钟信号，拉低相应的所述扫描线的扫描信号；
上拉模块，用于根据低电平信号和高电平信号，拉升相应的所述扫描线的扫描信号；
上拉维持模块，用于根据所述低电平信号和所述高电平信号，维持相应的所述扫描线的扫描电平信号的高电平；
自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号；
其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述上拉模块以及所述上拉维持模块；
其中所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入所述上一级的扫描信号，所述第一开关管的输入端输入低电平的扫描信号；所述第一开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接；
其中所述上拉维持模块包括第二电位维持电容，所述第二电位维持电容的一端与所述恒压高电平源连接，所述第二电位维持电容的另一端与所述第一开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端输入第一时钟信号，所述第二开关管的输出端输出本级的扫描信号。
在本发明所述的扫描驱动电路中，所述上拉模块包括第三开关管，所述第三开关管的控制端与所述恒压低电平源连接，所述第三开关管的输入端与所述恒压高电平源连接，所述第三开关管的输出端与所述第二开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述上拉维持模块还包括第四开关管、第五开关管、第六开关管以及第七开关管；
所述第四开关管的控制端与所述第二开关管的输入端连接，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述第一开关管的输出端连接；
所述第五开关管的控制端与所述第七开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接；
所述第六开关管的控制端与所述第一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接，所述第六开关管的输出端与所述第七开关管的输出端连接；
所述第七开关管的控制端输入第二时钟信号，所述第七开关管的输入端与所述恒压低电平源连接，所述第七开关管的输出端与所述第三开关管的控制端连接。
在本发明所述的扫描驱动电路中，所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块还包括第八开关管，所述第八开关管的控制端输入下一级的扫描信号，所述第八开关管的输入端输入低电平的扫描信号，所述第八开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
在本发明所述的扫描驱动电路中，所述上拉维持模块还包括第一电位维持电容，所述第一电位维持电容的一端与所述恒压高电平源连接，所述第一电位维持电容的另一端与所述第七开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管和第九开关管；
所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述第九开关管的输入端连接；
所述第九开关管的控制端输入第二时钟信号；所述第九开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
在本发明所述的扫描驱动电路中，所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块还包括第八开关管；
所述第八开关管的控制端输入低电平的扫描信号，所述第八开关管的输入端输入下一级的扫描信号；所述第八开关管的输出端与所述第九开关管的输入端连接。
本发明实施例还提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号以及第一时钟信号，拉低相应的所述扫描线的扫描信号；
上拉模块，用于根据低电平信号和高电平信号，拉升相应的所述扫描线的扫描信号；
上拉维持模块，用于根据所述低电平信号和所述高电平信号，维持相应的所述扫描线的扫描电平信号的高电平；
自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号；
其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述上拉模块、所述上拉维持模块。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入所述上一级的扫描信号，所述第一开关管的输入端输入低电平的扫描信号；所述第一开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
在本发明所述的扫描驱动电路中，所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端输入第一时钟信号，所述第二开关管的输出端输出本级的扫描信号。
在本发明所述的扫描驱动电路中，所述上拉模块包括第三开关管，所述第三开关管的控制端与所述恒压低电平源连接，所述第三开关管的输入端与所述恒压高电平源连接，所述第三开关管的输出端与所述第二开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述上拉维持模块包括第四开关管、第五开关管、第六开关管以及第七开关管；
所述第四开关管的控制端与所述第二开关管的输入端连接，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述第一开关管的输出端连接；
所述第五开关管的控制端与所述第七开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接；
所述第六开关管的控制端与所述第一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接，所述第六开关管的输出端与所述第七开关管的输出端连接；
所述第七开关管的控制端输入第二时钟信号，所述第七开关管的输入端与所述恒压低电平源连接，所述第七开关管的输出端与所述第三开关管的控制端连接；
其中所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块还包括第八开关管，所述第八开关管的控制端输入下一级的扫描信号，所述第八开关管的输入端输入低电平的扫描信号，所述第八开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
在本发明所述的扫描驱动电路中，所述上拉维持模块还包括第一电位维持电容，所述第一电位维持电容的一端与所述恒压高电平源连接，所述第一电位维持电容的另一端与所述第七开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述上拉维持模块还包括第二电位维持电容，所述第二电位维持电容的一端与所述恒压高电平源连接，所述第二电位维持电容的另一端与所述第一开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管和第九开关管；
所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述第九开关管的输入端连接；
所述第九开关管的控制端输入第二时钟信号；所述第九开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接；
其中所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第八开关管和第九开关管；
所述第八开关管的控制端输入低电平的扫描信号，所述第八开关管的输入端输入下一级的扫描信号；所述第八开关管的输出端与所述第九开关管的输入端连接。
有益效果
相较于现有的扫描驱动电路，本发明的扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制各模块，使得扫描驱动电路的整体结构简单，且能耗较小；解决了现有的扫描驱动电路的结构复杂且能耗较大的技术问题。
 附图说明
图1为一种现有的扫描驱动电路的结构示意图；
图2为本发明的扫描驱动电路的第一优选实施例的结构示意图；
图3为本发明的扫描驱动电路的第一优选实施例的信号波形图；
图4为本发明的扫描驱动电路的第二优选实施例的结构示意图；
图5为本发明的扫描驱动电路的第三优选实施例的结构示意图；
图6为本发明的扫描驱动电路的第四优选实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的扫描驱动电路的第一优选实施例的结构示意图。本优选实施例的扫描驱动电路20用于对级联的扫描线进行驱动操作，其包括下拉控制模块21、下拉模块22、上拉模块23、上拉维持模块24、自举电容C1、恒压低电平源以及恒压高电平源。该下拉控制模块21用于接收上一级的扫描信号G（N-1），并根据上一级的扫描信号G（N-1）生成相应的扫描线的低电平的扫描电平信号Q(N)；下拉模块22用于根据扫描电平信号Q(N)以及第一时钟信号CK，拉低相应的扫描线的扫描信号G(N)；上拉模块23用于根据低电平信号VGL和高电平信号VGH，拉升相应的扫描线的扫描信号G(N)；上拉维持模块24用于根据低电平信号VGL和高电平信号VGH，维持相应的扫描线的扫描电平信号Q(N)的高电平；自举电容C1用于生成扫描线的扫描电平信号Q(N)的低电平或高电平；恒压低电平源用于提供低电平信号VGL；恒压高电平源用于提供高电平信号VGH。
本优选实施例的扫描驱动电路20使用P型金属氧化物半导体类型的晶体管控制下拉控制模块21、下拉模块22、上拉模块23以及上拉维持模块24。
其中下拉控制模块21包括第一开关管T1，第一开关管T1的控制端输入上一级的扫描信号G（N-1），第一开关管T1的输入端输入低电平的扫描信号U2D，第一开关管T1的输出端分别与下拉模块22、上拉维持模块23以及自举电容C1连接。
下拉模块22包括第二开关管T2，第二开关管T2的控制端与下拉控制模块21的第一开关管T1的输出端连接，第二开关管T2的输入端输入第一时钟信号CK，第二开关管T2的输出端输出本级的扫描信号G（N）。
上拉模块23包括第三开关管T3，第三开关管T3的控制端与恒压低电平源连接，第三开关管T3的输入端与恒压高电平源连接，第三开关管T3的输出端与第二开关管T2的输出端连接。
上拉维持模块24包括第四开关管T4、第五开关管T5、第六开关管T6、第七开关管T7以及第一电位维持电容C2。
第四开关管T4的控制端与第二开关管T2的输入端连接，第四开关管T4的输入端与第五开关管T5的输出端连接，第四开关管T4的输出端与第一开关管T1的输出端连接。
第五开关管T5的控制端与第七开关管T7的输出端连接，第五开关管T5的输入端与恒压高电平源连接。
第六开关管T6的控制端与第一开关管T1的输出端连接，第六开关管T6的输入端与恒压高电平源连接，第六开关管T6的输出端与第七开关管T7的输出端连接。
第七开关管T7的控制端输入第二时钟信号XCK，第七开关管T7的输入端与恒压低电平源连接，第七开关管T7的输出端与第三开关管T3的控制端连接。
第一电位维持电容C2的一端和恒压高电平源连接，第一电位维持电容C2的另一端与第七开关管T7的输出端连接。
这里第一时钟信号CK和第二时钟信号XCK为反向时钟脉冲信号。
自举电容C1设置在第一开关管T1的输出端以及下拉模块22的第二开关管T2的输出端之间。
请参照图2和图3，图3为本发明的扫描驱动电路的第一优选实施例的信号波形图。本优选实施例中的开关管均为P型金属氧化物半导体类型的晶体管。本优选实施例的扫描驱动电路20使用时，当上一级的扫描信号G（N-1）转为低电平时，第一时钟信号CK为高电平，第二时钟信号XCK为低电平，第一开关管T1导通，低电平的扫描信号U2D通过第一开关管T1输出到第二开关管T2的控制端，从而将扫描线的扫描电平信号Q（N）拉低。这样第二开关管T2导通，但是由于第一时钟信号CK为高电平，因此扫描信号G(N)仍为高电平。同时第六开关管T6导通，第三开关管T3和第五开关管T5在高电平信号VGH的作用下断开，第四开关管T4在第一时钟信号CK的作用下断开。
随后上一级的扫描信号G（N-1）转为高电平，第一时钟信号CK转为低电平，第二时钟信号XCK转为高电平，第一开关管T1断开，第二开关管T2在自举电容C1的作用下依然导通，因此扫描信号G（N）通过第二开关管T2在第一时钟信号CK的作用下转为低电平。这样扫描线的扫描电平信号Q（N）在扫描信号G（N）和自举电容C1的作用下拉低电位，使得该阶段的扫描电平信号Q（N）的电位更低。这时由于第六开关管T6导通，第三开关管T3和第五开关管T5在高电平信号VGH的作用下依然断开，第四开关管T4在第一时钟信号CK的作用下导通。
随后第一时钟信号CK转为高电平，第二时钟信号XCK转为低电平，这时第七开关管T7在第二时钟信号的作用下导通，第三开关管T3和第五开关管T5在低电平信号VGL的作用下导通，这样扫描信号G（N）通过第三开关管T3被高电平信号HGL拉高，从而通过自举电容C1，将扫描线的扫描电平信号Q（N）也拉高。由于第四开关管T4在第一时钟信号CK的作用下断开，第一开关管T1在上一级的扫描信号G（N-1）的作用下也断开，因此扫描线的扫描电平信号Q（N）可以保持高电平，从而扫描信号G（N）也保持高电平。
随后第一时钟信号CK转为低电平，第二时钟信号XCK转为高电平，这时第四开关管T4在第一时钟信号CK的作用下导通，第五开关管T5在第一电位维持电容C2的作用下也导通，这样扫描线的扫描电平信号Q（N）可通过第四开关管T4、第五开关管T5接收高电平信号VGH，从而保持高电平，从而扫描信号G（N）也保持高电平。
这样扫描线的扫描电平信号Q（N）和扫描信号G（N）一直保持高电平（通过第三开关管T3或通过第四开关管T4和第五开关管T5），直至第一开关管T1导通，通过低电平的扫描信号U2D转到低电平。
这样即实现了本优选实施例的扫描驱动电路20的级联扫描线的驱动过程。
本发明的扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制各模块，使得扫描驱动电路的整体结构简单，且能耗较小。
请参照图4，图4为本发明的扫描驱动电路的第二优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路40的上拉维持模块44还包括第二电位维持电容C3，该第二电位维持电容C3的一端与恒压高电平源连接，第二电位维持电容C3的另一端与第一开关管T1的输出端连接。
该第二电位维持电容C3的设计可以避免扫描电平信号Q（N）通过其他开关管发生漏电现象，因此可通过第二电位维持电容C3和高电平信号HGL保持电平信号Q（N）的高电位。
请参照图5，图5为本发明的扫描驱动电路的第三优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路50的下拉控制模块51还包括第八开关管T8，第八开关管T8的控制端输入下一级的扫描信号G（N+1），第八开关管T8的输入端输入低电平的扫描信号D2U，第八开关管T8的输出端分别与下拉模块22、上拉维持模块24以及自举电容C1连接。
本优选实施例的扫描驱动电路50可以通过第八开关管T8实现反向扫描的功能，这样可通过下一级的扫描信号G（N+1）拉低本级的扫描信号G（N）。
请参照图6，图6为本发明的扫描驱动电路的第四优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路60的下拉控制模块61包括第一开关管T1、第九开关管T9以及第八开关管T8。
第一开关管T1的控制端输入低电平的扫描信号U2D，第一开关管T1的输入端输入上一级的扫描信号G（N-1），第一开关管T1的输出端与第九开关管T9的输入端连接。第九开关管T9的控制端输入第二时钟信号XCK，第九开关管T9的输出端分别与下拉模块22、上拉维持模块24以及自举电容C1连接，其中第二时钟信号XCK与第一时钟信号CK为反向时钟脉冲信号。第八开关管T8的控制端输入低电平的扫描信号D2U，第八开关管T8的输入端输入下一级的扫描信号G（N+1），第八开关管T8的输出端与第九开关管T9的输入端连接。
本优选实施例的第一开关管和第九开关管实现了第一优选实施例中的第一开关管的作用，第八开关管和第九开关管实现了第三优选实施例中的第八开关管的作用。
本优选实施例的扫描驱动电路的具体工作原理与上述的第一优选实施例和第三优选实施例的扫描驱动电路中的描述相同或相似，具体请参见上述第一优选实施例和第三优选实施例的扫描驱动电路中的相关描述。
本优选实施例的扫描驱动电路中的第一开关管和第八开关管一直处于导通状态，可以保证下拉控制模块的输出的低电平的稳定性。
本发明的扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制各模块，使得扫描驱动电路的整体结构简单，且能耗较小，从而可以较好的实现相应的液晶显示装置的窄边框设计；解决了现有的扫描驱动电路的结构复杂且能耗较大的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号以及第一时钟信号，拉低相应的所述扫描线的扫描信号；
    上拉模块，用于根据低电平信号和高电平信号，拉升相应的所述扫描线的扫描信号；
    上拉维持模块，用于根据所述低电平信号和所述高电平信号，维持相应的所述扫描线的扫描电平信号的高电平；
    自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号；
    其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述上拉模块以及所述上拉维持模块；
    其中所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入所述上一级的扫描信号，所述第一开关管的输入端输入低电平的扫描信号；所述第一开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接；
    其中所述上拉维持模块包括第二电位维持电容，所述第二电位维持电容的一端与所述恒压高电平源连接，所述第二电位维持电容的另一端与所述第一开关管的输出端连接。
  2. 根据权利要求1所述的扫描驱动电路，其中所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端输入第一时钟信号，所述第二开关管的输出端输出本级的扫描信号。
  3. 根据权利要求2所述的扫描驱动电路，其中所述上拉模块包括第三开关管，所述第三开关管的控制端与所述恒压低电平源连接，所述第三开关管的输入端与所述恒压高电平源连接，所述第三开关管的输出端与所述第二开关管的输出端连接。
  4. 根据权利要求3所述的扫描驱动电路，其中所述上拉维持模块还包括第四开关管、第五开关管、第六开关管以及第七开关管；
    所述第四开关管的控制端与所述第二开关管的输入端连接，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述第一开关管的输出端连接；
    所述第五开关管的控制端与所述第七开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接；
    所述第六开关管的控制端与所述第一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接，所述第六开关管的输出端与所述第七开关管的输出端连接；
    所述第七开关管的控制端输入第二时钟信号，所述第七开关管的输入端与所述恒压低电平源连接，所述第七开关管的输出端与所述第三开关管的控制端连接。
  5. 根据权利要求4所述的扫描驱动电路，其中所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
  6. 根据权利要求4所述的扫描驱动电路，其中所述下拉控制模块还包括第八开关管，所述第八开关管的控制端输入下一级的扫描信号，所述第八开关管的输入端输入低电平的扫描信号，所述第八开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
  7. 根据权利要求4所述的扫描驱动电路，其中所述上拉维持模块还包括第一电位维持电容，所述第一电位维持电容的一端与所述恒压高电平源连接，所述第一电位维持电容的另一端与所述第七开关管的输出端连接。
  8. 根据权利要求1所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管和第九开关管；
    所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述第九开关管的输入端连接；
    所述第九开关管的控制端输入第二时钟信号；所述第九开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
  9. 根据权利要求1所述的扫描驱动电路，其中所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
  10. 根据权利要求1所述的扫描驱动电路，其中所述下拉控制模块还包括第八开关管；
    所述第八开关管的控制端输入低电平的扫描信号，所述第八开关管的输入端输入下一级的扫描信号；所述第八开关管的输出端与所述第九开关管的输入端连接。
  11. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号以及第一时钟信号，拉低相应的所述扫描线的扫描信号；
    上拉模块，用于根据低电平信号和高电平信号，拉升相应的所述扫描线的扫描信号；
    上拉维持模块，用于根据所述低电平信号和所述高电平信号，维持相应的所述扫描线的扫描电平信号的高电平；
    自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号；
    其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述上拉模块以及所述上拉维持模块。
  12. 根据权利要求11所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入所述上一级的扫描信号，所述第一开关管的输入端输入低电平的扫描信号；所述第一开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
  13. 根据权利要求12所述的扫描驱动电路，其中所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端输入第一时钟信号，所述第二开关管的输出端输出本级的扫描信号。
  14. 根据权利要求13所述的扫描驱动电路，其中所述上拉模块包括第三开关管，所述第三开关管的控制端与所述恒压低电平源连接，所述第三开关管的输入端与所述恒压高电平源连接，所述第三开关管的输出端与所述第二开关管的输出端连接。
  15. 根据权利要求14所述的扫描驱动电路，其中所述上拉维持模块包括第四开关管、第五开关管、第六开关管以及第七开关管；
    所述第四开关管的控制端与所述第二开关管的输入端连接，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述第一开关管的输出端连接；
    所述第五开关管的控制端与所述第七开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接；
    所述第六开关管的控制端与所述第一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接，所述第六开关管的输出端与所述第七开关管的输出端连接；
    所述第七开关管的控制端输入第二时钟信号，所述第七开关管的输入端与所述恒压低电平源连接，所述第七开关管的输出端与所述第三开关管的控制端连接；
    其中所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
  16. 根据权利要求15所述的扫描驱动电路，其中所述下拉控制模块还包括第八开关管，所述第八开关管的控制端输入下一级的扫描信号，所述第八开关管的输入端输入低电平的扫描信号，所述第八开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接。
  17. 根据权利要求15所述的扫描驱动电路，其中所述上拉维持模块还包括第一电位维持电容，所述第一电位维持电容的一端与所述恒压高电平源连接，所述第一电位维持电容的另一端与所述第七开关管的输出端连接。
  18. 根据权利要求17所述的扫描驱动电路，其中所述上拉维持模块还包括第二电位维持电容，所述第二电位维持电容的一端与所述恒压高电平源连接，所述第二电位维持电容的另一端与所述第一开关管的输出端连接。
  19. 根据权利要求11所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管和第九开关管；
    所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述第九开关管的输入端连接；
    所述第九开关管的控制端输入第二时钟信号；所述第九开关管的输出端分别与所述下拉模块、所述上拉维持模块以及所述自举电容连接；
    其中所述第二时钟信号和所述第一时钟信号为反向时钟脉冲信号。
  20. 根据权利要求19所述的扫描驱动电路，其中所述下拉控制模块还包括第八开关管；
    所述第八开关管的控制端输入低电平的扫描信号，所述第八开关管的输入端输入下一级的扫描信号；所述第八开关管的输出端与所述第九开关管的输入端连接。
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CN110534048B (zh) * 2018-05-25 2022-02-22 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN110264948B (zh) * 2019-06-25 2022-04-01 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
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