WO2018010254A1 - 液晶显示面板外围设计电路及采用该电路的液晶显示面板 - Google Patents

液晶显示面板外围设计电路及采用该电路的液晶显示面板 Download PDF

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Publication number
WO2018010254A1
WO2018010254A1 PCT/CN2016/096055 CN2016096055W WO2018010254A1 WO 2018010254 A1 WO2018010254 A1 WO 2018010254A1 CN 2016096055 W CN2016096055 W CN 2016096055W WO 2018010254 A1 WO2018010254 A1 WO 2018010254A1
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WO
WIPO (PCT)
Prior art keywords
circuit
test
bonding pad
control switch
test line
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Application number
PCT/CN2016/096055
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English (en)
French (fr)
Inventor
王聪
杜鹏
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/318,991 priority Critical patent/US20180053473A1/en
Publication of WO2018010254A1 publication Critical patent/WO2018010254A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136268—Switch defects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to the field of liquid crystal display panels, and more particularly to a peripheral design circuit of a liquid crystal display panel and a liquid crystal display panel using the same.
  • LTTS Low temperature poly-silicon
  • FIG. 1 shows the circuit design of the peripheral structure of the traditional LTPS design.
  • Fanout structure (Fanout) 10 One end is connected to the lower bonding pad 12 under the driver integrated circuit (IC) 11, and the other end is connected to the splitter (DE-Mux) 13 .
  • Splitter 13 The end connected to the fan-out structure 10 is connected to a switch test 14 at the same time. Fan-out structure 10 and test line 14 throughout the structural design It is a parallel relationship.
  • the panel provides a transmission signal through the ODD/EVEN line of the test line 14, the TFT switch is turned on, and the display screen of the panel is realized by the splitter 13.
  • the TFT switch of the test circuit 14 is turned off, and the driver IC 11 inputs the signal normally through the splitter. 13 Achieve normal display of the panel.
  • the test circuit 13 occupies most of the space in the entire structure, which is not conducive to the narrow bezel design of the panel.
  • the technical problem to be solved by the present invention is to provide a peripheral design circuit of a liquid crystal display panel and a liquid crystal display panel using the same, which can effectively save the peripheral space of the liquid crystal display panel and better realize the narrow bezel design of the product.
  • the present invention provides a peripheral design circuit for a liquid crystal display panel, including a splitter, a test circuit, a driver integrated circuit region, and a fan-out structure
  • the drive integrated circuit region includes a relatively disposed upper bonding pad, a lower bonding pad and a driving integrated circuit connecting the upper bonding pad and the lower bonding pad, the fan-out structure connecting the lower bonding pad and the splitter, wherein the test line is disposed on the upper bonding Between the pad and the lower bonding pad, the driver integrated circuit overlies the test line, and the test line is connected to the lower bonding pad.
  • test line includes an odd signal transmission line and an even signal transmission line, and the test line outputs an alternating current signal of opposite polarity through the odd signal transmission line and the even signal transmission line.
  • odd signal transmission line and the even signal transmission line output mutually synchronized periodic pulse signals.
  • test line includes a signal unit test line for outputting an alternating current signal of opposite polarity.
  • test circuit includes a test control switch for controlling the opening and closing of the test line.
  • test control switch is an N-MOS thin film transistor, and the test circuit provides a high potential, the N-MOS The thin film transistor is turned on to turn on the test line.
  • test control switch is an N-MOS thin film transistor, and the test circuit provides a low potential
  • the P-MOS thin film transistor is turned on to turn on the test line.
  • the splitter includes an R signal control switch, a G signal control switch, and a B signal control switch.
  • the R signal control switch, the G signal control switch, and the B signal control switch are N-MOS thin film transistors or P-MOS thin film transistor.
  • the present invention also provides a liquid crystal display panel comprising a display area and a non-display area, the non-display area comprising the above-mentioned liquid crystal display panel peripheral design circuit.
  • the invention has the advantages that the peripheral space of the liquid crystal display panel is effectively saved without affecting the display effect of the liquid crystal display panel, so that the narrow bezel design of the liquid crystal display panel can be realized, and the appearance effect of the liquid crystal display panel can be improved.
  • FIG. 1 is a schematic structural view of a peripheral design circuit of a conventional liquid crystal display panel
  • FIG. 2 is a schematic structural view of a first embodiment of a peripheral design circuit of a liquid crystal display panel of the present invention
  • FIG. 3 is a timing waveform diagram of respective signals of the first embodiment of the peripheral design circuit of the liquid crystal display panel of the present invention.
  • FIG. 4 is a schematic structural view of a second embodiment of a peripheral design circuit of a liquid crystal display panel of the present invention.
  • FIG. 5 is a timing waveform diagram of respective signals of a second embodiment of a peripheral design circuit of a liquid crystal display panel of the present invention.
  • FIG. 6 is a schematic structural view of a third embodiment of a peripheral design circuit of a liquid crystal display panel of the present invention.
  • Fig. 7 is a timing waveform diagram of respective signals of a third embodiment of the peripheral design circuit of the liquid crystal display panel of the present invention.
  • the peripheral design circuit of the liquid crystal display panel of the present invention includes a splitter 20, a test line 21, a driver integrated circuit region 22, and a fan-out structure 23.
  • the driving integrated circuit region 22 includes opposite upper bonding pads 24, lower bonding pads 25, and the upper bonding pads 24 And the driving integrated circuit 22 of the lower bonding pad 25 .
  • the fan-out structure 23 connects the lower bonding pad 25 and the splitter 20.
  • the test line 21 is disposed between the upper bonding pad 24 and the lower bonding pad 25, and the driving integrated circuit 22 Covered on the test line 21.
  • the test line 21 is connected to the lower bonding pad 24, that is, the test line 21 passes through the lower bonding pad 24 and the fan-out structure 23 Connect in series.
  • the test line 21 includes an odd signal transmission line ODD and an even signal transmission line EVEN For outputting an alternating current signal of opposite polarity, the odd signal transmission line ODD and the even signal transmission line EVEN output are mutually synchronized periodic pulse signals.
  • the test line 21 also includes a test control switch S is used to control the opening and closing of the test line 21.
  • the test control switch S is an N-MOS thin film transistor.
  • the splitter 20 includes an R signal control switch TC1, a G signal control switch TC2, and a B signal control switch.
  • TC3 is used to control whether the data signal is passed into the RGB pixel unit.
  • the R signal control switch TC1, G signal control switch TC2 and B signal control switch TC3 is an N-MOS thin film transistor.
  • the working process of the peripheral design circuit of the liquid crystal display panel is as follows:
  • test control switch S of test line 21 is turned on, and the signal is transmitted by ODD/EVEN, and the signal passes through the fan-out structure. 23 Transfer to the splitter 20, drive the panel for display. After the test is completed, the test control switch S of the test line 21 is turned off, and the drive integrated circuit 22 passes through the fan-out structure. The transmission signal enters the splitter 20 to realize normal display of the panel.
  • FIG. 3 is a timing waveform diagram of each signal of a peripheral design circuit of the liquid crystal display panel of the present invention, see FIG.
  • the timing waveform diagram is a timing waveform diagram of each signal in the panel display red screen
  • ODD/EVEN provides an AC signal with polarity reversal, when the high potential is provided, the test control switch S is turned on, and the splitter 20 is provided.
  • R signal control switch When TC1 provides high potential, TC1 turns on, inputs signals to R pixels, TC2 and TC3 keep low output, and does not go to G and B. The pixel input signal and the LCD panel are displayed in red.
  • the liquid crystal display panel is displayed in green.
  • the signal is input to the B pixel, and the liquid crystal display panel is displayed in blue.
  • test line 21 is disposed on the upper bonding pad 24 and the lower bonding pad 25 Between, the space occupied by the test line is saved, which is beneficial to the design of the narrow frame of the liquid crystal display panel.
  • test line 21 provides a test signal using a signal unit test line SCT, the signal unit test line SCT Used to output AC signals with opposite polarities.
  • Fig. 5 is a timing waveform diagram of respective signals of the second embodiment of the peripheral design circuit of the liquid crystal display panel of the present invention. See Figure 5
  • the timing waveform diagram is a timing waveform diagram of each signal in the panel display red screen.
  • the signal unit test line SCT provides an AC signal with a polarity reversal.
  • the test control switch S When the high potential is supplied, the test control switch S is turned on, and the splitter 20 R signal control switch
  • TC1 provides high potential, TC1 turns on, inputs signals to R pixels, TC2 and TC3 keep low output, not to G and B.
  • the pixel input signal and the LCD panel are displayed in red.
  • test control switch S is a P-MOS thin film transistor
  • R signal control switch TC1 is a P-MOS thin film transistor
  • B signal control switch TC3 is a P-MOS thin film transistor.
  • the test circuit 21 can adopt an odd signal transmission line ODD and an even signal transmission line EVEN. Output an AC signal of opposite polarity, or use the signal unit test line SCT to output an AC signal of opposite polarity.
  • Fig. 7 is a timing waveform diagram of respective signals of a third embodiment of the peripheral design circuit of the liquid crystal display panel of the present invention. See Figure 7
  • the timing waveform diagram is a timing waveform diagram of each signal in the panel display red screen, signal unit test line SCT or odd signal transmission line ODD and even signal transmission line EVEN Provides an AC signal with polarity reversal.
  • the test control switch S When the low potential is provided, the test control switch S is turned on.
  • the R signal of the splitter 20 controls the switch TC1 to provide a low potential, TC1 turns on, and goes to R.
  • the pixel input signal, TC2 and TC3 always maintain a high potential output, no signal is input to the G and B pixels, and the liquid crystal display panel is displayed in red.
  • the present invention also provides a liquid crystal display panel (not shown in the drawing), the liquid crystal display panel includes a display area and a non-display area, and the non-display area includes the above-mentioned liquid crystal display panel peripheral design circuit.
  • the liquid crystal display panel has a test circuit disposed between the upper bonding pad and the lower bonding pad, which saves space occupied by the test circuit and is beneficial to the design of the narrow frame of the liquid crystal display panel.

Abstract

一种液晶显示面板外围设计电路及采用该电路的液晶显示面板，所述电路包括分路器（20）、测试线路（21）、驱动集成电路区域（22）及扇出结构（23），所述驱动集成电路区域（22）包括相对设置的上键合垫（24）、下键合垫（25）及连接所述上键合垫（24）及下键合垫（25）的驱动集成电路（22），所述扇出结构（23）连接所述下键合垫（25）及分路器（20），所述测试线路（21）设置在所述上键合垫（24）与下键合垫（25）之间，所述驱动集成电路（22）覆盖在所述测试线路（21）上，所述测试线路（21）连接至所述下键合垫（25）。该电路在不影响液晶显示面板显示效果的情况下，有效地节省了液晶显示面板的外围空间，实现液晶显示面板的窄边框设计，提高液晶显示面板的外观效果。

Description

液晶显示面板外围设计电路及采用该电路的液晶显示面板 技术领域
本发明涉及液晶显示面板领域，尤其涉及一种液晶显示面板外围设计电路及采用该电路的液晶显示面板。
背景技术
低温多晶硅（ Low temperature poly-silicon ，简称 LTPS ），由于其具有高的电子迁移率，可以有效的减小 TFT 的器件的面积，从而提升像素的开口率。增大面板显示亮度的同时可以降低整体的功耗，使得面板的制造成本大幅度降低。目前已成为液晶显示领域的研究热点。
随着 LCD 面板的不断发展，人们对于 LCD 越来越趋向于窄边框甚至是无边框。如何有效的利用 LCD 外围边框，也是近年来面板设计者们研究的热点。
图 1 为传统 LTPS 设计外围结构设计电路图。扇出结构（ Fanout ） 10 一端连接驱动集成电路（ IC ） 11 下方的下键合垫（ Bonding pad ） 12 ，另一端连接分路器（ DE-Mux ） 13 。分路器 13 与扇出结构 10 连接的一端同时连接测试线路（ Switch test ） 14 。整个结构设计中，扇出结构 10 与测试线路 14 为并联关系。在检测时，面板内通过测试线路 14 的 ODD/EVEN 线提供传输信号， TFT 开关打开，通过分路器 13 实现面板的显示画面。
模组键合完成后，测试线路 14 的 TFT 开关关闭，由驱动集成电路 11 正常输入信号，通过分路器 13 实现面板的正常显示。整个结构中测试线路 13 占据有大部分空间，不利于面板的窄边框设计。
 技术问题
本发明所要解决的技术问题是，提供一种液晶显示面板外围设计电路及采用该电路的液晶显示面板，其能够有效的节省液晶显示面板外围空间，更好的实现产品的窄边框设计。
技术解决方案
为了解决上述问题，本发明提供了一种液晶显示面板外围设计电路，包括分路器、测试线路、驱动集成电路区域及扇出结构，所述驱动集成电路区域包括相对设置的上键合垫、下键合垫及连接所述上键合垫及下键合垫的驱动集成电路，所述扇出结构连接所述下键合垫及分路器，所述测试线路设置在所述上键合垫与下键合垫之间，所述驱动集成电路覆盖在所述测试线路上，所述测试线路连接至所述下键合垫。
进一步，所述测试线路包括奇数信号传输线及偶数信号传输线，所述测试线路通过所述奇数信号传输线和所述偶数信号传输线输出极性相反的交流信号。
进一步，所述奇数信号传输线及偶数信号传输线输出互为反相同步的周期脉冲信号。
进一步，所述测试线路包括信号单元测试线，用于输出极性相反的交流信号。
进一步，所述测试线路包括测试控制开关，用于控制测试线路的开与关。
进一步，所述测试控制开关为 N-MOS 薄膜晶体管，所述测试线路提供高电位，所述 N-MOS 薄膜晶体管打开以开启所述测试线路。
进一步，所述测试控制开关为 N-MOS 薄膜晶体管，所述测试线路提供低电位，所述
P-MOS 薄膜晶体管打开以开启所述测试线路。
进一步，所述分路器包括 R 信号控制开关、 G 信号控制开关及 B 信号控制开关。
进一步，所述 R 信号控制开关、 G 信号控制开关及 B 信号控制开关为 N-MOS 薄膜晶体管或 P-MOS 薄膜晶体管。
本发明还提供一种液晶显示面板，包括显示区域及非显示区域，所述非显示区域包括上述的液晶显示面板外围设计电路。
 有益效果
本发明的优点在于，在不影响液晶显示面板显示效果的情况下，有效的节省了液晶显示面板的外围空间，这样能实现液晶显示面板的窄边框设计，提高液晶显示面板的外观效果。
附图说明
图 1 是现有的液晶显示面板外围设计电路的结构示意图；
图 2 是本发明液晶显示面板外围设计电路的第一具体实施方式的结构示意图；
图 3 是本发明液晶显示面板外围设计电路的第一具体实施方式的各个信号的时序波形图；
图 4 是本发明液晶显示面板外围设计电路的第二具体实施方式的结构示意图；
图 5 是本发明液晶显示面板外围设计电路的第二具体实施方式的各个信号的时序波形图；
图 6 是本发明液晶显示面板外围设计电路的第三具体实施方式的结构示意图；
图 7 是本发明液晶显示面板外围设计电路的第三具体实施方式的各个信号的时序波形图。
 本发明的最佳实施方式
下面结合附图对本发明提供的液晶显示面板外围设计电路及采用该电路的液晶显示面板的具体实施方式做详细说明。
图 2 是本发明液晶显示面板外围设计电路的第一具体实施方式的结构示意图，参见图 2 ，在本第一具体实施方式中，本发明液晶显示面板外围设计电路的包括分路器 20 、测试线路 21 、驱动集成电路区域 22 及扇出结构 23 。
所述驱动集成电路区域 22 包括相对设置的上键合垫 24 、下键合垫 25 及连接所述上键合垫 24 及下键合垫 25 的驱动集成电路 22 。所述扇出结构 23 连接所述下键合垫 25 及分路器 20 。
所述测试线路 21 设置在所述上键合垫 24 与下键合垫 25 之间，所述驱动集成电路 22 覆盖在所述测试线路 21 上。所述测试线路 21 连接至所述下键合垫 24 ，即所述测试线路 21 通过所述下键合垫 24 与扇出结构 23 串联连接。
所述测试线路 21 包括奇数信号传输线 ODD 及偶数信号传输线 EVEN ，用于输出极性相反的交流信号，所述奇数信号传输线 ODD 及偶数信号传输线 EVEN 输出互为反相同步的周期脉冲信号。所述测试线路 21 还包括测试控制开关 S ，用于控制测试线路 21 的开与关，在本具体实施方式中，所述测试控制开关 S 为 N-MOS 薄膜晶体管。
所述分路器 20 包括 R 信号控制开关 TC1 、 G 信号控制开关 TC2 及 B 信号控制开关 TC3 ，用于控制数据信号是否通入 RGB 像素单元。在本具体实施方式中，所述 R 信号控制开关 TC1 、 G 信号控制开关 TC2 及 B 信号控制开关 TC3 为 N-MOS 薄膜晶体管。
所述液晶显示面板外围设计电路的工作过程如下：
在测试时，测试线路 21 的测试控制开关 S 打开，由 ODD/EVEN 传输信号，信号通过扇出结构 23 传输入分路器 20 ，驱动面板进行显示。测试结束后， 测试线路 21 的测试控制开关 S 关闭，驱动集成电路 22 通过扇出结构 23 传输信号进入分路器 20 ，实现面板正常显示。
图 3 是本发明液晶显示面板外围设计电路的各个信号的时序波形图，参见图 3 ，该时序波形图是面板显示红色画面下的各个信号的时序波形图， ODD/EVEN 提供极性反转的交流信号，提供高电位时，测试控制开关 S 打开，分路器 20 的 R 信号控制开关 TC1 提供高电位时， TC1 开启， 向 R 像素输入信号， TC2 与 TC3 一直保持低电位输出，不向 G 与 B 像素输入信号，液晶显示面板显示为红色。依次类推，当所述 TC1 及 TC3 为低电位，所述 TC2 为高电位时，向 G 像素输入信号，液晶显示面板显示为绿色，当所述 TC1 及 TC2 为低电位，所述 TC3 为高电位时，向 B 像素输入信号，液晶显示面板显示为蓝色。
在本具体实施方式中，将所述测试线路 21 设置在上键合垫 24 与下键合垫 25 之间，节省了测试线路占用的空间，有利于液晶显示面板的窄边框的设计。
图 4 为本发明液晶显示面板外围设计电路的第二具体实施方式的结构示意图，参见图 4 ，本具体实施方式与第一具体实施方式的区别在于，所述测试线路 21 采用信号单元测试线 SCT 提供测试信号，所述信号单元测试线 SCT 用于输出极性相反的交流信号。
图 5 是本发明液晶显示面板外围设计电路的第二具体实施方式的各个信号的时序波形图。参见图 5 ，该时序波形图是面板显示红色画面下的各个信号的时序波形图，信号单元测试线 SCT 提供极性反转的交流信号，提供高电位时，测试控制开关 S 打开，分路器 20 的 R 信号控制开关 TC1 提供高电位时， TC1 开启， 向 R 像素输入信号， TC2 与 TC3 一直保持低电位输出，不向 G 与 B 像素输入信号，液晶显示面板显示为红色。
图 6 为本发明液晶显示面板外围设计电路的第三具体实施方式的结构示意图，参见图 6 ，本具体实施方式与第一具体实施方式的区别在于，所述测试控制开关 S 为 P-MOS 薄膜晶体管，所述 R 信号控制开关 TC1 、 G 信号控制开关 TC2 及 B 信号控制开关 TC3 为 P-MOS 薄膜晶体管。其中，所述测试线路 21 可采用奇数信号传输线 ODD 及偶数信号传输线 EVEN 输出极性相反的交流信号，或者采用信号单元测试线 SCT 输出极性相反的交流信号。
图 7 是本发明液晶显示面板外围设计电路的第三具体实施方式的各个信号的时序波形图。参见图 7 ，该时序波形图是面板显示红色画面下的各个信号的时序波形图，信号单元测试线 SCT 或奇数信号传输线 ODD 及偶数信号传输线 EVEN 提供极性反转的交流信号，提供低电位时，测试控制开关 S 打开，分路器 20 的 R 信号控制开关 TC1 提供低电位时， TC1 开启， 向 R 像素输入信号， TC2 与 TC3 一直保持高电位输出，不向 G 与 B 像素输入信号，液晶显示面板显示为红色。依次类推，当所述 TC1 及 TC3 为高电位，所述 TC2 为低电位时，向 G 像素输入信号，液晶显示面板显示为绿色，当所述 TC1 及 TC2 为高电位，所述 TC3 为低电位时，向 B 像素输入信号，液晶显示面板显示为蓝色。
本发明还提供一种液晶显示面板（附图中未标示），所述液晶显示面板包括显示区域及非显示区域，所述非显示区域包括上述的液晶显示面板外围设计电路。所述液晶显示面板将测试线路设置在上键合垫与下键合垫之间，节省了测试线路占用的空间，有利于液晶显示面板的窄边框的设计。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (14)

  1. 一种液晶显示面板外围设计电路，包括分路器、测试线路、驱动集成电路区域及扇出结构，所述驱动集成电路区域包括相对设置的上键合垫、下键合垫及连接所述上键合垫及下键合垫的驱动集成电路，所述扇出结构连接所述下键合垫及分路器，其中，所述测试线路设置在所述上键合垫与下键合垫之间，所述驱动集成电路覆盖在所述测试线路上，所述测试线路连接至所述下键合垫，所述测试线路包括奇数信号传输线及偶数信号传输线，所述测试线路通过所述奇数信号传输线和所述偶数信号传输线输出极性相反的交流信号，所述测试线路包括测试控制开关，用于控制测试线路的开与关。
  2. 根据权利要求 1 所述的电路，其中，所述奇数信号传输线及偶数信号传输线输出互为反相同步的周期脉冲信号。
  3. 根据权利要求 1 所述的电路，其中，所述测试控制开关为 N-MOS 薄膜晶体管，所述测试线路提供高电位，所述 N-MOS 薄膜晶体管打开以开启所述测试线路。
  4. 根据权利要求 1 所述的电路，其中，所述测试控制开关为 P-MOS 薄膜晶体管，所述测试线路提供低电位，所述 P-MOS 薄膜晶体管打开以开启所述测试线路。
  5. 一种液晶显示面板外围设计电路，包括分路器、测试线路、驱动集成电路区域及扇出结构，所述驱动集成电路区域包括相对设置的上键合垫、下键合垫及连接所述上键合垫及下键合垫的驱动集成电路，所述扇出结构连接所述下键合垫及分路器，其中，所述测试线路设置在所述上键合垫与下键合垫之间，所述驱动集成电路覆盖在所述测试线路上，所述测试线路连接至所述下键合垫。
  6. 根据权利要求 5 所述的电路，其中，所述测试线路包括奇数信号传输线及偶数信号传输线，所述测试线路通过所述奇数信号传输线和所述偶数信号传输线输出极性相反的交流信号。
  7. 根据权利要求 6 所述的电路，其中，所述奇数信号传输线及偶数信号传输线输出互为反相同步的周期脉冲信号。
  8. 根据权利要求 5 所述的电路，其中，所述测试线路包括信号单元测试线，用于输出极性相反的交流信号。
  9. 根据权利要求 5 所述的电路，其中，所述测试线路包括测试控制开关，用于控制测试线路的开与关。
  10. 根据权利要求 9 所述的电路，其中，所述测试控制开关为 N-MOS 薄膜晶体管，所述测试线路提供高电位，所述 N-MOS 薄膜晶体管打开以开启所述测试线路。
  11. 根据权利要求 9 所述的电路，其中，所述测试控制开关为 P-MOS 薄膜晶体管，所述测试线路提供低电位，所述 P-MOS 薄膜晶体管打开以开启所述测试线路。
  12. 根据权利要求 5 所述的电路，其中，所述分路器包括 R 信号控制开关、 G 信号控制开关及 B 信号控制开关。
  13. 根据权利要求 12 所述的电路，其中，所述 R 信号控制开关、 G 信号控制开关及 B 信号控制开关为 N-MOS 薄膜晶体管或 P-MOS 薄膜晶体管。
  14. 一种液晶显示面板，包括显示区域及非显示区域，其中，所述非显示区域包括权利要求 1 所述的电路 。
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