CN105096780B - 基板电路及显示面板的信号测试电路 - Google Patents

基板电路及显示面板的信号测试电路 Download PDF

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CN105096780B
CN105096780B CN201510458290.9A CN201510458290A CN105096780B CN 105096780 B CN105096780 B CN 105096780B CN 201510458290 A CN201510458290 A CN 201510458290A CN 105096780 B CN105096780 B CN 105096780B
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CN105096780A (zh
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赵莽
田勇
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开一种用于基板电路。所术基板电路包括一基板、一软板区、一芯片区、多个基板导线区、多个基板栅极驱动电路区及多个开关。所述多个基板导线区包括多条基板导线，所述多条基板导线与所述芯片区电气连接。所述多个基板栅极驱动电路区包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接。每一所述开关连接于一条所述栅极线与一条所述基板导线之间。

Description

基板电路及显示面板的信号测试电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种基于LTPS(Low-TemperaturePoly-Si)面板的基板电路及显示面板，特别适用于信号测试。
【背景技术】
随着低温多晶硅(LTPS)半导体薄膜晶体管的发展以及LTPS半导体本身超高载流子迁移率的特性，面板周边集成电路成为业界关注的焦点。出现大量关于System on Panel(SOP)的研究，使SOP逐步成为现实。
在一般面板设计的过程中，画素测试(Cell Test)电路只局限于面板成盒后的测试，利用率较低。
利用传统的画素测试电路进行驱动信号量测的过程中，面板GOA的负载会严重影响驱动信号的RC负载，影响IC侧经过WOA区域后的低RC负载波形的量测。
如图1所示，一传统的显示面板的基板电路的示意图。所述基板包括：主动区(Active)11、基板栅极驱动电路区(Gate On Array,GOA)18、外部连接区(Fanout)12、基板导线区(Wire On Array,WOA)13，芯片区(Integrated Chip,IC)14、软板区(FlexiblePrinted Circuit,FPC)15及画素测试区(Cell Test Region)16。主动区11用于像素的显示。基板栅极驱动电路区18用于产生所述面板内的薄膜晶体管的栅极驱动信号。外部连接区12用于芯片区14与主动区11之间数据线的走线连接；画素测试区16包括多个测试垫17，画素测试区16用于测试画素的显示效果，过程管理是在芯片区14连接之前。基板导线区13用于面板周围走线的连接。芯片区14用于芯片的连接，通过芯片驱动面板内的电路和薄膜晶体管。软板区15用于连接一主板。
图2所示为图1中的画素测试电路的连接示意图(画素测试电路未在图1中标出)。其中，在进行画素测试时，芯片区14是没有连接上去的。此时，对于图2中的画素测试电路20，信号从所述多个测试垫17输入到基板导线区13的走线之中，然后经由基板导线区13走线连接至基板栅极驱动电路区18，再驱动所述主动区11。由图可以看出，在面板设计当中，信号线也要从芯片区14侧引出，跟画素测试区16的信号线相互对应，以便于芯片区14连接之后通过芯片区14来进行面板10的驱动控制。
在传统面板中，只通过图2所示所述多个测试垫17量测信号，此时量测的信号是经过所述基板导线区13和所述基板栅极驱动电路区18的高RC负载之后输出的波形，如果RC负载出现问题，则不能确定是所述基板导线区13的问题，还是所述基板栅极驱动电路区18的问题。
故，有必要提出一种技术方案以解决上述问题。
【发明内容】
本发明提供一种利用信号测试垫进行面板驱动信号测量的方法，提高了画素测试电路的有效利用率。本发明提供的电路在输入到GOA模块的信号线之前添加了TFT的控制模块，用于控制输入到GOA内部的信号，实现对于面板驱动信号的有效控制。
本发明提供的电路设计不仅能够实现芯片区经过基板导线区和基板栅极驱动电路区的高RC负载之后输出的波形，也能够实现芯片区的信号经过基板导线区后低RC负载的波形准确的监控和量测。当量测的高RC负载信号不能够满足栅极线的驱动时，通过比对低RC负载和高RC负载的波形，很容易发现RC异常的区域(WOA或GOA)，为产品设计提供有力的参考。
本发明的目的在于提供一种基板电路，设置于一基板，特别适用于信号测试。
为实现上述目的，本发明提供一种用于基板电路。所术基板电路包括一芯片区、多个基板导线区、多个基板栅极驱动电路区及多个开关。
所述多个基板导线区包括多条基板导线，所述多条基板导线与所述芯片区电气连接。所述多个基板栅极驱动电路区包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接。每一所述开关连接于一条所述栅极线与一条所述基板导线之间。
在一实施例中，所述基板电路还包含一主动区，连接所述多个基板栅极驱动电路区。所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线。
在一实施例中，所述基板为一玻璃基板。
在一实施例中，所述基板电路还包括一软板区，用于连接所述芯片区至一外部组件。
在一实施例中，所述基板电路还包括一外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。
在一实施例中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
在一实施例中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括第一测试垫及多个第二测试垫。所述第一测试垫电气连接所述薄膜晶体管的所述控制端及所述芯片区。所述多个第二测试垫分别电气连接所述薄膜晶体管的第一端。
在一实施例中，所述第一端是源极、所述第二端是漏极及所述控制端是栅极。
在一实施例中，所述芯片区发出一控制信号，用于选择性导通/断开所述开关。
本发明的另一目的在于提供一种显示面板。
为实现上述目的，本发明提供一种包括上述其中之一的基板电路及一主板的显示面板。该主板与该基板电路连接并提供所述基板电路所需显示信息。
通过本发明的上述技术方案，产生的有益技术效果在于：
1.提高了画素测试电路的有效利用率。
2.通过比对低RC负载和高RC负载的波形，很容易发现RC异常的区域(WOA或GOA)，为产品设计提供有力的参考。
【附图说明】
图1为一传统的显示面板的基板电路的示意图。
图2为图1中的画素测试电路的连接示意图。
图3为本发明的显示面板的基板电路的示意图。
图4为图3中的画素测试电路的连接示意图。
图5为图3的基板电路在实际操作时的工作时序图。
【具体实施方式】
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
图3为本发明的显示面板的基板电路100的示意图。所述基板电路100设置于一基板190上，包括：、一主动区110、多个基板栅极驱动电路区180、一外部连接区120、多个基板导线区130，一芯片区140、一软板区150、多个画素测试区160及多个开关。所述软板150用于连接一外部组件192(即主板)。所述芯片区140电气连接所述软板150。所述多个基板导线区130包括多条基板导线132，所述多条基板导线132与所述芯片区140电气连接。所述多个基板栅极驱动电路区180包括多条栅极线182，每一所述栅极线182与所述基板导线132之一电气连接。所述主动区110连接所述多个基板栅极驱动电路区180。每一所述开关162连接于一条所述栅极线182与一条所述基板导线132之间。所述主动区110包括多个画素单元112，所述画素单元112连接所述基板栅极驱动电路区180及所述芯片区140的多条数据线146。仔细地，所述画素单元112是与所述基板栅极驱动电路区180的多条驱动信号线184电气连接。所述外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。每一所述画素测试区160包括第一测试垫164及多个第二测试垫166。其中所述多个基板栅极驱动电路区180、所述多个基板导线区130与所述芯片区140构成一画素测试电路200。
在本实施例中，所述基板190可以为玻璃基板。所述基板190还包括一主板192，用于连接所述软板区150，以提供所述基板电路100所需信息。
图4为图3中的画素测试电路200的连接示意图。在本实施例中，所述开关162是一薄膜晶体管。所述开关162包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线132，所述第二端连接一条所述栅极线182。仔细地，所述第一端是源极、所述第二端是漏极及所述控制端是栅极。所述第一测试垫164及所述芯片区140电气连接所述开关162的所述控制端。所述多个第二测试垫166分别电气连接所述开关162的第一端。根据测试需求，所述芯片区发出的一控制信号用于选择性导通/断开所述开关162。这也是本发明能够有效分辨问题是出现在所述多个基板栅极驱动电路区180或所述多个基板导线区130之中的原因。由示意图可知，在画素测试电路200对所述芯片区140发出的一测试信号144经过所述多个基板导线区130和所述多个基板栅极驱动电路区180后的高RC负载波形进行量测的时候，可以通过芯片区发出的一控制信号142打开所述开关162；在画素测试电路200对所述芯片区140发出的所述测试信号144经过所述多个基板导线区130后的低RC负载波形进行量测的时候，可以通过所述控制信号142关闭所述开关162，避免所述多个基板栅极驱动电路区180的RC负载的影响。
图5为图3的基板电路100在实际操作时的工作时序图。由时序图可知，可以通过所述控制信号142控制一测试结果信号输出波形的RC负载的效果。当所述控制信号142为高电平时，面板正常驱动，所述测试信号144为经过所述多个基板导线区130和所述多个基板栅极驱动电路区180两个区域后的高RC负载的波形。当所述控制信号142为低电平时，面板驱动关闭，所述测试信号144为经过所述多个基板导线区130区域后低RC负载的波形。当量测的高RC负载信号不能够满足Gate的驱动时，通过比对低RC负载和高RC负载的波形，很容易发现RC异常的区域，为产品设计提供有力的参考。比如，如果两个波形差不多，则需要减小所述多个基板导线区130区域的RC负载。如果两个波形差别过大，则需要修改减小所述多个基板栅极驱动电路区180区域的RC负载或者更换更大驱动能力的芯片。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (7)

1.一种基板电路，设置于一基板，其特征在于，包括：
一芯片区；
多个基板导线区，各包括多条基板导线，所述多条基板导线与所述芯片区电气连接；
多个基板栅极驱动电路区，各包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接；以及
多个开关，每一所述开关连接于一条所述栅极线与一条所述基板导线之间；
各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线；
所述基板电路还包括多个画素测试区，每一所述画素测试区包括：
第一测试垫，电气连接所述薄膜晶体管的所述控制端与所述芯片区；及多个第二测试垫，分别电气连接所述薄膜晶体管的第一端；
所述芯片区发出一控制信号，所述控制信号用于选择性导通/断开所述开关。
2.如权利要求1所述的基板电路，其特征在于，还包含一主动区，连接所述多个基板栅极驱动电路区，所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线。
3.如权利要求1所述的基板电路，其特征在于，所述基板为一玻璃基板。
4.如权利要求1所述的基板电路，其特征在于，所述基板电路还包括一软板区，用于连接所述芯片区至一外部组件。
5.如权利要求2所述的基板电路，其特征在于，所述基板电路还包括一外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。
6.如权利要求1所述的基板电路，其特征在于，所述第一端是源极、所述第二端是漏极及所述控制端是栅极。
7.一种显示面板，其特征在于，包括：
根据如权利要求1-6其中任一项所述的基板电路；及
一主板，其中该主板与该基板电路连接并提供所述基板电路所需显示信息。
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