WO2017015989A1 - 基板电路及显示面板 - Google Patents

基板电路及显示面板 Download PDF

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Publication number
WO2017015989A1
WO2017015989A1 PCT/CN2015/086588 CN2015086588W WO2017015989A1 WO 2017015989 A1 WO2017015989 A1 WO 2017015989A1 CN 2015086588 W CN2015086588 W CN 2015086588W WO 2017015989 A1 WO2017015989 A1 WO 2017015989A1
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WIPO (PCT)
Prior art keywords
substrate
circuit
wires
region
chip
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PCT/CN2015/086588
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English (en)
French (fr)
Inventor
赵莽
田勇
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武汉华星光电技术有限公司
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Priority to US14/773,355 priority Critical patent/US9835917B2/en
Publication of WO2017015989A1 publication Critical patent/WO2017015989A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a method based on LTPS (Low-Temperature)
  • LTPS Low-Temperature
  • the substrate circuit and display panel of the Poly-Si) panel are especially suitable for signal testing.
  • the Cell Test circuit In the process of general panel design, the Cell Test circuit is limited to the test after the panel is boxed, and the utilization rate is low.
  • the load of the panel GOA will seriously affect the RC load of the drive signal, affecting the measurement of the low RC load waveform after the IC side passes through the WOA region.
  • FIG. 1 a schematic diagram of a substrate circuit of a conventional display panel.
  • the substrate includes: an active area (Active) 11 and a substrate gate driving circuit area (Gate On Array, GOA) 18, external connection area (Fanout) 12, Wire On Array (WOA) 13, chip area (Integrated Chip, IC) 14, Flexible Printed Circuit (FPC) 15 and Pixel Test Area (Cell Test) Region) 16.
  • the active area 11 is used for display of pixels.
  • the substrate gate drive circuit region 18 is for generating a gate drive signal of the thin film transistor within the panel.
  • the external connection area 12 is used for the trace connection of the data lines between the chip area 14 and the active area 11; the pixel test area 16 includes a plurality of test pads 17 for testing the display effect of the pixels.
  • the substrate lead area 13 is used for the connection of the traces around the panel.
  • the chip area 14 is used for the connection of the chip, and the circuit and the thin film transistor in the panel are driven by the chip.
  • the soft board area 15 is
  • the connection diagram of the pixel test circuit in FIG. Among them, when the pixel test is performed, the chip area 14 is not connected. At this time, a signal is input from the plurality of test pads 17 into the trace of the substrate lead region 13, and then connected to the substrate gate drive circuit region 18 via the substrate lead region 13 and then driven to the active region 11. As can be seen from the figure, in the panel design, the signal lines are also taken out from the chip area 14 side, corresponding to the signal lines of the pixel test area 16, so that the board area 14 is driven by the chip area 14 after the chip area 14 is connected. control.
  • signals are only measured by the plurality of test pads 17 shown in FIG. 2, at which time the measured signals are high RC loads through the substrate lead regions 13 and the substrate gate drive circuit regions 18. After the waveform is output, if there is a problem with the RC load, it is not possible to determine whether it is a problem of the substrate wiring region 13, or a problem of the substrate gate driving circuit region 18.
  • the invention provides a method for measuring panel driving signals by using a signal test pad, which improves the effective utilization rate of the pixel test circuit.
  • the circuit provided by the invention adds a TFT control module before the signal line input to the GOA module for controlling the signal input to the GOA to realize effective control of the panel driving signal.
  • the circuit design provided by the invention can not only realize the waveform outputted after the chip region passes the high RC load of the substrate lead region and the substrate gate driving circuit region, but also realize the waveform of the low RC load after the signal of the chip region passes through the substrate lead region. Monitoring and measurement. When the equivalent RC load signal is not able to satisfy the gate line drive, it is easy to find the RC anomaly area (WOA or GOA) by comparing the waveforms of the low RC load and the high RC load, which provides a powerful product design. reference.
  • WOA RC anomaly area
  • the present invention provides a substrate circuit.
  • the substrate circuit comprises a chip area, a plurality of substrate lead areas, a plurality of substrate gate drive circuit areas, a plurality of switches, an active area, a soft board area and an external connection area.
  • the plurality of substrate lead regions includes a plurality of substrate leads, and the plurality of substrate leads are electrically connected to the chip region.
  • the plurality of substrate gate drive circuit regions includes a plurality of gate lines, each of the gate lines being electrically connected to one of the substrate wires. Each of the switches is connected between one of the gate lines and one of the substrate wires.
  • the active region is connected to the plurality of substrate gate drive circuit regions.
  • the active area includes a plurality of pixel units, and the pixel unit connects the plurality of substrate gate driving circuit regions and the plurality of data lines of the chip region.
  • the soft board area is configured to connect the chip area to an external component.
  • the external connection area is configured to receive a plurality of data lines connecting the active area and the chip area.
  • the chip area sends a control signal for selectively turning on/off the switch, and the chip area further sends a test signal, and the test signal can be selected to pass through the plurality of substrate wires according to the control signal.
  • each of the switches includes a thin film transistor
  • the thin film transistor includes a first end, a second end, and a control end, the first end is connected to one of the substrate wires, and the second end One end of the gate line is connected.
  • the substrate circuit further includes a plurality of pixel test areas, each of the pixel test areas including a first test pad and a plurality of second test pads.
  • the first test pad electrically connects the control terminal of the thin film transistor and the chip region.
  • the plurality of second test pads are electrically connected to the first ends of the thin film transistors, respectively.
  • the first end is a source
  • the second end is a drain
  • the control end is a gate
  • the present invention provides a substrate circuit.
  • the substrate circuit comprises a chip area, a plurality of substrate lead areas, a plurality of substrate gate drive circuit areas and a plurality of switches.
  • the plurality of substrate lead regions includes a plurality of substrate leads, and the plurality of substrate leads are electrically connected to the chip region.
  • the plurality of substrate gate drive circuit regions includes a plurality of gate lines, each of the gate lines being electrically connected to one of the substrate wires. Each of the switches is connected between one of the gate lines and one of the substrate wires.
  • the substrate circuit further includes an active region connecting the plurality of substrate gate drive circuit regions.
  • the active area includes a plurality of pixel units, and the pixel unit connects the plurality of substrate gate driving circuit regions and the plurality of data lines of the chip region.
  • the substrate is a glass substrate.
  • the substrate circuit further includes a flexible board region for connecting the chip region to an external component.
  • the substrate circuit further includes an external connection region for accommodating a plurality of data lines connecting the active region and the chip region.
  • each of the switches includes a thin film transistor
  • the thin film transistor includes a first end, a second end, and a control end, the first end is connected to one of the substrate wires, and the second end One end of the gate line is connected.
  • the substrate circuit further includes a plurality of pixel test areas, each of the pixel test areas including a first test pad and a plurality of second test pads.
  • the first test pad electrically connects the control terminal of the thin film transistor and the chip region.
  • the plurality of second test pads are electrically connected to the first ends of the thin film transistors, respectively.
  • the first end is a source
  • the second end is a drain
  • the control end is a gate
  • the chip area emits a control signal for selectively turning on/off the switch.
  • Another object of the present invention is to provide a display panel.
  • the present invention provides a display panel including the substrate circuit and a main board.
  • the motherboard is coupled to the substrate circuit and provides display information required by the substrate circuitry.
  • the present invention provides a substrate circuit.
  • the substrate circuit comprises a chip area, a plurality of substrate lead areas, a plurality of substrate gate drive circuit areas, a plurality of switches, an active area, a soft board area and an external connection area.
  • the plurality of substrate lead regions includes a plurality of substrate leads, and the plurality of substrate leads are electrically connected to the chip region.
  • the plurality of substrate gate drive circuit regions includes a plurality of gate lines, each of the gate lines being electrically connected to one of the substrate wires. Each of the switches is connected between one of the gate lines and one of the substrate wires.
  • the active region is connected to the plurality of substrate gate drive circuit regions.
  • the active area includes a plurality of pixel units, and the pixel unit connects the plurality of substrate gate driving circuit regions and the plurality of data lines of the chip region.
  • the soft board area is configured to connect the chip area to an external component.
  • the external connection area is configured to receive a plurality of data lines connecting the active area and the chip area.
  • the chip area sends a control signal for selectively turning on/off the switch, and the chip area further sends a test signal, and the test signal can be selected to pass through the plurality of substrate wires according to the control signal.
  • each of the switches includes a thin film transistor
  • the thin film transistor includes a first end, a second end, and a control end, the first end is connected to one of the substrate wires, and the second end One end of the gate line is connected.
  • the substrate circuit further includes a plurality of pixel test areas, each of the pixel test areas including a first test pad and a plurality of second test pads.
  • the first test pad electrically connects the control terminal of the thin film transistor and the chip region.
  • the plurality of second test pads are electrically connected to the first ends of the thin film transistors, respectively.
  • the first end is a source
  • the second end is a drain
  • the control end is a gate
  • FIG. 1 is a schematic view of a substrate circuit of a conventional display panel.
  • FIG. 2 is a connection diagram of the pixel test circuit of FIG. 1.
  • FIG 3 is a schematic view of a substrate circuit of a display panel of the present invention.
  • FIG. 4 is a connection diagram of the pixel test circuit of FIG. 3.
  • FIG. 5 is a timing chart showing the operation of the substrate circuit of FIG. 3 in actual operation.
  • the substrate circuit 100 is disposed on a substrate 190, and includes: an active region 110, a plurality of substrate gate driving circuit regions 180, an external connection region 120, a plurality of substrate wiring regions 130, a chip region 140, and a soft The board area 150, the plurality of pixel test areas 160, and a plurality of switches.
  • the flexible board 150 is used to connect an external component 192 (ie, a motherboard).
  • the chip area 140 is electrically connected to the flexible board 150.
  • the plurality of substrate lead regions 130 includes a plurality of substrate leads 132 electrically connected to the chip region 140.
  • the plurality of substrate gate drive circuit regions 180 includes a plurality of gate lines 182, each of which is electrically coupled to one of the substrate wires 132.
  • the active region 110 connects the plurality of substrate gate drive circuit regions 180.
  • Each of the switches 162 is connected between one of the gate lines 182 and one of the substrate wires 132.
  • the active area 110 includes a plurality of pixel units 112 that connect the substrate gate driving circuit area 180 and the plurality of data lines 146 of the chip area 140. Carefully, the pixel unit 112 is electrically coupled to a plurality of drive signal lines 184 of the substrate gate drive circuit region 180.
  • the external connection area is configured to receive a plurality of data lines connecting the active area and the chip area.
  • Each of the pixel test zones 160 includes a first test pad 164 and a plurality of second test pads 166.
  • the plurality of substrate gate driving circuit regions 180, the plurality of substrate wiring regions 130, and the chip region 140 constitute a pixel test circuit 200.
  • the substrate 190 may be a glass substrate.
  • the substrate 190 further includes a main board 192 for connecting the soft board area 150 to provide information required by the board circuit 100.
  • FIG. 4 is a schematic diagram showing the connection of the pixel test circuit 200 of FIG.
  • the switch 162 is a thin film transistor.
  • the switch 162 includes a first end, a second end and a control end.
  • the first end is connected to one of the substrate wires 132, and the second end is connected to one of the gate lines 182.
  • the first end is a source
  • the second end is a drain
  • the control end is a gate.
  • the first test pad 164 and the chip area 140 are electrically connected to the control end of the switch 162.
  • the plurality of second test pads 166 are electrically connected to the first ends of the switches 162, respectively.
  • a control signal from the chip area is used to selectively turn the switch 162 on/off according to test requirements.
  • the present invention can effectively distinguish that the problem occurs in the plurality of substrate gate drive circuit regions 180 or the plurality of substrate lead regions 130.
  • the high RC load waveform of the test signal 144 sent by the pixel test circuit 200 to the chip area 140 passes through the plurality of substrate lead regions 130 and the plurality of substrate gate drive circuit regions 180.
  • the switch 162 can be turned on by a control signal 142 from the chip area; the test signal 144 emitted by the pixel test circuit 200 to the chip area 140 passes through the plurality of substrate lead areas 130.
  • the switch 162 can be turned off by the control signal 142 to avoid the influence of the RC load of the plurality of substrate gate drive circuit regions 180.
  • FIG. 5 is a timing chart showing the operation of the substrate circuit 100 of FIG. 3 in actual operation.
  • the effect of the RC load of a test result signal 148 output waveform can be controlled by the control signal 142.
  • the control signal 142 is at a high level, the panel is normally driven, and the test signal 144 is a high RC load after passing through the plurality of substrate lead regions 130 and the plurality of substrate gate drive circuit regions 180.
  • Waveform When the control signal 142 is at a low level, the panel drive is turned off, and the test signal 144 is a waveform of a low RC load after passing through the plurality of substrate lead regions 130 regions.
  • the equivalent RC load signal cannot meet the Gate drive, it is easy to find the RC anomaly area by comparing the waveforms of the low RC load and the high RC load, which provides a powerful reference for product design. For example, if the two waveforms are similar, it is desirable to reduce the RC load of the plurality of substrate conductor regions 130 regions. If the two waveforms are too different, it is necessary to modify the chip that reduces the RC load of the plurality of substrate gate drive circuit regions 180 or replaces the larger drive capability.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Automation & Control Theory (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种用于基板电路。所述基板电路包括一基板（190）、一软板区（150）、一芯片区（140）、多个基板导线区（130）、多个基板栅极驱动电路区（180）及多个开关（162）。所述多个基板导线区（130）包括多条基板导线（132），所述多条基板导线（132）与所述芯片区（140）电气连接。所述多个基板栅极驱动电路区（180）包括多条栅极线（182），每一所述栅极线（182）与所述基板导线（132）之一电气连接。每一所述开关（162）连接于一条所述栅极线（182）与一条所述基板导线（132）之间。

Description

基板电路及显示面板 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种基于LTPS(Low-Temperature Poly-Si)面板的基板电路及显示面板，特别适用于信号测试。
 背景技术
随着低温多晶硅（LTPS）半导体薄膜晶体管的发展以及LTPS半导体本身超高载流子迁移率的特性，面板周边集成电路成为业界关注的焦点。出现大量关于System on Panel（SOP）的研究，使SOP逐步成为现实。
在一般面板设计的过程中，画素测试(Cell Test)电路只局限于面板成盒后的测试，利用率较低。
利用传统的画素测试电路进行驱动信号量测的过程中，面板GOA的负载会严重影响驱动信号的RC负载，影响IC侧经过WOA区域后的低RC负载波形的量测。
如图1所示，一传统的显示面板的基板电路的示意图。所述基板包括：主动区(Active)11、基板栅极驱动电路区(Gate On Array, GOA)18、外部连接区(Fanout)12、基板导线区(Wire On Array,WOA)13，芯片区(Integrated Chip, IC)14、软板区(Flexible Printed Circuit, FPC)15及画素测试区(Cell Test Region)16。主动区11用于像素的显示。基板栅极驱动电路区18用于产生所述面板内的薄膜晶体管的栅极驱动信号。外部连接区12用于芯片区14与主动区11之间数据线的走线连接；画素测试区16包括多个测试垫17，画素测试区16用于测试画素的显示效果。基板导线区13用于面板周围走线的连接。芯片区14用于芯片的连接，通过芯片驱动面板内的电路和薄膜晶体管。软板区15用于连接一主板。
如图2所示，图1中的画素测试电路的连接示意图。其中，在进行画素测试时，芯片区14是没有连接上去的。此时，信号从所述多个测试垫17输入到基板导线区13的走线之中，然后经由基板导线区13走线连接至基板栅极驱动电路区18，再驱动所述主动区11。由图可以看出，在面板设计当中，信号线也要从芯片区14侧引出，跟画素测试区16的信号线相互对应，以便于芯片区14连接之后通过芯片区14来进行面板10的驱动控制。
在传统面板中，只通过图2所示所述多个测试垫17量测信号，此时量测的信号是经过所述基板导线区13和所述基板栅极驱动电路区18的高RC负载之后输出的波形，如果RC负载出现问题，则不能确定是所述基板导线区13的问题，还是所述基板栅极驱动电路区18的问题。
故，有必要提出一种技术方案以解决上述问题。
 技术问题
本发明提供一种利用信号测试垫进行面板驱动信号测量的方法，提高了画素测试电路的有效利用率。
 技术解决方案
本发明提供的电路在输入到GOA模块的信号线之前添加了TFT的控制模块，用于控制输入到GOA内部的信号，实现对于面板驱动信号的有效控制。
本发明提供的电路设计不仅能够实现芯片区经过基板导线区和基板栅极驱动电路区的高RC负载之后输出的波形，也能够实现芯片区的信号经过基板导线区后低RC负载的波形准确的监控和量测。当量测的高RC负载信号不能够满足栅极线的驱动时，通过比对低RC负载和高RC负载的波形，很容易发现RC异常的区域(WOA或GOA)，为产品设计提供有力的参考。
本发明的目的在于提供一种基板电路，设置于一基板，特别适用于信号测试。
为实现上述目的，本发明提供一种用于基板电路。所术基板电路包括一芯片区、多个基板导线区、多个基板栅极驱动电路区、多个开关、一主动区、一软板区及外部连接区。
所述多个基板导线区包括多条基板导线，所述多条基板导线与所述芯片区电气连接。所述多个基板栅极驱动电路区包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接。每一所述开关连接于一条所述栅极线与一条所述基板导线之间。所述主动区，连接所述多个基板栅极驱动电路区。所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线。所述软板区，用于连接所述芯片区至一外部组件。所述外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。所述芯片区发出一控制信号，用于选择性导通/断开所述开关，所述芯片区还发出一测试信号，所述测试信号可根据所述控制信号选择经过所述多个基板导线区及所述多个基板栅极驱动电路区或仅经过所述多个基板导线区，所述基板为一玻璃基板。
在一实施例中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
在一实施例中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括第一测试垫及多个第二测试垫。所述第一测试垫电气连接所述薄膜晶体管的所述控制端及所述芯片区。所述多个第二测试垫分别电气连接所述薄膜晶体管的第一端。
在一实施例中，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。
本发明的目的在于提供一种基板电路，设置于一基板，特别适用于信号测试。
为实现上述目的，本发明提供一种用于基板电路。所术基板电路包括一芯片区、多个基板导线区、多个基板栅极驱动电路区及多个开关。
所述多个基板导线区包括多条基板导线，所述多条基板导线与所述芯片区电气连接。所述多个基板栅极驱动电路区包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接。每一所述开关连接于一条所述栅极线与一条所述基板导线之间。
在一实施例中，所述基板电路还包含一主动区，连接所述多个基板栅极驱动电路区。所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线。
在一实施例中，所述基板为一玻璃基板。
在一实施例中，所述基板电路还包括一软板区，用于连接所述芯片区至一外部组件。
在一实施例中，所述基板电路还包括一外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。
在一实施例中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
在一实施例中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括第一测试垫及多个第二测试垫。所述第一测试垫电气连接所述薄膜晶体管的所述控制端及所述芯片区。所述多个第二测试垫分别电气连接所述薄膜晶体管的第一端。
在一实施例中，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。
在一实施例中，所述芯片区发出一控制信号，用于选择性导通/断开所述开关。
本发明的另一目的在于提供一种显示面板。
为实现上述目的，本发明提供一种包括所述基板电路及一主板的显示面板。该主板与该基板电路连接并提供所述基板电路所需显示信息。本发明提供一种用于基板电路。所术基板电路包括一芯片区、多个基板导线区、多个基板栅极驱动电路区、多个开关、一主动区、一软板区及外部连接区。
所述多个基板导线区包括多条基板导线，所述多条基板导线与所述芯片区电气连接。所述多个基板栅极驱动电路区包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接。每一所述开关连接于一条所述栅极线与一条所述基板导线之间。所述主动区，连接所述多个基板栅极驱动电路区。所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线。所述软板区，用于连接所述芯片区至一外部组件。所述外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。所述芯片区发出一控制信号，用于选择性导通/断开所述开关，所述芯片区还发出一测试信号，所述测试信号可根据所述控制信号选择经过所述多个基板导线区及所述多个基板栅极驱动电路区或仅经过所述多个基板导线区，所述基板为一玻璃基板。
在一实施例中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
在一实施例中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括第一测试垫及多个第二测试垫。所述第一测试垫电气连接所述薄膜晶体管的所述控制端及所述芯片区。所述多个第二测试垫分别电气连接所述薄膜晶体管的第一端。
在一实施例中，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。
 有益效果
通过本发明的上述技术方案，产生的有益技术效果在于：
1.提高了画素测试电路的有效利用率。
2.通过比对低RC负载和高RC负载的波形，很容易发现RC异常的区域(WOA或GOA)，为产品设计提供有力的参考。
 附图说明
图1为一传统的显示面板的基板电路的示意图。
图2为图1中的画素测试电路的连接示意图。
图3为本发明的显示面板的基板电路的示意图。
图4为图3中的画素测试电路的连接示意图。
图5为图3的基板电路在实际操作时的工作时序图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
图3为本发明的显示面板的基板电路100的示意图。所述基板电路100设置于一基板190上，包括：、一主动区110、多个基板栅极驱动电路区180、一外部连接区120、多个基板导线区130，一芯片区140、一软板区150、多个画素测试区160及多个开关。所述软板150用于连接一外部组件192(即主板)。所述芯片区140电气连接所述软板150。所述多个基板导线区130包括多条基板导线132，所述多条基板导线132与所述芯片区140电气连接。所述多个基板栅极驱动电路区180包括多条栅极线182，每一所述栅极线182与所述基板导线132之一电气连接。所述主动区110连接所述多个基板栅极驱动电路区180。每一所述开关162连接于一条所述栅极线182与一条所述基板导线132之间。所述主动区110包括多个画素单元112，所述画素单元112连接所述基板栅极驱动电路区180及所述芯片区140的多条数据线146。仔细地，所述画素单元112是与所述基板栅极驱动电路区180的多条驱动信号线184电气连接。所述外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。每一所述画素测试区160包括第一测试垫164及多个第二测试垫166。其中所述多个基板栅极驱动电路区180、所述多个基板导线区130与所述芯片区140构成一画素测试电路200。
在本实施例中，所述基板190可以为玻璃基板。所述基板190还包括一主板192，用于连接所述软板区150，以提供所述基板电路100所需信息。
图4为图3中的画素测试电路200的连接示意图。在本实施例中，所述开关162是一薄膜晶体管。所述开关162包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线132，所述第二端连接一条所述栅极线182。仔细地，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。所述第一测试垫164及所述芯片区140电气连接所述开关162的所述控制端。所述多个第二测试垫166分别电气连接所述开关162的第一端。根据测试需求，所述芯片区发出的一控制信号用于选择性导通/断开所述开关162。这也是本发明能够有效分辨问题是出现在所述多个基板栅极驱动电路区180或所述多个基板导线区130之中的原因。由示意图可知，在画素测试电路200对所述芯片区140发出的一测试信号144经过所述多个基板导线区130和所述多个基板栅极驱动电路区180后的高RC负载波形进行量侧的时候，可以通过芯片区发出的一控制信号142打开所述开关162；在画素测试电路200对所述芯片区140发出的所述测试信号144经过所述多个基板导线区130后的低RC负载波形进行量侧的时候，可以通过所述控制信号142关闭所述开关162，避免所述多个基板栅极驱动电路区180的RC负载的影响。
图5为图3的基板电路100在实际操作时的工作时序图。由时序图可知，可以通过所述控制信号142控制一测试结果信号148输出波形的RC负载的效果。当所述控制信号142为高电平时，面板正常驱动，所述测试信号144为经过所述多个基板导线区130和所述多个基板栅极驱动电路区180两个区域后的高RC负载的波形。当所述控制信号142为低电平时，面板驱动关闭，所述测试信号144为经过所述多个基板导线区130区域后低RC负载的波形。当量测的高RC负载信号不能够满足Gate的驱动时，通过比对低RC负载和高RC负载的波形，很容易发现RC异常的区域，为产品设计提供有力的参考。比如，如果两个波形差不多，则需要减小所述多个基板导线区130区域的RC负载。如果两个波形差别过大，则需要修改减小所述多个基板栅极驱动电路区180区域的RC负载或者更换更大驱动能力的芯片。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种基板电路，设置于一基板，其中，包括：
    一芯片区；
    多个基板导线区，各包括多条基板导线，所述多条基板导线与所述芯片区电气连接；
    多个基板栅极驱动电路区，各包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接；
    多个开关，每一所述开关连接于一条所述栅极线与一条所述基板导线之间；
    一主动区，连接所述多个基板栅极驱动电路区，所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线；
    一软板区，用于连接所述芯片区至一外部组件；及
    一外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线；
    其中所述芯片区发出一控制信号，用于选择性导通/断开所述开关，所述芯片区还发出一测试信号，所述测试信号可根据所述控制信号选择经过所述多个基板导线区及所述多个基板栅极驱动电路区或仅经过所述多个基板导线区，所述基板为一玻璃基板。
  2. 如权利要求1 所述的基板电路，其中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
  3. 如权利要求2 所述的基板电路，其中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括：
    第一测试垫，电气连接所述薄膜晶体管的所述控制端与所述芯片区；及
    多个第二测试垫，分别电气连接所述薄膜晶体管的第一端。
  4. 如权利要求2 所述的基板电路，其中，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。
  5. 一种基板电路，设置于一基板，其中，包括：
    一芯片区；
    多个基板导线区，各包括多条基板导线，所述多条基板导线与所述芯片区电气连接；
    多个基板栅极驱动电路区，各包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接；
    及
    多个开关，每一所述开关连接于一条所述栅极线与一条所述基板导线之间。
  6. 如权利要求5 所述的基板电路，其中，还包含一主动区，连接所述多个基板栅极驱动电路区，所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线。
  7. 如权利要求5 所述的基板电路，其中，所述基板为一玻璃基板。
  8. 如权利要求5 所述的基板电路，其中，所述基板电路还包括一软板区，用于连接所述芯片区至一外部组件。
  9. 如权利要求5 所述的基板电路，其中，所述基板电路还包括一外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线。
  10. 如权利要求5 所述的基板电路，其中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
  11. 如权利要求10 所述的基板电路，其中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括：
    第一测试垫，电气连接所述薄膜晶体管的所述控制端与所述芯片区；及
    多个第二测试垫，分别电气连接所述薄膜晶体管的第一端。
  12. 如权利要求10 所述的基板电路，其中，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。
  13. 如权利要求5 所述的基板电路，其中，所述芯片区发出一控制信号，用于选择性导通/断开所述开关。
  14. 一种显示面板，其中，包括：
    基板电路及一主板，其中该主板与该基板电路连接并提供所述基板电路所需显示信息，所述基板电路包括：
    一芯片区；
    多个基板导线区，各包括多条基板导线，所述多条基板导线与所述芯片区电气连接；
    多个基板栅极驱动电路区，各包括多条栅极线，每一所述栅极线与所述基板导线之一电气连接；
    多个开关，每一所述开关连接于一条所述栅极线与一条所述基板导线之间；
    一主动区，连接所述多个基板栅极驱动电路区，所述主动区包括多个画素单元，所述画素单元连接所述多个基板栅极驱动电路区及所述芯片区的多条数据线；
    一软板区，用于连接所述芯片区至一外部组件；及
    一外部连接区，用于收容连接所述主动区与所述芯片区的多条数据线；
    其中所述芯片区发出一控制信号，用于选择性导通/断开所述开关，所述芯片区还发出一测试信号，所述测试信号可根据所述控制信号选择经过所述多个基板导线区及所述多个基板栅极驱动电路区或仅经过所述多个基板导线区，所述基板为一玻璃基板。
  15. 如权利要求14所述的显示面板，其中，各所述开关包含一薄膜晶体管，所述薄膜晶体管包括一第一端、一第二端及一控制端，所述第一端连接一条所述基板导线，所述第二端连接一条所述栅极线。
  16. 如权利要求15 所述的显示面板，其中，所述基板电路还包括多个画素测试区，每一所述画素测试区包括：
    第一测试垫，电气连接所述薄膜晶体管的所述控制端与所述芯片区；及
    多个第二测试垫，分别电气连接所述薄膜晶体管的第一端。
  17. 如权利要求15 所述的显示面板，其中，所述第一端是源极、所述第二端是汲极及所述控制端是栅极。
PCT/CN2015/086588 2015-07-29 2015-08-11 基板电路及显示面板 WO2017015989A1 (zh)

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