WO2017063204A1 - 一种显示面板、液晶显示器及显示面板的制备方法 - Google Patents

一种显示面板、液晶显示器及显示面板的制备方法 Download PDF

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Publication number
WO2017063204A1
WO2017063204A1 PCT/CN2015/092359 CN2015092359W WO2017063204A1 WO 2017063204 A1 WO2017063204 A1 WO 2017063204A1 CN 2015092359 W CN2015092359 W CN 2015092359W WO 2017063204 A1 WO2017063204 A1 WO 2017063204A1
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WIPO (PCT)
Prior art keywords
display panel
voltage
common voltage
color filter
array substrate
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PCT/CN2015/092359
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English (en)
French (fr)
Inventor
陈政鸿
姜佳丽
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深圳市华星光电技术有限公司
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Priority to US14/892,686 priority Critical patent/US20170192330A1/en
Publication of WO2017063204A1 publication Critical patent/WO2017063204A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/15—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on an electrochromic effect
    • G02F1/153—Constructional details
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133788—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by light irradiation, e.g. linearly polarised light photo-polymerisation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133354—Arrangements for aligning or assembling substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a display panel, a liquid crystal display, and a method for preparing the display panel.
  • LCD displays have two major display technologies, one is planar conversion (In-Plane) Switching, IPS) technology, the other is vertical alignment (Vertical Alignment, VA) technology, in which vertical alignment type liquid crystal displays are widely used due to their advantages of fast response speed and high contrast.
  • planar conversion In-Plane
  • IPS Planar conversion
  • VA Vertical Alignment
  • a conductive sheet is provided around the display panel of the liquid crystal display (Transfer) Pad), after the display panel is assembled, the common voltage Array-Vcom on the array substrate in the display panel is electrically connected with the common voltage CF-Vcom on the color filter substrate.
  • the usual process is to charge (or turn on) the scan lines connected to the sub-pixel units in the display panel, and the data lines connected to the sub-pixel units are grounded to the array substrate.
  • the common voltage Array-Vcom is connected to the AC signal (or other signal suitable for liquid crystal molecules for alignment curing), so that the pixel electrode of the sub-pixel unit and the data line potential are kept at the ground potential, and the common voltage of the color filter substrate CF-Vcom Consistent with the common voltage Array-Vcom of the array substrate as an alternating current signal, and further between the pixel electrode of the sub-pixel unit and the common electrode of the color filter substrate (the signal thereon is the common voltage CF-Vcom of the color filter substrate)
  • a suitable voltage difference is formed at both ends of the liquid crystal layer, and liquid crystal molecules in the liquid crystal layer can be aligned according to a preset tilt angle, and then cured under suitable illumination to achieve alignment of the liquid crystal layer.
  • the common voltage of the array substrate is realized by a functional circuit module, and the functional circuit module is directly or indirectly connected to the common electrode of the pixel electrode, the data line and the array substrate corresponding to the sub-pixel unit in the array substrate.
  • the change of the common voltage of the array substrate directly affects the voltage change of the pixel electrode. Therefore, a voltage difference suitable for the alignment of the liquid crystal layer cannot be formed between the pixel electrode and the color filter substrate, thereby causing poor alignment and even failing to achieve alignment.
  • the conductive film is disposed at the periphery thereof to realize the common voltage of the array substrate and the common voltage conduction of the color filter substrate cannot meet the requirements of the liquid crystal display with adaptive common voltage in the alignment. .
  • the technical problem to be solved by the present invention is to provide a display panel, a liquid crystal display, and a method for preparing the display panel, so that a stable voltage difference for alignment of the liquid crystal layer can be formed between the color filter substrate and the array substrate.
  • one technical solution adopted by the present invention is to provide a display panel including an array substrate and a color filter substrate which are disposed at intervals, the display panel further includes at least one semiconductor switch tube, and the semiconductor switch tube includes a control a terminal, an input end, and an output end, wherein one of the input end and the output end is connected to a common voltage of the array substrate, the other is connected to a common voltage of the color filter substrate, and the array substrate is controlled by controlling a signal applied to the control end The conduction and disconnection between the common voltage and the common voltage of the color filter substrate.
  • the first control voltage is applied to the control end to cause a closed state between the input end and the output end, thereby causing the common voltage of the array substrate and the common voltage of the color filter substrate to be disconnected;
  • the input terminal and the output terminal are rendered conductive by applying a second control voltage to the control terminal, thereby conducting conduction between the common voltage of the array substrate and the common voltage of the color filter substrate.
  • the semiconductor switch transistor is a thin film transistor, the control terminal is a gate of the thin film transistor, the input end is a source of the thin film transistor, and the output end is a drain of the thin film transistor.
  • the first control voltage is a low voltage
  • the second control voltage is a high voltage
  • the first control voltage is a signal of -8v ⁇ 0v
  • the second control voltage is a signal of 25v ⁇ 35v.
  • the semiconductor switch tube is disposed in a non-display area of the display panel.
  • the plurality of semiconductor switching tubes are disposed on the array substrate at intervals and located at a peripheral edge of the non-display area.
  • a plurality of semiconductor switch tubes are disposed on the color filter substrate at intervals, and are located at a peripheral edge of the non-display area.
  • a liquid crystal display including a display panel including an array substrate and a color filter substrate which are disposed at a relatively spaced interval, and the display panel further includes at least one semiconductor The switch tube, the semiconductor switch tube includes a control end, an input end, and an output end, wherein one of the input end and the output end is connected to a common voltage of the array substrate, and the other is connected to a common voltage of the color filter substrate, and is controlled to be applied to The signal of the control terminal controls the conduction and disconnection between the common voltage of the array substrate and the common voltage of the color filter substrate.
  • the first control voltage is applied to the control end to cause a closed state between the input end and the output end, thereby causing the common voltage of the array substrate and the common voltage of the color filter substrate to be disconnected;
  • the input terminal and the output terminal are rendered conductive by applying a second control voltage to the control terminal, thereby conducting conduction between the common voltage of the array substrate and the common voltage of the color filter substrate.
  • the semiconductor switch transistor is a thin film transistor, the control terminal is a gate of the thin film transistor, the input end is a source of the thin film transistor, and the output end is a drain of the thin film transistor.
  • the first control voltage is a low voltage
  • the second control voltage is a high voltage
  • the first control voltage is a signal of -8v ⁇ 0v
  • the second control voltage is a signal of 25v ⁇ 35v.
  • the semiconductor switch tube is disposed in a non-display area of the display panel.
  • the plurality of semiconductor switching tubes are disposed on the array substrate at intervals and located at a peripheral edge of the non-display area.
  • a plurality of semiconductor switch tubes are disposed on the color filter substrate at intervals, and are located at a peripheral edge of the non-display area.
  • the display panel includes an array substrate and a color filter substrate disposed at a relatively spaced interval.
  • the preparation method includes the following steps:
  • the semiconductor switch tube includes a control end, an input end, and an output end;
  • the first control voltage is applied to the control terminal to cause the input terminal and the output terminal to be in a closed state, thereby causing the common voltage of the array substrate and the common voltage of the color filter substrate to be disconnected;
  • the input terminal and the output terminal are brought into an on state by applying a second control voltage to the control terminal, thereby conducting conduction between the common voltage of the array substrate and the common voltage of the color filter substrate.
  • the invention provides a display panel, a liquid crystal display and a method for preparing the display panel, wherein at least one semiconductor switch tube is disposed on the display panel, and the semiconductor switch tube comprises a control end, an input end and an output end, One of the input end and the output end is connected to the common voltage of the array substrate, the other is connected to the common voltage of the color filter substrate, and the common voltage of the array substrate and the common voltage of the color filter substrate are controlled by controlling signals applied to the control end. Between and off. After the display panel provided by the present invention is assembled, the conductive film is no longer disposed at the peripheral edge thereof to realize the common voltage of the array substrate and the common voltage conduction of the color filter substrate.
  • the present invention controls the semiconductor switch tube by comparing with the prior art.
  • the signal at the control end enables the conduction and disconnection between the common voltage of the array substrate and the common voltage of the color filter substrate, and the voltage of the pixel electrode of the array substrate and the common voltage of the color filter substrate are independent of each other when disconnected.
  • the signal can be separately controlled, so that a voltage difference for alignment of the liquid crystal layer can be formed between the color film substrate and the array substrate, and the liquid crystal display with adaptive common voltage can be normally aligned to improve display quality and display effect;
  • the common voltage of the array substrate can be transmitted to the color filter substrate.
  • FIG. 1 is a schematic structural view of an embodiment of a display panel provided by the present invention.
  • Figure 2 is a schematic cross-sectional view of the display panel of Figure 1 along C-C;
  • FIG. 3 is a schematic structural view of the semiconductor switching transistor of FIG. 1 as a thin film transistor
  • FIG. 4 is a schematic diagram showing an equivalent circuit of the display panel of FIG. 1 including a plurality of sub-pixel units;
  • FIG. 5 is a timing diagram of forming a preset AC voltage difference in the liquid crystal layer in FIG. 4;
  • FIG. 6 is a schematic structural view of another embodiment of a display panel provided by the present invention.
  • FIG. 7 is a schematic structural view of an embodiment of a liquid crystal display provided by the present invention.
  • FIG. 8 is a schematic flow chart of an embodiment of a method for preparing a display panel provided by the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of a display panel provided by the present invention
  • FIG. 2 is a cross-sectional structural view of the display panel of FIG. 1 along C-C.
  • the display panel 10 includes an array substrate 111 and a color filter substrate 112 disposed at a relatively spaced interval, and a liquid crystal layer 113 between the color filter substrate 112 and the array substrate 111.
  • the display panel 10 is shown in FIG. Also included is at least one semiconductor switching transistor 114, exemplified in FIG.
  • FIG. 1 comprising a semiconductor switching transistor 114 comprising a control terminal i, an input terminal j and an output terminal k, wherein one of the input terminal j and the output terminal k is connected to the array
  • the common voltage Array-Vcom of the substrate 111 and the common voltage CF-Vcom of the color filter substrate 112 are connected.
  • the example shown in FIG. 1 is the common voltage Array-Vcom of the input terminal j connected to the array substrate 111 (shown as A in FIG. 1).
  • -Vcom the output terminal k is connected to the common voltage CF-Vcom of the color filter substrate 112, and the common voltage Array-Vcom of the array substrate 111 and the common voltage CF of the color filter substrate 112 are controlled by controlling signals applied to the control terminal i. - Turn on and off between Vcom.
  • the conduction and disconnection between the common voltage Array-Vcom of the array substrate 111 and the common voltage CF-Vcom of the color filter substrate 112 are specifically provided by disposing a conductive sheet on the display panel 10, thereby providing the semiconductor switch tube 114. to realise.
  • the upper surface of the array substrate 111 is provided with a pixel electrode 115 and a common electrode 117 insulated from the pixel electrode 115 .
  • the surface of the color filter substrate 112 is provided with a common electrode 116 .
  • the signal applied or possessed on the common electrode 117 of the array substrate 111 is the common voltage Array-Vcom of the array substrate 111
  • the signal applied or provided on the common electrode 116 of the color filter substrate 112 is the common voltage CF-Vcom of the color filter substrate 112. .
  • the first control voltage is applied to the control terminal i such that the input terminal j and the output terminal k are in a closed state, thereby causing the common voltage Array-Vcom of the array substrate 111 and the color filter substrate 112.
  • the common voltage CF-Vcom is disconnected.
  • the input terminal j and the output terminal k of the semiconductor switch tube 114 are in a closed state, and the leakage current is small, if it is applied to the common electrode 116 of the color filter substrate 112.
  • the common voltage CF-Vcom When the common voltage CF-Vcom is aligned, the common voltage CF-Vcom cannot be transmitted to the common electrode 117 of the array substrate 111 via the semiconductor switch 114 to form a common voltage Array-Vcom, thereby failing to affect the voltage of the pixel electrode 115. That is, the voltage of the pixel electrode 115 exhibits a different voltage difference from the common voltage CF-Vcom of the color filter substrate 112 for forming a preset voltage difference between the array substrate 111 and the color filter substrate 112 that can achieve the alignment of the liquid crystal layer 113.
  • the input terminal j and the output terminal k are rendered conductive by applying a second control voltage to the control terminal i, thereby causing the array substrate 1 to be turned on.
  • the common voltage Array-Vcom of 11 and the common voltage CF-Vcom of the color filter substrate 112 are turned on to realize normal display of the display panel 10.
  • FIG. 3 is a schematic structural view of the semiconductor switch transistor of FIG. 1 as a thin film transistor.
  • the semiconductor switch transistor 114 is a thin film transistor TFT
  • FIG. 3 is an example of an N-type thin film transistor TFT.
  • the control terminal i is the gate G of the thin film transistor TFT.
  • the input terminal j is the source S of the thin film transistor TFT
  • the output terminal k is the drain D of the thin film transistor TFT.
  • the input terminal j is also the drain D of the thin film transistor TFT
  • the output terminal k is the source S of the thin film transistor TFT.
  • the thin film transistor TFT when the thin film transistor TFT is N-type, when the voltage applied to the gate G is a low voltage, the source S and the drain D of the thin film transistor TFT are in a closed state; when the voltage applied to the gate G is a high voltage The source S and the drain D of the thin film transistor TFT are in an on state.
  • the first control voltage applied to the control terminal i is a low voltage, so that a closed state is present between the input terminal j and the output terminal k; and the second control voltage applied to the control terminal i is a high voltage, so that the input A conduction state is present between the terminal j and the output terminal k.
  • the first control voltage is a signal of -8v ⁇ 0v
  • the second control voltage is a signal of 25v ⁇ 35v.
  • the thin film transistor TFT when the thin film transistor TFT is of a P type, when the voltage applied to the gate G is a high voltage, the source S and the drain D of the thin film transistor TFT are in a closed state; when the voltage applied to the gate G is a low voltage The source S and the drain D of the thin film transistor TFT are in an on state.
  • the semiconductor switch transistor 114 can be a field effect transistor FET, such as a junction field effect transistor (JFET) or an insulated gate field effect transistor (MOSFET), in which case the control terminal i is the gate of the FET FET.
  • the terminal G is the source S of the FET, and the output terminal k is the drain D of the FET, which is similar to the operation of the semiconductor transistor 114 as a thin film transistor TFT, and will not be described here. .
  • FIG. 4 is an equivalent circuit diagram of the display panel of FIG. 1 including a plurality of sub-pixel units.
  • the display panel 10 includes a plurality of sub-pixel units Pixel arranged in an array in a row direction and a column direction, a plurality of data lines arranged in a column direction, and a plurality of scanning lines arranged in a row direction, in FIG.
  • each sub-pixel unit Pixel includes a pixel FET T and a capacitor sub-unit M, and the pixel FET T includes a gate (G) The source (S) and the drain (D), the gate G of the pixel field effect transistor T is connected to the corresponding scan line to receive the row driving signal, and the source S of the pixel field effect transistor T is connected to the data line of the corresponding column.
  • the capacitor sub-unit M includes a liquid crystal capacitor Clc and a storage capacitor Cs formed by liquid crystal molecules in the parallel liquid crystal layer 113, wherein the liquid crystal capacitor Clc of each sub-pixel unit T and the same end of the storage capacitor Cs are connected to corresponding pixel field effects.
  • the drain D of the tube T specifically, the drain D of the pixel field effect transistor T is connected to the pixel electrode 115 (as shown in FIG. 2), such that one end of the liquid crystal capacitor Clc is connected to the pixel electrode 115, and the other end of the liquid crystal capacitor Clc is passed.
  • the common electrode 116 is connected to the common voltage CF-Vcom of the color filter substrate 112, and the other end of the storage capacitor Cs is connected to the common voltage Array-Vcom of the array substrate 111 by connecting the common electrode 117 of the array substrate 111 (in FIG.
  • the array substrate 111, and the liquid crystal layer 113 are assembled as the display panel 10, and in the forward direction, when the common voltage of the array substrate 111 is Array-Vcom and the color filter substrate
  • the common voltage CF-Vcom of 112 is turned off, the gate G of each of the pixel field effect transistors T is turned on, and the third control voltage is input through the data line connected to the pixel field effect transistor T, so that the corresponding The voltage of the pixel electrode 115 is the third control voltage, and the fourth control voltage is applied to the common voltage CF-Vcom of the color filter substrate 112 to form a preset AC voltage difference at both ends of the liquid crystal layer 113.
  • the array substrate 111 of the display panel 10 includes a plurality of data lines disposed along the column direction and a plurality of scan lines disposed along the row direction, and the pixel field effect transistors T disposed in the adjacent data lines and the scan line enclosure regions. And the pixel electrode 115.
  • the pixel field effect transistor T includes a gate G, a source S and a drain D.
  • the gate S of the pixel field effect transistor T is connected to a corresponding scan line to receive a row driving signal, and the source of the pixel field effect transistor T S is connected to the data line of the corresponding column to receive the column driving signal, and the drain D is connected to the corresponding pixel electrode 115, wherein each of the pixel electrode 115 and the color film substrate 112, specifically the common electrode 116 thereon, is interposed between the liquid crystal layer 113.
  • the liquid crystal molecules form a liquid crystal capacitor Clc. One end of the liquid crystal capacitor Clc is connected to the pixel electrode 115, and the other end of the liquid crystal capacitor Clc is connected to the common voltage CF-Vcom of the color filter substrate 112.
  • the color filter substrate 112, the array substrate 111 and the liquid crystal layer 113 are formed. Before or after the display panel 10 is assembled, and before the alignment is performed, when the common voltage Array-Vcom of the array substrate 111 and the common voltage CF-Vcom of the color filter substrate 112 are disconnected, each pixel field effect transistor is passed.
  • the gate G of T is turned on, and the third control voltage is input to the data line connected to the pixel field effect transistor T, and the source S of the pixel field effect transistor T connected to the corresponding data line is also the third control voltage, corresponding to Pixel field effect
  • the drain D of the tube T is also a third control voltage, so that the voltage of the corresponding pixel electrode 115 is the third control voltage, and the fourth control voltage is connected to the common voltage CF-Vcom of the color filter substrate 112 to Both ends of the layer 113 form a preset AC voltage difference.
  • FIG. 5 is a timing diagram of forming a preset AC voltage difference in the liquid crystal layer in FIG.
  • the third control voltage is the ground zero voltage
  • the fourth control voltage is the AC voltage.
  • Line indicates that a DC voltage is applied to turn on the gate G of the pixel FET T in each sub-pixel unit Pixel to the corresponding data line (Data in FIG. 5)
  • Line indicates that a ground zero voltage is applied, and at this time, the pixel electrode 115 is also grounded with zero voltage, and the liquid crystal panel of the adaptive common voltage transmits the signal on the data line to the common electrode 117 of the array substrate 111.
  • the common voltage Array-Vcom of the substrate 111 (indicated by A-Vcom in FIG. 5) is also a ground zero voltage.
  • an alternating voltage is applied as a common voltage CF-Vcom on the common electrode 116 of the color filter substrate 112, the pixel electrode 115 and the color are made.
  • the common electrode 116 of the film substrate 112, that is, the two ends of the liquid crystal layer 113 have an alternating voltage difference, and the liquid crystal molecules in the liquid crystal layer 113 can be arranged according to a preset inclination angle under the influence of an alternating voltage difference, and will be followed under appropriate illumination.
  • the liquid crystal molecules of the preset tilt angle are solidified to achieve alignment of the liquid crystal layer.
  • the third control voltage is an alternating voltage
  • the fourth control voltage is a ground zero voltage, or other predetermined alternating voltage difference that enables the third control voltage and the fourth control voltage to form a liquid crystal layer alignment. Voltage signal.
  • the semiconductor switch tube 114 is disposed in the non-display area of the display panel 10 , as shown in FIG. 1 , the area inside the dotted line is the display area of the display panel 110 , and the area is on the array substrate 111 and the color filter substrate 112 .
  • the liquid crystal layer 113 is interposed therebetween, and the other regions are non-display regions.
  • the liquid crystal layer 113 is usually not contained between the array substrate 111 and the color filter substrate 112, and is mainly used for circuit connection with an external circuit.
  • the array substrate 111 and the color filter substrate 112 are also optionally divided into a display area and a non-display area for respectively or not interposing the liquid crystal layer 113 with the oppositely disposed color film substrate 112 or the array substrate 111.
  • FIG. 6 is a schematic structural diagram of another embodiment of a display panel provided by the present invention.
  • the display panel 60 includes substantially the same elements as the display panel 10 shown in FIG. 1 and is denoted by the same reference numerals.
  • the display panel 60 differs from that of FIG. 1 in that it includes a plurality of semiconductor switch tubes 114 that are spaced apart from the non-display area of the display panel 60, and are specifically disposed at the peripheral edge of the non-display area. .
  • the plurality of semiconductor switch tubes 114 are spaced apart on the array substrate 111 and located at peripheral edges of the non-display area of the array substrate 111.
  • a plurality of semiconductor switch tubes 114 are disposed on the color filter substrate 112 at intervals and located at a peripheral edge of the non-display area of the color filter substrate 112.
  • FIG. 7 is a schematic structural diagram of an embodiment of a liquid crystal display provided by the present invention.
  • the liquid crystal display 70 includes the display panel provided by the present invention described above, that is, includes substantially the same elements as the display panel 10 or 60 shown in FIG. 1 or FIG. 6, and is denoted by the same reference numerals.
  • FIG. 7 is exemplified to include the display panel 60 of FIG.
  • the liquid crystal display 70 further includes a flexible circuit board 71 for setting a driving circuit of the display panel 10.
  • the flexible circuit board 71 can be, for example, a COF (Chip). On Flim) a flexible substrate and a driver chip disposed on the flexible substrate.
  • the flexible circuit board 71 includes a plurality of source flexible circuit boards 711 on the side of the display panel 60 and a plurality of gate sub-flexible circuit boards 712 on the horizontal sides of the display panel 60, the example in FIG.
  • the four source flexible circuit boards 711 and the six gate sub-flexible circuit boards 712 are respectively used to apply column driving signals to the data lines of the display panel 60, specifically the array substrate 111, and to the display panel 60, specifically the array substrate.
  • a row driving signal is applied to the scanning line of 111.
  • the number of the source flexible circuit board 711 and the gate sub-flexible circuit board 712 in the liquid crystal display 70 is at least two, and the specific value is not limited. In other embodiments, if the size of the display panel 60 of the liquid crystal display 70 is small, the number of the optional source flexible circuit board 711 and the gate sub-flexible circuit board 712 is one.
  • the flexible circuit board 71 and the display panel 60 are bonded, and are also located in the non-display area of the display panel 10 after bonding. Further, as shown in FIG. 7, the source sub-flexible circuit board 711 and the gate sub-flexible circuit board 712 are spaced apart from the semiconductor switch 114.
  • FIG. 8 is a schematic flow chart of an embodiment of a method for fabricating a display panel according to the present invention.
  • the display panel includes an array substrate and a color filter substrate disposed at a relatively spaced interval, and the preparation method comprises the following steps:
  • Step 801 Providing at least one semiconductor switch tube on the display panel, the semiconductor switch tube includes a control end, an input end, and an output end;
  • Step 802 Connect one of the input end and the output end to a common voltage of the array substrate, and the other to a common voltage of the color filter substrate;
  • Step 803 When the display panel performs the alignment, by applying a first control voltage to the control end, the input terminal and the output end are brought into a closed state, thereby causing the common voltage of the array substrate and the common voltage of the color filter substrate to be disconnected;
  • Step 804 When the display panel is normally operated after the alignment is completed, the input terminal and the output terminal are rendered conductive by applying a second control voltage to the control terminal, thereby causing a common voltage between the array substrate and a common voltage of the color filter substrate. through.
  • the display panel in the present embodiment has the same structure as the display panel 10 or 60 shown in FIG. 1 or FIG. 6 , and the steps 801 to 804 correspond to the operations performed by the respective components when the display panel is prepared. No longer.
  • step 803 when the common voltage of the array substrate is disconnected from the common voltage of the color filter substrate, specifically, the semiconductor switch tube is set and the input end and the output end are disconnected by not providing a conductive sheet on the display panel. achieve.
  • the preparation method further comprises the following steps:
  • the third control voltage is a ground zero voltage
  • the fourth control voltage is an alternating current voltage.
  • the third control voltage is an alternating voltage
  • the fourth control voltage is a ground zero voltage, or other predetermined alternating voltage difference that enables the third control voltage and the fourth control voltage to form a liquid crystal layer alignment. Voltage signal.
  • the preparation method further includes the following steps:
  • This step is a step of effecting alignment curing of the liquid crystal layer.
  • the display panel, the liquid crystal display and the method for preparing the display panel provided by the present invention by providing at least one semiconductor switch tube on the display panel, and the semiconductor switch tube includes a control end, an input end and an output end, One of the input end and the output end is connected to the common voltage of the array substrate, the other is connected to the common voltage of the color filter substrate, and the common voltage of the array substrate and the common voltage of the color filter substrate are controlled by controlling signals applied to the control terminal. Turn on and off. After the display panel provided by the present invention is assembled, the conductive film is no longer disposed at the peripheral edge thereof to realize the common voltage of the array substrate and the common voltage conduction of the color filter substrate.
  • the present invention controls the semiconductor switch tube by comparing with the prior art.
  • the signal at the control end enables the conduction and disconnection between the common voltage of the array substrate and the common voltage of the color filter substrate, and the voltage of the pixel electrode of the array substrate and the common voltage of the color filter substrate are independent of each other when disconnected.
  • the signal can be separately controlled, so that a voltage difference for alignment of the liquid crystal layer can be formed between the color film substrate and the array substrate, and the display panel or the liquid crystal display that realizes the adaptive common voltage can be normally aligned to improve the display quality and display. Effect; the common voltage of the array substrate can be transmitted to the color filter substrate when conducting.

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Abstract

显示面板（10）、液晶显示器（70）及显示面板（10）的制备方法。显示面板（10）上设有至少一个半导体开关管（114），且半导体开关管（114）包括控制端（i）、输入端（j）和输出端（k），将输入端（j）和输出端（k）中的一个接入阵列基板（111）的公共电压（A-Vcom），另一个接入彩膜基板（112）的公共电压（CF-Vcom），且通过控制施加到控制端（i）的信号来控制阵列基板（111）的公共电压（A-Vcom）和彩膜基板（112）的公共电压（CF-Vcom）之间的导通和断开。阵列基板（111）的公共电压（A-Vcom）和彩膜基板（112）的公共电压（CF-Vcom）之间断开时，能够在自适应公共电压的液晶显示器（70）的彩膜基板（112）与阵列基板（111）之间形成用于液晶层（113）配向的电压差，在导通时，能够将阵列基板（111）的公共电压（A-Vcom）传递至彩膜基板（112）上。

Description

一种显示面板、液晶显示器及显示面板的制备方法
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种显示面板、液晶显示器及显示面板的制备方法。
【背景技术】
液晶显示器具有两大主流显示技术，一种是平面转换 (In-Plane Switching，IPS)技术，另一种是垂直配向（Vertical Alignment，VA）技术，其中，垂直配向型液晶显示器因具有响应速度快、对比度高等优点而得到广泛应用。
现有技术中液晶显示器的显示面板周边设有传导片（Transfer Pad），用于在显示面板组立后，将显示面板中阵列基板上的公共电压Array-Vcom与彩膜基板上的公共电压CF-Vcom导通在一起。液晶显示器在实现液晶层中液晶分子的配向固化时，通常采用的制程是将显示面板中子像素单元连接的扫描线进行充电（或打开），子像素单元连接的数据线接地，同时向阵列基板的公共电压Array-Vcom接入交流信号(或其他适合液晶分子进行配向固化的信号)，使得子像素单元的像素电极与数据线电位保持一致为接地电位，而彩膜基板的公共电压CF-Vcom与阵列基板的公共电压Array-Vcom保持一致为交流信号，进而在子像素单元的像素电极与彩膜基板的公共电极（其上具有的信号为彩膜基板的公共电压CF-Vcom）之间的液晶层的两端形成合适的电压差，进而液晶层中的液晶分子能够按照预设的倾角排列，然后在适合的光照下进行固化以实现液晶层的配向。
近来，出现了自适应公共电压（Self-adjust Vcom）的液晶显示器，其阵列基板的公共电压是通过一功能电路模块实现，而该功能电路模块分别与阵列基板中子像素单元对应的像素电极、数据线和阵列基板的公共电压直接或间接连接，此时阵列基板的公共电压的变化将直接影响像素电极的电压变化，因此像素电极与彩膜基板之间不能形成适于液晶层配向的电压差，进而导致配向不良，甚至无法实现配向。
综上，现有在液晶显示面板组立后，在其周边设置传导片实现阵列基板的公共电压与彩膜基板的公共电压导通的技术不能满足自适应公共电压的液晶显示器在配向时的要求。
【发明内容】
本发明主要解决的技术问题是提供一种显示面板、液晶显示器及显示面板的制备方法，使得彩膜基板与阵列基板之间能够形成用于液晶层配向的稳定的电压差。
为解决上述技术问题，本发明采用的一个技术方案是提供一种显示面板，该显示面板包括相对间隔设置的阵列基板和彩膜基板，显示面板还包括至少一个半导体开关管，半导体开关管包括控制端、输入端和输出端，其中，输入端和输出端中的一个接入阵列基板的公共电压，另一个接入彩膜基板的公共电压，且通过控制施加至控制端的信号来控制阵列基板的公共电压和彩膜基板的公共电压之间的导通和断开。
其中，在显示面板进行配向时，通过向控制端施加第一控制电压使得输入端和输出端之间呈现关闭状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间断开；在完成配向后显示面板正常工作时，通过向控制端施加第二控制电压使得输入端和输出端呈现导通状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间导通。
其中，半导体开关管为薄膜晶体管，控制端为薄膜晶体管的栅极，输入端为薄膜晶体管的源极，输出端为薄膜晶体管的漏极。
其中，第一控制电压为低电压，第二控制电压为高电压。
其中，第一控制电压为-8v~0v的信号，第二控制电压为25v~35v的信号。
其中，半导体开关管设置在显示面板的非显示区域。
其中，多个半导体开关管间隔设置在阵列基板上，且位于非显示区域的周边边缘。
可选的，多个半导体开关管间隔设置在彩膜基板上，且位于非显示区域的周边边缘。
为解决上述技术问题，本发明采用的另一个技术方案是提供一种液晶显示器，该液晶显示器包括显示面板，该显示面板包括相对间隔设置的阵列基板和彩膜基板，显示面板还包括至少一个半导体开关管，半导体开关管包括控制端、输入端和输出端，其中，输入端和输出端中的一个接入阵列基板的公共电压，另一个接入彩膜基板的公共电压，且通过控制施加至控制端的信号来控制阵列基板的公共电压和彩膜基板的公共电压之间的导通和断开。
其中，在显示面板进行配向时，通过向控制端施加第一控制电压使得输入端和输出端之间呈现关闭状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间断开；在完成配向后显示面板正常工作时，通过向控制端施加第二控制电压使得输入端和输出端呈现导通状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间导通。
其中，半导体开关管为薄膜晶体管，控制端为薄膜晶体管的栅极，输入端为薄膜晶体管的源极，输出端为薄膜晶体管的漏极。
其中，第一控制电压为低电压，第二控制电压为高电压。
其中，第一控制电压为-8v~0v的信号，第二控制电压为25v~35v的信号。
其中，半导体开关管设置在显示面板的非显示区域。
其中，多个半导体开关管间隔设置在阵列基板上，且位于非显示区域的周边边缘。
可选的，多个半导体开关管间隔设置在彩膜基板上，且位于非显示区域的周边边缘。
为解决上述技术问题，本发明采用的又一个技术方案是提供一种显示面板的制备方法，该显示面板包括相对间隔设置的阵列基板和彩膜基板，该制备方法包括以下步骤：
在显示面板上设置至少一个半导体开关管，半导体开关管包括控制端、输入端和输出端；
将输入端和输出端中的一个接入阵列基板的公共电压，另一个接入彩膜基板的公共电压；
在显示面板进行配向时，通过向控制端施加第一控制电压使得输入端和输出端之间呈现关闭状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间断开；
在完成配向后显示面板正常工作时，通过向控制端施加第二控制电压使得输入端和输出端呈现导通状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间导通。
本发明的有益效果是：本发明提供的显示面板、液晶显示器及显示面板的制备方法，通过在显示面板上设置至少一个半导体开关管，且该半导体开关管包括控制端、输入端和输出端，将输入端和输出端中的一个接入阵列基板的公共电压，另一个接入彩膜基板的公共电压，且通过控制施加至控制端的信号来控制阵列基板的公共电压和彩膜基板的公共电压之间的导通和断开。本发明提供的显示面板组立后，在其周边边缘不再设置传导片实现阵列基板的公共电压与彩膜基板的公共电压导通，与现有技术相比，本发明通过控制半导体开关管的控制端的信号能够使得阵列基板的公共电压与彩膜基板的公共电压之间的导通和断开，在断开时能够实现阵列基板的像素电极的电压与彩膜基板的公共电压为互相独立的、可单独控制的信号，进而使得彩膜基板与阵列基板之间能够形成用于液晶层配向的电压差，实现自适应公共电压的液晶显示器能够正常配向，以改善其显示品质及显示效果；在导通时能够将阵列基板的公共电压传递至彩膜基板上。
【附图说明】
图1是本发明提供的显示面板一实施方式的结构示意图；
图2是图1中显示面板沿C-C的截面结构示意图；
图3是图1中半导体开关管为薄膜晶体管的结构示意图；
图4是图1中显示面板包括多个子像素单元的等效电路示意图；
图5是图4中在液晶层形成预设交流电压差的时序示意图；
图6是本发明提供的显示面板的另一实施方式的结构示意图；
图7是本发明提供的液晶显示器一实施方式的结构示意图；
图8是本发明提供的显示面板的制备方法一实施方式的流程示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
请参阅图1和图2，其中图1是本发明提供的显示面板一实施方式的结构示意图，图2是图1中显示面板沿C-C的截面结构示意图。如图2所示，该显示面板10包括相对间隔设置的阵列基板111和彩膜基板112，及位于彩膜基板112和阵列基板111之间的液晶层113，结合图1所示，显示面板10还包括至少一个半导体开关管114，图1中示例为包括一个半导体开关管114，其包括控制端i、输入端j和输出端k，其中，输入端j和输出端k中的一个接入阵列基板111的公共电压Array-Vcom，另一个接入彩膜基板112的公共电压CF-Vcom，图1中示例为输入端j接入阵列基板111的公共电压Array-Vcom（图1中示为A-Vcom），输出端k接入彩膜基板112的公共电压CF-Vcom，且通过控制施加至控制端i的信号来控制阵列基板111的公共电压Array-Vcom和彩膜基板112的公共电压CF-Vcom之间的导通和断开。
其中，控制阵列基板111的公共电压Array-Vcom和彩膜基板112的公共电压CF-Vcom之间的导通和断开具体是通过在显示面板10上不设置传导片，而设置半导体开关管114来实现。
请继续参阅图2，进一步的，阵列基板111的上表面设置有像素电极115和与像素电极115绝缘设置的公共电极117，彩膜基板112的表面上设置有公共电极116。其中阵列基板111的公共电极117上施加或具有的信号为阵列基板111的公共电压Array-Vcom，彩膜基板112的公共电极116上施加或具有的信号为彩膜基板112的公共电压CF-Vcom。
其中，在显示面板10进行配向时，通过向控制端i施加第一控制电压使得输入端j和输出端k之间呈现关闭状态，进而使得阵列基板111的公共电压Array-Vcom和彩膜基板112的公共电压CF-Vcom之间断开，此时半导体开关管114的输入端j和输出端k之间呈现关闭状态，且漏电流较小，若通过向彩膜基板112的公共电极116上施加用于配向的公共电压CF-Vcom，则该公共电压CF-Vcom无法经由半导体开关管114传递至阵列基板111的公共电极117上以形成公共电压Array-Vcom，进而无法对像素电极115的电压产生影响，即像素电极115的电压呈现出与彩膜基板112的公共电压CF-Vcom不同的压差，用于在阵列基板111和彩膜基板112之间形成能够实现液晶层113配向的预设电压差；在完成配向后显示面板10正常工作时，通过向控制端i施加第二控制电压使得输入端j和输出端k呈现导通状态，进而使得阵列基板111的公共电压Array-Vcom和彩膜基板112的公共电压CF-Vcom之间导通，以实现显示面板10的正常显示。
请参阅图3，图3是图1中半导体开关管为薄膜晶体管的结构示意图。结合图1和图3所示，在一具体实施例中，半导体开关管114为薄膜晶体管TFT，图3中示例为N型薄膜晶体管TFT，此时控制端i为薄膜晶体管TFT的栅极G，输入端j为薄膜晶体管TFT的源极S，输出端k为薄膜晶体管TFT的漏极D。在其他实施方式中，也可选输入端j为薄膜晶体管TFT的漏极D，输出端k为薄膜晶体管TFT的源极S。
其中，当薄膜晶体管TFT为N型时，施加至栅极G的电压为低电压时，该薄膜晶体管TFT的源极S和漏极D为关闭状态；施加至栅极G的电压为高电压时，该薄膜晶体管TFT的源极S和漏极D为导通状态。
可以理解的是，施加至控制端i的第一控制电压为低电压，使得输入端j和输出端k之间呈现关闭状态；而施加至控制端i的第二控制电压为高电压，使得输入端j和输出端k之间呈现导通状态。在一具体实施例中，第一控制电压为-8v~0v的信号，第二控制电压为25v~35v的信号。
其中，当薄膜晶体管TFT为P型时，施加至栅极G的电压为高电压时，该薄膜晶体管TFT的源极S和漏极D为关闭状态；施加至栅极G的电压为低电压时，该薄膜晶体管TFT的源极S和漏极D为导通状态。
在其他实施方式中，半导体开关管114可选是场效应管FET，如结型场效应管（JFET）或绝缘栅型场效应管(MOSFET)，此时控制端i为场效应管FET的栅极G，输入端j为场效应管FET的源极S，输出端k为场效应管FET的漏极D，其与上述半导体开关管114为薄膜晶体管TFT的工作原理相似，此处不再赘述。
请一并参阅图4，图4是图1中显示面板包括多个子像素单元的等效电路示意图。如图4所示，显示面板10包括沿行方向和列方向阵列式排布的多个子像素单元Pixel、沿列方向设置的多条数据线和沿行方向设置的多条扫描线，图4中以Dn表示第n条数据线，Gn表示第n条扫描线，n为正整数，其中每个子像素单元Pixel包括像素场效应管T和电容子单元M，像素场效应管T包括栅极（G）、源极（S）和漏极（D），像素场效应管T的栅极G连接对应的扫描线以接收行驱动信号，像素场效应管T的源极S连接对应列的数据线以接收列驱动信号，电容子单元M包括并列的液晶层113中液晶分子形成的液晶电容Clc和存储电容Cs，其中每个子像素单元T的液晶电容Clc和存储电容Cs的同一端连接对应像素场效应管T的漏极D，具体的，像素场效应管T的漏极D连接像素电极115（如图2中所示），使得液晶电容Clc的一端连接像素电极115，液晶电容Clc的另一端通过连接彩膜基板112的公共电极116而接入彩膜基板112的公共电压CF-Vcom，存储电容Cs的另一端通过连接阵列基板111的公共电极117而接入阵列基板111的公共电压Array-Vcom（图4中以A-Vcom示例），可选在将彩膜基板112、阵列基板111与液晶层113组立为显示面板10之前或之后，且在配向前，当阵列基板111的公共电压Array-Vcom和彩膜基板112的公共电压CF-Vcom之间断开时，通过将每个所述像素场效应管T的栅极G打开，且通过向像素场效应管T连接的数据线上输入第三控制电压，使得对应的像素电极115的电压为第三控制电压，同时向彩膜基板112的公共电压CF-Vcom接入第四控制电压，以在液晶层113的两端形成预设的交流电压差。
其中，显示面板10的阵列基板111上包括沿列方向设置的多条数据线和沿行方向设置的多条扫描线，设置在相邻的数据线和扫描线围合区域的像素场效应管T及像素电极115。其中，每个像素场效应管T包括栅极G、源极S和漏极D，像素场效应管T的栅极S连接对应的扫描线以接收行驱动信号，像素场效应管T的源极S连接对应列的数据线以接收列驱动信号，漏极D连接对应的像素电极115，其中每个像素电极115与彩膜基板112具体是其上的公共电极116之间夹设液晶层113中液晶分子以形成液晶电容Clc，液晶电容Clc的一端连接像素电极115，液晶电容Clc的另一端接入彩膜基板112的公共电压CF-Vcom，在彩膜基板112、阵列基板111与液晶层113组立为显示面板10之前或之后，且在进行配向之前，当阵列基板111的公共电压Array-Vcom和彩膜基板112的公共电压CF-Vcom之间断开时，通过将每个像素场效应管T的栅极G打开，通过向像素场效应管T连接的数据线上输入第三控制电压，则与对应的数据线连接的像素场效应管T的源极S也为第三控制电压，对应的像素场效应管T的漏极D也为第三控制电压，进而使得对应的像素电极115的电压为第三控制电压，同时向彩膜基板112的公共电压CF-Vcom接入第四控制电压，以在液晶层113的两端形成预设的交流电压差。
请参阅图5，图5是图4中在液晶层形成预设交流电压差的时序示意图。如图5所示，以第三控制电压为接地零电压、第四控制电压为交流电压为例进行说明。当向沿行方向设置的多条扫描线（图5中以Scan line表示）上施加直流电压使得每个子像素单元Pixel中的像素场效应管T的栅极G打开，向对应的数据线（图5中以Data line表示）上施加接地零电压，此时像素电极115上也为接地零电压，而自适应公共电压的液晶面板是将数据线上的信号传递到阵列基板111的公共电极117上，此时阵列基板111的公共电压Array-Vcom（图5中以A-Vcom表示）也是接地零电压，在彩膜基板112的公共电极116上施加交流电压作为公共电压CF-Vcom时，使得像素电极115与彩膜基板112的公共电极116之间即液晶层113的两端具有交流电压差，进而液晶层113中的液晶分子能够在交流电压差的作用下按照预设倾角排列，在合适的光照下将按照预设倾角排列的液晶分子固化以实现液晶层的配向。
在其他实施方式中，可选第三控制电压为交流电压，第四控制电压为接地零电压，或其他能够使得第三控制电压和第四控制电压形成适合液晶层配向的预设的交流电压差的电压信号。
请继续参阅图1，半导体开关管114设置在显示面板10的非显示区域，如图1中所示，虚线内部的区域为显示面板110的显示区域，该区域在阵列基板111和彩膜基板112之间夹设有液晶层113，其他区域为非显示区域，其在阵列基板111和彩膜基板112之间通常不含有液晶层113，主要用于与外部电路进行线路连接。
可以理解的是，阵列基板111和彩膜基板112也可选分为显示区域和非显示区域，分别用于与相对设置的彩膜基板112或阵列基板111夹设或不夹设液晶层113。
请参阅图6，图6是本发明提供的显示面板的另一实施方式的结构示意图。如图6所示，该显示面板60包括与图1所示的显示面板10基本相同的元件并由相同的附图标记进行标示。该显示面板60与图1的区别在于，其包括多个半导体开关管114，该多个半导体开关管114间隔设置在显示面板60的非显示区域，具体可选是设置在非显示区域的周边边缘。
进一步的，该多个半导体开关管114间隔设置在阵列基板111上，且位于阵列基板111的非显示区域的周边边缘。可选的，多个半导体开关管114间隔设置在彩膜基板112上，且位于彩膜基板112的非显示区域的周边边缘。
请参阅图7，图7是本发明提供的液晶显示器一实施方式的结构示意图。如图7所示，该液晶显示器70包括上述本发明提供的显示面板，即包括与图1或图6所示的显示面板10或60基本相同的元件并由相同的附图标记进行标示。其中图7中示例为包括图6的显示面板60。
进一步的，该液晶显示器70还包括柔性电路板71，柔性电路板71用于设置显示面板10的驱动电路，其中，柔性电路板71例如可为COF(Chip On Flim)柔性基板及设置在柔性基板上的驱动芯片。
请继续参阅图7，柔性电路板71包括位于显示面板60天侧的多个源极子柔性电路板711和位于显示面板60水平两侧的多个栅极子柔性电路板712，图7中示例为4个源极子柔性电路板711和6个栅极子柔性电路板712，分别用于向显示面板60具体是阵列基板111的数据线上施加列驱动信号和向显示面板60具体是阵列基板111的扫描线上施加行驱动信号。
其中，通常情况下，液晶显示器70中源极子柔性电路板711和栅极子柔性电路板712数目分别为至少两个，具体数值不限。在其他实施方式中，若液晶显示器70的显示面板60的尺寸较小，也可选源极子柔性电路板711和栅极子柔性电路板712数目分别为1个。
其中，显示面板10进行液晶配向后，柔性电路板71与显示面板60进行邦定（Bonding），在邦定后也位于显示面板10的非显示区域。进一步的，如图7所示，源极子柔性电路板711和栅极子柔性电路板712与半导体开关114间隔设置。
请参阅图8，图8是本发明提供的显示面板的制备方法一实施方式的流程示意图。该显示面板包括相对间隔设置的阵列基板和彩膜基板，该制备方法包括以下步骤：
步骤801：在显示面板上设置至少一个半导体开关管，半导体开关管包括控制端、输入端和输出端；
步骤802：将输入端和输出端中的一个接入阵列基板的公共电压，另一个接入彩膜基板的公共电压；
步骤803：在显示面板进行配向时，通过向控制端施加第一控制电压使得输入端和输出端之间呈现关闭状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间断开；
步骤804：在完成配向后显示面板正常工作时，通过向控制端施加第二控制电压使得输入端和输出端呈现导通状态，进而使得阵列基板的公共电压和彩膜基板的公共电压之间导通。
其中，本实施方式中的显示面板与上述图1或图6所示的显示面板10或60具有相同的结构，步骤801至步骤804对应制备上述显示面板时的各个组成部分进行的操作，此处不再赘述。
其中，步骤803在使得阵列基板的公共电压与彩膜基板的公共电压断开时，具体是通过在显示面板上不设置传导片，而设置半导体开关管且控制其输入端和输出端断开来实现。
其中，在步骤803之后、步骤804之前该制备方法进一步包括以下步骤：
将每个像素场效应管的栅极打开；
向每个像素场效应管连接的数据线上输入第三控制电压，使得像素场效应管连接的像素电极的电压为第三控制电压，同时向彩膜基板的公共电压接入第四控制电压，以在液晶层上形成预设的交流电压差。
其中，第三控制电压为接地零电压，第四控制电压为交流电压。在其他实施方式中，可选第三控制电压为交流电压，第四控制电压为接地零电压，或其他能够使得第三控制电压和第四控制电压形成适合液晶层配向的预设的交流电压差的电压信号。
进一步的，在液晶层上形成预设的交流电压差的步骤之后、在步骤804之前，该制备方法进一步包括以下步骤：
施加光照在具有预设电压差的液晶层上使得液晶层中的液晶分子能够按照预设倾角排列的方式进行固化。该步骤是实现液晶层的配向固化的步骤。
区别于现有技术，本发明提供的显示面板、液晶显示器及显示面板的制备方法，通过在显示面板上设置至少一个半导体开关管，且该半导体开关管包括控制端、输入端和输出端，将输入端和输出端中的一个接入阵列基板的公共电压，另一个接入彩膜基板的公共电压，且通过控制施加至控制端的信号来控制阵列基板的公共电压和彩膜基板的公共电压之间的导通和断开。本发明提供的显示面板组立后，在其周边边缘不再设置传导片实现阵列基板的公共电压与彩膜基板的公共电压导通，与现有技术相比，本发明通过控制半导体开关管的控制端的信号能够使得阵列基板的公共电压与彩膜基板的公共电压之间的导通和断开，在断开时能够实现阵列基板的像素电极的电压与彩膜基板的公共电压为互相独立的、可单独控制的信号，进而使得彩膜基板与阵列基板之间能够形成用于液晶层配向的电压差，实现自适应公共电压的显示面板或液晶显示器能够正常配向，以改善其显示品质及显示效果；在导通时能够将阵列基板的公共电压传递至彩膜基板上。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种显示面板，所述显示面板包括相对间隔设置的阵列基板和彩膜基板，其中，所述显示面板还包括至少一个半导体开关管，所述半导体开关管包括控制端、输入端和输出端，其中，所述输入端和所述输出端中的一个接入所述阵列基板的公共电压，另一个接入所述彩膜基板的公共电压，且通过控制施加至所述控制端的信号来控制所述阵列基板的公共电压和所述彩膜基板的公共电压之间的导通和断开。
  2. 根据权利要求1所述的显示面板，其中，在所述显示面板进行配向时，通过向所述控制端施加第一控制电压使得所述输入端和所述输出端之间呈现关闭状态，进而使得所述阵列基板的公共电压和所述彩膜基板的公共电压之间断开；
    在完成配向后所述显示面板正常工作时，通过向所述控制端施加第二控制电压使得所述输入端和所述输出端呈现导通状态，进而使得所述阵列基板的公共电压和所述彩膜基板的公共电压之间导通。
  3. 根据权利要求1所述的显示面板，其中，所述半导体开关管为薄膜晶体管，其中所述控制端为所述薄膜晶体管的栅极，所述输入端为所述薄膜晶体管的源极，所述输出端为所述薄膜晶体管的漏极。
  4. 根据权利要求2所述的显示面板，其中，所述第一控制电压为低电压，所述第二控制电压为高电压。
  5. 根据权利要求4所述的显示面板，其中，所述第一控制电压为-8v~0v的信号，所述第二控制电压为25v~35v的信号。
  6. 根据权利要求1所述的显示面板，其中，所述半导体开关管设置在所述显示面板的非显示区域。
  7. 根据权利要求6所述的显示面板，其中，多个所述半导体开关管间隔设置在所述阵列基板上，且位于所述非显示区域的周边边缘。
  8. 根据权利要求6所述的显示面板，其中，多个所述半导体开关管间隔设置在所述彩膜基板上，且位于所述非显示区域的周边边缘。
  9. 一种液晶显示器，其中，所述液晶显示器包括显示面板，所述显示面板包括相对间隔设置的阵列基板和彩膜基板，所述显示面板还包括至少一个半导体开关管，所述半导体开关管包括控制端、输入端和输出端，其中，所述输入端和所述输出端中的一个接入所述阵列基板的公共电压，另一个接入所述彩膜基板的公共电压，且通过控制施加至所述控制端的信号来控制所述阵列基板的公共电压和所述彩膜基板的公共电压之间的导通和断开。
  10. 根据权利要求9所述的液晶显示器，其中，在所述显示面板进行配向时，通过向所述控制端施加第一控制电压使得所述输入端和所述输出端之间呈现关闭状态，进而使得所述阵列基板的公共电压和所述彩膜基板的公共电压之间断开；
    在完成配向后所述显示面板正常工作时，通过向所述控制端施加第二控制电压使得所述输入端和所述输出端呈现导通状态，进而使得所述阵列基板的公共电压和所述彩膜基板的公共电压之间导通。
  11. 根据权利要求9所述的液晶显示器，其中，所述半导体开关管为薄膜晶体管，其中所述控制端为所述薄膜晶体管的栅极，所述输入端为所述薄膜晶体管的源极，所述输出端为所述薄膜晶体管的漏极。
  12. 根据权利要求10所述的液晶显示器，其中，所述第一控制电压为低电压，所述第二控制电压为高电压。
  13. 根据权利要求12所述的液晶显示器，其中，所述第一控制电压为-8v~0v的信号，所述第二控制电压为25v~35v的信号。
  14. 根据权利要求9所述的液晶显示器，其中，所述半导体开关管设置在所述显示面板的非显示区域。
  15. 根据权利要求14所述的液晶显示器，其中，多个所述半导体开关管间隔设置在所述阵列基板上，且位于所述非显示区域的周边边缘。
  16. 根据权利要求14所述的液晶显示器，其中，多个所述半导体开关管间隔设置在所述彩膜基板上，且位于所述非显示区域的周边边缘。
  17. 一种显示面板的制备方法，所述显示面板包括相对间隔设置的阵列基板和彩膜基板，其中，所述制备方法包括以下步骤：
    在所述显示面板上设置至少一个半导体开关管，所述半导体开关管包括控制端、输入端和输出端；
    将所述输入端和所述输出端中的一个接入所述阵列基板的公共电压，另一个接入所述彩膜基板的公共电压；
    在所述显示面板进行配向时，通过向所述控制端施加第一控制电压使得所述输入端和所述输出端之间呈现关闭状态，进而使得所述阵列基板的公共电压和所述彩膜基板的公共电压之间断开；
    在完成配向后所述显示面板正常工作时，通过向所述控制端施加第二控制电压使得所述输入端和所述输出端呈现导通状态，进而使得所述阵列基板的公共电压和所述彩膜基板的公共电压之间导通。
PCT/CN2015/092359 2015-10-12 2015-10-21 一种显示面板、液晶显示器及显示面板的制备方法 WO2017063204A1 (zh)

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