WO2017215043A1 - 薄膜晶体管的制备方法 - Google Patents

薄膜晶体管的制备方法 Download PDF

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WO2017215043A1
WO2017215043A1 PCT/CN2016/087861 CN2016087861W WO2017215043A1 WO 2017215043 A1 WO2017215043 A1 WO 2017215043A1 CN 2016087861 W CN2016087861 W CN 2016087861W WO 2017215043 A1 WO2017215043 A1 WO 2017215043A1
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metal layer
thin film
film transistor
region
layer
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PCT/CN2016/087861
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French (fr)
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胡俊艳
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武汉华星光电技术有限公司
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Priority to US15/118,881 priority Critical patent/US10141433B2/en
Publication of WO2017215043A1 publication Critical patent/WO2017215043A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present application relates to the field of display, and in particular, to a method for fabricating a thin film transistor.
  • metal oxide-based thin film transistors have received more and more attention because of their high mobility, good light transmittance, stable film structure, low preparation temperature, and low cost.
  • metal oxide TFTs represented by indium gallium zinc oxide (In-Ga-Zn-O, IGZO) are highly compatible with current a-Si TFTs, and thus are obtained in the production of large-sized OLED panels. A wide range of applications.
  • the method for preparing a thin film transistor in the prior art includes four photomask steps, respectively:
  • the drain and source patterns are fabricated using a fourth mask.
  • the present application provides a method for fabricating a thin film transistor, which can save the cost of the mask and simplify the manufacturing process.
  • the bottom surface of the substrate is irradiated with UV light such that a portion of the semiconductor material in contact with the source and the drain is electrically enhanced.
  • the semiconductor material is amorphous indium gallium zinc oxide, and is formed by deposition using a sputtering apparatus at room temperature.
  • the step of “removing the photoresist and etching the second metal layer in the channel region such that the remaining second metal layer forms a source and a drain” includes:
  • the pattern of the block is the same as the gate pattern, and passes through the first light
  • exposure is performed from the bottom surface side of the substrate.
  • the second photomask is a translucent cover.
  • the material of the etch barrier layer is a silicon nitride (SiNx) material, or a silicon oxide (SiOx) material, or a composite layer of a silicon oxide material and a silicon nitride material.
  • the material of the first metal layer includes one or more of Al, Mo, Cu, Ag, Cr, Ti, AlNi, and MoTi.
  • the substrate is a glass substrate.
  • the material of the substrate comprises any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the material of the gate insulating layer comprises a silicon oxide material.
  • the manufacturing method of the thin film transistor of the present application only two photomasks are used, which are a first photomask (patterned by a gate shape, also referred to as a gate mask) and a second photomask (for half). Translucent cover).
  • a blocking block by using a gate mask, forming a source region, a drain region, and a channel region by using a semi-transmissive country, and then using UV light to illuminate from a side of the substrate bottom surface, so that the semiconductor material and the source and the The portion of the drain contact is electrically conductive.
  • the technical solution provided by the present application has fewer masks used in the manufacturing process than the prior art manufacturing methods. In the prior art, four masks are used. Therefore, the present application saves the cost of the mask and simplifies the process.
  • FIG. 1 is a schematic view showing a gate electrode formed on a substrate in a method of fabricating a thin film transistor according to a preferred embodiment of the present application.
  • FIG. 2 is a schematic diagram of fabricating a gate insulating layer, a semiconductor material, and an etch barrier layer on a gate electrode in a method for fabricating a thin film transistor according to a preferred embodiment of the present application.
  • FIG. 3 is a schematic diagram of fabricating a barrier block in a method of fabricating a thin film transistor according to a preferred embodiment of the present application.
  • FIG. 4 is a schematic diagram of depositing a second metal layer and fabricating a source region, a drain region, and a channel region in a method of fabricating a thin film transistor according to a preferred embodiment of the present application.
  • FIG. 5 is a schematic diagram of etching the source region, the drain region, and the surrounding region of the channel region in a method of fabricating a thin film transistor according to a preferred embodiment of the present invention, such that the gate insulating layer is exposed.
  • FIG. 6 is a schematic diagram of ashing a photoresist in the channel region by ashing and exposing the second metal layer in a method of fabricating a thin film transistor according to a preferred embodiment of the present application.
  • FIG. 7 is a method of fabricating a thin film transistor according to a preferred embodiment of the present invention, after removing a photoresist, irradiating a bottom surface of the substrate with UV light, so that the semiconductor material is in contact with the source and the drain.
  • FIG. 1 to FIG. 7 are schematic diagrams showing a method of fabricating a thin film transistor according to a preferred embodiment of the present application.
  • a substrate 10 is provided, and the substrate 10 is cleaned, a first metal layer is deposited on the top surface of the substrate 10, and the first metal layer is patterned to form a gate electrode 11.
  • the substrate 10 is a glass substrate.
  • the material of the substrate 10 may further include any one or more of an electrically insulating material such as quartz, mica, alumina or transparent plastic.
  • the substrate 10 is an insulating layer substrate capable of reducing high frequency loss of the substrate.
  • the material of the first metal layer ie, the material of the gate electrode 11
  • the gate 11 has a thickness of 1500 to 6000 angstroms.
  • a gate insulating layer 12, a semiconductor material 13 and an etch stop layer 14 are sequentially deposited on the gate electrode 11.
  • the semiconductor layer formed by the semiconductor material 13 is also referred to as a channel layer or an active layer.
  • the semiconductor material 13 is a metal oxide semiconductor layer, which may include, but is not limited to, one or more of the following materials: ZnO-based transparent oxide semiconductor material, SnO2-based transparent oxide Semiconductor material, In2O3-based transparent oxide semiconductor material, and the like.
  • the semiconductor material 13 is an amorphous indium gallium zinc oxide (a-IGZO) and is deposited at room temperature using a sputtering apparatus.
  • a-IGZO amorphous indium gallium zinc oxide
  • the material of the etch barrier layer is a silicon nitride (SiNx) material, or a silicon oxide (SiOx) material, or a composite layer of a silicon oxide material and a silicon nitride material.
  • the material of the gate insulating layer comprises a silicon oxide material, and the gate insulating layer may have a thickness of 1500 to 4000 angstroms.
  • the etch barrier layer 14 is patterned using a first mask to form a blocking block 141 disposed directly above the gate electrode 11. Specifically, in the process of patterning the etch stop layer 14 by the first reticle, the pattern of the block 141 is the same as the pattern of the gate 11 based on the pattern of the gate 11 . And in the process of forming the barrier block by the first photomask, exposure is performed from the bottom surface side of the substrate 10.
  • a second metal layer 15 is deposited, the second metal layer 15 covering the barrier block and the semiconductor material.
  • the material of the second metal layer 15 includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, and MoTi.
  • a source region 161 ie, a region labeled A1 in FIG. 4
  • a drain region 162 ie, a region labeled A2 in FIG. 4
  • a channel region 163 ie, the region labeled A3 in FIG. 4
  • the second photomask is a translucent cover.
  • the source region 161, the drain region 162, and the surrounding region of the channel region 163 are etched such that the gate insulating layer 12 is exposed, as shown in FIG. A portion of the layer 12 facing away from the substrate 10 is exposed, and the exposed regions surround the semiconductor material 13 and the second metal layer 15.
  • the photoresist is removed and the second metal layer in the channel region is etched such that the remaining second metal layer forms a source 151 and a drain 152.
  • the photoresist in the channel region is first ashed by ashing, and the second metal layer 15 is exposed; and the second metal layer in the channel region is etched again. 15.
  • the barrier block 141 is exposed (as shown in FIG. 6); finally, all of the remaining photoresist (portions labeled 161 and 162 in FIG. 6) are peeled off.
  • a portion of the bottom surface of the substrate 10 is irradiated with UV light (a line with an arrow on the bottom surface of the substrate 10) so that the semiconductor material 13 is in contact with the source 151 and the drain 152.
  • the conductivity is enhanced, that is, the semiconductor material 13 is formed into a first conductive region 131, a second conductive region 132, and an intermediate region (not labeled) between the first conductive region 131 and the second conductive region 132 by UV illumination.
  • the region 131 is in contact with the source 151
  • the second conductive region 132 is in contact with the drain 152.
  • the thin film transistor of the present application only two photomasks are used, which are a first photomask (patterned by a gate shape, also referred to as a gate mask) and a second photomask (for half). Translucent cover).
  • the blocking block 141 is formed by the gate mask, the source region, the drain region and the channel region are formed by the semi-transmissive cover, and the light is irradiated from the bottom surface of the substrate using UV light, so that the semiconductor material 13 and the source electrode 151 are used.
  • the portion of the contact with the drain 152 is electrically enhanced.
  • the technical solution provided by the present application has fewer masks used in the manufacturing process than the prior art manufacturing methods. In the prior art, four masks are used. Therefore, the present application saves the cost of the mask and simplifies the process.

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Abstract

一种薄膜晶体管的制备方法，包括如下步骤：在基板（10）的顶面形成栅极（11）；在栅极（11）上依次沉积形成栅极绝缘层（12）、半导体材料（13）及蚀刻阻挡层（14）；使用第一光罩对蚀刻阻挡层（14）图案化，形成设于栅极（11）正上方的阻挡块（141）；沉积第二金属层（15）；使用第二光罩及光刻胶在第二金属层（15）表面形成源极区（161）、漏极区（162）和沟道区（163）；蚀刻源极区（161）、漏极区（162）和沟道区（163）的周围区域，使得栅极绝缘层（12）外露；去除光刻胶及蚀刻沟道区中的第二金属层，使得留下的第二金属层形成源极（151）和漏极（152）；及使用UV光照射基板（10）的底面。本发明能够节省光罩成本，简化制造工艺。

Description

薄膜晶体管的制备方法
本申请要求2016年6月15日递交的发明名称为“薄膜晶体管的制备方法”的申请号201610417495.7的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请涉及显示领域，尤其涉及一种薄膜晶体管的制备方法。
背景技术
近年来，基于金属氧化物的薄膜晶体管因为其迁移率高、透光性好、薄膜结构稳定、制备温度低以及成本低等优点受到越来越多的重视。特别是以铟镓锌氧化物(In-Ga-Zn-O，IGZO)为代表的金属氧化物TFT，与目前a-Si TFT制成兼容性较高，因而在大尺寸OLED面板的生产中得到了广泛的应用。
现有技术中制备薄膜晶体管的方法包括四个光罩步骤，分别为：
使用第一光罩在基板上制作栅极；
使用第二光罩制作有源层图案；
使用第三光罩制作蚀刻阻挡层图案；及
使用第四光罩制作漏极和源极图案。
因此，如何节省光罩的成本及简化工艺为业界所持续研究的课题。
发明内容
本申请提供一种薄膜晶体管制备方法，能够节省光罩成本，简化制造工艺。
本申请一种实施方式提供的薄膜晶体管的制备方法，包括如下步骤：
在基板的顶面沉积第一金属层，并将所述第一金属层图案化，形成栅极；
在所述栅极上依次沉积形成栅极绝缘层、半导体材料及蚀刻阻挡层；
使用第一光罩对所述蚀刻阻挡层图案化，形成设于所述栅极正上方的阻挡 块；
沉积第二金属层，所述第二金属层覆盖所述阻挡块及所述半导体材料；
使用第二光罩及光刻胶在所述第二金属层表面形成源极区、漏极区和沟道区；
蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露；
去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极；及
使用UV光照射所述基板的底面，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强。
其中，所述半导体材料为非晶铟镓锌氧化物，且使用溅射设备在室温下沉积形成。
其中，“去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极”的步骤包括：
通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层；
蚀刻所述沟道区中的所述第二金属层；及
剥离剩下的所有的所述光刻胶。
其中，所述第一光罩对所述蚀刻阻挡层图案化的过程中，以所述栅极图案为基础，所述阻挡块的图案与所述栅极图案相同，且通过所述第一光罩形成所述阻挡块的过程中，从所述基板底面一侧进行曝光。
其中，所述第二光罩为半透光罩。
其中，所述蚀刻阻挡层的材料为氮化硅(SiNx)材料、或者氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
其中，所述第一金属层的材料包括Al、Mo、Cu、Ag、Cr、Ti、AlNi、MoTi中的一种或多种。
其中，所述基板为玻璃基板。
其中，所述基板的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。
其中，所述栅极绝缘层的材料包括氧化硅材料。
本申请的薄膜晶体管的制备方法在制造的过程中，只使用两块光罩，分别为第一光罩(以栅极形状为图案，又称为栅极光罩)和第二光罩(为半透光罩)。利用栅极光罩形成阻挡块，利用半透光国旧形成源极区、漏极区和沟道区，再使用UV光从基板底面一侧光照，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强。本申请提供的技术方案，制造过程中使用的光罩数量较现有技术的制造方法要少，现有技术中要用四块光罩，因此，本申请节省了光罩成本，简化了工艺。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一较佳实施方式的薄膜晶体管的制备方法中在基板上制作栅极的示意图。
图2为本申请一较佳实施方式的薄膜晶体管的制备方法中制作阻挡块在栅极上制作栅极绝缘层、半导体材料及蚀刻阻挡层的示意图。
图3为本申请一较佳实施方式的薄膜晶体管的制备方法中制作阻挡块的示意图。
图4为本申请一较佳实施方式的薄膜晶体管的制备方法中沉积第二金属层并制作源极区、漏极区及沟道区的示意图。
图5为本申请一较佳实施方式的薄膜晶体管的制备方法中蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露的示意图。
图6为本申请一较佳实施方式的薄膜晶体管的制备方法中通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层的示意图。
图7为本申请一较佳实施方式的薄膜晶体管的制备方法中去除光刻胶后，使用UV光照射所述基板的底面，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1至图7表述了本申请一较佳实施方式提供的的薄膜晶体管的制备方法的示意图。
请参阅图1，提供一个基板10，并将基板10清洗洁净，在基板10的顶面沉积第一金属层，并将所述第一金属层图案化，形成栅极11。一种实施方式中，所述基板10为玻璃基板。所述基板10的材料还可以包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板10为绝缘层衬底能够减小所述基板的高频损耗。所述第一金属层的材料(即栅极11的材料)包括Al、Mo、Cu、Ag、Cr、Ti、AlNi、MoTi中的一种或多种。在一实施方式中，所述栅极11的厚度为1500～6000埃。
请参阅图2，在所述栅极11上依次沉积形成栅极绝缘层12、半导体材料13及蚀刻阻挡层14。所述半导体材料13形成的半导体层也称为沟道层或者有源层。优选地，所述半导体材料13为金属氧化物半导体层，所述金属氧化物半导体层可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。举例而言，所述半导体材料13为非晶铟镓锌氧化物(amorphous indium gallium zinc oxide，a-IGZO)，且使用溅射设备在室温下沉积形成。
所述蚀刻阻挡层的材料为氮化硅(SiNx)材料、或者氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。所述栅极绝缘层的材料包括氧化硅材料，所述栅极绝缘层的厚度可以为1500～4000埃。
请参阅图3，使用第一光罩对所述蚀刻阻挡层14图案化，形成设于所述栅极11正上方的阻挡块141。具体而言，所述第一光罩对所述蚀刻阻挡层14图案化的过程中，以所述栅极11的图案为基础，所述阻挡块141的图案与所述栅极11图案相同，且通过所述第一光罩形成所述阻挡块的过程中，从所述基板10底面一侧进行曝光。
请参阅图4，沉积第二金属层15，所述第二金属层15覆盖所述阻挡块及所述半导体材料。所述第二金属层15的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
使用第二光罩及光刻胶在所述第二金属层15表面形成源极区161(即图4中标示为A1的区域)、漏极区162(即图4中标示为A2的区域)和沟道区163(即图4中标示为A3的区域)；所述第二光罩为半透光罩。
请参阅图5，蚀刻所述源极区161、所述漏极区162和所述沟道区163的周围区域，使得所述栅极绝缘层12外露，如图5所中示，栅极绝缘层12之背离基板10的部分表面外露，外露区域环绕半导体材料13和第二金属层15。
请参阅图6和图7，去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，15使得留下的所述第二金属层形成源极151和漏极152。具体而言，先通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层15；再蚀刻所述沟道区中的所述第二金属层15，并将阻挡块141暴露(如图6所示)；最后剥离剩下的所有的所述光刻胶(图6中标号为161和162的部分)。
如图7所示，使用UV光(基板10底面带箭头的线表示UV光)照射所述基板10的底面，使得所述半导体材料13与所述源极151和所述漏极152接触的部分导电性增强，即通过UV光照，将半导体材料13形成第一导电区131、第二导电区132及位于第一导电区131和第二导电区132之间的中间区域(未标号)第一导电区131与源极151接触，第二导电区132与漏极152接触。
本申请的薄膜晶体管的制备方法在制造的过程中，只使用两块光罩，分别为第一光罩(以栅极形状为图案，又称为栅极光罩)和第二光罩(为半透光罩)。利用栅极光罩形成阻挡块141，利用半透光罩形成源极区、漏极区和沟道区，再使用UV光从基板底面一侧光照，使得所述半导体材料13与所述源极151 和所述漏极152接触的部分导电性增强。本申请提供的技术方案，制造过程中使用的光罩数量较现有技术的制造方法要少，现有技术中要用四块光罩，因此，本申请节省了光罩成本，简化了工艺。
以上所揭露的仅为本申请一种较佳实施例而已，当然不能以此来限定本申请之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本申请权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括：
    在基板的顶面沉积第一金属层，并将所述第一金属层图案化，形成栅极；
    在所述栅极上依次沉积形成栅极绝缘层、半导体材料及蚀刻阻挡层；
    使用第一光罩对所述蚀刻阻挡层图案化，形成设于所述栅极正上方的阻挡块；
    沉积第二金属层，所述第二金属层覆盖所述阻挡块及所述半导体材料；
    使用第二光罩及光刻胶在所述第二金属层表面形成源极区、漏极区和沟道区；
    蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露；
    去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极；及
    使用UV光照射所述基板的底面，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强。
  2. 如权利要求1所述的薄膜晶体管制备方法，其中，所述半导体材料为非晶铟镓锌氧化物，且使用溅射设备在室温下沉积形成。
  3. 如权利要求2所述的薄膜晶体管制备方法，其中，“去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极”的步骤包括：
    通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层；
    蚀刻所述沟道区中的所述第二金属层；及
    剥离剩下的所有的所述光刻胶。
  4. 如权利要求3所述的薄膜晶体管制备方法，其中，所述第一光罩对所述蚀刻阻挡层图案化的过程中，以所述栅极图案为基础，所述阻挡块的图案与所述栅极图案相同，且通过所述第一光罩形成所述阻挡块的过程中，从所述基 板底面一侧进行曝光。
  5. 如权利要求4所述的薄膜晶体管制备方法，其中，所述第二光罩为半透光罩。
  6. 如权利要求5所述的薄膜晶体管制备方法，其中，所述蚀刻阻挡层的材料为氮化硅(SiNx)材料、或者氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
  7. 如权利要求5所述的薄膜晶体管制备方法，其中，所述第一金属层的材料包括Al、Mo、Cu、Ag、Cr、Ti、AlNi、MoTi中的一种或多种。
  8. 如权利要求5所述的薄膜晶体管制备方法，其中，所述基板为玻璃基板。
  9. 如权利要求5所述的薄膜晶体管制备方法，其中，所述基板的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。
  10. 如权利要求5所述的薄膜晶体管制备方法，其中，所述栅极绝缘层的材料包括氧化硅材料。
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