CN105895534A - 薄膜晶体管的制备方法 - Google Patents

薄膜晶体管的制备方法 Download PDF

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CN105895534A
CN105895534A CN201610417495.7A CN201610417495A CN105895534A CN 105895534 A CN105895534 A CN 105895534A CN 201610417495 A CN201610417495 A CN 201610417495A CN 105895534 A CN105895534 A CN 105895534A
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CN105895534B (zh
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胡俊艳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管的制备方法。包括如下步骤：在基板的顶面形成栅极；在所述栅极上依次沉积形成栅极绝缘层、半导体材料及蚀刻阻挡层；使用第一光罩对所述蚀刻阻挡层图案化，形成设于所述栅极正上方的阻挡块；沉积第二金属层；使用第二光罩及光刻胶在所述第二金属层表面形成源极区、漏极区和沟道区；蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露；去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极；及使用UV光照射所述基板的底面。本发明能够节省光罩成本，简化制造工艺。

Description

薄膜晶体管的制备方法
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管的制备方法。
背景技术
近年来，基于金属氧化物的薄膜晶体管因为其迁移率高、透光性好、薄膜结构稳定、制备温度低以及成本低等优点受到越来越多的重视。特别是以铟镓锌氧化物(In-Ga-Zn-O,IGZO)为代表的金属氧化物TFT，与目前a-Si TFT制成兼容性较高，因而在大尺寸OLED面板的生产中得到了广泛的应用。
现有技术中制备薄膜晶体管的方法包括四个光罩步骤，分别为：
使用第一光罩在基板上制作栅极；
使用第二光罩制作有源层图案；
使用第三光罩制作蚀刻阻挡层图案；及
使用第四光罩制作漏极和源极图案。
因此，如何节省光罩的成本及简化工艺为业界所持续研究的课题。
发明内容
本发明提供一种薄膜晶体管制备方法，能够节省光罩成本，简化制造工艺。
本发明一种实施方式提供的薄膜晶体管的制备方法，包括如下步骤：
在基板的顶面沉积第一金属层，并将所述第一金属层图案化，形成栅极；
在所述栅极上依次沉积形成栅极绝缘层、半导体材料及蚀刻阻挡层；
使用第一光罩对所述蚀刻阻挡层图案化，形成设于所述栅极正上方的阻挡块；
沉积第二金属层，所述第二金属层覆盖所述阻挡块及所述半导体材料；
使用第二光罩及光刻胶在所述第二金属层表面形成源极区、漏极区和沟道区；
蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露；
去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极；及
使用UV光照射所述基板的底面，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强。
其中，所述半导体材料为非晶铟镓锌氧化物，且使用溅射设备在室温下沉积形成。
其中，“去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极”的步骤包括：
通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层；
蚀刻所述沟道区中的所述第二金属层；及
剥离剩下的所有的所述光刻胶。
其中，所述第一光罩对所述蚀刻阻挡层图案化的过程中，以所述栅极图案为基础，所述阻挡块的图案与所述栅极图案相同，且通过所述第一光罩形成所述阻挡块的过程中，从所述基板底面一侧进行曝光。
其中，所述第二光罩为半透光罩。
其中，所述蚀刻阻挡层的材料为氮化硅(SiNx)材料、或者氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
其中，所述第一金属层的材料包括Al、Mo、Cu、Ag、Cr、Ti、AlNi、MoTi中的一种或多种。
其中，所述基板为玻璃基板。
其中，所述基板的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。
其中，所述栅极绝缘层的材料包括氧化硅材料。
本发明的薄膜晶体管的制备方法在制造的过程中，只使用两块光罩，分别为第一光罩(以栅极形状为图案，又称为栅极光罩)和第二光罩(为半透光罩)。利用栅极光罩形成阻挡块，利用半透光国旧形成源极区、漏极区和沟道区，再使用UV光从基板底面一侧光照，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强。本发明提供的技术方案，制造过程中使用的光罩数量较现有技术的制造方法要少，现有技术中要用四块光罩，因此，本发明节省了光罩成本，简化了工艺。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的制备方法中在基板上制作栅极的示意图。
图2为本发明一较佳实施方式的薄膜晶体管的制备方法中制作阻挡块在栅极上制作栅极绝缘层、半导体材料及蚀刻阻挡层的示意图。
图3为本发明一较佳实施方式的薄膜晶体管的制备方法中制作阻挡块的示意图。
图4为本发明一较佳实施方式的薄膜晶体管的制备方法中沉积第二金属层并制作源极区、漏极区及沟道区的示意图。
图5为本发明一较佳实施方式的薄膜晶体管的制备方法中蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露的示意图。
图6为本发明一较佳实施方式的薄膜晶体管的制备方法中通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层的示意图。
图7为本发明一较佳实施方式的薄膜晶体管的制备方法中去除光刻胶后，使用UV光照射所述基板的底面，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1至图7表述了本发明一较佳实施方式提供的的薄膜晶体管的制备方法的示意图。
请参阅图1，提供一个基板10，并将基板10清洗洁净，在基板10的顶面沉积第一金属层，并将所述第一金属层图案化，形成栅极11。一种实施方式中，所述基板10为玻璃基板。所述基板10的材料还可以包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板10为绝缘层衬底能够减小所述基板的高频损耗。所述第一金属层的材料(即栅极11的材料)包括Al、Mo、Cu、Ag、Cr、Ti、AlNi、MoTi中的一种或多种。在一实施方式中，所述栅极11的厚度为1500～6000埃。
请参阅图2，在所述栅极11上依次沉积形成栅极绝缘层12、半导体材料13及蚀刻阻挡层14。所述半导体材料13形成的半导体层也称为沟道层或者有源层。优选地，所述半导体材料13为金属氧化物半导体层，所述金属氧化物半导体层可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。举例而言，所述半导体材料13为非晶铟镓锌氧化物(amorphous indium gallium zincoxide,a-IGZO)，且使用溅射设备在室温下沉积形成。
所述蚀刻阻挡层的材料为氮化硅(SiNx)材料、或者氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。所述栅极绝缘层的材料包括氧化硅材料，所述栅极绝缘层的厚度可以为1500～4000埃。
请参阅图3，使用第一光罩对所述蚀刻阻挡层14图案化，形成设于所述栅极11正上方的阻挡块141。具体而言，所述第一光罩对所述蚀刻阻挡层14图案化的过程中，以所述栅极11的图案为基础，所述阻挡块141的图案与所述栅极11图案相同，且通过所述第一光罩形成所述阻挡块的过程中，从所述基板10底面一侧进行曝光。
请参阅图4，沉积第二金属层15，所述第二金属层15覆盖所述阻挡块及所述半导体材料。所述第二金属层15的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
使用第二光罩及光刻胶在所述第二金属层15表面形成源极区161(即图4中标示为A1的区域)、漏极区162(即图4中标示为A2的区域)和沟道区163(即图4中标示为A3的区域)；所述第二光罩为半透光罩。
请参阅图5，蚀刻所述源极区161、所述漏极区162和所述沟道区163的周围区域，使得所述栅极绝缘层12外露，如图5所中示，栅极绝缘层12之背离基板10的部分表面外露，外露区域环绕半导体材料13和第二金属层15。
请参阅图6和图7，去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，15使得留下的所述第二金属层形成源极151和漏极152。具体而言，先通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层15；再蚀刻所述沟道区中的所述第二金属层15，并将阻挡块141暴露(如图6所示)；最后剥离剩下的所有的所述光刻胶(图6中标号为161和162的部分)。
如图7所示，使用UV光(基板10底面带箭头的线表示UV光)照射所述基板10的底面，使得所述半导体材料13与所述源极151和所述漏极152接触的部分导电性增强，即通过UV光照，将半导体材料13形成第一导电区131、第二导电区132及位于第一导电区131和第二导电区132之间的中间区域(未标号)第一导电区131与源极151接触，第二导电区132与漏极152接触。
本发明的薄膜晶体管的制备方法在制造的过程中，只使用两块光罩，分别为第一光罩(以栅极形状为图案，又称为栅极光罩)和第二光罩(为半透光罩)。利用栅极光罩形成阻挡块141，利用半透光罩形成源极区、漏极区和沟道区，再使用UV光从基板底面一侧光照，使得所述半导体材料13与所述源极151和所述漏极152接触的部分导电性增强。本发明提供的技术方案，制造过程中使用的光罩数量较现有技术的制造方法要少，现有技术中要用四块光罩，因此，本发明节省了光罩成本，简化了工艺。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

1.一种薄膜晶体管的制备方法，其特征在于，所述薄膜晶体管的制备方法包括：
在基板的顶面沉积第一金属层，并将所述第一金属层图案化，形成栅极；
在所述栅极上依次沉积形成栅极绝缘层、半导体材料及蚀刻阻挡层；
使用第一光罩对所述蚀刻阻挡层图案化，形成设于所述栅极正上方的阻挡块；
沉积第二金属层，所述第二金属层覆盖所述阻挡块及所述半导体材料；
使用第二光罩及光刻胶在所述第二金属层表面形成源极区、漏极区和沟道区；
蚀刻所述源极区、所述漏极区和所述沟道区的周围区域，使得所述栅极绝缘层外露；
去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极；及
使用UV光照射所述基板的底面，使得所述半导体材料与所述源极和所述漏极接触的部分导电性增强。
2.如权利要求1所述的薄膜晶体管制备方法，其特征在于，所述半导体材料为非晶铟镓锌氧化物，且使用溅射设备在室温下沉积形成。
3.如权利要求2所述的薄膜晶体管制备方法，其特征在于，“去除所述光刻胶及蚀刻所述沟道区中的所述第二金属层，使得留下的所述第二金属层形成源极和漏极”的步骤包括：
通过灰化的方法将所述沟道区中的光刻胶灰化干净，并暴露所述第二金属层；
蚀刻所述沟道区中的所述第二金属层；及
剥离剩下的所有的所述光刻胶。
4.如权利要求3所述的薄膜晶体管制备方法，其特征在于，所述第一光罩对所述蚀刻阻挡层图案化的过程中，以所述栅极图案为基础，所述阻挡块的图案与所述栅极图案相同，且通过所述第一光罩形成所述阻挡块的过程中，从所述基板底面一侧进行曝光。
5.如权利要求4所述的薄膜晶体管制备方法，其特征在于，所述第二光罩为半透光罩。
6.如权利要求5所述的薄膜晶体管制备方法，其特征在于，所述蚀刻阻挡层的材料为氮化硅(SiNx)材料、或者氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
7.如权利要求5所述的薄膜晶体管制备方法，其特征在于，所述第一金属层的材料包括Al、Mo、Cu、Ag、Cr、Ti、AlNi、MoTi中的一种或多种。
8.如权利要求5所述的薄膜晶体管制备方法，其特征在于，所述基板为玻璃基板。
9.如权利要求5所述的薄膜晶体管制备方法，其特征在于，所述基板的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。
10.如权利要求5所述的薄膜晶体管制备方法，其特征在于，所述栅极绝缘层的材料包括氧化硅材料。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862234A (en) * 1986-11-29 1989-08-29 Sharp Kabushiki Kaisha Thin-film transistor
CN1056187A (zh) * 1990-04-17 1991-11-13 通用电气公司 用背面曝光和非镜面反射层光刻形成自对准掩模的方法
CN101478005A (zh) * 2009-02-13 2009-07-08 北京大学深圳研究生院 一种金属氧化物薄膜晶体管及其制作方法
US20150311233A1 (en) * 2014-04-25 2015-10-29 Everdisplay Optronics (Shanghai) Limited Tft array substrate and method for manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101051004B1 (ko) 2004-12-01 2011-07-26 엘지디스플레이 주식회사 두 가지 타입의 박막트랜지스터를 포함하는액정표시장치용 어레이기판 및 그 제조방법
WO2007043493A1 (en) * 2005-10-14 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7968932B2 (en) * 2005-12-26 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP5442228B2 (ja) * 2008-08-07 2014-03-12 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
US8273600B2 (en) 2009-04-21 2012-09-25 Chan-Long Shieh Self-aligned metal oxide TFT with reduced number of masks
KR20110125105A (ko) * 2010-05-12 2011-11-18 엘지디스플레이 주식회사 산화물 박막 트랜지스터 및 그 제조방법
US8952377B2 (en) * 2011-07-08 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN104637950A (zh) 2013-11-14 2015-05-20 上海和辉光电有限公司 薄膜晶体管驱动背板及其制造方法
CN104157613B (zh) * 2014-07-31 2017-03-08 京东方科技集团股份有限公司 一种阵列基板的制备方法
CN105655359A (zh) * 2016-03-31 2016-06-08 武汉华星光电技术有限公司 Tft基板的制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862234A (en) * 1986-11-29 1989-08-29 Sharp Kabushiki Kaisha Thin-film transistor
CN1056187A (zh) * 1990-04-17 1991-11-13 通用电气公司 用背面曝光和非镜面反射层光刻形成自对准掩模的方法
CN101478005A (zh) * 2009-02-13 2009-07-08 北京大学深圳研究生院 一种金属氧化物薄膜晶体管及其制作方法
US20150311233A1 (en) * 2014-04-25 2015-10-29 Everdisplay Optronics (Shanghai) Limited Tft array substrate and method for manufacturing the same

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