WO2017197676A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2017197676A1
WO2017197676A1 PCT/CN2016/085461 CN2016085461W WO2017197676A1 WO 2017197676 A1 WO2017197676 A1 WO 2017197676A1 CN 2016085461 W CN2016085461 W CN 2016085461W WO 2017197676 A1 WO2017197676 A1 WO 2017197676A1
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Prior art keywords
layer
signal line
electrode
array substrate
film transistor
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Application number
PCT/CN2016/085461
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English (en)
French (fr)
Inventor
李子健
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to RU2018128061A priority Critical patent/RU2688814C1/ru
Priority to JP2018543314A priority patent/JP6621188B2/ja
Priority to US15/109,652 priority patent/US10115749B2/en
Priority to GB1811891.9A priority patent/GB2562187B/en
Priority to KR1020187021718A priority patent/KR102154418B1/ko
Publication of WO2017197676A1 publication Critical patent/WO2017197676A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • TFT-LCD thin film transistor liquid crystal display
  • the TFT-LCD controls the corresponding voltage on and off of the pixel electrode through the TFT on the array substrate to control the liquid crystal steering to realize corresponding display.
  • the structure of the array substrate is relatively complicated, it is usually required to etch five or four masks.
  • the present application provides an array substrate and a manufacturing method thereof, which can reduce the manufacturing time of the array substrate and reduce the production cost.
  • a first aspect of the present application provides a method for fabricating an array substrate, comprising: depositing a conductive layer on a substrate, and etching the conductive layer from a third electrode of the thin film transistor and a first signal line by using a first photomask; a second signal line, wherein the first signal line includes a first portion and a second portion separated on both sides of the second signal line; an intermediate layer is sequentially deposited, and the intermediate layer is etched by using a second mask a first connection bridge connecting the first portion and the second portion; depositing a conductive electrode, and etching the conductive electrode out of the pixel electrode and electrically connecting the first portion and the second portion by using a third mask Connection line.
  • the first portion of the first signal line is electrically connected to the first electrode of the thin film transistor
  • the second signal line is electrically connected to the second electrode of the thin film transistor
  • the intermediate layer includes stacked insulation a layer, an active layer, an ohmic contact layer and a protective layer
  • the step of etching the intermediate layer to the first connecting bridge connecting the first portion and the second portion by using a second mask further comprises: adopting a second light The cover etches the intermediate layer to a second connection bridge connecting the second pole and the third pole of the thin film transistor; the third light mask etches the conductive electrode out of the pixel electrode and electrically connects
  • the step of connecting the first portion and the second portion further includes: using the third reticle to correspond the conductive electrode, the protective layer and the ohmic contact layer on the second connecting bridge to the The second and third poles are etched open.
  • the step of etching the intermediate layer to the second connection bridge connecting the second electrode and the third electrode of the thin film transistor by using the second photomask further comprises: using the hydrofluoric acid to the first The edges of the protective layer and the insulating layer in the two connecting bridges are etched such that the active layer and the ohmic contact layer in the second connecting bridge protrude outward to form a contact ring.
  • the step of etching the intermediate layer to the first connecting bridge connecting the first portion and the second portion by using the second mask further comprises: etching the intermediate layer by using a second mask a capacitor insulating structure on the first portion; the step of etching the conductive electrode out of the pixel electrode and electrically connecting the connecting portion of the first portion and the second portion by using a third mask further comprises: adopting a A three-pass mask etches the conductive electrode out of the storage capacitor electrode above the capacitive insulating structure.
  • width of the first connecting bridge is wider than the width of the first portion and the second portion.
  • the conductive electrode on the second connecting bridge is disposed on the contact ring to electrically connect the conductive electrode with the contact ring and the second or third pole.
  • the first pole, the second pole, and the third pole of the thin film transistor are a gate, a source, and a drain, respectively, and the first signal line is a scan line and the second signal line is a data line.
  • a second aspect of the present application provides an array substrate, including: a substrate; a three-pole, a first signal line, and a second signal line of the thin film transistor disposed on the substrate, wherein the first signal line includes the first a first portion and a second portion on both sides of the two signal lines; a first connection bridge disposed between the first portion and the second portion, wherein the second connection bridge is insulated from the second signal line; and a pixel An electrode and a connecting line disposed above the first connecting bridge, the connecting line for electrically connecting the first portion and the second portion.
  • the first portion of the first signal line is electrically connected to the first electrode of the thin film transistor;
  • the array substrate further includes a second connection bridge disposed between the second pole and the third pole of the thin film transistor And a first conductive electrode and a second conductive electrode disposed on the second connecting bridge,
  • the second connecting bridge includes an insulating layer, an active layer, an ohmic contact layer and a protective layer, and the second connecting bridge
  • the protective layer and the resistive contact layer are both disposed corresponding to the second pole and the third pole, wherein the first conductive electrode is electrically connected to the second pole and the active layer and the second signal line, and the conductive electrode Electrically connected to the third pole and the active layer and the pixel electrode.
  • the active layer and the ohmic contact layer in the second connecting bridge are outwardly convex to form a contact ring.
  • the conductive electrode on the second connecting bridge is disposed on the contact ring to electrically connect the conductive electrode with the contact ring and the second or third pole.
  • the method further includes a capacitor insulating structure and a storage capacitor electrode sequentially disposed on the first portion.
  • the first pole, the second pole, and the third pole of the thin film transistor are a gate, a source, and a drain, respectively, and the first signal line is a scan line and the second signal line is a data line.
  • the third aspect of the present application provides an array substrate, the method for fabricating the array substrate includes the steps of: depositing a conductive layer on the substrate, and etching the conductive layer from the three-pole of the thin film transistor by using a first photomask; a first signal line, a second signal line, wherein the first signal line includes a first portion and a second portion separated on both sides of the second signal line; sequentially depositing an intermediate layer and using a second mask The intermediate layer etches a first connection bridge connecting the first portion and the second portion; depositing a conductive electrode, and etching the conductive electrode out of the pixel electrode and electrically connecting the first portion with a third mask a connecting line of the second portion.
  • the first portion of the first signal line is electrically connected to the first electrode of the thin film transistor
  • the second signal line is electrically connected to the second electrode of the thin film transistor
  • the intermediate layer includes stacked insulation a layer, an active layer, an ohmic contact layer, and a protective layer
  • the second photomask is used to etch the intermediate layer to connect the first connection connecting the first portion and the second portion
  • the step of the bridge further includes etching the intermediate layer with a second photomask to connect a second connection bridge connecting the second pole and the third pole of the thin film transistor
  • the step of etching the pixel electrode by the conductive electrode and electrically connecting the connecting line of the first portion and the second portion further comprises: using the third mask to the conductive electrode on the second connecting bridge, the protection The layer and the ohmic contact layer are etched off corresponding to the second and third electrodes.
  • the step of etching the intermediate layer by using a second mask to etch the second connection bridge connecting the second pole and the third pole of the thin film transistor further comprises: etching an edge of the protective layer and the insulating layer in the second connecting bridge with hydrofluoric acid, so that the active layer and the ohmic contact layer in the second connecting bridge protrude outward to form a contact ring.
  • the conductive electrode on the second connecting bridge is disposed on the contact ring to electrically connect the conductive electrode with the contact ring and the second or third pole.
  • the step of etching the intermediate layer by using the second mask to etch the first connecting bridge connecting the first portion and the second portion further comprises: using the second light a mask etches the intermediate layer from a capacitive insulating structure over the first portion; the third photomask etches the conductive electrode out of the pixel electrode and electrically connects the first portion and the second portion
  • the step of connecting the wire further includes etching the conductive electrode from the storage capacitor electrode located above the capacitor insulating structure by using a third mask.
  • the first pole, the second pole, and the third pole of the thin film transistor are a gate, a source, and a drain, respectively, and the first signal line is a scan line and the second signal line is a data line.
  • the first signal line of the array substrate is segmented corresponding to the two sides of the second signal line, and the connecting line connecting the first signal line is formed in the subsequent mask, so that the first signal line can be normalized.
  • Wiring, and the first and second signal lines can be formed in a reticle without splitting the reticle, reducing the number of masks in the process of fabricating the array substrate, reducing the manufacturing time of the array substrate, and reducing the production cost. .
  • FIG. 1 is a flow chart of an embodiment of a method for fabricating an array substrate of the present application
  • FIG. 2 is a schematic top plan view of the array substrate obtained through the step S11 shown in FIG. 1;
  • FIG. 3 is a schematic top plan view of the array substrate obtained through the step S12 shown in FIG. 1;
  • FIG. 4 is a cross-sectional view of the array substrate of the contact ring not shown in FIG. 3 taken along the line AA;
  • FIG. 5 is a cross-sectional view of the array substrate of the contact ring obtained by etching shown in FIG. 3 along the AA direction;
  • FIG. 6 is a first top structural view of the array substrate obtained by performing the process of step S13 shown in FIG. 1;
  • FIG. 7 is a second top plan view of the array substrate obtained through the step S13 shown in FIG. 1;
  • Figure 8 is a cross-sectional view of the array substrate of Figure 7 taken along the line AA;
  • Figure 9 is a cross-sectional view of another embodiment of the array substrate of Figure 7 taken along the line AA.
  • FIG. 1 is a schematic diagram of an embodiment of an array substrate of the present application.
  • the method of this embodiment includes the following steps:
  • S11 depositing a conductive layer on the substrate, and etching the conductive layer from the three poles of the thin film transistor and the first signal line and the second signal line by using a first mask.
  • the substrate may be a substrate formed of a glass substrate or other transparent insulating material.
  • the conductive layer may be a metal layer or other conductive non-metallic material.
  • PVD Physical Vapor Deposition
  • first etches the conductive layer with a first mask provided with a pattern International: Photo Lithography
  • a pattern of the thin film transistor three poles and the first signal line and the second signal line on the conductive layer, and continuing to form the first pole 201, the second pole 202, and the third pole of the thin film transistor by wet etching 203 and a first signal line 204 and a second signal line 205.
  • the first signal line 204 and the second signal line 205 are alternately arranged, such as vertically.
  • the first signal line 204 includes a first portion 204a and a second portion 204b separated on both sides of the second signal line 205, and the first portion 204a and the second portion 204b are not electrically connected to the second signal 205.
  • the first portion 204a of the first signal line 204 is electrically connected to the first pole 201 of the thin film transistor, and the second signal line 205 is electrically connected to the second pole 202 of the thin film transistor.
  • S12 depositing the intermediate layer in sequence, and etching the intermediate layer into the first connecting bridge, the second connecting bridge, and the capacitor insulating structure by using a second mask.
  • the intermediate layer 207 includes an insulating layer (also referred to as a gate insulating layer, English: Gate Insulator) , abbreviated as: GI) 207a, active layer 207b, ohmic contact layer 207c, and protective layer 207d (English: passivation).
  • insulating layer also referred to as a gate insulating layer, English: Gate Insulator
  • GI gate insulating layer
  • active layer 207b active layer
  • ohmic contact layer 207c ohmic contact layer
  • protective layer 207d “passivation”.
  • PECVD plasma enhanced chemical vapor deposition
  • the active layer 207b includes a-Si and/or p-Si, etc.
  • the ohmic contact layer 207c is n+ a-Si.
  • the intermediate layer 207 is first yellow-etched by using a second photomask provided with a pattern to define a first connection bridge 208 connecting the first portion 204a and the second portion 204b on the intermediate layer 207, and the connection portion a second connection bridge 209 of the second pole 202 and the third pole 203 and a pattern of the capacitor insulating structure 210 above the first portion 204a, and continuing to etch into the conductive layer by a dry etching process to form the first connection Bridge 208, second connection bridge 209 (also referred to as silicon conduction) and capacitive insulation structure 210.
  • a dry etching process to form the first connection Bridge 208, second connection bridge 209 (also referred to as silicon conduction) and capacitive insulation structure 210.
  • the first connecting bridge 208 and the capacitor insulating structure 210 completely cover the first signal line in width.
  • the first connection bridge 208 is wider than the first portion 204a and the second portion 204b of the first signal line, and the width of the capacitive insulation structure 210 is wider than the first portion 204a.
  • the method further includes: using hydrofluoric acid (HF) to the first
  • HF hydrofluoric acid
  • the edges of the protective layer and the insulating layer in the second connecting bridge 209 are etched such that the active layer 207b and the ohmic contact layer 207c in the second connecting bridge protrude outward to form a contact ring 209a.
  • FIG. 4-5 The cross-sectional view in the AA direction shown in FIG. 3 obtained after performing the above dry etching is as shown in FIG.
  • the contact ring can be formed without etching, and the active layer and the ohmic contact layer have no protruding portions relative to the protective layer and the insulating layer.
  • the substrate after S12 can be deposited with PVD transparent conductive electrodes such as indium tin oxide.
  • PVD transparent conductive electrodes such as indium tin oxide.
  • Tin Oxide abbreviated as: ITO
  • ITO a semiconductor transparent conductive film, which is first etched by a third photomask provided with a pattern to define a connection between the pixel electrode 211 and the electrical connection on the transparent conductive electrode.
  • the transparent conductive electrode is etched by a wet etching process to form the pixel electrode 211, the connection line 212, and the storage capacitor electrode 213, as shown in FIG.
  • the transparent conductive electrode, the protective layer 209 and the ohmic contact layer 207b of the opening portion 214 are etched away by a dry etching process so that the transparent conductive electrode, the protective layer 209 and the ohmic respectively correspond to the second and third electrodes.
  • Contact layer 207c is not connected, as shown in Figures 7 and 8.
  • the upper portion of the active layer 207b of the break 214 may also be etched open, as shown in FIG.
  • the pattern of the opening portion 214 may not be defined first when the yellow etching is performed. After the conductive structure is obtained by wet etching, a second yellow etching is performed to obtain the opening portion 214. Dry etching is then performed to obtain the break 214.
  • a conductive electrode on the second connecting bridge is disposed on the contact ring 209a to electrically connect the conductive electrode with the contact ring 209a and the second pole 202 or the third pole 203.
  • the conductive electrode corresponding to the position of the second pole 202 on the second connecting bridge is a first conductive electrode 215, and the first conductive electrode 215 passes through a contact ring covering a side of the second connecting bridge to connect the active layer and the first The two poles 202 form a passage.
  • the conductive electrode corresponding to the position of the third pole 203 on the second connecting bridge is a second conductive electrode 216, and the second conductive electrode 216 passes through a contact ring covering a side of the second connecting bridge to connect the active layer and the third pole 203 Form a pathway.
  • the first conductive electrode 215 is in electrical contact with the second signal line 205, thereby ensuring that the second signal line 205 is electrically connected to the second electrode 202 of the thin film transistor.
  • the second conductive electrode 216 is in electrical contact with the pixel electrode 211, thereby electrically connecting the pixel electrode 211 and the third electrode 203 of the thin film transistor.
  • the connecting line 212 is longer than the first connecting bridge 208 and narrower than the first connecting bridge 208 to ensure that the connecting line 212 is insulated from the second signal line 204 and can be combined with the first portion 204a and the second portion.
  • the portion 204b is electrically connected.
  • the connecting line can be electrically connected to the first portion 204a and the second portion 204b through the through hole of the first connecting bridge 208.
  • the length of the connecting line 212 need not be longer than the first connecting bridge 208.
  • the storage capacitor electrode 213 can form a storage capacitor with the corresponding first portion 204a through the capacitor insulating structure 210.
  • the first, second, and third poles of the thin film transistor correspond to a gate, a source, and a drain of the thin film transistor, and the first signal line is a scan line, and the second signal line is Data line.
  • the second and third poles may correspond to a drain and a source; or the first signal line is a data line, and the second signal line is a scan line, and correspondingly, the first source A pole or a drain, the second pole.
  • the first, second, and third reticle are generally ordinary reticle or half-color reticle.
  • FIG. 7 is a schematic top plan view of an embodiment of the array substrate of the present application
  • FIG. 8 is a cross-sectional view of the array substrate of FIG. 7 taken along the A-A direction.
  • the array substrate comprises:
  • first pole 201 a first pole 201, a second pole 202, and a third pole 203 of the thin film transistor disposed on the substrate 206, and a first signal line 204 and a second signal line 205, wherein the first signal line 204 includes a partition a first portion 204a and a second portion 204b on both sides of the second signal line 205;
  • first connecting bridge 208 disposed between the first portion 204a and the second portion 204b;
  • connection line 212 for electrically connecting the first portion 204a and the second portion 204b.
  • the substrate may be a substrate formed of a glass substrate or other transparent insulating material.
  • the conductive layer may be a metal layer or other conductive non-metallic material.
  • the conductive electrode may be a transparent conductive electrode such as ITO or the like.
  • the first connecting bridge 208 is wider than the area that covers the first portion 204a and the area that covers the second portion 204b.
  • the connecting line 212 can be longer than the first connecting bridge 208 and narrower than the first connecting bridge 208.
  • the connecting line can pass through the through hole of the first connecting bridge 208 and the first portion 204a and the second portion 204b. Electrically connected, the length of the connecting line 212 need not be longer than the first connecting bridge 208.
  • the first connecting bridge 208 includes an insulating layer 207a, an active layer 207b, an ohmic contact layer 207c, and a protective layer 207d from the side close to the substrate 206.
  • an insulating layer 207a an active layer 207b, an ohmic contact layer 207c, and a protective layer 207d from the side close to the substrate 206.
  • the first portion 204a of the first signal line is electrically connected to the first pole 201 of the thin film transistor, and the second signal line 205 is electrically connected to the second pole 202 of the thin film transistor.
  • the array substrate further includes a second connection bridge 209 disposed between the second pole 202 and the third pole 203 of the thin film transistor, and first conductive electrodes 215 and second disposed on the second connection bridge 209 Conductive electrode 216.
  • the second connecting bridge 209 includes the insulating layer 207a, the active layer 207b, the ohmic contact layer 207c and the protective layer 207d as described above, and the protective layer 207d and the resistive contact layer 207c of the second connecting bridge 209 correspond to the The second pole and the third pole are disconnected, i.e., disconnected by the break 214.
  • the upper portion of the active layer 207b can also be disconnected through the break 214, as shown in FIG.
  • the first conductive electrode 215 is electrically connected to the second pole 202 and the active layer 207b, and is electrically connected to the second signal line 205; the conductive electrode is electrically connected to the third pole 203 and the active layer 207b, And electrically connected to the pixel electrode 211.
  • an edge of the active layer 207b and the ohmic contact layer 207c of the second connection bridge 209 protrudes from the insulating layer 207a and the protective layer 207d to form a contact ring 209a.
  • the first conductive electrode 215 and the second conductive electrode 216 are both covered on the contact ring 209a to be electrically connected to the active layer.
  • the array substrate further includes a storage capacitor electrode 213 and a capacitor insulation structure 210 disposed between the storage capacitor electrode 213 and the first portion 204.
  • the capacitive insulating structure may include the insulating layer 207a, the active layer 207b, the ohmic contact layer 207c, and the protective layer 207d as described above.
  • the first signal line 204 and the second signal line 205 are alternately arranged, such as vertically.
  • the first, second and third poles of the thin film transistor correspond to a gate, a source and a drain of the thin film transistor, the first signal line is a scan line, and the second signal line is a data line.
  • the second and third poles may correspond to a drain and a source; or the first signal line is a data line, and the second signal line is a scan line, and correspondingly, the first source A pole or a drain, the second pole.
  • the application also provides an array substrate, which is fabricated by the above manufacturing method.
  • the array substrate in the above solution may be an array substrate in a liquid crystal display.
  • the application also provides a display panel comprising an array substrate, a color filter substrate and a liquid crystal sandwiched between the two substrates.
  • the first signal line of the array substrate is segmented corresponding to the two sides of the second signal line, and the connecting line connecting the first signal line is formed in the subsequent mask, so that the first signal line can be normalized.
  • Wiring, and the first and second signal lines can be formed in a reticle without splitting the reticle, reducing the number of masks in the process of fabricating the array substrate, reducing the manufacturing time of the array substrate, and reducing the production cost. .

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Abstract

一种阵列基板面板及其制作方法。其中，该制作方法包括在基板上沉积导电层，并采用第一道光罩将导电层刻蚀出薄膜晶体管的三极以及第一信号线（204）、第二信号线（205），其中，第一信号线包括分隔在第二信号线两侧的第一部分（204a）和第二部分（204b）；依序沉积中间层（207），并采用第二道光罩将中间层刻蚀出连接第一部分和第二部分的第一连接桥（208）；沉积导电电极，并采用第三道光罩将导电电极刻蚀出像素电极以及电连接第一部分和第二部分的连接线（212）。通过该方式，能够减少阵列基板的制作耗时，降低生产成本。

Description

阵列基板及其制作方法
【技术领域】
本申请涉及显示技术领域，特别是涉及阵列基板及其制作方法。
【背景技术】
目前，薄膜晶体管液晶显示器（英文：thin film transistor-liquid crystal display，简称：TFT-LCD）为被广泛使用的主流显示器。TFT-LCD通过阵列基板上的TFT控制像素电极的相应电压通断，以控制液晶转向，进行实现相应显示。在目前阵列基板制作工艺中，由于阵列基板的结构较为复杂，通常是需要5道或4道光罩进行刻蚀得到。
然而，由于目前阵列基板工艺中需要用的光罩刻蚀工序较多，使得制作耗时较长，而且增加了生产成本。
【发明内容】
本申请提供一种阵列基板及其制作方法，能够减少阵列基板的制作耗时，降低生产成本。
本申请第一方面提供一种阵列基板的制作方法，包括：在基板上沉积导电层，并采用第一道光罩将所述导电层刻蚀出薄膜晶体管的三极以及第一信号线、第二信号线，其中，所述第一信号线包括分隔在所述第二信号线两侧的第一部分和第二部分；依序沉积中间层，并采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥；沉积导电电极，并采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线。
其中，所述第一信号线的第一部分与所述薄膜晶体管的第一极电连接，所述第二信号线与所述薄膜晶体管的第二极电连接，所述中间层包括叠置的绝缘层、主动层、欧姆接触层和保护层；所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥；所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：采用第三道光罩将所述第二连接桥上的所述导电电极、所述保护层及所述欧姆接触层对应所述第二极和第三极进行刻蚀断开。
其中，所述采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥的步骤还包括：采用氢氟酸对所述第二连接桥中的保护层和绝缘层的边缘进行刻蚀，使所述第二连接桥中的主动层和欧姆接触层向外凸出形成接触环。
其中，所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：采用第二道光罩将所述中间层刻蚀出位于所述第一部分上面的电容绝缘结构；所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：采用第三道光罩将所述导电电极刻蚀出位于所述电容绝缘结构上面的存储电容电极。
其中，所述第一连接桥的宽度宽于所述第一部分和所述第二部分的宽度。
其中，所述第二连接桥上的导电电极设置在所述接触环上，以使所述导电电极与所述接触环和所述第二极或第三极电连接。
其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
本申请第二方面提供一种阵列基板，包括：基板；设置在基板上的薄膜晶体管的三极、第一信号线和第二信号线，其中，所述第一信号线包括分隔在所述第二信号线两侧的第一部分和第二部分；设置在所述第一部分和第二部分之间的第一连接桥，其中，所述第二连接桥与所述第二信号线绝缘；以及像素电极和设置在所述第一连接桥上面的连接线，所述连接线用于电连接所述第一部分和所述第二部分。
其中，所述第一信号线的第一部分与所述薄膜晶体管的第一极电连接；所述阵列基板还包括设置在所述薄膜晶体管的第二极和第三极之间的第二连接桥，以及设置在所述第二连接桥上的第一导电电极和第二导电电极，所述第二连接桥包括绝缘层、主动层、欧姆接触层及保护层，且所述第二连接桥的保护层和电阻接触层均对应所述第二极和第三极断开设置，所述第一导电电极电连接于所述第二极和主动层及所述第二信号线，所述导电电极电连接于所述第三极和所述主动层及所述像素电极。
其中，还包括所述第二连接桥中的主动层和欧姆接触层向外凸出形成得接触环。
其中，所述第二连接桥上的导电电极设置在所述接触环上，以使所述导电电极与所述接触环和所述第二极或第三极电连接。
其中，还包括依序设置在所述第一部分上面的电容绝缘结构和存储电容电极。
其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
本申请第三方面提供一种阵列基板，所述阵列基板的制作方法包括以下步骤：在基板上沉积导电层，并采用第一道光罩将所述导电层刻蚀出薄膜晶体管的三极以及第一信号线、第二信号线，其中，所述第一信号线包括分隔在所述第二信号线两侧的第一部分和第二部分；依序沉积中间层，并采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥；沉积导电电极，并采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线。
其中，所述第一信号线的第一部分与所述薄膜晶体管的第一极电连接，所述第二信号线与所述薄膜晶体管的第二极电连接，所述中间层包括叠置的绝缘层、主动层、欧姆接触层和保护层；在所述阵列基板的制作方法中，所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥；所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：采用第三道光罩将所述第二连接桥上的所述导电电极、所述保护层及所述欧姆接触层对应所述第二极和第三极进行刻蚀断开。
其中，在所述阵列基板的制作方法中，所述采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥的步骤还包括：采用氢氟酸对所述第二连接桥中的保护层和绝缘层的边缘进行刻蚀，使所述第二连接桥中的主动层和欧姆接触层向外凸出形成接触环。
其中，所述第二连接桥上的导电电极设置在所述接触环上，以使所述导电电极与所述接触环和所述第二极或第三极电连接。
其中，在所述阵列基板的制作方法中，所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：采用第二道光罩将所述中间层刻蚀出位于所述第一部分上面的电容绝缘结构；所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：采用第三道光罩将所述导电电极刻蚀出位于所述电容绝缘结构上面的存储电容电极。
其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
上述方案中，通过将阵列基板的第一信号线对应第二信号线两侧分段设置，并在后续光罩中形成连接该第一信号线的连接线，既可实现第一信号线的正常布线，而且使得在一道光罩中即可形成第一、第二信号线，而无需分两道光罩实现，减少了阵列基板制作过程的光罩次数，减少阵列基板的制作耗时，降低生产成本。
【附图说明】
图1是本申请阵列基板的制作方法一实施方式的流程图；
图2是经图1所示的S11步骤所得的阵列基板的俯视结构示意图；
图3是经图1所示的S12步骤所得的阵列基板的俯视结构示意图；
图4是图3所示未经刻蚀得到接触环的阵列基板沿AA方向的剖视图；
图5是图3所示经刻蚀得到接触环的阵列基板沿AA方向的剖视图；
图6是执行图1所示的S13步骤过程所得的阵列基板的第一俯视结构示意图；
图7是经图1所示的S13步骤所得的阵列基板的第二俯视结构示意图；
图8是图7所示阵列基板沿AA方向一实施方式的剖视图；
图9是图7所示阵列基板沿AA方向另一实施方式的剖视图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
请参阅图1，图1是本申请阵列基板一实施方式的路程图。本实施例方法，包括以下步骤：
S11：在基板上沉积导电层，并采用第一道光罩将所述导电层刻蚀出薄膜晶体管的三极以及第一信号线、第二信号线。
该基板可以为玻璃基板或者其他透明绝缘材料形成的基板。该导电层可以为金属层，或者为其他可导电的非金属材料。
例如，请结合参阅图2，在基板206上可采用物理气相沉积（英文：Physical Vapor Deposition，简称：PVD）沉积导电层，并采用设置有图案的第一道光罩先对导电层进行黄光刻蚀（英文：Photo Lithography），以在导电层上定义出薄膜晶体管三极和第一信号线、第二信号线的图案，并继续采用湿刻蚀形成薄膜晶体管的第一极201、第二极202、第三极203和第一信号线204、第二信号线205。
其中，该第一信号线204与该第二信号线205交错设置，如垂直设置。该第一信号线204包括分隔在所述第二信号线205两侧的第一部分204a和第二部分204b，且该第一部分204a和第二部分204b均不与第二信号205电连接。
本实施例中，所述第一信号线204的第一部分204a与所述薄膜晶体管的第一极201电连接，所述第二信号线205与所述薄膜晶体管的第二极202电连接。
S12：依序沉积中间层，并采用第二道光罩将所述中间层刻蚀出第一连接桥、第二连接桥以及电容绝缘结构。
例如，该中间层207包括绝缘层（又称栅极绝缘层，英文：Gate Insulator ，简称：GI）207a、主动层207b、欧姆接触层207c和保护层207d（英文：passivation）。请结合参阅图3，在如图2所示的基板上可采用等离子体增强化学气相沉积法（英文：Plasma Enhanced Chemical Vapor Deposition，简称：PECVD）依序沉积绝缘层207a、主动层207b、欧姆接触层207c和保护层207d。其中，该主动层207b包括a-Si和/或p-Si等，该欧姆接触层207c如为n+ a-Si。
然后，采用设置有图案的第二道光罩先对中间层207进行黄光刻蚀，以在中间层207上定义出连接所述第一部分204a和第二部分204b的第一连接桥208、连接第二极202和第三极203的第二连接桥209以及位于所述第一部分204a上面的电容绝缘结构210的图案，并继续采用干刻蚀工艺刻蚀到上述导电层，以形成该第一连接桥208、第二连接桥209（也称硅导）以及电容绝缘结构210。
优选地，为保证上述导电层与下述导电电极的对应位置绝缘，该第一连接桥208和电容绝缘结构210在宽度上完全覆盖该第一信号线。如，第一连接桥208宽度宽于第一信号线的第一部分204a和第二部分204b，电容绝缘结构210的宽度宽于第一部分204a。
进一步地，为保证主动层和欧姆接触层与下面导电层以及下述导电电极的良好接触，在本步骤形成上述第二连接桥209之后，还包括：采用氢氟酸（HF）对所述第二连接桥209中的保护层和绝缘层的边缘进行刻蚀，使所述第二连接桥中的主动层207b和欧姆接触层207c向外凸出形成接触环209a。例如，请结合参阅图4-5，在进行上述干刻蚀之后得到的图3所示的A-A方向的剖面图如图4所示，采用HF刻蚀工艺（因为HF对Si与SiOx刻蚀有选择性）对对所述第二连接桥209中的保护层209和绝缘层206的边缘进行刻蚀，以保留第二连接桥209中的主动层207b和欧姆接触层207c的边缘，形成外围半O-ring 接触环209a。
可以理解的是，在其他实际应用中，在形成第二连接桥后也可不进行刻蚀形成接触环，则主动层和欧姆接触层相对保护层和绝缘层无凸出部分。
S13：沉积导电电极，并采用第三道光罩将所述导电电极刻蚀出像素电极、连接线和存储电容电极、并将所述第二连接桥上的所述导电电极、所述保护层及所述欧姆接触层对应所述第二极和第三极进行刻蚀断开。
例如，请结合参阅图6-8，将经S12后的基板可采用PVD沉积透明导电电极如铟锡氧化物（英文：Indium tin oxide，简称：ITO）半导体透明导电膜，采用设置有图案的第三道光罩先对该透明导电电极进行黄光刻蚀，以在透明导电电极上定义出连接所述像素电极211、电连接该第一部分204a和第二部分204b的连接线212、位于电容绝缘结构210上面的存储电容电极213以及第二连接桥上位于第二极和第三极之间的断开处214的图案，并继续采用湿刻蚀工艺刻蚀到上述透明导电电极，以形成该像素电极211、连接线212以及存储电容电极213，如图6所示。
然后，再采用干刻蚀工艺将断开处214的透明导电电极、保护层209和欧姆接触层207b刻蚀掉，使得分别对应第二极和第三极的透明导电电极、保护层209和欧姆接触层207c不连接，如图7和8所示。在其他实施例中，也可把断开处214的主动层207b的上部分也进行刻蚀断开，如图9所示。
可以理解的是，可以在进行上述黄光刻蚀时先不定义断开处214的图案，在湿刻蚀得到上述导电结构后，再进行第二次的黄光刻蚀得到断开处214，再进行干刻蚀得到该断开处214。
可选地，所述第二连接桥上的导电电极设置在所述接触环209a上，以使所述导电电极与所述接触环209a和所述第二极202或第三极203电连接。具体如，该第二连接桥上对应第二极202位置的导电电极为第一导电电极215，该第一导电电极215通过覆盖该第二连接桥的侧面的接触环，以连接主动层和第二极202形成通路。该第二连接桥上对应第三极203位置的导电电极为第二导电电极216，该第二导电电极216通过覆盖该第二连接桥的侧面的接触环，以连接主动层和第三极203形成通路。该第一导电电极215与第二信号线205电接触，进而保证第二信号线205与薄膜晶体管的第二极202电连接。该第二导电电极216与像素电极211电接触，进而实现像素电极211与薄膜晶体管的第三极203电连接。
本实施例中，该连接线212长于该第一连接桥208，且窄于该第一连接桥208，以保证该连接线212与第二信号线204绝缘，且能够与第一部分204a和第二部分204b电连接，当然，上述可以采用连接线通过第一连接桥208的贯通孔与第一部分204a和第二部分204b电连接，此时则连接线212的长度无需长于第一连接桥208。该存储电容电极213通过电容绝缘结构210可与下面对应的第一部分204a形成存储电容。
在一实施例中，该薄膜晶体管的第一极、第二极、第三极对应为薄膜晶体管的栅极、源极和漏极，该第一信号线为扫描线，该第二信号线为数据线。当然，在其他实施例中，该第二极和第三极可对应为漏极和源极；或者第一信号线为数据线，第二信号线为扫描线，对应地，该第一极为源极或漏极，该第二极为栅极。
上述第一、第二、第三道光罩为一般的普通光罩，或者为半色光罩。
请参阅图7和8，图7是本申请阵列基板一实施方式的俯视结构示意图，图8是图7所示阵列基板沿A-A方向的剖视图。本实施例中，该种阵列基板包括：
基板206；
设置在基板206上的薄膜晶体管的第一极201、第二极202和第三极203以及第一信号线204、第二信号线205，其中，所述第一信号线204包括分隔在所述第二信号线205两侧的第一部分204a和第二部分204b；
设置在所述第一部分204a和第二部分204b之间的第一连接桥208；
像素电极211和设置在所述第一连接桥208上面的连接线212，所述连接线212用于电连接所述第一部分204a和所述第二部分204b。
其中，该基板可以为玻璃基板或者其他透明绝缘材料形成的基板。该导电层可以为金属层，或者为其他可导电的非金属材料。该导电电极可以为透明导电电极，如ITO等。
可选地，该第一连接桥208宽于其覆盖第一部分204a的区域和其覆盖第二部分204b的区域。而且，该连接线212可长于该第一连接桥208，且窄于该第一连接桥208，当然，上述可以采用连接线通过第一连接桥208的贯通孔与第一部分204a和第二部分204b电连接，此时则连接线212的长度无需长于第一连接桥208。
可选地，该第一连接桥208包括从靠近基板206一侧依序为绝缘层207a、主动层207b、欧姆接触层207c和保护层207d，上述四层具体描述请参阅上面实施例相关说明。
可选地，所述第一信号线的第一部分204a与所述薄膜晶体管的第一极201电连接，所述第二信号线205与所述薄膜晶体管的第二极202电连接。
该阵列基板还包括设置在所述薄膜晶体管的第二极202和第三极203之间的第二连接桥209，以及设置在所述第二连接桥209上的第一导电电极215和第二导电电极216。其中，该第二连接桥209包括如上述的绝缘层207a、主动层207b、欧姆接触层207c和保护层207d，且所述第二连接桥209的保护层207d和电阻接触层207c均对应所述第二极和第三极断开设置，即通过该断开处214断开。当然，该主动层207b的上部分也可通过该断开处214断开，如图9所示。
该第一导电电极215电连接于所述第二极202和主动层207b，且与第二信号线205电连接；所述导电电极电连接于所述第三极203和所述主动层207b，且与像素电极211电连接。
进一步地，该第二连接桥209的主动层207b和欧姆接触层207c的边缘相对绝缘层207a和保护层207d凸出，形成接触环209a。该第一导电电极215和第二导电电极216均覆盖在该接触环209a上，以与主动层电连接。
可选地，该阵列基板还包括存储电容电极213以及设置在存储电容电极213和第一部分204之间的电容绝缘结构210。具体，该电容绝缘结构可以包括如上述的绝缘层207a、主动层207b、欧姆接触层207c和保护层207d。
本实施例中，该第一信号线204与该第二信号线205交错设置，如垂直设置。且该薄膜晶体管的第一极、第二极、第三极对应为薄膜晶体管的栅极、源极和漏极，该第一信号线为扫描线，该第二信号线为数据线。当然，在其他实施例中，该第二极和第三极可对应为漏极和源极；或者第一信号线为数据线，第二信号线为扫描线，对应地，该第一极为源极或漏极，该第二极为栅极。
本申请还提供一种阵列基板，该阵列基板由上述制作方法制作而成。
上述方案中的阵列基板可为液晶显示器中的阵列基板。
本申请还提供显示面板，包括阵列基板、彩膜基板及夹置在该两个基板之间的液晶。
上述方案中，通过将阵列基板的第一信号线对应第二信号线两侧分段设置，并在后续光罩中形成连接该第一信号线的连接线，既可实现第一信号线的正常布线，而且使得在一道光罩中即可形成第一、第二信号线，而无需分两道光罩实现，减少了阵列基板制作过程的光罩次数，减少阵列基板的制作耗时，降低生产成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板的制作方法，其中，包括：
    在基板上沉积导电层，并采用第一道光罩将所述导电层刻蚀出薄膜晶体管的三极以及第一信号线、第二信号线，其中，所述第一信号线包括分隔在所述第二信号线两侧的第一部分和第二部分；
    依序沉积中间层，并采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥；
    沉积导电电极，并采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线。
  2. 根据权利要求1所述的制作方法，其中，所述第一信号线的第一部分与所述薄膜晶体管的第一极电连接，所述第二信号线与所述薄膜晶体管的第二极电连接，所述中间层包括叠置的绝缘层、主动层、欧姆接触层和保护层；
    所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：
    采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥；
    所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：
    采用第三道光罩将所述第二连接桥上的所述导电电极、所述保护层及所述欧姆接触层对应所述第二极和第三极进行刻蚀断开。
  3. 根据权利要求2所述的制作方法，其中，所述采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥的步骤还包括：
    采用氢氟酸对所述第二连接桥中的保护层和绝缘层的边缘进行刻蚀，使所述第二连接桥中的主动层和欧姆接触层向外凸出形成接触环。
  4. 根据权利要求3所述的制作方法，其中，所述第二连接桥上的导电电极设置在所述接触环上，以使所述导电电极与所述接触环和所述第二极或第三极电连接。
  5. 根据权利要求1所述的制作方法，其中，所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：
    采用第二道光罩将所述中间层刻蚀出位于所述第一部分上面的电容绝缘结构；
    所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：
    采用第三道光罩将所述导电电极刻蚀出位于所述电容绝缘结构上面的存储电容电极。
  6. 根据权利要求1所述的制作方法，其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
  7. 根据权利要求4所述的制作方法，其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
  8. 一种阵列基板，其中，包括：
    基板；
    设置在基板上的薄膜晶体管的三极、第一信号线和第二信号线，其中，所述第一信号线包括分隔在所述第二信号线两侧的第一部分和第二部分；
    设置在所述第一部分和第二部分之间的第一连接桥，其中，所述第二连接桥与所述第二信号线绝缘；以及
    像素电极和设置在所述第一连接桥上面的连接线，所述连接线用于电连接所述第一部分和所述第二部分。
  9. 根据权利要求8所述的阵列基板，其中，所述第一信号线的第一部分与所述薄膜晶体管的第一极电连接；
    所述阵列基板还包括设置在所述薄膜晶体管的第二极和第三极之间的第二连接桥，以及设置在所述第二连接桥上的第一导电电极和第二导电电极，所述第二连接桥包括绝缘层、主动层、欧姆接触层及保护层，且所述第二连接桥的保护层和电阻接触层均对应所述第二极和第三极断开设置，所述第一导电电极电连接于所述第二极和主动层及所述第二信号线，所述导电电极电连接于所述第三极和所述主动层及所述像素电极。
  10. 根据权利要求9所述的阵列基板，其中，还包括所述第二连接桥中的主动层和欧姆接触层向外凸出形成得接触环。
  11. 根据权利要求10所述的阵列基板，其中，所述第二连接桥上的导电电极设置在所述接触环上，以使所述导电电极与所述接触环和所述第二极或第三极电连接。
  12. 根据权利要求8所述的阵列基板，其中，还包括依序设置在所述第一部分上面的电容绝缘结构和存储电容电极。
  13. 根据权利要求8所述的方法，其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
  14. 根据权利要求9所述的方法，其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
  15. 一种阵列基板，其中，所述阵列基板的制作方法包括以下步骤：
    在基板上沉积导电层，并采用第一道光罩将所述导电层刻蚀出薄膜晶体管的三极以及第一信号线、第二信号线，其中，所述第一信号线包括分隔在所述第二信号线两侧的第一部分和第二部分；
    依序沉积中间层，并采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥；
    沉积导电电极，并采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线。
  16. 根据权利要求15所述的阵列基板，其中，所述第一信号线的第一部分与所述薄膜晶体管的第一极电连接，所述第二信号线与所述薄膜晶体管的第二极电连接，所述中间层包括叠置的绝缘层、主动层、欧姆接触层和保护层；
    在所述阵列基板的制作方法中，所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：
    采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥；
    所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：
    采用第三道光罩将所述第二连接桥上的所述导电电极、所述保护层及所述欧姆接触层对应所述第二极和第三极进行刻蚀断开。
  17. 根据权利要求16所述的阵列基板，其中，在所述阵列基板的制作方法中，所述采用第二道光罩将所述中间层刻蚀出连接所述第二极和所述薄膜晶体管的第三极的第二连接桥的步骤还包括：
    采用氢氟酸对所述第二连接桥中的保护层和绝缘层的边缘进行刻蚀，使所述第二连接桥中的主动层和欧姆接触层向外凸出形成接触环。
  18. 根据权利要求17所述的阵列基板，其中，所述第二连接桥上的导电电极设置在所述接触环上，以使所述导电电极与所述接触环和所述第二极或第三极电连接。
  19. 根据权利要求15所述的阵列基板，其中，在所述阵列基板的制作方法中，所述采用第二道光罩将所述中间层刻蚀出连接所述第一部分和第二部分的第一连接桥的步骤还包括：
    采用第二道光罩将所述中间层刻蚀出位于所述第一部分上面的电容绝缘结构；
    所述采用第三道光罩将所述导电电极刻蚀出像素电极以及电连接所述第一部分和所述第二部分的连接线的步骤还包括：
    采用第三道光罩将所述导电电极刻蚀出位于所述电容绝缘结构上面的存储电容电极。
  20. 根据权利要求15所述的阵列基板，其中，所述薄膜晶体管的第一极、第二极、第三极分别是栅极、源极、漏极，所述第一信号线为扫描线、第二信号线为数据线。
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