WO2017145258A1 - 負荷変調増幅器 - Google Patents
負荷変調増幅器 Download PDFInfo
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- WO2017145258A1 WO2017145258A1 PCT/JP2016/055214 JP2016055214W WO2017145258A1 WO 2017145258 A1 WO2017145258 A1 WO 2017145258A1 JP 2016055214 W JP2016055214 W JP 2016055214W WO 2017145258 A1 WO2017145258 A1 WO 2017145258A1
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 29
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- 230000002194 synthesizing effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 9
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- 229920006395 saturated elastomer Polymers 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
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- BTYUGHWCEFRRRF-UHFFFAOYSA-N [As].[K] Chemical compound [As].[K] BTYUGHWCEFRRRF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
- H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
- H03F1/07—Doherty-type amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/391—Indexing scheme relating to amplifiers the output circuit of an amplifying stage comprising an LC-network
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/399—A parallel resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Definitions
- the present invention relates to a load modulation amplifier used for terrestrial microwave communication, mobile communication, and the like.
- the Doherty amplifier roughly distributes the input high frequency input signal into two signals.
- One of the distributed signals is input to the carrier amplifier, and the other is input to the peak amplifier with a phase delay of 90 degrees, that is, 1 / 4 ⁇ .
- Both the carrier amplifier and the peak amplifier have matching circuits for impedance matching on the input side and the output side, respectively.
- the carrier amplifier operates, for example, with a class A or class AB bias and always amplifies the input signal.
- the peak amplifier operates with a class C bias and amplifies an input signal having a predetermined power or more.
- the signals that have passed through the two amplifiers are combined in the combining circuit section after passing through the impedance conversion sections.
- the combining circuit unit further includes a quarter wavelength phase delay line that gives a 90-degree phase delay to the output on the carrier amplifier side before combining.
- the synthesized signal is output via an impedance converter.
- the Doherty amplifier In the Doherty amplifier, there are ideally two output powers at which the drain efficiency is maximized, so that the output power range in which the drain efficiency is high can be widened. Therefore, it can be said that the Doherty amplifier is one of the effective methods for realizing high efficiency characteristics in a system in which a signal having a large difference between peak power and average power is used. The Doherty amplifier will be described in detail later.
- the present invention has been made in order to solve the above-described problems, and is more compact in a load modulation amplifier such as a Doherty amplifier used in a system for processing a signal having a large difference between peak power and average power.
- the object is to realize high efficiency characteristics over a wide band.
- the present invention relates to a high-frequency circuit board, a distributor that is formed on the high-frequency circuit board, and distributes the input signal to the first and second input signals, and the distributed second input signal.
- An input distribution circuit unit having a phase delay circuit configured on a signal line, a carrier amplifier having a first high-frequency transistor and amplifying the first input signal from the input distribution circuit unit;
- An output synthesizing circuit unit comprising: a synthesizer that synthesizes the output of the phase delay circuit and the output of the peak amplifier; and an impedance conversion circuit that converts the output impedance of the synthesizer; Wherein the carrier amplifier and the peak amplifier, directly without converting the output impedance, which is connected to the output combiner unit, in a load modulation amplifier or the like.
- FIG. 1 is a schematic circuit configuration diagram of a load modulation amplifier according to a first embodiment of the present invention.
- FIG. 2 is a diagram for explaining an example of a circuit configuration between each amplifier and an output synthesis circuit unit in FIG. 1. It is a figure for demonstrating the effect of the load modulation amplifier by Embodiment 1 of this invention.
- It is a schematic circuit block diagram of the load modulation amplifier by Embodiment 2 of this invention.
- FIG. 5 is a diagram for explaining an example of a circuit configuration between each amplifier of FIG. 4 and an output synthesis circuit unit.
- FIG. 5 is a diagram for explaining another example of a circuit configuration between each amplifier and the output synthesis circuit unit in FIG. 4. It is a schematic circuit block diagram of the load modulation amplifier by Embodiment 3 of this invention.
- FIG. 10 is a schematic circuit configuration diagram of an example of a Doherty amplifier which is a general load modulation amplifier as disclosed in, for example, the above-mentioned Patent Document 1.
- the Doherty amplifier 1000 includes a carrier amplifier 101, a peak amplifier 102, an input distribution circuit unit 103, and an output synthesis circuit unit 104 formed on a high frequency circuit board CB.
- the input distribution circuit unit 103 distributes the high-frequency input signal input to the high-frequency input terminal 105 into two signals by the distributor 103a so that the power is equalized, for example.
- One of the distributed signals is input to the carrier amplifier 101, and the other is input to the peak amplifier 102 via a quarter wavelength phase delay line 103b that gives a phase delay of 90 degrees.
- the carrier amplifier 101 includes a carrier amplifying element 101b, and an input matching circuit 101a and an output matching circuit 101c on its input side and output side, respectively.
- the peak amplifier 102 includes a peak amplifying element 102b and an input matching circuit 102a and an output matching circuit 102c on its input side and output side, respectively.
- the carrier amplifying element 101b operates, for example, with a class A or class AB bias and always amplifies the input signal.
- the peak amplifying element 102b operates with a class C bias and amplifies an input signal having a predetermined power or more.
- the two signals that have passed through each amplifier are synthesized by the output synthesis circuit unit 104.
- the output synthesis circuit unit 104 includes an offset line 104a and a quarter-wavelength phase delay line 104b that gives a phase delay of 90 degrees on the carrier amplifier side. Further, an offset line 104d is provided on the peak amplifier side. Further, a synthesizer 104c and an impedance conversion circuit 104e are provided. The impedance conversion circuit 104e outputs the output of the load modulation amplifier from the high frequency output terminal 106.
- the output matching circuit 101c connected to the carrier amplifying element 101b matches the output impedance of the high-frequency transistor constituting the carrier amplifying element 101b with the characteristic impedance (for example, 50 ⁇ ) of the 1 ⁇ 4 wavelength phase delay line 104b. That is, when the output impedance of the high-frequency transistor is 5 ⁇ , it is matched with the characteristic impedance 50 ⁇ of the quarter wavelength phase delay line 104b.
- the 1/4 wavelength phase delay line 104 b gives a phase delay of 90 degrees on the output side of the carrier amplifier 101.
- the electrical length of the offset line 104a is set so that the impedance of the peak amplifier 102 as viewed from the synthesis point during the back-off operation is high, ideally in an open state.
- the electrical length of the offset line 104a is the same as the electrical length of the offset line 104d.
- the signal synthesized by the synthesizer 104 c is converted in output impedance by the impedance conversion circuit 104 e and output from the high frequency output terminal 106.
- Each circuit of the Doherty amplifier 1000 shown in FIG. 10 is connected by a high-frequency signal line SL.
- FIG. 11 is a diagram showing the drain efficiency with respect to the output voltage of the above-described general Doherty amplifier.
- the drain efficiency is maximized.
- the load is doubled compared to when both the carrier amplifier 101 and the peak amplifier 102 are operating.
- the drain efficiency is maximized at an output of 6 dB backoff.
- the Doherty amplifier since the Doherty amplifier has ideally two output powers at which the drain efficiency is maximized, the output power range with high drain efficiency can be widened. Therefore, it can be said that the Doherty amplifier is one of the effective methods for realizing high efficiency characteristics in a system in which a signal having a large difference between the peak power and the average power is used.
- the reactance component of the quarter wavelength phase delay line is large, so the impedance depends on the frequency. Therefore, there is a problem that the desired high-frequency characteristics cannot be obtained.
- the load modulation depending on the output power at the intrinsic node of the high frequency transistor is caused by the parasitic capacitance component of the high frequency transistor such as an FET constituting the carrier amplifier and the peak amplifier. This is not performed correctly, and there is a problem that high-efficiency characteristics cannot be obtained in a wide band.
- the output side matching circuit is connected to the output side of the peak amplifier, it is difficult to sufficiently increase the impedance of the peak amplifier as seen from the synthesis point during the back-off operation, and the efficiency during the back-off operation is degraded. There is a possibility that. Furthermore, since the 1/4 wavelength phase delay line is long, there is a problem that the amplifier size becomes large.
- FIG. 1 is a schematic circuit configuration diagram of a Doherty amplifier which is a load modulation amplifier according to Embodiment 1 of the present invention.
- the Doherty amplifier 2000 includes a carrier amplifier 1, a peak amplifier 2, an input distribution circuit unit 3, and an output synthesis circuit unit 4 formed on a high-frequency circuit board CB.
- Each circuit and its constituent elements of the Doherty amplifier 2000 are connected by a high-frequency signal line SL made of, for example, a microstrip line formed on the high-frequency circuit board CB, and a part thereof is constituted by the high-frequency signal line SL.
- the input distribution circuit unit 3 distributes the high-frequency input signal input to the high-frequency input terminal 5 into two signals composed of the first and second input signals by the distributor 3a so that the power becomes uniform, for example.
- One of the distributed signals, here the first input signal is input to the carrier amplifier 1, while the second input signal, here, is input to the peak amplifier 2 via the phase delay circuit 3b.
- the phase delay circuit 3b can also be configured by a phase delay line formed by, for example, a high frequency signal line SL.
- the carrier amplifier 1 includes a first high-frequency transistor 1a made of, for example, a field effect transistor (FET) and an input matching circuit 1b, and does not have an impedance conversion circuit such as a matching circuit on the output side.
- the peak amplifier 2 includes a second high-frequency transistor 2a made of, for example, an FET and an input matching circuit 2b, and similarly does not have an impedance conversion circuit such as a matching circuit on the output side.
- the carrier amplifier 1 operates with a class A or class AB bias, for example, and always amplifies the input signal.
- the peak amplifier 2 operates with a class C bias and amplifies an input signal having a predetermined power or more.
- the output synthesis circuit unit 4 includes a 90-degree phase delay circuit 4a directly connected to the carrier amplifier 1, a synthesizer 4b that synthesizes the output signal of the 90-degree phase delay circuit 4a and the output signal of the peak amplifier 2, and an impedance for converting the output impedance. It consists of a conversion circuit 4c.
- the signals of the carrier amplifier 1 and the peak amplifier 2 are synthesized by the 90-degree phase delay circuit 4a at the synthesis point, that is, the synthesizer 4b, in a state where the phases coincide with each other during the saturation operation.
- the synthesized signal is output from the high frequency output terminal 6 via the impedance conversion circuit 4c.
- the 90-degree phase delay circuit 4a is composed of, for example, a phase delay line including a signal line SL.
- the phase delay line is equivalently represented by a parallel capacitance component and a series inductor component as shown by a 90-degree phase delay circuit 4a in FIG.
- the load modulation depending on the output power is not correctly performed at the intrinsic node of the high-frequency transistor due to the parasitic capacitance component of the high-frequency transistor such as an FET constituting the high-frequency amplifier. There is. Therefore, as shown in FIG. 2, by using the parasitic capacitance component of each high-frequency transistor constituting the carrier amplifier 1 and the peak amplifier 2 as a parallel capacitance component of the phase delay line constituting the 90-degree phase delay circuit 4a, the Doherty amplifier The load modulation can be realized normally, and highly efficient characteristics can be realized.
- FIG. 3 is a diagram illustrating frequency characteristics of drain efficiency with respect to the output power back-off amount of the Doherty amplifier.
- the frequency is Basic frequency indicated by X1 Basic frequency indicated by X2 ⁇ 1.3
- a (Condition 1) is an ideal case where there is no parasitic capacitance of a high-frequency transistor.
- the case where the parasitic capacitance is absorbed in the phase delay line, that is, the case where the parasitic capacitance is used in the phase delay line is B (condition 2: Embodiment 1 of the present invention), C and D when the output matching circuit is connected due to parasitic capacitance (Conditions 3 and 4: Conventional configuration)
- a (condition 1) is indicated by a one-dot chain line
- B (condition 2) is indicated by a solid line
- C (condition 3) is indicated by a broken line
- D (condition 4) is indicated by a dotted line.
- Conditions 3 and 4 assumed different output matching circuit losses.
- the fundamental frequency (X1) the ideal case (A) and the configuration (B) shown in the first embodiment of the present invention achieve the same high efficiency characteristics, but the conventional configuration (C , D), it can be seen that the efficiency characteristic deteriorates according to the loss of the output matching circuit.
- the configuration (B) shown in the first embodiment of the present invention is adopted, so that the frequency is 10 compared with the conventional configuration (C, D). It can be seen that the efficiency can be improved by about a point.
- the parasitic capacitance components of the first high-frequency transistor 1a of the carrier amplifier 1 and the second high-frequency transistor 2a of the peak amplifier 2 are converted into the output combining circuit unit 4.
- the 90 degree phase delay circuit 4a By absorbing the 90 degree phase delay circuit 4a, the load modulation of the Doherty amplifier can be normally realized and a highly efficient characteristic can be realized. That is, the 90 degree phase delay circuit 4a has a circuit constant in which the parasitic capacitance components of the first and second high-frequency transistors 1a and 2a are incorporated.
- the carrier amplifier 1 and the peak amplifier 2 are connected to the output synthesis circuit unit 4 without providing an impedance conversion circuit such as a matching circuit, the amplifier size can be reduced.
- loss due to the matching circuit does not occur, it is possible to achieve high efficiency, and it is possible to increase the impedance of the peak amplifier 2 viewed from the synthesis point at the time of back-off operation, thereby improving efficiency at the time of back-off operation. Can also be realized.
- FIG. 4 is a schematic circuit diagram of a Doherty amplifier which is a load modulation amplifier according to Embodiment 2 of the present invention.
- the Doherty amplifier 2000 includes a carrier amplifier 1, a peak amplifier 2, an input distribution circuit unit 3, and an output synthesis circuit unit 4 formed on a high-frequency circuit board CB.
- the carrier amplifier 1 includes a first high-frequency transistor 1a, a first resonance circuit 1c that resonates with the parasitic capacitance of the first high-frequency transistor 1a, and an input matching circuit 1b, and an impedance conversion circuit such as a matching circuit on the output side. Does not have.
- the peak amplifier 2 includes a second high-frequency transistor 2a, a second resonance circuit 2c that resonates with the parasitic capacitance of the second high-frequency transistor 2a, and an input matching circuit 2b.
- the impedance conversion circuit is not provided.
- the carrier amplifier 1 operates with a class A or class AB bias, for example, and always amplifies the input signal.
- the peak amplifier 2 operates with a class C bias and amplifies an input signal having a predetermined power or more.
- FIG. 5 shows the first high-frequency transistor 1a and the resonance circuit 1c of the carrier amplifier 1 of FIG. 4, the second high-frequency transistor 2a and the resonance circuit 2c of the peak amplifier 2, and the 90-degree phase delay circuit 4a of the output synthesis circuit unit 4. It is a figure for demonstrating an example of a circuit structure. As described above, in the Doherty amplifier, the load modulation depending on the output power is not correctly performed at the intrinsic node of the high-frequency transistor due to the parasitic capacitance component of the high-frequency transistor such as an FET constituting the high-frequency amplifier. There is. Therefore, as shown in FIG.
- load modulation of the Doherty amplifier is normally realized by canceling the parasitic capacitance components of the high-frequency transistors constituting the carrier amplifier 1 and the peak amplifier 2 by the resonance circuits 1 c and 2 c, thereby achieving high efficiency.
- load modulation of the Doherty amplifier is normally realized by canceling the parasitic capacitance components of the high-frequency transistors constituting the carrier amplifier 1 and the peak amplifier 2 by the resonance circuits 1 c and 2 c, thereby achieving high efficiency.
- the frequency characteristics of the drain efficiency with respect to the output power back-off amount of the Doherty amplifier are almost the same as those in FIG.
- the resonance circuits 1c and 2c to be connected may be different. Further, as shown in FIG. 6, a part of the parasitic capacitance component of each high-frequency transistor is canceled out by the resonance circuits 1c and 2c, and the remaining parasitic capacitance component is 90 degrees constituted by the phase delay line as in the first embodiment. The same high efficiency characteristic can also be realized by absorbing the phase delay circuit 4a. 5 and 6, the resonance circuit 1c and the resonance circuit 2c are shown as an example of an inductance element connected in parallel to the signal line SL. However, the configuration of the resonance circuit is limited to this. is not.
- the parasitic capacitance components of the first high-frequency transistor 1a of the carrier amplifier 1 that is a high-frequency transistor and the second high-frequency transistor 2a of the peak amplifier 2 are resonant.
- load modulation of the Doherty amplifier can be normally realized and high-efficiency characteristics can be realized. Can do.
- the resonance circuits 1c and 2c have circuit constants that cancel all or part of the parasitic capacitance components of the high-frequency transistors 1a and 2a, and the 90-degree phase delay circuit 4a has circuit constants that incorporate the remaining capacitance components that are partially canceled.
- the carrier amplifier 1 and the peak amplifier 2 are connected to the output synthesis circuit unit 4 without providing an impedance conversion circuit such as a matching circuit, the amplifier size can be reduced. it can.
- loss due to the matching circuit does not occur, it is possible to achieve high efficiency, and it is possible to increase the impedance of the peak amplifier 2 viewed from the synthesis point at the time of back-off operation, thereby improving efficiency at the time of back-off operation. Can also be realized.
- FIG. 7 is a schematic circuit diagram of a Doherty amplifier which is a load modulation amplifier according to Embodiment 3 of the present invention.
- the carrier amplifier 1, the peak amplifier 2, the input distribution circuit unit 3, and the output synthesis circuit unit 4 are formed as a monolithic integrated circuit using a semiconductor substrate such as potassium arsenic (GaAs).
- GaAs potassium arsenic
- the semiconductor substrate of the monolithic integrated circuit is shown as a semiconductor substrate SCB.
- the carrier amplifier 1 includes a first high-frequency transistor 1a and an input matching circuit 1b, and does not have an impedance conversion circuit such as a matching circuit on the output side.
- the drain bias line of the first high-frequency transistor 1a made of FET is configured by the line SL1 or the inductance element 1dd provided on the semiconductor substrate SCB, and also serves as a resonance circuit that cancels the parasitic capacitance component of the first high-frequency transistor 1a. In addition to increasing the efficiency of the Doherty amplifier, the size can be reduced.
- the peak amplifier 2 includes a second high-frequency transistor 2a and an input matching circuit 2b, and similarly does not have an impedance conversion circuit such as a matching circuit on the output side.
- the drain bias line of the second high-frequency transistor 2a made of FET is constituted by a line SL2 or an inductance element 2dd provided on the semiconductor substrate SCB, and also serves as a resonance circuit that cancels the parasitic capacitance component of the second high-frequency transistor 2a. The same effect as that of the carrier amplifier 1 is realized.
- the outputs of the carrier amplifier 1 and the peak amplifier 2 are directly connected to the output synthesis circuit unit 4 without being connected to an impedance conversion circuit such as a matching circuit. That is, the output of the carrier amplifier 1 passes through an LPF (low-pass filter) type circuit element that is a 90-degree phase delay circuit 4a, and then in-phase combined with the output of the peak amplifier 2 in a combiner 4b composed of lines. Will be.
- LPF low-pass filter
- FIG. 7 it is assumed that the output of the carrier amplifier 1 is input to the circuit of the LPF type circuit element or the circuit element group of the LPF type, but the HPF (High Pass Filter) type circuit shown in FIG. Even if it is a case where it is a case where it inputs into the circuit of a circuit element group which is an element or HPF type, there is no problem.
- the output impedance of the carrier amplifier 1 depends on the size of the high-frequency transistor 1a, but is approximately 20 ⁇ when a peak output power of several hundred milliwatts is required. Therefore, the characteristic impedance of the 90-degree phase delay circuit 4a in FIG. 7 is set to about 20 ⁇ .
- the line width exceeds 200 ⁇ m, and the chip layout of the amplifier is difficult.
- the 90-degree phase delay circuit 4a may be configured by a line on a GaAs semiconductor substrate SCB or may be configured by a circuit element.
- the circuit element or the circuit element group may be LPF type or HPF type.
- the output of the synthesizer 4b is connected to the impedance conversion circuit 4c.
- the impedance conversion circuit 4c uses LPF type circuit elements or circuit element groups.
- the impedance conversion circuit 4c can be realized by a line SL provided on a GaAs semiconductor substrate SCB, and further uses an HPF type circuit element or circuit element group shown in FIG. You can also.
- the 90-degree phase delay circuit 4a and the impedance conversion circuit 4c are configured using LPF type circuit elements or circuit element groups, thereby suppressing the harmonic level at the output of the Doherty amplifier.
- the LPF connected to the output side of the amplifier can be eliminated or the filter order can be reduced, contributing to the miniaturization and cost reduction of the entire transmitter.
- the phase delay circuit 3b of the input distribution circuit unit 3 may also be composed of a line on a GaAs semiconductor substrate SCB as shown in FIG. It may also be composed of circuit elements.
- the circuit element or circuit element group may be the LPF type or the HPF type shown in FIG.
- the present invention can be applied to load modulation amplifiers of communication devices in various fields.
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Abstract
Description
なお、ドハティ増幅器に関しては後で詳しく述べる。
高周波入力信号の周波数が変化した場合、1/4波長位相遅延線路のインピーダンスの周波数依存性、キャリア増幅器およびピーク増幅器を構成する高周波トランジスタンの寄生容量成分による特性の変動、により広帯域に亘って所望の高周波特性が得られない、
増幅器の出力整合回路やピーク増幅器のオフ時のインピーダンスを高めるための補正線路のため、増幅器のサイズが大きくなってしまう、
等の課題があった。
ピーク増幅器102は、ピーク増幅素子102bと、その入力側と出力側に入力整合回路102aと出力整合回路102cをそれぞれ備えている。
キャリア増幅素子101bは例えばA級またはAB級バイアスで動作し入力信号を常に増幅する。一方、ピーク増幅素子102bはC級バイアスで動作し所定の電力以上の入力信号を増幅する。
合成器104cにおいて合成された信号は、インピーダンス変換回路104eにより出力インピーダンスを変換し、高周波出力端子106から出力される。
なお、図10に示すドハティ増幅器1000の各回路は高周波信号線路SLにより接続されている。
また同様に、高周波入力信号の周波数が変化した場合、キャリア増幅器およびピーク増幅器を構成する例えばFETのような高周波トランジスタンの寄生容量成分により、高周波トランジスタの真性ノードにおいて出力電力に依存した負荷変調が正しく行われず、広帯域に高効率な特性が得られないという問題が生じる。
またピーク増幅器の出力側に出力側整合回路を接続しているため、バックオフ動作時における合成点からみたピーク増幅器のインピーダンスを十分に高めることは困難であり、バックオフ動作時の効率を劣化させてしまう可能性がある。
さらに1/4波長位相遅延線路は長いため、増幅器サイズが大きくなってしまうという問題がある。
図1はこの発明の実施の形態1による負荷変調増幅器であるドハティ増幅器の概略的な回路構成図である。ドハティ増幅器2000は、キャリア増幅器1、ピーク増幅器2、入力分配回路部3、出力合成回路部4が、高周波回路基板CB上に形成されてなる。ドハティ増幅器2000の各回路およびその構成素子は、例えば高周波回路基板CB上に形成されたマイクロストリップライン等からなる高周波信号線路SLにより接続され、また一部は高周波信号線路SLにより構成されている。
また、ピーク増幅器2は、例えばFETからなる第2の高周波トランジスタ2aと入力整合回路2bから成り、同様に出力側に整合回路などのインピーダンス変換回路を有しない。
ここで、キャリア増幅器1は例えばA級またはAB級バイアスで動作し入力信号を常に増幅する。ピーク増幅器2はC級バイアスで動作し所定の電力以上の入力信号を増幅する。
周波数は、
X1で示す基本周波数
X2で示す基本周波数×1.3
の2点とした。
また各周波数において、
高周波トランジスタの寄生容量がない理想的な場合をA(条件1)、
寄生容量を位相遅延線路に吸収させている、すなわち寄生容量を位相遅延線路で使用する場合をB(条件2:この発明の実施の形態1)、
寄生容量があり出力整合回路を接続した場合をC,D(条件3,4:従来の構成)
でそれぞれ示している。
A(条件1)が一点鎖線、B(条件2)が実線、C(条件3)が破線、D(条件4)が点線、で示されている。
また周波数が変わり基本周波数×1.3となった場合(X2)にも、この発明の実施の形態1に示す構成(B)を採用することにより、従来構成(C,D)と比較し10ポイント程度効率を改善できることが分かる。
すなわち90度位相遅延回路4aは、第1および第2の高周波トランジスタ1a、2aの寄生容量成分が組み入れた回路定数を有する。
さらに、キャリア増幅器1およびピーク増幅器2には整合回路などのインピーダンス変換回路を備えることなく出力合成回路部4と接続しているため、増幅器サイズの小形化を実現できる。また、整合回路に起因する損失は生じないために高効率化を実現できるとともに、バックオフ動作時における合成点からみたピーク増幅器2のインピーダンスを高めることが可能となり、バックオフ動作時の高効率化もまた実現することができる。
図4はこの発明の実施の形態2による負荷変調増幅器であるドハティ増幅器の概略的な回路構成図である。ドハティ増幅器2000は、キャリア増幅器1、ピーク増幅器2、入力分配回路部3、出力合成回路部4が、高周波回路基板CB上に形成されてなる。
また、ピーク増幅器2は、第2の高周波トランジスタ2aと、第2の高周波トランジスタ2aの寄生容量と共振する第2の共振回路2cと、入力整合回路2bから成り、同様に出力側に整合回路などのインピーダンス変換回路を有しない。
ここで、キャリア増幅器1は例えばA級またはAB級バイアスで動作し入力信号を常に増幅する。ピーク増幅器2はC級バイアスで動作し所定の電力以上の入力信号を増幅する。
なお図5,図6において共振回路1c、共振回路2cを、一例として信号線路SLに対して並列に接続されたインダクタンス素子からなるものとして示したが、共振回路の構成はこれに限定されるものではない。
すなわち、共振回路1c,2cは高周波トランジスタ1a、2aの寄生容量成分の全部または一部を打ち消す回路定数を有し、90度位相遅延回路4aは一部打ち消した残りの容量成分が組み入れた回路定数を有する。
図7はこの発明の実施の形態3による負荷変調増幅器であるドハティ増幅器の概略的な回路構成図である。ドハティ増幅器2000は、キャリア増幅器1、ピーク増幅器2、入力分配回路部3、出力合成回路部4が、カリウムヒ素(GaAs)などの半導体基板を用いてモノリシック集積回路として形成されてなる。図7では、モノリシック集積回路の半導体基板を半導体基板SCBとして示す。
FETからなる第1の高周波トランジスタ1aのドレインバイアス線路は、半導体基板SCB上に設けた線路SL1またはインダクタンス素子1ddにより構成し、第1の高周波トランジスタ1aの寄生容量成分を打ち消す共振回路を兼ねることで、ドハティ増幅器の高効率化に加えサイズの小形化も実現する。
また、ピーク増幅器2は、第2の高周波トランジスタ2aと、入力整合回路2bから成り、同様に出力側に整合回路などのインピーダンス変換回路を有しない。
FETからなる第2の高周波トランジスタ2aのドレインバイアス線路は、半導体基板SCB上に設けた線路SL2またはインダクタンス素子2ddにより構成し、第2の高周波トランジスタ2aの寄生容量成分を打ち消す共振回路を兼ねることで、キャリア増幅器1の場合と同様の効果を実現する。
すなわち、90度位相遅延回路4aは、GaAsの半導体基板SCB上の線路で構成されてもよく、また回路素子で構成されていてもよい。90度位相遅延回路4aが回路素子で構成される場合、回路素子または回路素子群はLPF型でもHPF型でもよい。
Claims (7)
- 高周波回路基板と、
それぞれ前記高周波回路基板上に形成された、
1つの入力信号を第1および第2の入力信号に分配する分配器と、分配された前記第2の入力信号の信号線路上に構成された位相遅延回路と、を有する入力分配回路部と、
第1の高周波トランジスタを有し、前記入力分配回路部からの前記第1の入力信号を増幅するキャリア増幅器と、
第2の高周波トランジスタを有し、前記入力分配回路部からの前記第2の入力信号を増幅するピーク増幅器と、
前記キャリア増幅器の出力の信号線路上に構成された90度位相遅延回路と、前記90度位相遅延回路の出力と前記ピーク増幅器の出力とを合成する合成器と、前記合成器の出力インピーダンスを変換するインピーダンス変換回路と、を有する出力合成回路部と、
を備え、
前記キャリア増幅器および前記ピーク増幅器が、出力インピーダンスを変換することなく直接、前記出力合成回路部と接続された、負荷変調増幅器。 - 高周波回路基板と、
それぞれ前記高周波回路基板上に形成された、
1つの入力信号を第1および第2の入力信号に分配する分配器と、分配された前記第2の入力信号の信号線路上に構成された位相遅延回路と、を有する入力分配回路部と、
第1の高周波トランジスタを有し、前記入力分配回路部からの前記第1の入力信号を増幅するキャリア増幅器と、
第2の高周波トランジスタを有し、前記入力分配回路部からの前記第2の入力信号を増幅するピーク増幅器と、
前記キャリア増幅器の出力の信号線路上に構成された90度位相遅延回路と、前記90度位相遅延回路の出力と前記ピーク増幅器の出力とを合成する合成器と、前記合成器の出力インピーダンスを変換するインピーダンス変換回路と、を有する出力合成回路部と、
を備え、
前記キャリア増幅器は、前記第1の高周波トランジスタの寄生容量と共振する第1の共振回路を有し、出力インピーダンスを変換することなく直接、前記出力合成回路部と接続され、
前記ピーク増幅器は、前記第2の高周波トランジスタの寄生容量と共振する第2の共振回路を有し、出力インピーダンスを変換することなく直接、前記出力合成回路部と接続されている、負荷変調増幅器。 - 前記第1の共振回路および前記第2の共振回路はそれぞれ、信号線路に対し並列に接続されたインダクタンス素子を含む、請求項2に記載の負荷変調増幅器。
- 前記負荷変調増幅器がモノリシック集積回路であり、前記出力合成回路部の前記90度位相遅延回路が前記高周波回路基板上の信号線路で構成されている、請求項1から3までのいずれか1項に記載の負荷変調増幅器。
- 前記負荷変調増幅器がモノリシック集積回路であり、前記出力合成回路部の前記90度位相遅延回路がHPF型またはLPF型の回路素子で構成されている、請求項1から3までのいずれか1項に記載の負荷変調増幅器。
- 前記負荷変調増幅器がモノリシック集積回路であり、前記入力分配回路部の前記位相遅延回路が前記高周波回路基板上の信号線路で構成されている、請求項4または5に記載の負荷変調増幅器。
- 前記負荷変調増幅器がモノリシック集積回路であり、前記入力分配回路部の前記位相遅延回路がHPF型またはLPF型の回路素子で構成されている、請求項4または5に記載の負荷変調増幅器。
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CN108702134B (zh) | 2022-04-01 |
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US20190028062A1 (en) | 2019-01-24 |
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