WO2017133126A1 - 阵列基板及阵列基板的制备方法 - Google Patents

阵列基板及阵列基板的制备方法 Download PDF

Info

Publication number
WO2017133126A1
WO2017133126A1 PCT/CN2016/082105 CN2016082105W WO2017133126A1 WO 2017133126 A1 WO2017133126 A1 WO 2017133126A1 CN 2016082105 W CN2016082105 W CN 2016082105W WO 2017133126 A1 WO2017133126 A1 WO 2017133126A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
common electrode
gate
disposed
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/082105
Other languages
English (en)
French (fr)
Inventor
徐向阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/101,880 priority Critical patent/US10048556B2/en
Publication of WO2017133126A1 publication Critical patent/WO2017133126A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si

Definitions

  • the present invention relates to the field of display, and in particular, to a method for preparing an array substrate and an array substrate.
  • a display device such as a liquid crystal display (LCD) is a commonly used electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • a trans-flective liquid crystal display device has both transmissive and reflective characteristics.
  • the transflective liquid crystal panel includes a transmissive region with a transparent electrode and a reflective region with a reflective layer in one pixel domain. .
  • the transmission area and the backlight of the pixel area can be used to display the image, and the reflection area of the pixel area and the external light can be used to display the image in a bright place. Therefore, the transflective liquid crystal display device can be widely applied to adapt to different bright and dark environments.
  • the transflective liquid crystal display device has a weak ability to reflect external light, thereby causing the transflective liquid crystal display device to have poor display quality when displaying a picture when reflecting external light.
  • the present invention provides an array substrate including a substrate and a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines disposed on the same side of the substrate, the substrate including a first surface, A plurality of gate lines are disposed on the first surface, and the plurality of gate lines extend in a first direction and are spaced apart in a second direction, the plurality of data lines and the plurality of gate lines An insulating layer is disposed through the first insulating layer, and the plurality of data lines extend toward the second direction and are spaced apart along the first direction, the plurality of common electrode lines being parallel to the plurality of gate lines, a common electrode line is disposed between two adjacent gate lines, the common electrode line and the data line being insulated from the first insulating layer, the common electrode line being disposed adjacent to the first surface, And the common electrode line is a metal layer, and two adjacent ones A pixel region is defined between the gate line and the adjacent two data lines, the array substrate further includes a thin film transistor, a common electrode
  • the pixel electrode is a metal layer for reflecting light incident on the pixel electrode.
  • the thin film transistor further includes a first ohmic contact layer disposed between the channel layer and the source for reducing the channel layer and the source Contact resistance between.
  • the thin film transistor further includes a second ohmic contact layer disposed between the channel layer and the drain for reducing the channel layer and the drain Contact resistance between.
  • the first insulating layer includes a first through hole corresponding to the gate line
  • the second insulating layer includes a second through hole corresponding to the first through hole and corresponding to the data line.
  • a third through hole the array substrate further includes a gate terminal and a data terminal, wherein the gate terminal electrically connects the gate line through the first through hole and the second through hole, and the data terminal passes The third via hole electrically connects the data line, wherein the gate terminal and the data terminal are electrically conductive.
  • the invention also provides a method for preparing an array substrate, and the method for preparing the array substrate comprises:
  • the step of “forming a channel layer disposed corresponding to the gate on the surface of the first insulating layer away from the substrate” includes:
  • the ion doping is N-type ion doping.
  • the method for preparing the array substrate further includes:
  • a first through hole corresponding to the gate line is formed on the first insulating layer, and a second through hole corresponding to the first through hole and a corresponding portion of the data line are formed on the second insulating layer
  • Patterning the transparent conductive material layer retaining a transparent conductive material layer corresponding to the second through hole and the first through hole, and a transparent conductive material layer corresponding to the third through hole, wherein, corresponding to the second
  • the transparent conductive material layer of the through hole and the first through hole is a gate terminal, and the transparent conductive material layer corresponding to the third through hole is a data terminal.
  • the transparent conductive material layer comprises indium tin oxide.
  • the common electrode line in the array substrate of the present invention is a metal layer, and the common electrode line can reflect light incident on the common electrode line; the common electrode is a transparent conductive layer, and The light incident on the common electrode is transmitted such that the liquid crystal display device to which the array substrate is applied has a transflective performance.
  • the image reflected by the common electrode line can be used to display an image, thereby improving the display quality when the liquid crystal display device displays a picture.
  • the common electrode line is disposed on the common electrode and electrically connected to the common electrode, and thus, electrical conductivity between the common electrode line and the common electrode is improved.
  • FIG. 1 is a top plan view of an array substrate in accordance with a preferred embodiment of the present invention.
  • Figure 2 is a schematic cross-sectional view taken along line I-I of Figure 1.
  • FIG. 3 is a flow chart of a method of fabricating an array substrate according to a preferred embodiment of the present invention.
  • FIG. 1 is a plan view of an array substrate according to a preferred embodiment of the present invention
  • FIG. 2 is a cross-sectional structural view taken along line I-I of FIG.
  • the array substrate 10 can be applied to a Fringe Field Switching (FFS) panel device.
  • the array substrate 10 includes a substrate 100 and a plurality of gate lines 200 disposed on the same side of the substrate 100, a plurality of data lines 300, and a plurality of common electrode lines 400.
  • the substrate 100 includes a first surface 110.
  • the plurality of gate lines 200 are disposed on the first surface 110, and the plurality of gate lines 200 extend toward the first direction D1 and along The second direction D2 is arranged at intervals.
  • the plurality of data lines 300 are insulated from the plurality of gate lines 200 by a first insulating layer 520, and the data lines 300 extend toward the second direction D2 and are spaced apart along the first direction D1. .
  • the plurality of common electrode lines 400 are parallel to the plurality of gate lines 200, and one common electrode line 400 is disposed between two adjacent gate lines 200, the common electrode lines 400 and the data lines 300.
  • the first electrode layer 820 is insulated from the first insulating layer 820, the common electrode line 400 is disposed adjacent to the first surface 110, and the common electrode line 400 is a metal layer.
  • a pixel area is defined between two adjacent gate lines 200 and two adjacent data lines 300.
  • the array substrate 10 further includes a thin film transistor 800, a common electrode 500, and a pixel electrode 600 disposed in the pixel region.
  • the thin film transistor 800 includes a gate 810, the first insulating layer 820, a channel layer 830, a source 840, and a drain 850.
  • the gate electrode 810 is disposed on the first surface 110, the common electrode 500 is electrically connected to the common electrode line 400, and the common electrode 500 is disposed on the first surface 110, the common electrode 500 is a transparent conductive layer, and the common electrode line 400 is disposed on the common electrode 500 and electrically connected to the common electrode 500.
  • the channel layer 830, the source 840, and the drain 850 are disposed on the first insulating layer 820, and the source 840 and the drain 850 are disposed opposite to the channel layer 830.
  • the pixel electrode 600 is disposed on the first insulating layer 820 and corresponds to the common electrode 500, and the pixel electrode 600 is electrically connected to the drain 850, and a second insulating layer 860 is covered.
  • the channel layer 830, the source 840, the drain 850, the pixel electrode 600, and the data line 300 are described.
  • the first direction D1 may be an X-axis direction
  • the second direction D2 may be a Y-axis direction. It can be understood that in other embodiments, the first direction D1 may be a Y-axis direction, and the second direction D2 may be an X-axis direction.
  • the substrate 100 may be not limited to a glass substrate or an insulating substrate such as a plastic substrate.
  • the common electrode line 400 is a metal layer, and the common electrode line 400 can reflect the light incident on the common electrode line 400; the common electrode 500 is a transparent conductive layer, and can be transmitted through the incident The light of the common electrode 500 is described such that the liquid crystal display device to which the array substrate 10 is applied has a transflective performance.
  • the common electrode line 400 is disposed at The common electrode 500 is electrically connected to the common electrode 500, and thus, the electrical conductivity between the common electrode line 400 and the common electrode 500 is improved.
  • the pixel electrode 600 has a comb shape.
  • the pixel electrode 600 is a metal layer for reflecting light incident on the pixel electrode 600.
  • the image reflected by the pixel electrode 600 can be used to display an image, thereby improving the display quality when the liquid crystal display device displays a screen.
  • the thin film transistor 800 further includes a first ohmic contact layer 870 disposed between the channel layer 830 and the source 840 for reducing The contact resistance between the channel layer 830 and the source 840 is described.
  • the thin film transistor 800 further includes a second ohmic contact layer 880 disposed between the channel layer 830 and the drain 850 for reducing the channel layer 830 and Contact resistance between the drains 850.
  • the first insulating layer 820 includes a first through hole 821 corresponding to the gate line 200.
  • the second insulating layer 860 includes a second through hole 861 corresponding to the first through hole 821 and a third through hole 862 corresponding to the data line 300.
  • the array substrate 10 further includes a gate terminal 210 and a data terminal 310.
  • the gate terminal 210 is electrically connected to the gate line 200 through the first through hole 821 and the second through hole 861
  • the data terminal 310 is electrically connected to the data line through the third through hole 862 300, wherein the gate terminal 210 and the data terminal 310 are electrically conductive.
  • the gate terminal 210 and the data terminal 310 can be electrically connected to an integrated chip to receive signals of the integrated chip.
  • the common electrode line 400 in the array substrate 10 of the present invention is a metal layer, and the common electrode line 400 can reflect light incident on the common electrode line 400; the common electrode 500 is The transparent conductive layer can transmit the light incident to the common electrode 500, so that the liquid crystal display device to which the array substrate 10 is applied has a transflective performance.
  • the liquid crystal display device to which the array substrate 10 is applied is in a bright place, the light reflected by the common electrode line 400 can display an image, thereby improving the display quality when the liquid crystal display device displays a screen.
  • the common electrode line 400 is disposed on the common electrode 500 and electrically connected to the common electrode 500, and therefore, electrical conductivity between the common electrode line 400 and the common electrode 500 is improved.
  • FIG. 3 is a flowchart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the preparation method of the array substrate includes, but is not limited to, the following steps.
  • the substrate 110 is provided.
  • the substrate 110 may be, but not limited to, a glass substrate or an insulating substrate such as a plastic substrate.
  • Step S120 depositing a whole layer of the first transparent conductive layer on the first surface 111 of the substrate 110.
  • the first transparent conductive layer may be, but not limited to, indium tin oxide.
  • Step S130 patterning the first transparent conductive layer to form a plurality of common electrodes 500.
  • the first metal layer includes, but is not limited to, any one or more of aluminum (Al), molybdenum (Mo), and copper (Cu).
  • the first metal layer may be formed by physical vapor deposition (PVD), and the first metal layer may have a thickness of 3000 angstroms to 6000 angstroms.
  • Step S150 patterning the first metal layer to form a plurality of gate lines 200 parallel to the common electrode 500, a gate electrode 810 disposed between the two gate lines 200 and spaced apart, and a first A plurality of common electrode lines 400 extending in the direction D1 and spaced apart in the second direction D2 and disposed on the common electrode 500, wherein a common electrode 500 is disposed between the two gate lines 200.
  • the patterning of the first metal layer can be performed by exposure, development, etching, and stripping through a mask.
  • a first insulating layer 820 covering the gate line 810, the common electrode 500, the common electrode line 400, and the gate line 200 is formed.
  • the first insulating layer 820 may deposit an insulating material having a film thickness of 3000 ⁇ to 6000 ⁇ by a plasma enhanced chemical vapor deposition (PECVD) to form the first insulating layer 820.
  • the insulating layer material may be, but not limited to, silicon nitride (SiNx).
  • Step S170 forming a channel layer 830 disposed corresponding to the gate 810 on a surface of the first insulating layer 820 away from the substrate 110.
  • the step S170 includes the following steps.
  • Step S171 forming an entire layer of amorphous silicon layer on the surface of the first insulating layer 820 away from the substrate 110.
  • the amorphous silicon layer may form an amorphous silicon material having a film thickness of 1500 angstroms to 3000 angstroms by plasma enhanced chemical vapor deposition to form the amorphous silicon layer.
  • Step S172 patterning the amorphous silicon layer, and retaining the non-corresponding to the gate 810 Crystalline silicon layer.
  • Step S173 performing ion doping on both ends of the remaining amorphous silicon layer to form a first ohmic contact layer 870 and a second ohmic contact layer 880, respectively, and the amorphous silicon layer not ion-doped is The channel layer 830.
  • the ion doping is N-type ion doping.
  • Step S180 forming a second metal layer covering the first insulating layer 820 and the channel layer 830.
  • the second metal layer includes, but is not limited to, any one or more of Al, Mo, and Cu.
  • the second metal layer may be formed by PVD, and the second metal layer may have a thickness of 3000 ⁇ to 6000 ⁇ .
  • Step S190 patterning the second metal layer to form a plurality of data lines 300 extending along the second direction D2 and arranged along the first direction D1, and two adjacent data sets A source 840 and a drain 850 disposed between the lines 300 and corresponding to both ends of the channel layer 830, and a pixel electrode 600 electrically connected to the drain 850.
  • Patterning of the second metal layer can be performed by exposure, development, etching, and stripping through a mask.
  • a second insulating layer 860 covering the channel layer 830, the source 840, the drain 850, the pixel electrode 600, and the data line 300 is formed.
  • the second insulating layer 860 may deposit an insulating material having a film thickness of 2000 ⁇ to 56,000 ⁇ by PECVD to form the second insulating layer 860.
  • the insulating layer material may be, but not limited to, silicon nitride (SiNx). ).
  • the method for preparing the array substrate further includes the following steps.
  • Step 1 a first through hole 821 corresponding to the gate line 300 is formed on the first insulating layer 820 , and a second through hole corresponding to the first through hole 821 is defined in the second insulating layer 860 . 861 and a third through hole 862 corresponding to the data line 300.
  • Step II forming a transparent conductive material layer on the second insulating layer 860.
  • the conductive material layer may be, but not limited to, Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • the transparent conductive material layer has a thickness of 400 angstroms to 1000 angstroms.
  • Step III patterning the transparent conductive material layer, leaving a transparent conductive material layer corresponding to the second through hole 861 and the first through hole 821 and a transparent conductive material layer corresponding to the third through hole 862, wherein
  • the transparent conductive material layer corresponding to the second through hole 861 and the first through hole 821 is a gate terminal 210
  • the transparent conductive material layer corresponding to the third through hole 862 is a data terminal 310.
  • the gate electrode 810 and the common electrode line in the method for fabricating the array substrate of the present invention 400 Compared with the prior art, the gate electrode 810 and the common electrode line in the method for fabricating the array substrate of the present invention 400.
  • the gate line 200 is prepared in the same preparation process, which saves the preparation process.
  • the common electrode line 400 is a metal layer for reflecting light incident to the common electrode line 400. Therefore, when the liquid crystal display panel to which the array substrate 10 is applied is in a bright place, the light reflected by the common electrode line 400 can display an image, thereby improving the display quality when the liquid crystal display device displays a screen.
  • the source 840, the drain 850, the pixel electrode 600, and the data line 300 are prepared in the same preparation process, which saves the preparation process.
  • the pixel electrode 600 is a metal layer that can reflect light incident on the pixel electrode 600. Therefore, when the liquid crystal display panel to which the array substrate 10 is applied is in a bright place, an image can be displayed by the light reflected by the pixel electrode 400, thereby improving the display quality when the liquid crystal display device displays a screen.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板（10）及阵列基板（10）的制备方法。阵列基板（10）包括基板（100）及设置在基板（100）同侧的多个栅极线（200）、多个数据线（300）及多个公共电极线（400），基板（100）包括第一表面（110），栅极线（200）间隔排布在第一表面（110）上且与间隔排布数据线（300）通过第一绝缘层（820）绝缘设置，相邻的两条栅极线（200）及相邻的两条数据线（300）之间为像素区域，阵列基板（10）还包括设置在像素区域内的薄膜晶体管（800）、公共电极（500）及像素电极（600），薄膜晶体管（800）包括栅极（810）、沟道层（830）、源极（840）及漏极（850），栅极（810）及公共电极（500）设置在第一表面（110）上，公共电极（500）与栅极（810）平行、与公共电极线（400）电连接且为透明导电层，沟道层（830）、源极（840）、漏极（850）及像素电极（600）设置在第一绝缘层（820）上，且源极（840）与漏极（850）设置在沟道层（830）相对的两端，像素电极（600）与公共电极（500）对应且与漏极（850）电连接。

Description

阵列基板及阵列基板的制备方法
本发明要求2016年2月1日递交的发明名称为“阵列基板及阵列基板的制备方法”的申请号201610069410.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及阵列基板的制备方法。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。半透半反式液晶显示装置(Trans-flective Liquid Crystal Display)同时具有透射式和反射式特性，半透半反式液晶面板在一个像素域内包括有透明电极的透射区和有反射层的反射区。在黑暗的地方可以利用像素区域的透射区和背光源来显示画像，在明亮的地方利用像素区域的反射区和外光来显示画像。因此，半透半反式液晶显示装置可以适应不同的亮暗环境而得到广泛应用。现有技术中，所述半透半反式液晶显示装置中反射外来光线的能力较弱，从而导致半透半反式液晶显示装置在反射外来光线时显示画面时的显示质量较差。
发明内容
本发明提供一种阵列基板，所述阵列基板包括基板及设置在所述基板同侧的多个栅极线、多个数据线及多个公共电极线，所述基板包括第一表面，所述多个栅极线设置在所述第一表面上，且所述多个栅极线向第一方向延伸且沿第二方向间隔排布，所述多个数据线与所述多个栅极线通过第一绝缘层绝缘设置，且所述多个数据线向所述第二方向延伸且沿所述第一方向间隔排布，所述多个公共电极线与所述多个栅极线平行，一个公共电极线设置于相邻的两个栅极线之间，所述公共电极线与所述数据线通过所述第一绝缘层绝缘设置，所述公共电极线邻近所述第一表面设置，且所述公共电极线为金属层，相邻的两条 栅极线及相邻的两条数据线之间限定一个像素区域，所述阵列基板还包括设置在所述像素区域内的薄膜晶体管、公共电极及像素电极，所述薄膜晶体管包括栅极、所述第一绝缘层、沟道层、源极及漏极，所述栅极设置在所述第一表面上，所述公共电极与所述公共电极线电连接，且所述公共电极设置在所述第一表面上，所述公共电极为透明导电层，所述公共电极线设置在公共电极上且与所述公共电极电连接，所述沟道层、所述源极及所述漏极设置在所述第一绝缘层上且所述源极与所述漏极设置在所述沟道层相对的两端，所述像素电极设置在所述第一绝缘层上且与所述公共电极对应，且所述像素电极与所述漏极电连接，一第二绝缘层覆盖所述沟道层、所述源极、所述漏极、所述像素电极及所述数据线。
其中所述像素电极为金属层，用于反射入射至所述像素电极的光线。
其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置在所述沟道层与所述源极之间，用于减小所述沟道层与所述源极之间的接触电阻。
其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置在所述沟道层与所述漏极之间，用于减小所述沟道层与所述漏极之间的接触电阻。
其中，所述第一绝缘层包括对应所述栅极线开设的第一贯孔，所述第二绝缘层包括对应所述第一贯孔开设的第二贯孔及对应所述数据线开设的第三贯孔，所述阵列基板还包括栅极端子及数据端子，所述栅极端子通过所述第一贯孔及所述第二贯孔电连接所述栅极线，所述数据端子通过所述第三贯孔电连接所述数据线，其中，所述栅极端子及所述数据端子为导电的。
本发明还提供了一种阵列基板的制备方法，所述阵列基板的制备方法包括：
提供基板；
在所述基板的第一表面沉积整层的第一透明导电层；
图案化所述第一透明导电层，以形成多个公共电极；
沉积整层第一金属层；
图案化所述第一金属层，以形成与所述公共电极平行的多个栅极线，设置 在两栅极线之间的且间隔设置的栅极，以及向第一方向延伸且沿第二方向间隔排布的且设置在所述公共电极上的多个公共电极线，其中，两个栅极线之间设置一个公共电极；
形成覆盖所述栅极线、所述公共电极、所述公共电极线及所述栅极线的第一绝缘层；
在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层；
形成覆盖所述第一绝缘层及所述沟道层的第二金属层；
图案化所述第二金属层，以形成多个沿所述第二方向延伸且沿所述第一方向排布的多条数据线，以及设置在相邻的两条数据线之间且对应所述沟道层的两端设置的源极及漏极、及与所述漏极电连接的像素电极；
形成覆盖所述沟道层、所述源极、所述漏极、所述像素电极及所述数据线的第二绝缘层。
其中，所述步骤“在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层”包括：
在所述第一绝缘层远离所述基板的表面形成整层的非晶硅层；
图案化所述非晶硅层，保留对应所述栅极设置的所述非晶硅层；
对保留的所述非晶硅层的两端进行离子掺杂，以分别形成第一欧姆接触层及第二欧姆接触层，未进行离子掺杂的所述非晶硅层为所述沟道层。
其中，所述离子掺杂为N型离子掺杂。
其中，所述阵列基板的制备方法还包括：
在所述第一绝缘层上开设对应所述栅极线的第一贯孔，在所述第二绝缘层上开设对应所述第一贯孔的第二贯孔及对应所述数据线的第三贯孔；
在所述第二绝缘层上形成透明导电材料层；
图案化所述透明导电材料层，保留对应所述第二贯孔及所述第一贯孔的透明导电材料层以及对应所述第三贯孔的透明导电材料层，其中，对应所述第二贯孔及所述第一贯孔的透明导电材料层为栅极端子，对应所述第三贯孔的透明导电材料层为数据端子。
其中，所述透明导电材料层包括氧化铟锡。
相较于现有技术，本发明的阵列基板中的所述公共电极线为金属层，所述公共电极线可以反射入射到所述公共电极线的光线；所述公共电极为透明导电层，可以透射入射到所述公共电极的光线，从而使得所述阵列基板所应用的液晶显示装置具有半透半反的性能。当所述阵列基板所应用的液晶显示装置处于明亮的地方时，能够利用所述公共电极线反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。且所述公共电极线设置在所述公共电极上且与所述公共电极电连接，因此，所述公共电极线与所述公共电极之间的导电性能得到提高。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的俯视图。
图2为图1中沿I-I线的剖面结构示意图。
图3为本发明一较佳实施方式的阵列基板的制备方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1及图2，图1为本发明一较佳实施方式的阵列基板的俯视图；图2为图1中沿I-I线的剖面结构示意图。所述阵列基板10可应用于半透半反式边缘开关(Fringe Field Switching，FFS)面板装置。所述阵列基板10包括基板100及设置在所述基板100同侧的多个栅极线200、多个数据线300及多个公共电极线400。所述基板100包括第一表面110。所述多个栅极线200设置在所述第一表面110上，且所述多个栅极线200向第一方向D1延伸且沿 第二方向D2间隔排布。所述多个数据线300与所述多个栅极线200通过第一绝缘层520绝缘设置，且所述数据线300向所述第二方向D2延伸且沿所述第一方向D1间隔排布。所述多个公共电极线400与所述多个栅极线200平行，一个公共电极线400设置于相邻的两个栅极线200之间，所述公共电极线400与所述数据线300通过所述第一绝缘层820绝缘设置，所述公共电极线400邻近所述第一表面110设置，且所述公共电极线400为金属层。相邻的两条栅极线200及相邻的两条数据线300之间限定一个像素区域。所述阵列基板10还包括设置在所述像素区域内的薄膜晶体管800、公共电极500及像素电极600。所述薄膜晶体管800包括栅极810、所述第一绝缘层820、沟道层830、源极840及漏极850。所述栅极810设置在所述第一表面110上，所述公共电极500与所述公共电极线400电连接，且所述公共电极500设置于所述第一表面110上，所述公共电极500为透明导电层，所述公共电极线400设置在所述公共电极500上且与所述公共电极500电连接。所述沟道层830、所述源极840及所述漏极850设置在所述第一绝缘层820上且所述源极840与所述漏极850设置在所述沟道层830相对的两端，所述像素电极600设置在所述第一绝缘层820上且与所述公共电极500对应，且所述像素电极600与所述漏极850电连接，一第二绝缘层860覆盖所述沟道层830、所述源极840、所述漏极850、所述像素电极600及所述数据线300。在本实施方式中，所述第一方向D1可以为X轴方向，所述第二方向D2可以为Y轴方向。可以理解地，在其他实施方式中，所述第一方向D1可以为Y轴方向，所述第二方向D2可以为X轴方向。
所述基板100可以为的那不仅限于为玻璃基板或者为塑料基板等绝缘基板。
在本实施方式中，所述公共电极线400为金属层，所述公共电极线400可以反射入射到所述公共电极线400的光线；所述公共电极500为透明导电层，可以透射入射到所述公共电极500的光线，从而使得所述阵列基板10所应用的液晶显示装置具有半透半反的性能。当所述阵列基板10所应用的液晶显示装置处于明亮的地方时，能够利用所述公共电极线400反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。且所述公共电极线400设置在 所述公共电极500上且与所述公共电极500电连接，因此，所述公共电极线400与所述公共电极500之间的导电性能得到提高。
在本实施方式中，所述像素电极600呈梳状。所述像素电极600为金属层，用于反射入射至所述像素电极600的光线。当所述阵列基板10所应用的液晶显示装置处于明亮的地方时，能够利用所述像素电极600反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
在本实施方式中，所述薄膜晶体管800还包括第一欧姆接触层870，所述第一欧姆接触层870设置在所述沟道层830与所述源极840之间，用于减小所述沟道层830与所述源极840之间的接触电阻。
所述薄膜晶体管800还包括第二欧姆接触层880，所述第二欧姆接触层880设置在所述沟道层830与所述漏极850之间，用于减小所述沟道层830与所述漏极850之间的接触电阻。
在本实施方中，所述第一绝缘层820包括对应所述栅极线200开设的第一贯孔821。所述第二绝缘层860包括对应所述第一贯孔821开设的第二贯孔861及对应所述数据线300开设的第三贯孔862。所述阵列基板10还包括栅极端子210及数据端子310。所述栅极端子210通过所述第一贯孔821及所述第二贯孔861电连接所述栅极线200，所述数据端子310通过所述第三贯孔862电连接所述数据线300，其中，所述栅极端子210及所述数据端子310为导电的。所述栅极端子210及所述数据端子310可与一集成芯片电连接，以接收所述集成芯片的信号。
相较于现有技术，本发明的阵列基板10中的所述公共电极线400为金属层，所述公共电极线400可以反射入射到所述公共电极线400的光线；所述公共电极500为透明导电层，可以透射入射到所述公共电极500的光线，从而使得所述阵列基板10所应用的液晶显示装置具有半透半反的性能。当所述阵列基板10所应用的液晶显示装置处于明亮的地方时，能够利用所述公共电极线400反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。且所述公共电极线400设置在所述公共电极500上且与所述公共电极500电连接，因此，所述公共电极线400与所述公共电极500之间的导电性能得到提高。
下面结合图1和图2以及前面对阵列基板10的描述，对本发明的阵列基 板的制备方法进行介绍。请一并参阅图3，图3为本发明一较佳实施方式的阵列基板的制备方法的流程图。所述阵列基板的制备方法包括但不仅限于以下步骤。
步骤S110，提供基板110。所述基板110可以为但不仅限于为玻璃基板或者为塑料基板等绝缘基板。
步骤S120，在所述基板110的第一表面111沉积整层的第一透明导电层。所述第一透明导电层可以为但不仅限于为氧化铟锡。
步骤S130，图案化所述第一透明导电层，以形成多个公共电极500。
步骤S140，沉积整层第一金属层。所述第一金属层包括但不仅限于铝(Al)，钼(Mo)，铜(Cu)中的任意一种或者多种。所述第一金属层可以通过物理气相沉积(Physical Vapor Deposition，PVD)的方式形成，所述第一金属层的厚度可以为3000埃～6000埃。
步骤S150，图案化所述第一金属层，以形成与所述公共电极500平行的多个栅极线200，设置在两栅极线200之间的且间隔设置的栅极810，以及向第一方向D1延伸且沿第二方向D2间隔排布的且设置在所述公共电极500上的多个公共电极线400，其中，两个栅极线200之间设置一个公共电极500。所述第一金属层的图案化可以通过掩膜板进行曝光，显影，蚀刻及剥离的方式进行。
步骤S160，形成覆盖所述栅极线810、所述公共电极500、所述公共电极线400及所述栅极线200的第一绝缘层820。所述第一绝缘层820可以通过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积一层膜厚为3000埃～6000埃的绝缘材料以形成所述第一绝缘层820，所述绝缘层材料可以为但不仅限于为氮化硅(SiNx)。
步骤S170，在所述第一绝缘层820远离所述基板110的表面形成与所述栅极810对应设置的沟道层830。具体地，所述步骤S170包括如下步骤。
步骤S171，在所述第一绝缘层820远离所述基板110的表面形成整层的非晶硅层。所述非晶硅层可以通过等离子体增强化学气相沉积法形成膜厚为1500埃～3000埃的非晶硅材料以形成所述非晶硅层。
步骤S172，图案化所述非晶硅层，保留对应所述栅极810设置的所述非 晶硅层。
步骤S173，对保留的所述非晶硅层的两端进行离子掺杂，以分别形成第一欧姆接触层870及第二欧姆接触层880，未进行离子掺杂的所述非晶硅层为所述沟道层830。在一实施方式中，所述离子掺杂为N型离子掺杂。
步骤S180，形成覆盖所述第一绝缘层820及所述沟道层830的第二金属层。所述第二金属层包括但不仅限于Al，Mo，Cu中的任意一种或者多种。所述第二金属层可以通过PVD的方式形成，所述第二金属层的厚度可以为3000埃～6000埃。
步骤S190，图案化所述第二金属层，以形成多个沿所述第二方向D2延伸且沿所述第一方向D1排布的多条数据线300，以及设置在相邻的两条数据线300之间且对应所述沟道层830的两端设置的源极840及漏极850、及与所述漏极850电连接的像素电极600。所述第二金属层的图案化可以通过掩膜板进行曝光，显影，蚀刻及剥离的方式进行。
步骤S210，形成覆盖所述沟道层830、所述源极840、所述漏极850、所述像素电极600及所述数据线300的第二绝缘层860。所述第二绝缘层860可以通过PECVD沉积一层膜厚为2000埃～56000埃的绝缘材料以形成所述第二绝缘层860，所述绝缘层材料可以为但不仅限于为氮化硅(SiNx)。
在本实施方式中，所述阵列基板的制备方法还包括如下步骤。
步骤I，在所述第一绝缘层820上开设对应所述栅极线300的第一贯孔821，在所述第二绝缘层860上开设对应所述第一贯孔821的第二贯孔861及对应所述数据线300的第三贯孔862。
步骤II，在所述第二绝缘层860上形成透明导电材料层。所述导电材料层可以为但不仅限于为氧化铟锡(Indium Tin Oxide，ITO)。所述透明导电材料层的厚度为400埃～1000埃。
步骤III，图案化所述透明导电材料层，保留对应所述第二贯孔861及所述第一贯孔821的透明导电材料层以及对应所述第三贯孔862的透明导电材料层，其中，对应所述第二贯孔861及所述第一贯孔821的透明导电材料层为栅极端子210，对应所述第三贯孔862的透明导电材料层为数据端子310。
相较于现有技术，本发明的阵列基板的制备方法中栅极810、公共电极线 400、栅极线200在同一制备工序中制备，节约了制备工序。且所述公共电极线400为金属层，用于反射入射至所述公共电极线400的光线。因此，在所述阵列基板10所应用的液晶显示面板处于明亮的地方时，能够利用所述公共电极线400反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
进一步地，所述源极840、所述漏极850、所述像素电极600及所述数据线300在同一制备工序中制备，节约了制备工序。且所述像素电极600为金属层，可以反射入射至所述像素电极600的光线。因此，在所述阵列基板10所应用的液晶显示面板处于明亮的地方时，能够利用所述像素电极400反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板，其中，所述阵列基板包括基板及设置在所述基板同侧的多个栅极线、多个数据线及多个公共电极线，所述基板包括第一表面，所述多个栅极线设置在所述第一表面上，且所述多个栅极线向第一方向延伸且沿第二方向间隔排布，所述多个数据线与所述多个栅极线通过第一绝缘层绝缘设置，且所述多个数据线向所述第二方向延伸且沿所述第一方向间隔排布，所述多个公共电极线与所述多个栅极线平行，一个公共电极线设置于相邻的两个栅极线之间，所述公共电极线与所述数据线通过所述第一绝缘层绝缘设置，所述公共电极线邻近所述第一表面设置，且所述公共电极线为金属层，相邻的两条栅极线及相邻的两条数据线之间限定一个像素区域，所述阵列基板还包括设置在所述像素区域内的薄膜晶体管、公共电极及像素电极，所述薄膜晶体管包括栅极、所述第一绝缘层、沟道层、源极及漏极，所述栅极设置在所述第一表面上，所述公共电极与所述公共电极线电连接，且所述公共电极设置在所述第一表面上，所述公共电极为透明导电层，所述公共电极线设置在公共电极上且与所述公共电极电连接，所述沟道层、所述源极及所述漏极设置在所述第一绝缘层上且所述源极与所述漏极设置在所述沟道层相对的两端，所述像素电极设置在所述第一绝缘层上且与所述公共电极对应，且所述像素电极与所述漏极电连接，一第二绝缘层覆盖所述沟道层、所述源极、所述漏极、所述像素电极及所述数据线。
  2. 如权利要求1所述的阵列基板，其中，所述像素电极为金属层，用于反射入射至所述像素电极的光线。
  3. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置在所述沟道层与所述源极之间，用于减小所述沟道层与所述源极之间的接触电阻。
  4. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括第二欧姆 接触层，所述第二欧姆接触层设置在所述沟道层与所述漏极之间，用于减小所述沟道层与所述漏极之间的接触电阻。
  5. 如权利要求1所述的阵列基板，其中，所述第一绝缘层包括对应所述栅极线开设的第一贯孔，所述第二绝缘层包括对应所述第一贯孔开设的第二贯孔及对应所述数据线开设的第三贯孔，所述阵列基板还包括栅极端子及数据端子，所述栅极端子通过所述第一贯孔及所述第二贯孔电连接所述栅极线，所述数据端子通过所述第三贯孔电连接所述数据线，其中，所述栅极端子及所述数据端子为导电的。
  6. 一种阵列基板的制备方法，其中，所述阵列基板的制备方法包括：
    提供基板；
    在所述基板的第一表面沉积整层的第一透明导电层；
    图案化所述第一透明导电层，以形成多个公共电极；
    沉积整层第一金属层；
    图案化所述第一金属层，以形成与所述公共电极平行的多个栅极线，设置在两栅极线之间的且间隔设置的栅极，以及向第一方向延伸且沿第二方向间隔排布的且设置在所述公共电极上的多个公共电极线，其中，两个栅极线之间设置一个公共电极；
    形成覆盖所述栅极线、所述公共电极、所述公共电极线及所述栅极线的第一绝缘层；
    在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层；
    形成覆盖所述第一绝缘层及所述沟道层的第二金属层；
    图案化所述第二金属层，以形成多个沿所述第二方向延伸且沿所述第一方向排布的多条数据线，以及设置在相邻的两条数据线之间且对应所述沟道层的两端设置的源极及漏极、及与所述漏极电连接的像素电极；
    形成覆盖所述沟道层、所述源极、所述漏极、所述像素电极及所述数据线的第二绝缘层。
  7. 如权利要求6所述的阵列基板的制备方法，其中，所述步骤“在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层”包括：
    在所述第一绝缘层远离所述基板的表面形成整层的非晶硅层；
    图案化所述非晶硅层，保留对应所述栅极设置的所述非晶硅层；
    对保留的所述非晶硅层的两端进行离子掺杂，以分别形成第一欧姆接触层及第二欧姆接触层，未进行离子掺杂的所述非晶硅层为所述沟道层。
  8. 如权利要求7所述的阵列基板的制备方法，其中，所述离子掺杂为N型离子掺杂。
  9. 如权利要求6所述的阵列基板的制备方法，其中，所述阵列基板的制备方法还包括：
    在所述第一绝缘层上开设对应所述栅极线的第一贯孔，在所述第二绝缘层上开设对应所述第一贯孔的第二贯孔及对应所述数据线的第三贯孔；
    在所述第二绝缘层上形成透明导电材料层；
    图案化所述透明导电材料层，保留对应所述第二贯孔及所述第一贯孔的透明导电材料层以及对应所述第三贯孔的透明导电材料层，其中，对应所述第二贯孔及所述第一贯孔的透明导电材料层为栅极端子，对应所述第三贯孔的透明导电材料层为数据端子。
  10. 如权利要求8所述的阵列基板的制备方法，其中，所述透明导电材料层包括氧化铟锡。
PCT/CN2016/082105 2016-02-01 2016-05-13 阵列基板及阵列基板的制备方法 Ceased WO2017133126A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/101,880 US10048556B2 (en) 2016-02-01 2016-05-13 Array substrate having multiple common electrode lines

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610069410.0A CN105487285B (zh) 2016-02-01 2016-02-01 阵列基板及阵列基板的制备方法
CN201610069410.0 2016-02-01

Publications (1)

Publication Number Publication Date
WO2017133126A1 true WO2017133126A1 (zh) 2017-08-10

Family

ID=55674362

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/082105 Ceased WO2017133126A1 (zh) 2016-02-01 2016-05-13 阵列基板及阵列基板的制备方法

Country Status (3)

Country Link
US (1) US10048556B2 (zh)
CN (1) CN105487285B (zh)
WO (1) WO2017133126A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679773B (zh) * 2016-01-29 2018-12-07 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法
CN105487285B (zh) 2016-02-01 2018-09-14 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法
CN106707648B (zh) * 2017-02-21 2019-12-03 京东方科技集团股份有限公司 一种显示基板、显示装置及其驱动方法
CN107450239A (zh) * 2017-08-29 2017-12-08 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
JP2019070744A (ja) * 2017-10-10 2019-05-09 三菱電機株式会社 液晶表示装置
CN112631030B (zh) * 2020-12-03 2022-04-01 Tcl华星光电技术有限公司 阵列基板及测量阵列基板电容的方法
CN114326232A (zh) * 2021-12-30 2022-04-12 广州华星光电半导体显示技术有限公司 阵列基板及其制造方法、显示面板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070258035A1 (en) * 2006-05-02 2007-11-08 Au Optronics Corporation Liquid Crystal Display Array Substrate and its Manufacturing Method
CN101609236A (zh) * 2009-07-15 2009-12-23 上海广电光电子有限公司 薄膜晶体管阵列基板制造方法
CN102543863A (zh) * 2012-02-06 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN103048838A (zh) * 2012-12-13 2013-04-17 北京京东方光电科技有限公司 一种阵列基板、液晶显示面板及驱动方法
CN104122713A (zh) * 2013-05-09 2014-10-29 深超光电（深圳）有限公司 一种液晶显示器阵列基板的制造方法
CN104570523A (zh) * 2015-01-16 2015-04-29 昆山龙腾光电有限公司 一种阵列基板、阵列基板的形成方法及液晶显示装置
CN105487285A (zh) * 2016-02-01 2016-04-13 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100483358B1 (ko) * 2001-09-07 2005-04-14 엘지.필립스 엘시디 주식회사 반사투과형 액정표시장치용 어레이기판과 그 제조방법
US8125601B2 (en) * 2003-01-08 2012-02-28 Samsung Electronics Co., Ltd. Upper substrate and liquid crystal display device having the same
JP4354205B2 (ja) * 2003-03-27 2009-10-28 三菱電機株式会社 液晶表示装置及びその製造方法
KR100602062B1 (ko) * 2003-04-03 2006-07-14 엘지.필립스 엘시디 주식회사 수평 전계 인가형 액정 표시 장치 및 그 제조 방법
CN100371813C (zh) * 2003-10-14 2008-02-27 Lg.菲利浦Lcd株式会社 面内切换型液晶显示装置中的液晶显示板及其制造方法
KR100560399B1 (ko) * 2003-11-04 2006-03-14 엘지.필립스 엘시디 주식회사 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법
KR101036723B1 (ko) * 2003-12-30 2011-05-24 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
KR101182557B1 (ko) * 2005-06-24 2012-10-02 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
KR101269002B1 (ko) * 2006-10-25 2013-05-29 엘지디스플레이 주식회사 횡전계 방식 액정표시장치용 어레이기판과 그 제조방법
KR101421166B1 (ko) * 2007-03-02 2014-07-18 엘지디스플레이 주식회사 액정표시장치의 제조방법
KR20090075369A (ko) * 2008-01-04 2009-07-08 삼성전자주식회사 표시 패널
KR101287478B1 (ko) * 2009-06-02 2013-07-19 엘지디스플레이 주식회사 산화물 박막트랜지스터를 구비한 표시소자 및 그 제조방법
US8405810B2 (en) * 2009-07-23 2013-03-26 Lg Display Co., Ltd. Liquid crystal display and fabricating method thereof
KR20110074377A (ko) * 2009-12-24 2011-06-30 엘지디스플레이 주식회사 박막 트랜지스터 어레이기판 및 그의 제조방법
KR20120014808A (ko) * 2010-08-10 2012-02-20 엘지디스플레이 주식회사 터치 센서가 내장된 액정 표시 장치 및 그 구동 방법과 그 제조 방법
KR101396943B1 (ko) * 2012-06-25 2014-05-19 엘지디스플레이 주식회사 액정표시장치 및 제조방법
CN103325792A (zh) * 2013-05-23 2013-09-25 合肥京东方光电科技有限公司 一种阵列基板及制备方法、显示装置
KR20150036940A (ko) * 2013-09-30 2015-04-08 엘지디스플레이 주식회사 액정표시장치의 제조방법
US9711543B2 (en) * 2013-11-29 2017-07-18 Lg Display Co., Ltd. Liquid crystal display and method for manufacturing the same
KR102132445B1 (ko) * 2013-12-31 2020-07-09 엘지디스플레이 주식회사 액정 디스플레이 패널 및 이의 제조 방법
CN104217994B (zh) * 2014-08-29 2017-10-03 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制备方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070258035A1 (en) * 2006-05-02 2007-11-08 Au Optronics Corporation Liquid Crystal Display Array Substrate and its Manufacturing Method
CN101609236A (zh) * 2009-07-15 2009-12-23 上海广电光电子有限公司 薄膜晶体管阵列基板制造方法
CN102543863A (zh) * 2012-02-06 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN103048838A (zh) * 2012-12-13 2013-04-17 北京京东方光电科技有限公司 一种阵列基板、液晶显示面板及驱动方法
CN104122713A (zh) * 2013-05-09 2014-10-29 深超光电（深圳）有限公司 一种液晶显示器阵列基板的制造方法
CN104570523A (zh) * 2015-01-16 2015-04-29 昆山龙腾光电有限公司 一种阵列基板、阵列基板的形成方法及液晶显示装置
CN105487285A (zh) * 2016-02-01 2016-04-13 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法

Also Published As

Publication number Publication date
US20180046050A1 (en) 2018-02-15
US10048556B2 (en) 2018-08-14
CN105487285B (zh) 2018-09-14
CN105487285A (zh) 2016-04-13

Similar Documents

Publication Publication Date Title
CN105487285B (zh) 阵列基板及阵列基板的制备方法
US8218117B2 (en) Liquid crystal display and method of manufacturing the same
KR101881020B1 (ko) 액정 표시 장치 및 그 형성 방법
WO2017147974A1 (zh) 阵列基板的制作方法及制得的阵列基板
TWI497182B (zh) 顯示裝置
US9978880B2 (en) Display device
WO2015000255A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
CN113467145B (zh) 阵列基板及制作方法、显示面板
CN106483726A (zh) 薄膜晶体管阵列基板及制作方法和液晶显示面板
CN108054140B (zh) Ffs模式阵列基板的制造方法
CN105742292A (zh) 阵列基板的制作方法及制得的阵列基板
WO2017152508A1 (zh) 阵列基板及液晶显示面板
WO2014183420A1 (zh) 一种阵列基板及其制作方法和显示面板
CN105679773B (zh) 阵列基板及阵列基板的制备方法
CN114402430A (zh) 阵列基板及制作方法、显示面板
TW201044087A (en) Pixel designs of improving the aperture ratio in an LCD
TWI444737B (zh) 平面內切換型液晶顯示面板及其製造方法
WO2019100495A1 (zh) Ffs型薄膜晶体管阵列基板及其制作方法
CN107908054B (zh) 显示装置、半透半反的阵列基板及其制造方法
WO2017147973A1 (zh) 阵列基板的制作方法及制得的阵列基板
CN106707635A (zh) 阵列基板及其制造方法、液晶显示面板及液晶显示装置
US9685463B2 (en) Array substrate, its manufacturing method, display panel and display device
US10461102B2 (en) Display device, transflective array substrate, and manufacturing method thereof
CN114236931B (zh) 阵列基板及制作方法、显示面板
KR101058669B1 (ko) 액정표시장치 및 그 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15101880

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16888948

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16888948

Country of ref document: EP

Kind code of ref document: A1