WO2017133095A1 - 一种双栅极阵列基板及显示装置 - Google Patents

一种双栅极阵列基板及显示装置 Download PDF

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Publication number
WO2017133095A1
WO2017133095A1 PCT/CN2016/081109 CN2016081109W WO2017133095A1 WO 2017133095 A1 WO2017133095 A1 WO 2017133095A1 CN 2016081109 W CN2016081109 W CN 2016081109W WO 2017133095 A1 WO2017133095 A1 WO 2017133095A1
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Prior art keywords
array substrate
signal line
electrode
dry
gate array
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PCT/CN2016/081109
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English (en)
French (fr)
Inventor
臧鹏程
黄炜赟
祁小敬
刘庭良
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/519,596 priority Critical patent/US10488718B2/en
Publication of WO2017133095A1 publication Critical patent/WO2017133095A1/zh
Anticipated expiration legal-status Critical
Priority to US16/656,969 priority patent/US11442318B2/en
Priority to US17/884,708 priority patent/US11906864B2/en
Priority to US18/420,881 priority patent/US12429741B2/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a dual gate array substrate and a display device.
  • FIG. 1(a) and FIG. 1(b) it is a schematic diagram of a conventional dual-gate driven array substrate.
  • a pixel field switch (FFS) display mode is taken as an example to define pixel units as a pixel unit A, and a pixel unit B adjacent to the pixel unit A in the horizontal direction; as shown in FIG.
  • FFS pixel field switch
  • the TFT devices of the two pixel units are respectively located above and below the pixel unit, and each passes through a respective The source is connected to the same data line L S , and the gate of the TFT device is connected to the gate line L G .
  • two gate lines L G are disposed between adjacent pixel units in the vertical direction, which is convenient for realizing double gate Extreme drive.
  • adjacent pixel units A and P units B are connected to the data line L S between the two, and the pixel unit B is adjacent to another one. There is no data line set between the pixel units A.
  • the coupling capacitance generated between the electrodes needs to be set larger at the position (the corresponding area of the broken line in the figure) of the dry electrode 121 of the common electrode 12, and it is preferable to enable the dry electrode 121 of the common electrode at the position to be in the array
  • the orthographic projections on the substrate can overlap with the adjacent pixel electrodes 11, respectively, so as to well block the influence of the coupling capacitance on the rotation of the liquid crystal.
  • the dual gate array substrate is provided with two gate lines between adjacent pixel units, an additional gate line is added compared to the prior art, and an additional black matrix corresponding to the color film substrate side is necessarily required.
  • the aperture ratio of the panel formed by the array substrate is reduced, in other words, the transmittance of the array substrate is lowered.
  • a common electrode at the gap between adjacent pixel units is caused. The larger the area, the structure also causes the aperture ratio of the array substrate to decrease and the transmittance to decrease.
  • the embodiment of the invention provides a dual-gate array substrate and a display device, which can improve the transmittance of the prior art double-gate array substrate.
  • a dual gate array substrate comprising:
  • the adjacent two gate lines are insulated from the main signal line or the sub-signal line to form a plurality of pixel units, and the main signal lines are led out by the driving unit and respectively adjacent to the pixels Unit connection
  • the sub-signal line is connected to the common electrode, wherein the common electrode includes a plurality of dry electrodes and a plurality of branch electrodes, and an orthographic projection of the dry electrodes on the array substrate is respectively associated with an adjacent pixel electrode
  • the orthographic projection on the dual gate array substrate has an overlap region and covers at least the main signal line.
  • the voltage connecting the sub-signal lines is relatively stable.
  • the voltage completely avoids the possibility of generating coupling capacitance with adjacent pixel electrodes. Therefore, the present invention does not need to reduce the coupling capacitance in a manner that increases the size of the dry electrode in the prior art, that is, the dry electrode located above the sub-signal line may not necessarily be set large, thereby increasing the aperture ratio of the array substrate.
  • the line width of the sub signal line is not greater than the line width of the main signal line.
  • the line width of the sub-signal line is not greater than the line width of the main signal line, so that the size of the black matrix corresponding to the color film substrate side can be reduced, thereby increasing the aperture ratio of the dual-gate array substrate.
  • the dry electrode of the common electrode is disposed along a direction in which the main signal line extends, the branch electrode is parallel to the dry electrode, and any two adjacent dry electrodes and the two dry Electricity a common electrode pattern formed by the branch electrodes between the poles corresponds to one pixel unit;
  • An orthographic projection of the first dry electrode on the array substrate respectively overlaps an orthographic projection of an adjacent pixel electrode on the dual gate array substrate and covers at least the main signal line
  • the An orthographic projection of the second dry electrode adjacent to the first dry electrode on the dual gate array substrate is located in a gap between adjacent pixel electrodes and covers the sub signal line.
  • the stable capacitance can be superimposed with the capacitance generated by the pixel electrode and the common electrode to become a storage capacitor required for the dual gate array substrate, thereby better controlling the voltage at the junction of the pixel electrode and the common electrode.
  • the direction of the electric field required for the rotation of the liquid crystal is the same as the direction of the electric field superimposed at the boundary, and is relatively stable. Therefore, the electric field generated by the superposed storage capacitor can promote the liquid crystal at the interface. Rotate, and in turn, increase the transmittance of the panel.
  • the orthographic projection of the second dry electrode adjacent to the first dry electrode on the array substrate coincides with the sub-signal line.
  • the superposed fringe field can be optimally increased, and the rotation of the liquid crystal at the interface between the pixel electrode and the common electrode is improved, thereby increasing the transmittance of the panel.
  • the dry electrode of the common electrode is disposed along a direction in which the main signal line extends, the branch electrode is disposed in a direction crossing the main signal line, and any two adjacent dry electrodes are disposed.
  • a common electrode pattern formed by the branch electrode between the two dry electrodes corresponds to two adjacent pixel units;
  • the orthographic projections of the two dry electrodes on the array substrate respectively overlap an orthographic projection of an adjacent pixel electrode on the dual gate array substrate and cover at least the main signal line, the branch
  • the electrodes are continuous in pattern at the interface between adjacent pixel cells.
  • the direction of the electric field required for the rotation of the liquid crystal is different from the direction of the electric field superimposed at the boundary. Therefore, the dry electrode above the sub-signal line can be removed, and at the same time, the size of the pixel electrode adjacent to the sub-signal line is increased. Thereby, the overlapping area of the branch electrode and the pixel electrode is made more, and, The increase of the overlap region increases the electric field required for the rotation of the liquid crystal, and more importantly, the increased overlap region is located at the boundary between the pixel electrode and the sub-signal line, thereby causing the liquid crystal at the junction to rotate, thereby Increase the transmittance of the panel.
  • the branch electrodes are provided with a corner structure at the interface between adjacent pixel units.
  • the sub signal line is made of a metal or a transparent oxide.
  • the sub signal line is made of indium tin oxide.
  • a display device includes a color filter substrate, and further includes the dual gate array substrate.
  • a black matrix is disposed at a position corresponding to the side signal line of the array substrate side in the color filter substrate, wherein an orthographic projection of the black matrix on the array substrate and the The orthogonal projection of the sub-signal lines on the array substrate coincides.
  • 1(a) and 1(b) are schematic diagrams of a conventional dual gate driven array substrate
  • FIGS. 2(a) and 2(b) are schematic structural views of a dual gate array substrate provided by the present invention.
  • 3(a) is a schematic diagram of a pixel unit pattern in an array substrate corresponding to an FFS display mode
  • 3(b) is a schematic diagram of a pixel unit pattern in an array substrate corresponding to an FFS display mode
  • FIG. 4(a) is a schematic structural view of an array substrate of an FFS display mode in the first embodiment
  • Example 4(b) is a cross-sectional view showing an array substrate of an FFS display mode in Example 1 of the present invention
  • Example 5(a) is a schematic structural view of an array substrate of an AFFS display mode in Example 2 of the present invention.
  • 5(b) and 5(c) are array substrates of the AFFS display mode in the second embodiment of the present invention, respectively. a cross-sectional view of the middle section A-A and the section B-B;
  • Fig. 6 is a schematic view showing a structure in which a branch electrode of a common electrode is provided with a corner structure in Example 2 of the present invention.
  • a schematic diagram of a structure of a dual-gate array substrate provided in the present invention is mainly provided with: a plurality of gate lines 21 arranged along a first direction, along a second direction
  • the plurality of main signal lines 22 and the sub-signal lines 23 are alternately arranged, and the gate lines 21 are insulated and overlapped with the main signal lines 22 and the sub-signal lines 23, respectively, to form a plurality of pixel units 24 adjacent to the main signal lines 22.
  • the pixel units 24 are respectively connected to the main signal line 22, which is connected as a data line to a driving unit (not shown), and the sub-signal line 23 is connected to the common electrode 25.
  • the array substrate mainly includes a base substrate 26, a first insulating layer 27, and a first patterned pixel electrode 28 alternately disposed adjacent to the pixel electrode.
  • the main signal line 22 and the sub-signal line 23 between 28 cover the pixel electrode 28 and the main signal line 22, the second insulating layer 29 of the sub-signal line 23, and the common electrode 25 located above the second insulating layer 29, wherein
  • the sub-signal line 23 can be electrically connected to the common electrode 25 through the via hole, or can be connected to other existing methods.
  • the common electrode 25 includes a plurality of dry electrodes 251 and a plurality of branch electrodes, and the orthographic projections of the dry electrodes 251 on the dual gate array substrate overlap with the orthographic projections of adjacent pixel electrodes 28 on the dual gate array substrate, respectively.
  • the present invention alternately sets the main signal line and the sub-signal line at the gap positions between the adjacent pixel electrodes.
  • the main signal line is still led out by the driving unit, and is connected to the source of the TFT device in the pixel unit on both sides at the corresponding position, thereby realizing the purpose of driving one main signal line to control two pixel units; and because the main signal line is connected It is a varying voltage signal that necessarily produces a coupling capacitance with an adjacent pixel electrode.
  • a dry electrode is disposed above the main signal line to cover the occlusion coupling capacitor; at the same time, the sub-signal line is connected to the common electrode, so that the voltage of the sub-signal line is a relatively stable voltage, completely avoiding the phase
  • the neighboring pixel electrode creates the possibility of coupling capacitance. Therefore, the present invention does not need to reduce the coupling capacitance in a manner that increases the size of the dry electrode in the prior art, that is, the dry electrode located above the sub-signal line may not necessarily be set large, thereby increasing the aperture ratio of the array substrate.
  • the main signal line involved is a data line.
  • the line width of the sub signal line is not greater than the line width of the main signal line, thereby reducing the size of the black matrix corresponding to the color film substrate side, thereby improving the opening of the dual gate array substrate. rate.
  • the present invention describes the technical solutions of the present invention in the following specific examples. It should be noted that the present invention mainly describes the structure of the dual-gate array substrate corresponding to the two display modes of Fringe Field Switching (FFS) and Advanced Fringe Field Switching (AFFS), wherein The common electrode pattern corresponding to one pixel unit in the array substrate corresponding to the FFS display mode is as shown in FIG. 3( a ), and the common electrode pattern corresponding to one pixel unit in the array substrate corresponding to the AFFS display mode is as shown in FIG. 3( b ). The difference between the two structures is mainly because the patterns of the common electrodes are different.
  • FFS Fringe Field Switching
  • AFFS Advanced Fringe Field Switching
  • the dry electrodes 31 and the branch electrodes 32 of the dual-gate array substrate corresponding to the FFS display mode are arranged in parallel, and they extend almost along the direction of the data lines, generally in the figure.
  • the "Z" shape is arranged; and the dry electrode 33 and the branch electrode 34 are arranged substantially vertically in the array substrate corresponding to the AFFS display mode, the dry electrode 33 is arranged along the extending direction of the data line, and the branch electrode 34 is arranged in a "V" shape. Between adjacent dry electrodes.
  • FIG. 4(a) a schematic structural diagram of an array substrate of an FFS display mode according to an embodiment of the present invention, wherein any two adjacent dry electrodes 411 and the two dry electrodes 411 of the common electrode 41 are shown.
  • the common electricity formed by the branch electrode 412 The pole pattern corresponds to one pixel unit P; in combination with the cross-sectional structure diagram of FIG.
  • the orthographic projection of the first dry electrode 411 (the left dry electrode in the figure) on the dual gate array substrate and the adjacent pixel respectively
  • the orthographic projection of the electrode 42 on the dual gate array substrate has an overlap region (dashed oval frame in the drawing) and at least covers the main signal line 43, and a second dry electrode 411 adjacent to the first dry electrode 411 (illustration
  • the orthographic projection of the dry electrode in the middle right side on the dual gate array substrate is located in the gap between the adjacent pixel electrodes 42 and covers the sub signal line 44.
  • the dual gate array substrate further includes other related film layers such as an insulating layer, which are not shown for convenience of description.
  • the coupling capacitance of the sub-signal line and the adjacent pixel electrode is avoided, and the orthographic projection of the dry electrode above the sub-signal line on the dual-gate array substrate is avoided. It is defined in a gap between adjacent pixel electrodes and covers the sub-signal line, so that a stable capacitance generated between the sub-signal line and the adjacent pixel electrode can be superimposed with a capacitance generated by the pixel electrode and the common electrode to become the double gate.
  • first and second do not mean order, importance, etc., but merely describe the names of two different dry electrodes.
  • the orthographic projections of the first dry electrodes on the array substrate respectively overlap the orthographic projections of adjacent pixel electrodes on the dual gate array substrate and cover at least the main a signal line, wherein the second dry electrode is adjacent to the first dry electrode, and an orthographic projection of the second dry electrode on the dual gate array substrate is located in a gap between adjacent pixel electrodes and covers the sub signal line .
  • the orthographic projection on the array substrate adjacent to the second dry electrode (the right dry electrode in the drawing) adjacent to the first dry electrode coincides with the sub-signal line.
  • the electric field required to rotate the liquid crystal required in the present invention is the fringe field between the pixel electrode and the common electrode, and therefore, in order to allow the fringe field between the pixel electrode and the common electrode to be between the pixel electrode and the sub-signal line
  • the fringe field is well superimposed, and the fringe field between the pixel electrode and the sub-signal line does not affect the fringe field between the pixel electrode and the common electrode, and preferably the dry electrode of the common electrode is on the double-gate array substrate.
  • the projection coincides with the sub-signal line. In this way, the superimposed fringe field can be optimally increased, and the rotation of the liquid crystal at the interface between the pixel electrode and the common electrode is improved, thereby increasing the transmittance of the panel.
  • FIG. 5(a) a schematic structural diagram of an array substrate of the AFFS display mode in the second embodiment, wherein the dry electrode 511 of the common electrode 51 is disposed along the extending direction of the main signal line 53, and the branch electrode 512 is along the main signal line.
  • the lateral direction of the 53 is arranged, or the branch electrode 512 can be considered to be disposed in a direction crossing the main signal line 53, and the common electrode formed by the branch electrode 512 between the two adjacent dry electrodes 511 and the two dry electrodes 511
  • the pattern corresponds to two adjacent pixel units Q; in combination with the cross-sectional view at section AA shown in FIG.
  • the two dry electrodes 511 are at the double gate
  • the orthographic projections on the array substrate respectively overlap the adjacent projections of the adjacent pixel electrodes 52 on the dual gate array substrate and cover at least the main signal line 53, and the junction of the support electrodes 512 between adjacent pixel units Q
  • the pattern is continuous. Based on the above scheme, after the sub-signal line 54 is connected to the common electrode, the sub-signal line is prevented from generating a coupling capacitance with the adjacent pixel electrode, and further, in the display mode, the direction of the electric field required for the rotation of the liquid crystal is superimposed on the boundary. The direction of the electric field is different.
  • the dry electrode above the sub-signal line can be removed, and at the same time, the size of the pixel electrode adjacent to the sub-signal line is increased, so that the overlapping area of the branch electrode and the pixel electrode is more (see FIG. 5).
  • the cross-sectional view shown since the increase of the overlap region increases the electric field required for the rotation of the liquid crystal, it is more important that the increased overlap region is located at the boundary between the pixel electrode and the sub-signal line. Therefore, the liquid crystal at the junction can be caused to rotate, thereby increasing the transmittance of the panel.
  • the branch electrode 512 is provided with a corner structure 55 at the boundary between adjacent pixel units Q. Since the signal lines are disposed between adjacent pixel units, the black matrix is required to be blocked, and thus display defects due to touch are apt to occur in the areas where the signal lines are located. Therefore, the present invention provides a corner structure at the boundary between adjacent pixel units, which can improve such display defects, thereby alleviating display unevenness caused by movement or pressing of the touch process.
  • the material of the sub signal line is metal or transparent oxide.
  • the sub signal line is made of indium tin oxide.
  • the embodiment of the present invention further provides a display device, including a color filter substrate, and the double gate array substrate according to any one of the embodiments of the present invention.
  • a black matrix is disposed at a position corresponding to the side signal line of the double gate array substrate side in the color filter substrate, wherein the orthographic projection and the sub signal line of the black matrix on the dual gate array substrate are The orthographic projections on the array substrate coincide.
  • the display device of the present invention may be any product or component having a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.

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Abstract

一种双栅极阵列基板及显示装置，用以解决现有技术中存在的双栅极阵列基板的透过率较低的问题。该双栅极阵列基板及显示装置中，在各个相邻像素电极（11）之间的空隙位置交替设置主信号线（43）和副信号线（44），主信号线（43）作为数据线仍由驱动单元引出，并同时连接两侧像素单元（24）以实现一条主信号线（43）驱动控制两个像素单元（24）的目的；副信号线（44）连接至公共电极（41），从而，使得副信号线（44）的电压为较为稳定的电压，完全避免了与相邻像素电极（11）产生耦合电容的可能。从而，无需按照现有技术中增大干电极尺寸的方式减小耦合电容，即位于副信号线（44）上方的干电极（251）可以不必设置的很大，进而，提升了阵列基板的透过率。

Description

一种双栅极阵列基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种双栅极阵列基板及显示装置。
背景技术
随着显示面板的分辨率的增加，驱动IC的性能及成本必然提升。因此，为了降低驱动IC成本，同时提升驱动IC的绑定良率，在显示面板上一般采用双栅极驱动的设计方案。如图1(a)和图1(b)所示，为目前常见的双栅极驱动的阵列基板示意图，为了便于描述，以边缘场开关(FFS)显示模式为例，将像素单元分别定义为像素单元A，以及与像素单元A在水平方向上相邻的像素单元B；如图1(a)所示，两个像素单元的TFT器件分别位于像素单元的上、下方，且均通过各自的源极连接至同一数据线LS，TFT器件的栅极连接至栅线LG，由图中可见，竖直方向相邻的像素单元之间设置有两条栅线LG，便于实现双栅极驱动。结合图1(b)所示的剖面结构可知，该阵列基板中，相邻的像素单元A与像素单元B均连接至两者之间的数据线LS，且像素单元B与另外一个相邻的像素单元A之间没有设置数据线。由上述图1(a)以及图1(b)可知，无论在相邻两个像素电极11之间是否设置有数据线LS，都会产生不需要的耦合电容，因而，为了减小相邻像素电极之间产生的耦合电容，需要在该位置处(如图中虚线对应区域)的公共电极12的干电极121设置的较大，最好能够使得该位置处的公共电极的干电极121在阵列基板上的正投影能够分别与相邻的像素电极11有交叠，从而很好的阻挡住耦合电容对液晶旋转的影响。
然而，双栅极阵列基板由于在相邻像素单元之间设置有两条栅线，相比现有技术而言，增加了一条栅线，必然需要在彩膜基板侧对应的设置额外的黑矩阵，从而导致阵列基板形成的面板的开口率减小，换言之，阵列基板的穿透率降低。而且，为了减小耦合电容，导致相邻像素单元之间的空隙处的公共电极 的面积较大，这一结构同样会导致阵列基板的开口率减小，穿透率降低。
发明内容
本发明实施例提供一种双栅极阵列基板及显示装置，可以提高现有技术中双栅极阵列基板的透过率。
本发明实施例采用以下技术方案：
一种双栅极阵列基板，包括：
沿第一方向排布的多条栅线；
沿第二方向交替排布的多条主信号线和副信号线；
所述相邻两条栅线与所述主信号线或所述副信号线绝缘交叠围设而成多个像素单元，所述主信号线由驱动单元引出，并分别与自身相邻的像素单元连接；
所述副信号线连接至公共电极，其中，所述公共电极包括多个干电极和多个支电极，且所述干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线。
在本发明实施例中，通过在双栅极阵列基板中设置交替排布的主信号线以及副信号线，并将副信号线连接至公共电极，从而，使得副信号线连通的电压为较稳定的电压，完全避免了与相邻像素电极产生耦合电容的可能。因此，本发明无需按照现有技术中增大干电极尺寸的方式减小耦合电容，即位于副信号线上方的干电极可以不必设置的很大，进而，提升了阵列基板的开口率。
在本发明的一个实施例中，所述副信号线的线宽不大于所述主信号线的线宽。
在本发明实施例中，副信号线的线宽不大于主信号线的线宽，从而，可以减小彩膜基板侧对应的黑矩阵的尺寸，进而提升该双栅极阵列基板的开口率。
在本发明的一个实施例中，所述公共电极中干电极沿所述主信号线延伸方向设置，所述支电极平行于所述干电极，任意相邻的两个干电极与该两个干电 极之间的支电极所构成的公共电极图案对应一个像素单元；
其中第一干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线，与所述其中第一干电极相邻的第二干电极在所述双栅极阵列基板上的正投影位于相邻像素电极之间的空隙内且覆盖所述副信号线。
通过将副信号线上方的干电极在双栅极阵列基板上的正投影限定在位于相邻像素电极之间的空隙内且覆盖副信号线，使得副信号线与相邻像素电极之间产生的稳定的电容能够与像素电极与公共电极产生的电容叠加，成为该双栅极阵列基板所需的存储电容，从而，能够更好的控制像素电极与公共电极交界处的电压。另外，由于该FFS显示模式的结构中，液晶旋转所需的电场方向与交界处叠加的电场方向相同，且比较稳定，因此，该叠加后的存储电容产生的电场能够促进该交界处的液晶的旋转，进而，提升面板的透过率。
在本发明的一个实施例中，与所述其中第一干电极相邻的第二干电极在所述阵列基板上的正投影与所述副信号线重合。
能够使得叠加的边缘场达到最佳值，提升像素电极与公共电极的交界处的液晶的旋转，进而提升面板的透过率。
在本发明的一个实施例中，所述公共电极中干电极沿所述主信号线延伸方向设置，所述支电极沿与所述主信号线交叉的方向设置，任意相邻的两个干电极与该两个干电极之间的支电极所构成的公共电极图案对应相邻的两个像素单元；
其中，两个干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线，所述支电极在相邻的像素单元之间的交界处图案连续。
在该技术方案中，液晶旋转所需的电场方向与交界处叠加的电场方向不同，因此，可以去掉副信号线上方的干电极，同时，增大与副信号线相邻的像素电极的尺寸，从而，使得支电极与像素电极的交叠区域更多，而且，由于该 交叠区域的增加会增大液晶旋转所需的电场，更为关键的是，增加的交叠区域位于像素电极与副信号线的交界处，因此，可以促使该交界处的液晶旋转，从而，提升面板的透过率。
在本发明的一个实施例中，所述支电极在相邻的像素单元之间的交界处设置有拐角结构。
通过该技术方案，缓解了触摸过程的移动或按压导致的显示不均现象。
在本发明的一个实施例中，所述副信号线的材质为金属或透明氧化物。
在本发明的一个实施例中，所述副信号线的材质为铟锡氧化物。
一种显示装置，包括彩膜基板，还包括所述的双栅极阵列基板。
在本发明的一个实施例中，所述彩膜基板中与所述阵列基板侧副信号线对应的位置设置有黑矩阵，其中，所述黑矩阵在所述阵列基板上的正投影与所述副信号线在所述阵列基板上的正投影重合。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1(a)和图1(b)为目前常见的双栅极驱动的阵列基板示意图；
图2(a)和图2(b)为本发明提供的一种双栅极阵列基板的结构示意图；
图3(a)为FFS显示模式对应的阵列基板中像素单元图案的示意图；
图3(b)为FFS显示模式对应的阵列基板中像素单元图案的示意图；
图4(a)为本实例1中FFS显示模式的阵列基板的结构简图；
图4(b)为本发明实例1中FFS显示模式的阵列基板的剖视图；
图5(a)为本发明实例2中AFFS显示模式的阵列基板的结构简图；
图5(b)和图5(c)分别为本发明实例2中AFFS显示模式的阵列基板 中截面A-A以及截面B-B的剖视图；
图6为本发明实例2中公共电极的支电极设置有拐角结构的示意图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
下面通过具体的实施例对本发明所涉及的技术方案进行详细描述，本发明包括但并不限于以下实施例。
如图2(a)所示，为本发明提供的一种双栅极阵列基板的结构示意图，该阵列基板中主要设置有：沿第一方向排布的多条栅线21，沿第二方向交替排布的多条主信号线22和副信号线23，栅线21分别与主信号线22和副信号线23绝缘交叠围设而成多个像素单元24，与主信号线22相邻的像素单元24分别连接至主信号线22，主信号线22作为数据线连接至驱动单元(未示出)，副信号线23连接至公共电极25。图中仅为示出其连接关系，具体的膜层图案结构并未真实示出。结合图2(b)所示的针对b-b截面的剖视图可知，该阵列基板主要包括：衬底基板26，第一绝缘层27，第一图案化的像素电极28，交替设置在相邻的像素电极28之间的主信号线22以及副信号线23，覆盖像素电极28以及主信号线22、副信号线23的第二绝缘层29，以及位于第二绝缘层29之上的公共电极25，其中，副信号线23可通过过孔与公共电极25建立电连接，也可以通过其他现有方式。公共电极25包括多个干电极251和多个支电极，且干电极251在双栅极阵列基板上的正投影分别与相邻的像素电极28在双栅极阵列基板上的正投影有交叠区域且至少覆盖主信号线22。
由上述方案可知，为了对已有的双栅极阵列基板进行改进，提升其透过率，本发明在各个相邻像素电极之间的空隙位置交替设置主信号线和副信号线，其 中，主信号线仍由驱动单元引出，并在相应位置与两侧像素单元内的TFT器件源极连接，实现一条主信号线驱动控制两个像素单元的目的；而由于该主信号线连通的是变化的电压信号，必然与相邻的像素电极产生耦合电容。根据本发明的实施例，在该主信号线上方设置一干电极以覆盖遮挡耦合电容；同时，副信号线连接至公共电极，从而使得副信号线的电压为较为稳定的电压，完全避免了与相邻像素电极产生耦合电容的可能。因此，本发明无需按照现有技术中增大干电极尺寸的方式减小耦合电容，即位于副信号线上方的干电极可以不必设置的很大，进而，提升了阵列基板的开口率。
在本发明实施例中，所涉及的主信号线为数据线。
进一步，在本发明实施例中，副信号线的线宽不大于主信号线的线宽，从而，可以减小彩膜基板侧对应的黑矩阵的尺寸，进而提升该双栅极阵列基板的开口率。
为了更好的对上述方案进行描述，本发明以下述几个具体的实例对本发明的技术方案进行说明。需要解释的是，本发明主要针对边缘场开关技术(Fringe Field Switching，FFS)以及超级边缘电场转换(Advanced Fringe Field Switching，AFFS)两种显示模式对应的双栅极阵列基板的结构进行说明，其中，FFS显示模式对应的阵列基板中一个像素单元对应的公共电极图案如图3(a)所示，AFFS显示模式对应的阵列基板中一个像素单元对应的公共电极图案如图3(b)所示，两者结构的区别主要在于公共电极的图案不同，FFS显示模式对应的双栅极阵列基板中干电极31与支电极32平行设置，它们几乎沿着数据线的方向延伸，一般呈图示中的“之”字形排布；而AFFS显示模式对应的阵列基板中干电极33与支电极34近乎垂直设置，干电极33沿着数据线延伸方向设置，支电极34则呈“V”字形排布在相邻干电极之间。
下面结合图4描述本发明的一个实施例。如图4(a)所示，为本发明的一个实施例的FFS显示模式的阵列基板的结构简图，其中，公共电极41中任意相邻的两个干电极411与该两个干电极411之间的支电极412所构成的公共电 极图案对应一个像素单元P；结合图4(b)的剖面结构图，其中第一干电极411(图示中左边的干电极)在双栅极阵列基板上的正投影分别与相邻的像素电极42在双栅极阵列基板上的正投影有交叠区域(图示中虚线椭圆框)且至少覆盖主信号线43，与其中第一干电极411相邻的第二干电极411(图示中右边的干电极)在双栅极阵列基板上的正投影位于相邻像素电极42之间的空隙内且覆盖副信号线44。另外，该双栅极阵列基板还包括绝缘层等其他相关膜层，为了便于描述，并未示出。基于上述方案，在将副信号线连接至公共电极之后，避免了副信号线与相邻像素电极产生耦合电容，而且，通过将副信号线上方的干电极在双栅极阵列基板上的正投影限定在位于相邻像素电极之间的空隙内且覆盖副信号线，使得副信号线与相邻像素电极之间产生的稳定的电容能够与像素电极与公共电极产生的电容叠加，成为该双栅极阵列基板所需的存储电容，从而，能够更好的控制像素电极与公共电极交界处的电压。另外，由于该FFS显示模式的结构中液晶旋转所需的电场方向与交界处叠加的电场方向相同，且比较稳定，因此，该叠加后的存储电容产生的电场能够促进该交界处的液晶的旋转，进而，提升面板的透过率。在此，要说明的是，“第一”和“第二”并不代表次序、重要性等意义，而仅为了说明两个不同的干电极的名称。例如，在本实施例中，第一干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线，而第二干电极与第一干电极相邻，并且第二干电极在所述双栅极阵列基板上的正投影位于相邻像素电极之间的空隙内且覆盖所述副信号线。
进一步，基于上述实施例，与其中第一干电极相邻的第二干电极(图示中右边的干电极)在阵列基板上的正投影与副信号线重合。考虑本发明中所需的能够使得液晶旋转的电场为像素电极与公共电极之间的边缘场，因此，为了让像素电极与公共电极之间的边缘场能够与像素电极与副信号线之间的边缘场很好的叠加，且不致于像素电极与副信号线之间的边缘场对像素电极与公共电极之间的边缘场造成影响，优选以公共电极的干电极在双栅极阵列基板上的正 投影与副信号线重合为佳。这样，能够使得叠加的边缘场达到最佳值，提升像素电极与公共电极的交界处的液晶的旋转，进而提升面板的透过率。
下面结合图5还描述本发明的第一实施例。如图5(a)所示，为本实例2中AFFS显示模式的阵列基板的结构简图，其中，公共电极51中干电极511沿主信号线53延伸方向设置，支电极512沿主信号线53的横向方向布置，或者可以认为支电极512沿与主信号线53交叉的方向设置，任意相邻的两个干电极511与该两个干电极511之间的支电极512所构成的公共电极图案对应相邻的两个像素单元Q；结合图5(b)所示的截面A-A处的剖视图，以及图5(c)所示的截面B-B处的剖视图，两个干电极511在双栅极阵列基板上的正投影分别与相邻的像素电极52在双栅极阵列基板上的正投影有交叠区域且至少覆盖主信号线53，支电极512在相邻的像素单元Q之间的交界处图案连续。基于上述方案，在将副信号线54连接至公共电极之后，避免了副信号线与相邻像素电极产生耦合电容，而且，在该显示模式中，液晶旋转所需的电场方向与交界处叠加的电场方向不同，因此，可以去掉副信号线上方的干电极，同时，增大与副信号线相邻的像素电极的尺寸，从而，使得支电极与像素电极的交叠区域更多(参见图5(c)所示的剖视图)，而且，由于该交叠区域的增加会增大液晶旋转所需的电场，更为关键的是，增加的交叠区域位于像素电极与副信号线的交界处，因此，可以促使该交界处的液晶旋转，从而，提升面板的透过率。
进一步，基于上述实例2的方案，参见图6所示，支电极512在相邻的像素单元Q之间的交界处设置有拐角结构55。由于相邻像素单元之间设置有信号线，需要黑矩阵进行阻挡，因此，在这些信号线所在区域容易发生由于触摸而导致的显示缺陷。因此，本发明在相邻的像素单元之间的交界处设置拐角结构，可以改善这种显示缺陷，从而，缓解了触摸过程的移动或按压导致的显示不均现象。
优选地，在本发明实施例中，副信号线的材质为金属或透明氧化物。
一种可行的实施例，为了提升双栅极阵列基板的透过率，副信号线的材质为铟锡氧化物。
此外，本发明实施例还提供了一种显示装置，包括彩膜基板，以及本发明实施例提供的任意一种所述的双栅极阵列基板。
在本发明的一个实施例中，彩膜基板中与双栅极阵列基板侧副信号线对应的位置设置有黑矩阵，其中，黑矩阵在双栅极阵列基板上的正投影与副信号线在阵列基板上的正投影重合。
本发明所述的显示装置可以为液晶面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (11)

  1. 一种双栅极阵列基板，其特征在于，包括：
    沿第一方向排布的多条栅线；
    沿第二方向交替排布的多条主信号线和副信号线；
    所述相邻两条栅线与所述主信号线或所述副信号线绝缘交叠围设而成多个像素单元，所述主信号线由驱动单元引出，并分别与自身相邻的像素单元连接；
    所述副信号线连接至公共电极，其中，所述公共电极包括多个干电极和多个支电极，且所述干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线。
  2. 如权利要求1所述的双栅极阵列基板，其特征在于，所述副信号线的线宽不大于所述主信号线的线宽。
  3. 如权利要求1或2所述的双栅极阵列基板，其特征在于，所述公共电极中干电极沿所述主信号线延伸方向设置，所述支电极平行于所述干电极，任意相邻的两个干电极与该两个干电极之间的支电极所构成的公共电极图案对应一个像素单元；
    其中第一干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线，与所述其中第一干电极相邻的第二干电极在所述双栅极阵列基板上的正投影位于相邻像素电极之间的空隙内且覆盖所述副信号线。
  4. 如权利要求3所述的双栅极阵列基板，其特征在于，与所述其中第一干电极相邻的第二干电极在所述阵列基板上的正投影与所述副信号线重合。
  5. 如权利要求1或2所述的双栅极阵列基板，其特征在于，所述公共电极中干电极沿所述主信号线延伸方向设置，所述支电极沿与所述主信号线交叉的方向设置，任意相邻的两个干电极与该两个干电极之间的支电极所构成的公共电极图案对应相邻的两个像素单元；
    其中，两个干电极在所述阵列基板上的正投影分别与相邻的像素电极在所述双栅极阵列基板上的正投影有交叠区域且至少覆盖所述主信号线，所述支电极在相邻的像素单元之间的交界处图案连续。
  6. 如权利要求5所述的双栅极阵列基板，其特征在于，所述支电极在相邻的像素单元之间的交界处设置有拐角结构。
  7. 如权利要求1、2、4、6任一项所述的双栅极阵列基板，其特征在于，所述副信号线的材质为金属或透明氧化物。
  8. 如权利要求7所述的双栅极阵列基板，其特征在于，所述副信号线的材质为铟锡氧化物。
  9. 如权利要求1所述的双栅极阵列基板，其特征在于，主信号线是数据线。
  10. 一种显示装置，包括彩膜基板，其特征在于，还包括：权利要求1-9任一项所述的双栅极阵列基板。
  11. 如权利要求10所述的显示装置，其特征在于，所述彩膜基板中与所述阵列基板侧副信号线对应的位置设置有黑矩阵，其中，所述黑矩阵在所述阵列基板上的正投影与所述副信号线在所述阵列基板上的正投影重合。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107436521A (zh) * 2017-09-29 2017-12-05 深圳市华星光电技术有限公司 阵列基板及其像素的制作方法、液晶面板

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11906864B2 (en) 2016-02-02 2024-02-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Dual-gate array substrate and display device
US11442318B2 (en) 2016-02-02 2022-09-13 Chengdu Boe Optoelectronics Technology Co., Ltd. Dual-gate array substrate and display device
CN106154667A (zh) * 2016-09-09 2016-11-23 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN106371256A (zh) * 2016-11-30 2017-02-01 京东方科技集团股份有限公司 像素结构、显示面板及显示装置
CN109283758B (zh) * 2017-07-21 2021-09-28 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN107403810B (zh) 2017-07-21 2022-01-18 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN107611146B (zh) * 2017-09-29 2024-01-23 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN207380420U (zh) * 2017-11-17 2018-05-18 京东方科技集团股份有限公司 一种阵列基板及显示装置
JP6968710B2 (ja) * 2018-01-11 2021-11-17 株式会社ジャパンディスプレイ 表示装置
CN108363253B (zh) * 2018-02-09 2020-12-22 京东方科技集团股份有限公司 阵列基板及其驱动方法和制造方法
CN109239994A (zh) * 2018-10-25 2019-01-18 京东方科技集团股份有限公司 阵列基板及显示装置
CN112394578B (zh) * 2019-08-16 2023-06-27 京东方科技集团股份有限公司 阵列基板、显示面板及其驱动方法
CN112684645B (zh) * 2019-10-18 2023-02-03 京东方科技集团股份有限公司 双栅极阵列基板及显示装置
CN211718666U (zh) * 2020-01-02 2020-10-20 京东方科技集团股份有限公司 一种基板及显示装置
US11294248B2 (en) 2020-03-31 2022-04-05 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device
CN111258144A (zh) * 2020-03-31 2020-06-09 深圳市华星光电半导体显示技术有限公司 显示面板、显示装置
CN111338144B (zh) * 2020-04-14 2023-08-18 京东方科技集团股份有限公司 显示面板及显示装置
CN113805392A (zh) * 2020-06-12 2021-12-17 京东方科技集团股份有限公司 显示基板、显示面板及显示基板的制作方法
CN112925142A (zh) * 2021-03-16 2021-06-08 京东方科技集团股份有限公司 一种基板和显示装置
CN116324606B (zh) * 2021-04-27 2024-07-23 京东方科技集团股份有限公司 一种显示基板、液晶显示面板及显示装置
CN115373186A (zh) * 2021-05-21 2022-11-22 北京京东方显示技术有限公司 一种显示面板及显示装置
WO2023028883A1 (zh) 2021-08-31 2023-03-09 京东方科技集团股份有限公司 显示基板及显示面板
CN114994989B (zh) 2022-05-25 2023-10-27 京东方科技集团股份有限公司 阵列基板及显示装置
CN120112844A (zh) * 2023-09-25 2025-06-06 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946058A (en) * 1995-07-24 1999-08-31 Fujitsu Limited Transistor matrix device including features for minimizing the effect of parasitic capacitances
CN1794067A (zh) * 2004-12-24 2006-06-28 三星电子株式会社 液晶显示器以及用于该液晶显示器的面板
CN102998859A (zh) * 2012-12-14 2013-03-27 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN103926770A (zh) * 2013-01-10 2014-07-16 三星显示有限公司 薄膜晶体管阵列面板及其制造方法
CN103941488A (zh) * 2013-11-01 2014-07-23 上海中航光电子有限公司 一种边缘场型液晶显示装置、阵列基板及其制造方法
CN103984162A (zh) * 2013-02-12 2014-08-13 三星显示有限公司 液晶显示器
CN104714345A (zh) * 2015-04-08 2015-06-17 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板、液晶显示面板及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100209281B1 (ko) * 1996-10-16 1999-07-15 김영환 액정 표시 소자 및 그 제조방법
US8035765B2 (en) * 2006-11-13 2011-10-11 Hannstar Display Corp. TFT array substrate, LCD panel and liquid crystal display
KR101473839B1 (ko) * 2007-10-17 2014-12-18 엘지디스플레이 주식회사 횡전계방식 액정표시장치 및 그 제조방법
CN101661174B (zh) * 2008-08-29 2011-04-27 群康科技(深圳)有限公司 液晶显示面板及其制造方法
JP5390337B2 (ja) * 2009-10-26 2014-01-15 株式会社東芝 半導体記憶装置
KR20140044453A (ko) * 2012-10-05 2014-04-15 삼성디스플레이 주식회사 표시 기판 및 이를 포함하는 액정 표시 패널
CN102955637B (zh) * 2012-11-02 2015-09-09 北京京东方光电科技有限公司 一种电容式内嵌触摸屏、其驱动方法及显示装置
CN203941365U (zh) * 2014-07-09 2014-11-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN105159001B (zh) * 2015-10-20 2018-06-12 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板以及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946058A (en) * 1995-07-24 1999-08-31 Fujitsu Limited Transistor matrix device including features for minimizing the effect of parasitic capacitances
CN1794067A (zh) * 2004-12-24 2006-06-28 三星电子株式会社 液晶显示器以及用于该液晶显示器的面板
CN102998859A (zh) * 2012-12-14 2013-03-27 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN103926770A (zh) * 2013-01-10 2014-07-16 三星显示有限公司 薄膜晶体管阵列面板及其制造方法
CN103984162A (zh) * 2013-02-12 2014-08-13 三星显示有限公司 液晶显示器
CN103941488A (zh) * 2013-11-01 2014-07-23 上海中航光电子有限公司 一种边缘场型液晶显示装置、阵列基板及其制造方法
CN104714345A (zh) * 2015-04-08 2015-06-17 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板、液晶显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107436521A (zh) * 2017-09-29 2017-12-05 深圳市华星光电技术有限公司 阵列基板及其像素的制作方法、液晶面板

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