WO2017128633A1 - 制造薄膜晶体管的方法 - Google Patents

制造薄膜晶体管的方法 Download PDF

Info

Publication number
WO2017128633A1
WO2017128633A1 PCT/CN2016/089760 CN2016089760W WO2017128633A1 WO 2017128633 A1 WO2017128633 A1 WO 2017128633A1 CN 2016089760 W CN2016089760 W CN 2016089760W WO 2017128633 A1 WO2017128633 A1 WO 2017128633A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate insulating
insulating layer
layer
gate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/089760
Other languages
English (en)
French (fr)
Inventor
蔡良毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/119,718 priority Critical patent/US20180068855A1/en
Publication of WO2017128633A1 publication Critical patent/WO2017128633A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/687—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having cavities, e.g. porous gate dielectrics having gasses therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Definitions

  • the invention belongs to the field of thin film transistors, and in particular to a method for manufacturing a thin film transistor.
  • TFT-LCD Color Thin Film Transistor Liquid Crystal Display
  • the main application areas are laptops, desktop monitors, workstations, industrial monitors, global positioning systems (GPS), personal data processing, game consoles, video phones, portable VCDs, DVDs and other portable devices.
  • GPS global positioning systems
  • TFT-LCD has rapidly grown into a mainstream display.
  • the working principle of the TFT-LCD is to control the switching of each pixel by the change of the voltage, and precisely control the color and brightness of each pixel to obtain the desired picture.
  • the mainstream TFT-LCD on the market now requires a large driving voltage (generally a driving voltage greater than 10V) for proper operation and requires a sufficient current switching ratio. Large operating voltages result in high power consumption and large parasitic capacitance, which is not conducive to the design of portable electronic products.
  • Chinese Patent Application Publication No. CN103762178A discloses a method of fabricating a low temperature polysilicon thin film transistor, the method comprising forming a composite gate insulating layer by a plurality of PECVD processes, wherein the gate insulating layer comprises SiO 2 .
  • the method in the process is complicated and the manufacturing cost is increased.
  • An object of the present invention is to overcome the above-mentioned deficiencies of the prior art and to provide a method of manufacturing a TFT which can reduce the operating voltage of a TFT-LCD and reduce parasitic capacitance. This method can improve the operating voltage of the TFT, thereby improving the quality of the TFT product and reducing power consumption.
  • a method of fabricating a thin film transistor may include the steps of: disposing a substrate, disposing a gate on the substrate, and providing a gate insulating layer on the gate at the gate a semiconductor layer is disposed on the insulating layer, a source and a drain are respectively disposed on the semiconductor layer, a passivation layer is disposed on the source and the drain, and a pixel electrode is disposed on the passivation layer, wherein the gate insulating layer is porous The formation of SiO 2 .
  • the step of forming the gate insulating layer may include depositing porous SiO 2 as a gate insulating layer on the gate electrode with SiH 4 and O 2 as reaction gases.
  • porous SiO 2 may be deposited by a plasma enhanced chemical vapor deposition method.
  • the thickness of the gate insulating layer may be
  • the forming of the semiconductor layer may include: providing a photoresist layer on the gate insulating layer to cover a majority of the surface of the gate insulating layer, and making the gate insulating layer correspond to the gate electrode Area exposure; the exposed regions of the gate insulating layer are treated with H 3 PO 4 to allow -PO 3 H 2 to enter the porous SiO 2 of the gate insulating layer; exposure on the photoresist layer and the gate insulating layer A semiconductor oxide is deposited on the portion, and then the photoresist layer and the semiconductor oxide deposited on the photoresist layer are stripped to form a semiconductor layer.
  • a semiconductor oxide may be deposited on the exposed gate insulating layer and photoresist layer by a method of physical vapor deposition.
  • treating the gate insulating layer using H 3 PO 4 may include spraying and/or immersing the gate insulating layer using 60 wt% to 80 wt% of H 3 PO 4 .
  • the photoresist layer may be a positive photoresist layer.
  • the photoresist layer may have a thickness of 1 ⁇ m to 2 ⁇ m.
  • the semiconductor layer may include indium gallium zinc oxide.
  • the method of manufacturing a thin film transistor according to the present invention can improve the operating voltage of the TFT, thereby improving the quality of the TFT product and reducing power consumption.
  • FIG. 1 is a view schematically showing a step of manufacturing a gate in a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention
  • FIG. 2 is a view schematically showing a step of manufacturing a gate insulating layer in a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention
  • FIG. 3A to 3C are diagrams schematically showing sequentially a step of manufacturing a semiconductor layer in a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention, wherein FIG. 3A is a view schematically showing an exemplary according to the present invention.
  • the step of providing a photoresist layer on the gate insulating layer in the method of fabricating the thin film transistor of the embodiment and FIG. 3B is a schematic view showing the exposed gate in the method of manufacturing the thin film transistor according to an exemplary embodiment of the present invention a step of disposing a semiconductor oxide on the insulating layer and on the photoresist layer
  • FIG. 3C is a view schematically showing formation of an island-shaped semiconductor layer on the gate insulating layer in the method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention step;
  • FIG. 4 is a view schematically showing steps of forming a source, a drain, a passivation layer, and a pixel electrode layer on a semiconductor layer, respectively, in a method of fabricating a thin film transistor, according to an exemplary embodiment of the present invention.
  • the working principle of the TFT-LCD is to control the switching of each pixel by the change of the voltage, and precisely control the color and brightness of each pixel to obtain the desired picture.
  • the current mainstream TFT-LCDs on the market require a large driving voltage (generally a driving voltage greater than 10 V) for proper operation and a sufficient current switching ratio. Large operating voltages result in high power consumption and large parasitic capacitance, which is not conducive to the design of portable electronic products.
  • An exemplary embodiment of the present invention to be described below with reference to the accompanying drawings provides a method of manufacturing a thin film transistor which uses SiH4 and O2 as a reactive gas to deposit porous SiO2 as a gate insulating layer of a TFT by a PECVD method. Thereby the parasitic capacitance is effectively reduced and the power consumption is reduced.
  • FIG. 1 is a view schematically showing a step of manufacturing a gate electrode in a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.
  • FIG. 2 is a view schematically showing a step of manufacturing a gate insulating layer in a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.
  • 3A-3C are diagrams schematically illustrating a step of fabricating a semiconductor layer in a method of fabricating a thin film transistor according to an exemplary embodiment of the present invention, wherein FIG. 3A is a view schematically showing an exemplary embodiment according to the present invention. a step of disposing a photoresist layer on a gate insulating layer in a method of fabricating a thin film transistor, and FIG.
  • FIG. 3B is a view schematically showing an exposed gate insulating layer in a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention The step of providing a semiconductor oxide on the upper and photoresist layers
  • FIG. 3C is a view schematically showing a step of forming an island-shaped semiconductor layer on the gate insulating layer in the method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.
  • 4 is a view schematically showing steps of forming a source, a drain, a passivation layer, and a pixel electrode layer on a semiconductor layer, respectively, in a method of fabricating a thin film transistor, according to an exemplary embodiment of the present invention.
  • a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention will be fully described below with reference to FIGS. 1 through 4.
  • a method of fabricating a thin film transistor according to an exemplary embodiment of the present invention includes the following steps:
  • a substrate SU is provided, and a gate G is provided on the substrate.
  • the substrate SU may be a glass substrate or the like generally used in the art, but the present invention is not limited thereto.
  • the gate G may be formed on the substrate using a process such as etching. Further, in order to prevent metal particles from entering the substrate SU during etching, a buffer layer may be disposed between the substrate SU and the gate G.
  • a gate insulating layer is formed on the exposed portions of the gate G and the substrate SU.
  • the gate insulating layer GI is formed of porous SiO 2 .
  • Porous SiO 2 may be deposited on the exposed portions of the gate G and the substrate SU using plasma enhanced chemical vapor deposition (PECVD) to form a gate insulating layer G1 having a predetermined thickness.
  • PECVD plasma enhanced chemical vapor deposition
  • SiH 4 and O 2 may be used as the reaction gas at room temperature (e.g., 5 ° C to 35 ° C) during the deposition.
  • the thickness of the formed gate insulating layer GI may be approximately
  • the invention is not limited thereto.
  • a semiconductor layer SE is provided on the gate insulating layer GI as shown in FIGS. 3A to 3C.
  • the step of disposing the semiconductor layer SE may preferably include, but is not limited to, the following aspects:
  • a photoresist layer PR is provided on a portion of the gate insulating layer GI as shown in FIG. 3A.
  • a photoresist layer PR having a predetermined thickness for example, 1 ⁇ m - 2 ⁇ m, may be disposed on the gate insulating layer GI to cover most of the surface of the gate insulating layer GI and insulate the gate.
  • the area of the layer GI corresponding to the gate G is exposed to protect the metal lines.
  • the photoresist layer PR is disposed to expose a partial region of the gate insulating layer GI corresponding to the gate G, and cover other regions of the gate insulating layer GI.
  • a positive photoresist layer may be disposed on the gate insulating layer GI.
  • a high concentration for example, 60 wt% to 80 wt%) of H 3 PO 4 treatment (for example, shower treatment, immersion treatment, etc.) of the gate insulating layer GI may be used.
  • the exposed regions are for a predetermined period of time so that -PO 3 H 2 can enter the porous SiO 2 of the gate insulating layer GI.
  • a semiconductor oxide SO is deposited on the exposed portions of the photoresist layer PR and the gate insulating layer GI as shown in FIG. 3B.
  • a semiconductor oxide SO may be deposited on the exposed gate insulating layer GI and the photoresist layer PR by a method of physical vapor deposition (PVD).
  • the semiconductor oxide SO according to an exemplary embodiment of the present invention may be IGZO (Indium Gallium Zinc Oxide).
  • a peeling resist layer PR for example, a positive photoresist layer
  • a stripping liquid for example, a strip stripping solution
  • a semiconductor oxide for example, IGZO
  • a photoresist layer PR is not formed on a region of the gate insulating layer GI corresponding to the gate G, that is, a region of the gate insulating layer GI corresponding to the gate G and
  • the semiconductor layer SE is in direct contact, and therefore, after the photoresist layer PR is peeled off, the semiconductor layer SE located on the region of the gate insulating layer GI corresponding to the gate G is not peeled off and remains on the gate insulating layer GI.
  • an island-shaped IGZO semiconductor layer SE is formed after the photoresist layer PR and the semiconductor oxide SO deposited on the photoresist layer are peeled off.
  • a source S and the drain D may be sequentially disposed on the semiconductor layer SE in accordance with the prior art.
  • a source S and a drain D may be formed on the semiconductor layer SE using a film formation or masking method such that they are on the same layer and then at the source Forming a passivation layer PV on the drain S and the drain D, and forming a pixel electrode PE on the formed passivation layer, thereby fabricating a thin film transistor,
  • porous SiO 2 is used as the gate insulating layer, so that the TFT channel is electrically coupled with the TFT channel electrons to form a large electric double layer (EDL) capacitor. Further, after the gate insulating layer is formed by H 3 PO 4 of the porous SiO 2 is processed so that the proton conductive property SiO 2 porous with H 3 PO 4 after processing enhancements.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

提供一种制造薄膜晶体管的方法，该方法包括设置基底（SU）；在基底（SU）上设置栅极（G），在栅极（G）上设置栅极绝缘层（GI），在栅极绝缘层（GI）上设置半导体层（SE），在半导体层（SE）上分别设置源极（S）和漏极（D），在源极（S）和漏极（D）上设置钝化层（PV），在钝化层（PV）上设置像素电极（PE）。其中，该栅极绝缘层（GI）由多孔的SiO2形成。

Description

制造薄膜晶体管的方法 技术领域
本发明属于薄膜晶体管领域，具体地讲，涉及一种制造薄膜晶体管的方法。
背景技术
TFT－LCD(彩色薄膜晶体管液晶显示器)主要应用于计算机、视频终端、通讯及仪器仪表等行业。主要应用领域有笔记本电脑、台式计算机监视器、工作站、工业监视器、全球卫星定位系统(GPS)、个人数据处理、游戏机、可视电话、便携式VCD、DVD以及其它一些便携装置。经过不断的发展创新，TFT-LCD迅速成长为主流显示器.
TFT-LCD的工作原理是通过电压的变化控制每个像素的开关，精准地控制每个像素的颜色和亮度，从而得到需要的画面。
现市场上主流的TFT-LCD需要较大的驱动电压(一般驱动电压大于10V)才能正常的工作，并且需要足够的电流开关比。工作电压较大导致了高功耗和较大寄生电容，不利于便携式电子产品的设计。
公开号为CN103762178A的中国专利申请公开了一种低温多晶硅薄膜晶体管的制造方法，所述方法包括通过多次PECVD工序形成复合的栅极绝缘层，其中，所述栅极绝缘层包括SiO2。该中方法工序复杂，且制造成本增加。
发明内容
本发明的目的在于克服上述现有技术的不足，提供一种可以降低TFT-LCD的工作电压和减小寄生电容的制造TFT的方法。这种方法能够改善TFT的工作电压，从而提高TFT产品的质量，降低功耗。
根据本发明的示例性实施例，提供了一种制造薄膜晶体管的方法，所述方 法可以包括以下步骤：设置基底，在基底上设置栅极，在栅极上设置栅极绝缘层，在栅极绝缘层上设置半导体层，在半导体层上分别设置源极和漏极，在源极和漏极上设置钝化层，在钝化层上设置像素电极，其中，所述栅极绝缘层由多孔的SiO2形成。
根据本发明的示例性实施例，形成栅极绝缘层的步骤可以包括：以SiH4和O2作为反应气体在栅极上沉积多孔的SiO2作为栅极绝缘层。
根据本发明的示例性实施例，可以通过等离子体增强的化学气相沉积方法来沉积多孔的SiO2。
根据本发明的示例性实施例，所述栅极绝缘层的厚度可以为
Figure PCTCN2016089760-appb-000001
根据本发明的示例性实施例，形成半导体层的步骤可以包括：在栅极绝缘层上设置光阻层以覆盖栅极绝缘层的大部分表面，并使栅极绝缘层的与栅极对应的区域暴露；使用H3PO4处理栅极绝缘层的被暴露的区域，以使-PO3H2进入栅极绝缘层的多孔的SiO2中；在光阻层上以及栅极绝缘层的暴露的部分上沉积半导体氧化物，然后剥离光阻层以及沉积在光阻层上的半导体氧化物，从而形成半导体层。
根据本发明的示例性实施例，可以采用物理气相沉积的方法在暴露的栅极绝缘层和光阻层上沉积半导体氧化物。
根据本发明的示例性实施例，使用H3PO4处理栅极绝缘层可以包括使用60wt％～80wt％的H3PO4对栅极绝缘层进行喷淋和/或浸泡处理。
根据本发明的示例性实施例，光阻层可以为正性光阻层。
根据本发明的示例性实施例，光阻层的厚度可以为1μm-2μm。
根据本发明的示例性实施例，半导体层可以包括铟镓锌氧化物。
通过结合示例性实施例的本发明的以上描述，根据本发明的制造薄膜晶体管的方法能够改善TFT的工作电压，从而提高TFT产品的质量，降低功耗。
附图说明
通过结合附图的示例性实施例的以下描述，本发明的各方面将变得清楚。其中，
图1是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中制造栅极的步骤；
图2是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中制造栅极绝缘层的步骤；
图3A-图3C是顺序地示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中制造半导体层的步骤，其中，图3A是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在栅极绝缘层上设置光阻层的步骤，图3B是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在暴露的栅极绝缘层上和光阻层上设置半导体氧化物的步骤，图3C是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在栅极绝缘层上形成岛状的半导体层的步骤；
图4是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在半导体层上分别形成源极、漏极、钝化层和像素电极层的步骤。
具体实施方式
TFT-LCD的工作原理是通过电压的变化控制每个像素的开关，精准地控制每个像素的的颜色和亮度，从而得到需要的画面。然而，现市场上主流的TFT-LCD需要较大的驱动电压(一般驱动电压大于10V)才能正常的工作，并且需要足够的电流开关比。工作电压较大导致了高功耗和较大寄生电容，不利于便携式电子产品的设计。
下面将要参照附图描述的本发明的示例性实施例提供了一种制造薄膜晶体管的方法，所述方法使用SiH4和O2作为反应气体，通过PECVD的方法沉积多孔SiO2作为TFT的栅极绝缘层，从而有效地减少了寄生电容并且降低了功耗。
以下，将结合附图来详细描述本发明的示例性实施例，然而，本发明的保护范围不受附图和下面将要描述的示例性实施例的限制。下面的示例性实施例 的描述是为了让本领域技术人员能够更充分地了解本发明的具体实施，并将本发明的范围更充分地传递给本领域技术人员。在附图中，为了清楚性，可以夸大层和区域的厚度。此外，同样的附图标记始终指示为同样的元件。
图1是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中制造栅极的步骤。图2是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中制造栅极绝缘层的步骤。图3A-图3C是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中制造半导体层的步骤，其中，图3A是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在栅极绝缘层上设置光阻层的步骤，图3B是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在暴露的栅极绝缘层上和光阻层上设置半导体氧化物的步骤，图3C是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在栅极绝缘层上形成孤岛状的半导体层的步骤。图4是示意性地示出根据本发明的示例性实施例的制造薄膜晶体管的方法中在半导体层上分别形成源极、漏极、钝化层和像素电极层的步骤。
以下将结合图1至图4来充分地描述根据本发明的示例性实施例的制造薄膜晶体管的方法。
参照图1-图4，根据本发明的示例性实施例的制造薄膜晶体管的方法包括以下步骤：
首先，如图1所示，设置基底SU，并在基底上设置栅极G。
根据本发明的示例性实施例，基底SU可以为本领域所普遍使用的玻璃基底等，但本发明不限于此。可使用蚀刻等工艺将栅极G形成在基底上。此外，为了避免在蚀刻过程中金属粒子进入到基底SU，可以在基底SU与栅极G之间设置缓冲层。
然后，如图2所示，在栅极G和基底SU的暴露的部分上形成栅极绝缘层。
根据本发明的示例性实施例，栅极绝缘层GI由多孔的SiO2形成。可以使用等离子增强的化学气相沉积(PECVD)在栅极G和基底SU的暴露的部分上沉积多孔的SiO2，以形成具有预定厚度的栅极绝缘层G1。优选地，在沉积过 程中，可以在室温(例如，5℃～35℃)下以SiH4和O2作为反应气体。优选地，形成的栅极绝缘层GI的厚度可以为大约
Figure PCTCN2016089760-appb-000002
但本发明不限于此。
在栅极绝缘层GI形成之后，在栅极绝缘层GI上设置半导体层SE，如图3A至图3C所示。
根据本发明的示例性实施例，参照图3A至图3C，设置半导体层SE的步骤优选地，可以包括但不限于以下方面：
(1)在栅极绝缘层GI的部分上设置光阻层PR，如图3A所示。具体地，如图3A所示，可以在栅极绝缘层GI上设置具有预定厚度的光阻层PR，例如，1μm-2μm，以覆盖栅极绝缘层GI的大部分表面，并使栅极绝缘层GI的与栅极G对应的区域暴露，从而保护金属线。换言之，光阻层PR被设置为使与栅极G对应的栅极绝缘层GI的部分区域暴露，并且覆盖栅极绝缘层GI的其它区域。可以通过沉积和掩模等方式来实现上述目的，但本发明不限于此。优选地，可以在栅极绝缘层GI上设置正性光阻层。此外，优选地，在形成光阻层PR后，可以使用高浓度(例如，60wt％～80wt％)的H3PO4处理(例如，喷淋处理、浸泡处理等)栅极绝缘层GI的被暴露的区域预定时间段，从而可以使-PO3H2进入栅极绝缘层GI的多孔的SiO2中。
(2)在光阻层PR和栅极绝缘层GI的被暴露的部分上沉积半导体氧化物SO，如图3B所示。根据本发明的示例性实施例，可以采用物理气相沉积(PVD)的方法在暴露的栅极绝缘层GI和光阻层PR上沉积半导体氧化物SO。此外，根据本发明的示例性实施例的半导体氧化物SO可以为IGZO(铟镓锌氧化物)。
(3)使用诸如剥离液(例如，Strip剥离液)等剥离光阻层PR(例如，正性光阻层)以及沉积在光阻层PR上的半导体氧化物(例如，IGZO)SO，从而形成半导体层SE，如图3C所示。根据本发明的一个示例性实施例，由于栅极绝缘层GI的与栅极G对应的区域上并未形成有光阻层PR，即，栅极绝缘层GI的与栅极G对应的区域与半导体层SE直接接触，因此，在剥离光阻层PR后，位于栅极绝缘层GI的与栅极G对应的区域上的半导体层SE未被剥离而保留在栅极绝缘层GI上。根据本发明的一个示例性实施例，在将光阻层PR和沉积在光阻层上的半导体氧化物SO剥离后，形成了岛状IGZO半导体层SE。
在半导体层SE形成之后，可以根据现有技术而在半导体层SE上分别依次地设置源极S和漏极D、钝化层PV以及像素电极层PE等。例如，如图4所示，根据本发明的示例性实施例，可以使用成膜或掩模的方法在半导体层SE上形成源极S和漏极D，使得它们位于同一层上，然后在源极S和漏极D上形成钝化层PV，并在形成的钝化层上形成像素电极PE，从而制造出薄膜晶体管，
以上，结合附图详细描述了根据本发明的示例性实施例的制造薄膜晶体管的方法。通过使用上述方法，采用多孔的SiO2作为栅极绝缘层，使得TFT沟道在电场驱动下和TFT沟道电子相互耦合形成大的双电层(EDL)电容。此外，在栅极绝缘层形成后，通过H3PO4对多孔的SiO2进行处理，使得经H3PO4处理后的多孔的SiO2中的质子导电特性增强。这是由于连接在SiO2颗粒表面的-PO3H2相互作用形成了Grotthuss链，而H+可以在Grotthuss链构成的输运网络中自由跳跃，使得薄膜的质子传递能力得以增强。磷酸处理后的EDL电容增大使得栅极和沟道之间耦合增强，从而使栅极电压能够感应更多的沟道电子，达到减小寄生电容和降低工作电压的作用。

Claims (10)

  1. 一种制造薄膜晶体管的方法，其中，所述方法包括以下步骤：
    设置基底，
    在基底上设置栅极，
    在栅极上设置栅极绝缘层，
    在栅极绝缘层上设置半导体层，
    在半导体层上分别设置源极和漏极，
    在源极和漏极上设置钝化层，
    在钝化层上设置像素电极，
    其中，所述栅极绝缘层由多孔的SiO2形成。
  2. 如权利要求1所述的方法，其中，形成栅极绝缘层的步骤包括：
    以SiH4和O2作为反应气体在栅极上沉积多孔的SiO2作为栅极绝缘层。
  3. 如权利要求2所述的方法，其中，采用等离子体增强的化学气相沉积方法来沉积多孔的SiO2。
  4. 如权利要求2所述的方法，其中，所述栅极绝缘层的厚度为
    Figure PCTCN2016089760-appb-100001
  5. 如权利要求1所述的方法，其中，形成半导体层的步骤包括：
    在栅极绝缘层上设置光阻层以覆盖栅极绝缘层的大部分表面，并使栅极绝缘层的与栅极对应的区域暴露，
    使用H3PO4处理栅极绝缘层的被暴露的区域，以使-PO3H2进入栅极绝缘层的多孔的SiO2中，
    在光阻层上以及栅极绝缘层的暴露的部分上沉积半导体氧化物，然后剥离光阻层以及沉积在光阻层上的半导体氧化物，从而形成半导体层。
  6. 如权利要求5所述的方法，其中，采用物理气相沉积的方法在暴露的栅极绝缘层和光阻层上沉积半导体氧化物。
  7. 如权利要求5所述的方法，其中，使用H3PO4处理栅极绝缘层包括使用60wt％～80wt％的H3PO4对栅极绝缘层进行喷淋和/或浸泡处理。
  8. 如权利要求5所述的方法，其中，光阻层为正性光阻层。
  9. 如权利要求5所述的方法，其中，光阻层的厚度为1μm-2μm。
  10. 如权利要求1所述的方法，其中，半导体层包括铟镓锌氧化物。
PCT/CN2016/089760 2016-01-28 2016-07-12 制造薄膜晶体管的方法 Ceased WO2017128633A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/119,718 US20180068855A1 (en) 2016-01-28 2016-07-12 Method of Manufacturing Thin Film Transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610061764.0 2016-01-28
CN201610061764.0A CN105632896B (zh) 2016-01-28 2016-01-28 制造薄膜晶体管的方法

Publications (1)

Publication Number Publication Date
WO2017128633A1 true WO2017128633A1 (zh) 2017-08-03

Family

ID=56047701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/089760 Ceased WO2017128633A1 (zh) 2016-01-28 2016-07-12 制造薄膜晶体管的方法

Country Status (3)

Country Link
US (1) US20180068855A1 (zh)
CN (1) CN105632896B (zh)
WO (1) WO2017128633A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105632896B (zh) * 2016-01-28 2018-06-15 深圳市华星光电技术有限公司 制造薄膜晶体管的方法
CN106653688B (zh) * 2016-12-30 2019-10-18 惠科股份有限公司 主动阵列基板的制造方法
CN107799466B (zh) 2017-11-16 2020-04-07 深圳市华星光电半导体显示技术有限公司 Tft基板及其制作方法
CN113013253B (zh) * 2021-02-24 2022-06-28 中国科学院宁波材料技术与工程研究所 一种p型薄膜晶体管及其制备方法和反相器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1794426A (zh) * 2004-12-25 2006-06-28 鸿富锦精密工业（深圳）有限公司 一种超薄闸极氧化层及其成长方法
CN102738260A (zh) * 2011-04-15 2012-10-17 元太科技工业股份有限公司 光电二极管、光感测组件及光电二极管的制造方法
US20130234124A1 (en) * 2010-02-19 2013-09-12 Samsung Display Co., Ltd. Thin-film transistor substrate, method of manufacturing the same, and display device including the same
CN105632896A (zh) * 2016-01-28 2016-06-01 深圳市华星光电技术有限公司 制造薄膜晶体管的方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261880B1 (en) * 1999-05-24 2001-07-17 Chi Mei Electronics Corp Process for manufacturing thin film transistors
KR20060084589A (ko) * 2005-01-20 2006-07-25 삼성전자주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN100463193C (zh) * 2006-11-03 2009-02-18 北京京东方光电科技有限公司 一种tft阵列结构及其制造方法
CN100466182C (zh) * 2007-01-04 2009-03-04 北京京东方光电科技有限公司 金属导线、电极及薄膜晶体管阵列基板的制造方法
CN101819363B (zh) * 2009-02-27 2011-12-28 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
EP2256814B1 (en) * 2009-05-29 2019-01-16 Semiconductor Energy Laboratory Co, Ltd. Oxide semiconductor device and method for manufacturing the same
KR101460868B1 (ko) * 2009-07-10 2014-11-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101733718B1 (ko) * 2009-09-24 2017-05-10 어플라이드 머티어리얼스, 인코포레이티드 소스 및 드레인 금속 식각을 위해 습식 프로세스를 이용하여 금속 산화물 또는 금속 산질화물 ｔｆｔ들을 제조하는 방법들
US8759917B2 (en) * 2010-01-04 2014-06-24 Samsung Electronics Co., Ltd. Thin-film transistor having etch stop multi-layer and method of manufacturing the same
US8685787B2 (en) * 2010-08-25 2014-04-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US8883555B2 (en) * 2010-08-25 2014-11-11 Semiconductor Energy Laboratory Co., Ltd. Electronic device, manufacturing method of electronic device, and sputtering target
WO2012066996A1 (ja) * 2010-11-16 2012-05-24 シャープ株式会社 表示装置
CN102651316B (zh) * 2011-05-09 2014-08-13 京东方科技集团股份有限公司 过孔的刻蚀方法、阵列基板、液晶面板及显示设备
CN102651340B (zh) * 2011-12-31 2014-11-19 京东方科技集团股份有限公司 一种tft阵列基板的制造方法
CN102646632B (zh) * 2012-03-08 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN102629592A (zh) * 2012-03-23 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN103117284A (zh) * 2013-02-01 2013-05-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
JP2016027597A (ja) * 2013-12-06 2016-02-18 株式会社半導体エネルギー研究所 半導体装置
CN103915379B (zh) * 2014-03-24 2017-07-04 京东方科技集团股份有限公司 一种氧化物薄膜晶体管阵列基板的制造方法
CN104078501A (zh) * 2014-06-13 2014-10-01 上海交通大学 一种基于二维半导体材料的低压场效应晶体管
US20170329185A1 (en) * 2014-11-28 2017-11-16 Sharp Kabushiki Kaisha Liquid crystal display device
CN105990448B (zh) * 2015-02-16 2019-06-18 南京瀚宇彩欣科技有限责任公司 薄膜晶体管
CN104952935B (zh) * 2015-07-14 2018-06-22 深圳市华星光电技术有限公司 一种薄膜晶体管结构及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1794426A (zh) * 2004-12-25 2006-06-28 鸿富锦精密工业（深圳）有限公司 一种超薄闸极氧化层及其成长方法
US20130234124A1 (en) * 2010-02-19 2013-09-12 Samsung Display Co., Ltd. Thin-film transistor substrate, method of manufacturing the same, and display device including the same
CN102738260A (zh) * 2011-04-15 2012-10-17 元太科技工业股份有限公司 光电二极管、光感测组件及光电二极管的制造方法
CN105632896A (zh) * 2016-01-28 2016-06-01 深圳市华星光电技术有限公司 制造薄膜晶体管的方法

Also Published As

Publication number Publication date
US20180068855A1 (en) 2018-03-08
CN105632896B (zh) 2018-06-15
CN105632896A (zh) 2016-06-01

Similar Documents

Publication Publication Date Title
US10192908B2 (en) TFT array manufacturing method of optimized 4M production process
US9391207B2 (en) Thin film transistor, array substrate and manufacturing method thereof, and display device
CN104681627B (zh) 阵列基板、薄膜晶体管及制作方法、显示装置
CN103021939B (zh) 一种阵列基板及其制造方法、显示装置
CN107994066B (zh) Tft、制作方法、阵列基板、显示面板及装置
JP2015529012A (ja) アレイ基板の製造方法、アレイ基板及び表示装置
CN103314431A (zh) 制造氧化物薄膜晶体管阵列的方法和结合其的装置
US20160172389A1 (en) Thin film transistor and manufacturing method thereof
CN105140131A (zh) 氧化物薄膜晶体管的制备方法
US20170213916A1 (en) Dual-Gate TFT Array Substrate and Manufacturing Method Thereof, and Display Device
CN102881598B (zh) 薄膜晶体管的制造方法、阵列基板的制造方法及显示装置
CN106784014A (zh) 薄膜晶体管及其制作方法、显示基板、显示装置
CN104505372B (zh) 金属氧化物薄膜晶体管阵列基板的制作方法
CN104637872B (zh) 氧化物半导体薄膜晶体管阵列基板的制作方法
CN103715266A (zh) 氧化物薄膜晶体管、阵列基板的制造方法及显示器件
US10367081B2 (en) Method of manufacturing thin film transistor
CN105140296A (zh) 一种薄膜晶体管、其制备方法、阵列基板及显示面板
CN106356306A (zh) 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
US9159746B2 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
CN107799466B (zh) Tft基板及其制作方法
CN105632896B (zh) 制造薄膜晶体管的方法
US10170506B2 (en) LTPS array substrate and method for producing the same
CN104362180B (zh) 一种薄膜晶体管及其制作方法、显示基板和显示装置
CN105047675B (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
US10153308B1 (en) Manufacturing method for thin film transistor and array substrate

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15119718

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16887512

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16887512

Country of ref document: EP

Kind code of ref document: A1