WO2017128459A1 - 一种阵列基板及触摸屏 - Google Patents

一种阵列基板及触摸屏 Download PDF

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Publication number
WO2017128459A1
WO2017128459A1 PCT/CN2016/074229 CN2016074229W WO2017128459A1 WO 2017128459 A1 WO2017128459 A1 WO 2017128459A1 CN 2016074229 W CN2016074229 W CN 2016074229W WO 2017128459 A1 WO2017128459 A1 WO 2017128459A1
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Prior art keywords
electrode layer
layer
touch electrode
touch
pixel electrode
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Ceased
Application number
PCT/CN2016/074229
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English (en)
French (fr)
Inventor
陈彩琴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to GB1811835.6A priority Critical patent/GB2562002B/en
Priority to KR1020187021513A priority patent/KR102097227B1/ko
Priority to RU2018130388A priority patent/RU2689722C1/ru
Priority to JP2018538845A priority patent/JP6581731B2/ja
Priority to US14/917,950 priority patent/US10025129B2/en
Publication of WO2017128459A1 publication Critical patent/WO2017128459A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds

Definitions

  • the present invention relates to the field of touch technologies, and in particular, to an array substrate and a touch screen.
  • touch screens have gradually spread to people's lives.
  • the touch screen has the advantages of sturdy and durable, fast response, space saving, easy to communicate, etc.
  • the user only needs to touch the graphic characters on the screen with a finger to realize the operation of the host, thereby making the human-computer interaction more straightforward. .
  • the touch screen includes an on-cell touch panel and an in-cell touch panel (In-cell Touch) Panel).
  • the in-cell touch panel embeds the touch sensing function into the metallurgical pixel, which can better realize the thinning and light weight of the panel, and is favored by manufacturers.
  • FIG. 1 is a schematic structural view of a liquid crystal panel of the prior art.
  • the liquid crystal panel includes an upper substrate 11, a lower substrate 12, and a liquid crystal layer 13 between the upper substrate 11 and the lower substrate 12.
  • a source/drain metal layer 121 of a thin film transistor TFT, an organic insulating layer 122, a common electrode layer 123, a passivation layer 124, and a pixel electrode layer 125 are formed on the lower substrate 12.
  • FIG. 2 is a schematic structural diagram of an in-cell touch panel in the prior art.
  • the touch electrode layer 21 and the insulating layer 22 are usually added to the lower substrate 12.
  • the touch electrode layer 21 and the common electrode layer 123 are used as sensing electrodes to implement a touch sensing function of the touch screen.
  • the insulating layer 22 covers the common electrode layer 123
  • the touch electrode layer 21 is located on the partial insulating layer 22
  • the passivation layer 124 covers the touch electrode layer 21 and the insulating layer 22 .
  • the pixel electrode layer 125 is on the passivation layer 124.
  • a thick insulating layer 22 is usually formed to reduce the touch electrode layer 21 and the common electrode. The parasitic capacitance between layers 123.
  • the thickness of the insulating layer 22 will change the pitch between the pixel electrode layer 125 and the upper substrate 11, and the spacing between the pixel electrode 125 and the common electrode layer 123, so if it is necessary to increase the insulating layer 22
  • the thickness of the touch electrode is reduced to reduce the parasitic capacitance of the touch electrode, the size of the liquid crystal capacitor and the storage capacitor are also affected, thereby degrading the display quality.
  • the technical problem to be solved by the present invention is to provide an array substrate and a touch screen, which can reduce the parasitic capacitance between the touch electrodes without affecting the size of the liquid crystal capacitor and the storage capacitor.
  • the present invention adopts a technical solution for providing an array substrate for a touch screen, including a pixel electrode layer, a first touch electrode layer, and sequentially stacked on the first touch electrode layer.
  • the vertical projection area has no insulating layer; the first touch electrode layer is a common electrode layer, and the second touch electrode layer is located in a vertical projection area of the black matrix.
  • the pixel electrode layer does not overlap with the second touch electrode layer, the pixel electrode layer includes a plurality of pixel electrode strips, and the insulating layer includes a plurality of intervals arranged in the first An insulating layer on the touch electrode layer, the second touch electrode layer is located in one of the insulating layers, and the passivation layer is disposed on the first touch between the second touch electrode layer and the insulating layer On the control electrode layer, the plurality of pixel electrode strips are respectively disposed on the passivation layer between the insulating layers, and the vertical projection area of each of the pixel electrode strips is free of the insulating layer.
  • the pixel electrode layer does not overlap with the second touch electrode layer, the pixel electrode layer includes a plurality of pixel electrode strips, and the insulating layer covers a portion of the first touch electrode. a layer, the passivation layer is disposed on the second touch electrode layer and the first touch electrode layer not covered by the insulating layer, and the plurality of pixel electrode strips are disposed on the passivation layer Above, there is no such insulating layer between the vertical projection area of each of the pixel electrode strips and the pixel electrode strip.
  • an array substrate for a touch screen including a pixel electrode layer, a first touch electrode layer, and a layered on the first touch electrode layer.
  • the vertical projection area has no such insulating layer.
  • the pixel electrode layer does not overlap with the second touch electrode layer, the pixel electrode layer includes a plurality of pixel electrode strips, and the insulating layer includes a plurality of intervals arranged in the first An insulating layer on the touch electrode layer, the second touch electrode layer is located in one of the insulating layers, and the passivation layer is disposed on the first touch between the second touch electrode layer and the insulating layer On the control electrode layer, the plurality of pixel electrode strips are respectively disposed on the passivation layer between the insulating layers, and the vertical projection area of each of the pixel electrode strips is free of the insulating layer.
  • the pixel electrode layer does not overlap with the second touch electrode layer, the pixel electrode layer includes a plurality of pixel electrode strips, and the insulating layer covers a portion of the first touch electrode. a layer, the passivation layer is disposed on the second touch electrode layer and the first touch electrode layer not covered by the insulating layer, and the plurality of pixel electrode strips are disposed on the passivation layer Above, there is no such insulating layer between the vertical projection area of each of the pixel electrode strips and the pixel electrode strip.
  • the first touch electrode layer is a common electrode layer.
  • the second touch electrode layer is located in a vertical projection area of the black matrix.
  • a touch screen including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate
  • the array substrate includes a pixel electrode layer, a first touch electrode layer, and an insulating layer and a second touch electrode layer which are sequentially stacked on the first touch electrode layer; wherein the pixel electrode layer and the first touch At least one of the control electrode layer and the second touch electrode layer does not overlap, and the insulating layer is absent at least in a vertical projection area of the pixel electrode layer.
  • the array substrate further includes a passivation layer; the pixel electrode layer does not overlap with the second touch electrode layer, the pixel electrode layer includes a plurality of pixel electrode strips, and the insulating layer includes a plurality of spaced layers
  • the insulating layer on the first touch electrode layer, the second touch electrode layer is located in one of the insulating layers, and the passivation layer is disposed between the second touch electrode layer and the insulating layer
  • the plurality of pixel electrode strips are respectively disposed on the passivation layer between the insulating layers, and the vertical projection area of each of the pixel electrode strips is free of the insulating layer.
  • the array substrate further includes a passivation layer; the pixel electrode layer and the second touch electrode layer do not overlap, the pixel electrode layer includes a plurality of pixel electrode strips, and the insulating layer covers a portion of the first a touch electrode layer, the passivation layer is disposed on the second touch electrode layer and the first touch electrode layer not covered by the insulating layer, and the plurality of pixel electrode strips are disposed in the On the passivation layer, the vertical projection area of each of the pixel electrode strips and the pixel electrode strip are free of the insulating layer.
  • the first touch electrode layer is a common electrode layer.
  • the color filter substrate includes a black matrix, and the second touch electrode layer is located in a vertical projection area of the black matrix.
  • the invention has the beneficial effects that the insulating layer is disposed between the first touch electrode layer and the second touch electrode layer, and is not disposed in the vertical projection area of the pixel electrode layer.
  • the insulating layer that is, the insulating layer between the first touch electrode layer and the second touch electrode layer is not formed in the vertical projection area of the pixel electrode layer, and thus is formed on the first touch electrode layer and the second touch.
  • the thickness of the insulating layer between the control electrode layers does not affect the spacing between the pixel electrode and the common electrode on the other substrate, and does not affect the spacing between the pixel electrode and the common electrode on the array substrate. Therefore, when the thickness of the insulating layer between the first touch electrode layer and the second touch electrode layer is increased to reduce the parasitic capacitance between the touch electrode layers, the influence on the liquid crystal capacitance and the storage capacitance can be avoided.
  • FIG. 1 is a schematic structural view of a liquid crystal panel of the prior art
  • FIG. 2 is a schematic structural view of an in-cell touch panel of the prior art
  • FIG. 3 is a schematic structural view of an embodiment of an array substrate for a touch screen according to the present invention.
  • FIG. 4 is a schematic structural view of another embodiment of an array substrate for a touch screen according to the present invention.
  • FIG. 5 is a schematic structural view of an embodiment of a touch screen of the present invention.
  • liquid crystal panel suitable for use in the array substrate of the present invention will be described.
  • the array substrate and the color filter substrate are relatively bonded, and then liquid crystal is added between the array substrate and the color filter substrate to obtain a liquid crystal panel.
  • the parallel plate capacitor formed by the pixel electrode on the array substrate and the common electrode on the color filter substrate is a liquid crystal capacitor, and the parallel plate capacitor formed by the pixel electrode on the array substrate and the common electrode on the array substrate is stored. capacitance.
  • the array substrate includes a pixel electrode layer 31, a first touch electrode layer 32, and an insulating layer 33 and a second touch layer which are sequentially stacked on the first touch electrode layer 32.
  • the control electrode layer 34 that is, the insulating layer 33 is located between the first touch electrode layer 32 and the second touch electrode layer 34.
  • the first touch electrode layer 32 may be a driving electrode
  • the second touch electrode layer 34 may be a sensing electrode, and the two cooperate with each other to implement touch detection.
  • the pixel electrode layer 31 and the second touch electrode layer 34 do not overlap, and the vertical projection area of the pixel electrode layer 31 is not provided with the insulating layer 33, that is, formed on the first touch electrode layer 32 and the second touch electrode layer 34.
  • the insulating layer 33 is not formed in the vertical projection region of the pixel electrode layer 31. Therefore, when the array substrate and the other color filter substrate are relatively bonded, the thickness of the insulating layer 33 formed between the first touch electrode layer 32 and the second touch electrode layer 34 does not affect the pixel electrode layer 31.
  • the spacing between the common electrode layers on the color filter substrate is affected, and the spacing between the pixel electrode layer 31 and the common electrode layer on the array substrate is not affected, thereby increasing the first touch electrode when needed
  • the thickness of the insulating layer 33 between the layer 32 and the second touch electrode layer 34 is used to reduce the parasitic capacitance between the touch electrode layers 32 and 34, the influence of the size of the liquid crystal capacitor and the storage capacitor can be avoided, and the display can be guaranteed. quality.
  • the array substrate further includes a passivation layer 35.
  • the first touch electrode layer 32 is a common electrode layer of the array substrate.
  • the pixel electrode layer 31 and the second touch electrode layer 34 do not overlap.
  • the pixel electrode layer 31 partially overlaps the first touch electrode layer 32 and is located on the first touch electrode layer 32.
  • the insulating layer 33 includes a plurality of insulating layers 33 spaced apart from each other on the first touch electrode layer 32.
  • the second touch electrode layer 34 is disposed on one of the insulating layers 33, and the first touch electrode layer 32 between the insulating layers 33. There is no insulating layer 33 on it.
  • the passivation layer 35 is disposed on the first touch electrode layer 32 between the second touch electrode layer 34 and the insulating layer 33 and the insulating layer 33 not covered by the second touch electrode layer 34.
  • the pixel electrode layer 31 includes a plurality of pixel electrode strips 311 respectively located on the passivation layer 35 between the insulating layers 33, that is, the plurality of pixel electrode strips 311 are directly overlying the first touch electrode layer 32.
  • the pixel electrode strip 311 is in direct contact with the passivation layer 35, so that there is no insulating layer 33 in the vertical projection area of the pixel electrode cover 311.
  • the insulating layer 33 is provided between the pixel electrode strips 311, and the passivation layer 35 is also provided on the insulating layer 33 between the pixel electrode strips 311.
  • the array substrate further includes a substrate 36 and a gate insulating layer 37, ILD (Insulator) sequentially formed on the substrate 36.
  • ILD Insulator
  • the first touch electrode layer 31 is formed on the organic insulating layer 40.
  • the array substrate of the present embodiment can be formed by the following method steps:
  • Step S41 Providing the substrate 36.
  • Step S42 A gate insulating layer 37, an ILD layer 38, a source/drain metal layer 39, and an organic insulating layer 40 are sequentially formed on the substrate 36.
  • Step S43 forming a first touch electrode layer 32 on the organic insulating layer 40.
  • Step S44 forming an insulating layer 33 on the first touch electrode layer 32, and the insulating layer 33 covers the first touch electrode layer 32.
  • Step S45 The partial insulating layer 33 is removed to form a plurality of insulating layers 33 spaced apart from each other on the first touch electrode layer 32, and the first touch electrode layer 32 between the insulating layers 33 is exposed.
  • Step S46 forming a second touch electrode layer 34 on one of the insulating layers 33.
  • Step S47 forming a passivation layer 35 on the second touch electrode layer 34, the first touch electrode layer 32 between the insulating layers 33, and the insulating layer 33 not covered by the second touch electrode layer 34.
  • Step S48 forming a pixel electrode strip 311 on the passivation layer 35 between the insulating layers 33.
  • the second touch electrode layer 34 may be formed on the insulating layer 33, and then the second touch electrode layer 34 may be formed.
  • a plurality of spaced-apart insulating layers 33 are formed on the first touch electrode layer 32, and the insulating layer 33 is exposed.
  • the first touch electrode layer 32 is interposed.
  • the insulating layer 33 can be omitted in the vertical projection area of the pixel electrode strip 311, so that the insulating layer 33 or the insulating layer 33 of different thickness is required to reduce the first touch electrode layer 32 and the second touch electrode.
  • the parasitic capacitance between the layers 34 is used, the influence of the insulating layer 33 on the size of the liquid crystal capacitance and the storage capacitance can be avoided.
  • the respective pixel electrode strips 311 can be formed with reference to the height of the insulating layer 33, which is advantageous for ensuring the flatness of the respective pixel electrode strips 311, which is the flatness. Refers to the consistency of the height of each pixel electrode strip.
  • the main difference from the embodiment shown in FIG. 3 is that, in addition to the insulating layer 33 formed at a position corresponding to the second touch electrode layer 34, The insulating layer 33 is not formed at other positions of the touch electrode layer 32, that is, the insulating layer 33 is not disposed between the pixel electrode strips 11.
  • the insulating layer 33 is formed on the first touch electrode layer 32, and then the second touch electrode layer is formed on the insulating layer 33. 34.
  • the insulating layer 33 can be exposed by using the second touch electrode layer 34 as a self-aligning mask to remove other insulating layers than the insulating layer 33 covered by the second touch electrode layer 34.
  • a passivation layer 35 is formed on the second touch electrode layer 34 and the exposed first touch electrode layer 32, and then a plurality of pixels are formed on the passivation layer 35 in direct contact with the first touch electrode layer 32.
  • the process can be simplified by removing the insulating layer other than the insulating layer 33 covered by the second touch electrode layer 34.
  • the second touch electrode layer 34 is located in a vertical projection area corresponding to the black matrix, that is, the second touch electrode layer 34 is located between the pixel units, and the black matrix is located in the color.
  • the filter substrate one of the pixel units corresponds to a red color resist layer (R) or a green color resist layer (G) or a blue color resist layer (B) on the color filter substrate.
  • the first touch electrode layer 32 may further increase the touch electrode layer for implementing touch sensing in the array substrate.
  • the pixel electrode layer 31 and the first touch electrode may be Layers 32, 34 do not overlap.
  • the touch screen is a liquid crystal display having a touch function.
  • the touch screen includes an array substrate 51, a color filter substrate 52, and a liquid crystal layer 53 between the array substrate and the color filter substrate 52.
  • the array substrate 51 is the array substrate according to any of the above embodiments.
  • the array substrate shown in FIG. 3 will be described as an example.
  • a spacer 531 is disposed in the liquid crystal layer 53 to ensure a liquid crystal gap.
  • the array substrate 51 includes a pixel electrode layer 31, a first touch electrode layer 32, and an insulating layer 33 and a second touch electrode layer 34 which are sequentially stacked on the first touch electrode layer 32, that is, the insulating layer 33 is located at the first touch. Between the control electrode layer 32 and the second touch electrode layer 34.
  • the pixel electrode layer 31 and the second touch electrode layer 34 do not overlap, and the vertical projection area of the pixel electrode layer 31 is not provided with the insulating layer 33, that is, formed on the first touch electrode layer 32 and the second touch electrode layer.
  • the insulating layer 33 between 34 is not formed in the vertical projection region of the pixel electrode layer 31. Therefore, when the array substrate 51 and the color filter substrate 52 are relatively bonded, the thickness of the insulating layer 33 formed between the first touch electrode layer 32 and the second touch electrode layer 34 does not affect the pixel electrode layer 31.
  • the spacing between the common electrode layers on the color filter substrate 52 is affected, and the spacing between the pixel electrode layer 31 and the common electrode layer on the array substrate 51 is not affected, thereby increasing the first touch.
  • the thickness of the insulating layer 33 between the control electrode layer 32 and the second touch electrode layer 34 is used to reduce the parasitic capacitance between the touch electrode layers 32 and 34, the influence on the size of the liquid crystal capacitor and the storage capacitor can be avoided. Guaranteed display quality.
  • the array substrate 51 further includes a passivation layer 35.
  • the first touch electrode layer 32 is a common electrode layer of the array substrate 51.
  • the pixel electrode layer 31 and the second touch electrode layer 34 do not overlap.
  • the pixel electrode layer 31 partially overlaps the first touch electrode layer 32 and is located on the first touch electrode layer 32.
  • the insulating layer 33 includes a plurality of insulating layers 33 spaced apart from each other on the first touch electrode layer 32.
  • the second touch electrode layer 34 is disposed on one of the insulating layers 33, and the first touch electrode layer 32 between the insulating layers 33. There is no insulating layer 33 on it.
  • the passivation layer 35 is disposed on the first touch electrode layer 32 between the second touch electrode layer 34 and the insulating layer 33 and the insulating layer 33 not covered by the second touch electrode layer 34.
  • the pixel electrode layer 31 includes a plurality of pixel electrode strips 311 respectively located on the passivation layer 35 between the insulating layers 33, that is, the plurality of pixel electrode strips 311 are directly overlying the first touch electrode layer 32.
  • the pixel electrode strip 311 is in direct contact with the passivation layer 35, so that there is no insulating layer 33 in the vertical projection area of the pixel electrode cover 311.
  • the array substrate 51 further includes a substrate 36 and a gate insulating layer 37, ILD (Insulator) sequentially formed on the substrate 36.
  • ILD Insulator
  • the first touch electrode layer 31 is formed on the organic insulating layer 40.
  • the color filter substrate 52 includes a glass substrate 521 and a color resist layer formed on the glass substrate.
  • the color resist layer includes a red color resist layer, a green color resist layer, and a blue color resist layer, and each color resist layer corresponds to the array.
  • the color filter substrate 52 further includes a black matrix 522 and a flat layer 525 between the color resist layers.
  • the flat layer 525 is a transparent flat layer.
  • the color filter substrate 52 is further provided with a common electrode layer (not shown).
  • the spacer 531 is located in the liquid crystal layer 53 in the vertical projection area of the black matrix 522.
  • the second touch electrode layer 34 of the array substrate 51 is located in a vertical projection area of the black matrix 522.
  • the insulating layer 33 is not disposed in the vertical projection area of the pixel electrode layer, so that the insulating layer 33 needs to be disposed between the first touch electrode layer 32 and the second touch electrode layer 34 or differently disposed.
  • the insulating layer 33 of the thickness is used to reduce the parasitic capacitance between the first touch electrode layer 32 and the second touch electrode layer 34, the influence of the insulating layer 33 on the size of the liquid crystal capacitor and the storage capacitor can be avoided.

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  • Physics & Mathematics (AREA)
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Abstract

一种阵列基板及触摸屏，阵列基板包括像素电极层（31）、第一触控电极层（32）以及依次层叠设置在第一触控电极层（32）上的绝缘层（33）、第二触控电极层（34）；其中像素电极层（31）与第一触控电极层（32）、第二触控电极层（34）中至少一个不重叠，并且至少在像素电极层（31）的垂直投影区域无绝缘层（33）。通过这种方式，能够在减小触控电极间的寄生电容的同时，不影响液晶电容和存储电容的大小。

Description

一种阵列基板及触摸屏
【技术领域】
本发明涉及触控技术领域，特别是涉及一种阵列基板及触摸屏。
【背景技术】
随着电子技术的不断发展，触摸屏已逐渐普及到人们的生活中。触摸屏具有坚固耐用、反应速度快、节省空间、易于交流等优点，利用触摸屏，用户只需要手指轻轻触碰屏幕上的图文字符即可实现对主机的操作，从而使得人机交互更为直截了当。
触摸屏包括覆盖表面式触摸屏（On-cell Touch Panel）和内嵌式触摸屏（In-cell Touch Panel）。其中，内嵌式触摸屏是将触控感应功能嵌入到冶金像素中，可以更好地实现面板的薄型化和轻量化，备受厂商青睐。
如图1所示，图1是现有技术一种液晶面板的结构示意图。液晶面板包括上基板11、下基板12以及位于上基板11和下基板12之间的液晶层13。下基板12上形成有薄膜晶体管TFT的源漏金属层121、有机绝缘层122、公共电极层123、钝化层124和像素电极层125。
如图2所示，图2是现有技术一种内嵌式触摸屏的结构示意图。现有的内嵌式触摸屏中，通常是在下基板12上增加触控电极层21和绝缘层22。触控电极层21和公共电极层123作为感应电极用以实现触摸屏的触控感应功能。其中，绝缘层22覆盖公共电极层123，触控电极层21位于部分绝缘层22上，钝化层124覆盖触控电极层21和绝缘层22。像素电极层125位于钝化层124上。由于触控电极层21和公共电极层123之间会产生寄生电容，因此现有技术中为了避免寄生电容过大，通常会形成较厚的绝缘层22，以降低触控电极层21和公共电极层123之间的寄生电容。
然而，如图2所示，绝缘层22的厚度将会改变像素电极层125和上基板11之间的间距，以及像素电极125和公共电极层123之间的间距，因此若需要增加绝缘层22的厚度以降低触控电极的寄生电容时，液晶电容和存储电容的大小也会受到影响，降低显示品质。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及触摸屏，能够在减小触控电极间的寄生电容的同时，不影响液晶电容和存储电容的大小。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种用于触摸屏的阵列基板，包括像素电极层、第一触控电极层以及依次层叠设置在所述第一触控电极层上的绝缘层、第二触控电极层；其中所述像素电极层与所述第一触控电极层、所述第二触控电极层中至少一个不重叠，并且至少在所述像素电极层的垂直投影区域无所述绝缘层；所述第一触控电极层为公共电极层，所述第二触控电极层位于黑色矩阵的垂直投影区域内。
其中，还包括钝化层；所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层包括多个间隔排列于所述第一触控电极层上的绝缘层，所述第二触控电极层位于其中一个所述绝缘层，所述钝化层设置在所述第二触控电极层以及绝缘层之间的第一触控电极层上，所述多个像素电极条分别设置在绝缘层之间的所述钝化层上，每个所述像素电极条的垂直投影区域无所述绝缘层。
其中，还包括钝化层；所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层覆盖部分所述第一触控电极层，所述钝化层设置在所述第二触控电极层以及未被所述绝缘层覆盖的所述第一触控电极层上，所述多个像素电极条设置在所述钝化层上，每个所述像素电极条的垂直投影区域以及像素电极条之间无所述绝缘层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种用于触摸屏的阵列基板，包括像素电极层、第一触控电极层以及依次层叠设置在所述第一触控电极层上的绝缘层、第二触控电极层；其中所述像素电极层与所述第一触控电极层、所述第二触控电极层中至少一个不重叠，并且至少在所述像素电极层的垂直投影区域无所述绝缘层。
其中，还包括钝化层；所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层包括多个间隔排列于所述第一触控电极层上的绝缘层，所述第二触控电极层位于其中一个所述绝缘层，所述钝化层设置在所述第二触控电极层以及绝缘层之间的第一触控电极层上，所述多个像素电极条分别设置在绝缘层之间的所述钝化层上，每个所述像素电极条的垂直投影区域无所述绝缘层。
其中，还包括钝化层；所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层覆盖部分所述第一触控电极层，所述钝化层设置在所述第二触控电极层以及未被所述绝缘层覆盖的所述第一触控电极层上，所述多个像素电极条设置在所述钝化层上，每个所述像素电极条的垂直投影区域以及像素电极条之间无所述绝缘层。
其中，所述第一触控电极层为公共电极层。
其中，所述第二触控电极层位于黑色矩阵的垂直投影区域内。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种触摸屏，包括阵列基板、彩色滤光基板和位于所述阵列基板和所述彩色滤光基板之间的液晶层，所述阵列基板包括像素电极层、第一触控电极层以及依次层叠设置在所述第一触控电极层上的绝缘层、第二触控电极层；其中所述像素电极层与所述第一触控电极层、所述第二触控电极层中至少一个不重叠，并且至少在所述像素电极层的垂直投影区域无所述绝缘层。
其中，所述阵列基板还包括钝化层；所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层包括多个间隔排列于所述第一触控电极层上的绝缘层，所述第二触控电极层位于其中一个所述绝缘层，所述钝化层设置在所述第二触控电极层以及绝缘层之间的第一触控电极层上，所述多个像素电极条分别设置在绝缘层之间的所述钝化层上，每个所述像素电极条的垂直投影区域无所述绝缘层。
其中，所述阵列基板还包括钝化层；所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层覆盖部分所述第一触控电极层，所述钝化层设置在所述第二触控电极层以及未被所述绝缘层覆盖的所述第一触控电极层上，所述多个像素电极条设置在所述钝化层上，每个所述像素电极条的垂直投影区域以及像素电极条之间无所述绝缘层。
其中，所述第一触控电极层为公共电极层。
其中，所述彩色滤光基板包括黑色矩阵，所述第二触控电极层位于所述黑色矩阵的垂直投影区域内。
本发明的有益效果是：区别于现有技术的情况，本发明在第一触控电极层和第二触控电极层之间设置有绝缘层，且在像素电极层的垂直投影区域不设置有所述绝缘层，即第一触控电极层和第二触控电极层之间的绝缘层未在像素电极层的垂直投影区域内形成有，因此形成在第一触控电极层和第二触控电极层之间的绝缘层的厚度不会对像素电极与另一基板上的公共电极之间的间距造成影响，也不会对像素电极与阵列基板上的公共电极之间的间距造成影响，因此当增加第一触控电极层和第二触控电极层之间的绝缘层的厚度以降低触控电极层之间的寄生电容时，可以避免对液晶电容和存储电容的产生影响。
【附图说明】
图1是现有技术一种液晶面板的结构示意图；
图2是现有技术一种内嵌式触摸屏的结构示意图；
图3是本发明用于触摸屏的阵列基板一实施方式的结构示意图；
图4是本发明用于触摸屏的阵列基板另一实施方式的结构示意图；
图5是本发明触摸屏一实施方式的结构示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
在对本发明进行介绍之前，先对适用于本发明的阵列基板的液晶面板进行说明。阵列基板和彩色滤光基板相对贴合，然后在阵列基板和彩色滤光基板之间加入液晶从而得到液晶面板。其中，由阵列基板上的像素电极和彩色滤光基板上的公共电极所形成的平行板电容为液晶电容，由阵列基板上的像素电极和阵列基板上的公共电极所形成的平行板电容为存储电容。
参阅图3，本发明阵列基板的一实施方式中，阵列基板包括像素电极层31、第一触控电极层32以及依次层叠设置在第一触控电极层32上的绝缘层33、第二触控电极层34，即绝缘层33位于第一触控电极层32和第二触控电极层34之间。
其中，在进行触控功能时，第一触控电极层32可以是驱动电极，第二触控电极层34可以是感应电极，两者相互配合实现触控检测。
像素电极层31和第二触控电极层34不重叠，并且像素电极层31的垂直投影区域不设置有绝缘层33，即形成在第一触控电极层32和第二触控电极层34之间的绝缘层33，未在像素电极层31的垂直投影区域内形成。因此，当将阵列基板和另一彩色滤光基板相对贴合时，形成在第一触控电极层32和第二触控电极层34之间的绝缘层33的厚度不会对像素电极层31和彩色滤光基板上的公共电极层之间的间距造成影响，也不会对像素电极层31和阵列基板上的公共电极层之间的间距造成影响，由此当需要增加第一触控电极层32和第二触控电极层34之间的绝缘层33的厚度以降低触控电极层32、34之间的寄生电容时，可以避免对液晶电容和存储电容的大小产生影响，能够保证显示品质。
进一步地，本发明实施方式中，阵列基板还包括钝化层35。第一触控电极层32为阵列基板的公共电极层。其中，像素电极层31与第二触控电极层34不重叠。像素电极层31与第一触控电极层32部分重叠，其位于第一触控电极层32上。绝缘层33包括多个间隔排列于第一触控电极层32上的绝缘层33，第二触控电极层34位于其中一个绝缘层33上，绝缘层33之间的第一触控电极层32上无绝缘层33。
其中，钝化层35设置在第二触控电极层34、绝缘层33之间的第一触控电极层32以及未被第二触控电极层34覆盖的绝缘层33上。像素电极层31包括多个像素电极条311，多个像素电极条311分别位于绝缘层33之间的钝化层35上，即多个像素电极条311位于直接覆盖在第一触控电极层32上的钝化层35上，且像素电极条311直接与钝化层35接触，从而使得像素电极套311的垂直投影区域内无绝缘层33。
因此，本实施方式中，像素电极条311之间设置有绝缘层33，且像素电极条311之间的绝缘层33上也设置有钝化层35。
其中，阵列基板进一步还包括基底36以及依次形成于基底36上的栅极绝缘层37、ILD（Insulator layer，绝缘层）层38、源漏金属层39以及有机绝缘层40。第一触控电极层31形成于有机绝缘层40上。
因此，本实施方式的阵列基板，可以通过如下方法步骤形成：
步骤S41：提供基底36。
步骤S42：在基底36上依次形成栅极绝缘层37、ILD层38、源漏金属层39以及有机绝缘层40。
步骤S43：在有机绝缘层40上形成第一触控电极层32。
步骤S44：在第一触控电极层32上形成绝缘层33，绝缘层33覆盖第一触控电极层32。
步骤S45：除去部分绝缘层33以形成多个间隔排列于第一触控电极层32上的绝缘层33，并暴露绝缘层33之间的第一触控电极层32。
步骤S46：在其中一个绝缘层33上形成第二触控电极层34。
步骤S47：在第二触控电极层34、位于绝缘层33之间的第一触控电极层32以及未被第二触控电极层34覆盖的绝缘层33上形成钝化层35。
步骤S48：在绝缘层33之间的钝化层35上形成像素电极条311。
在步骤S45和步骤S46中，在第一触控电极层32上形成绝缘层33后，也可以是在绝缘层33上先形成第二触控电极层34，然后以第二触控电极层34为自对准光罩以除去部分没有被第二触控电极层34覆盖的绝缘层33，以在第一触控电极层32上形成多个间隔排列的绝缘层33，并暴露绝缘层33之间的第一触控电极层32。
通过上述方式，可以使得像素电极条311的垂直投影区域内无绝缘层33，从而当需要设置绝缘层33或者设置不同厚度的绝缘层33以降低第一触控电极层32和第二触控电极层34之间的寄生电容时，可以避免绝缘层33对液晶电容和存储电容的大小的影响。并且，通过使像素电极条311形成于绝缘层33之间，可以以绝缘层33的高度为参考来形成各个像素电极条311，有利于保证各个像素电极条311的平坦度，所述平坦度即是指各个像素电极条的高度的一致性。
参阅图4，在本发明阵列基板的另一实施方式中，与图3所示的实施方式主要不同的是，除了与第二触控电极层34对应的位置上形成有绝缘层33外，第一触控电极层32的其他位置上不形成有绝缘层33，即像素电极条11之间不设置有绝缘层33。
因此，在形成本实施方式的阵列基板步骤中，形成第一触控电极层32后，在第一触控电极层32上形成绝缘层33，然后在绝缘层33上形成第二触控电极层34，之后可以以第二触控电极层34为自对准光罩对绝缘层33进行曝光，以除去除第二触控电极层34覆盖的绝缘层33之外的其他绝缘层。然后，在第二触控电极层34上和暴露的第一触控电极层32上形成钝化层35，然后在与第一触控电极层32直接接触的钝化层35上形成多个像素电极条311，其中多个像素电极条311与第二触控电极层34不重叠，由此使得像素电极条311的垂直投影区域上无绝缘层33，绝缘层33仅位于第一触控电极层32和第二触控电极层33之间。
本实施方式的阵列基板，通过除去第二触控电极层34覆盖的绝缘层33之外的其他绝缘层，可以简化工艺过程。
其中，在本发明的阵列基板的实施方式中，第二触控电极层34位于黑色矩阵对应的垂直投影区域内，即第二触控电极层34位于像素单元之间，所述黑色矩阵位于彩色滤光基板上，一个所述像素单元与彩色滤光基板上的一个红色色阻层（R）或者一个绿色色阻层（G）或者一个蓝色色阻层（B）相对应。
其中，在另一种实施方式中，第一触控电极层32也可以是额外增加在阵列基板中用以实现触摸感应的触控电极层，此时像素电极层31可以与第一触控电极层32、34均不重叠。
参阅图5，在本发明触摸屏一实施方式中，触摸屏为具有触摸功能的液晶显示屏。其中，触摸屏包括阵列基板51、彩色滤光基板52以及位于阵列基板和彩色滤光基板52之间的液晶层53。
其中，阵列基板51为上述任一实施方式所述的阵列基板。其中，以图3所示的阵列基板为例进行说明。本实施方式的触摸屏中，液晶层53中设置有间隔物531，用以保证液晶间隙。阵列基板51包括像素电极层31、第一触控电极层32以及依次层叠设置在第一触控电极层32上的绝缘层33、第二触控电极层34，即绝缘层33位于第一触控电极层32和第二触控电极层34之间。
其中，像素电极层31和第二触控电极层34不重叠，并且像素电极层31的垂直投影区域不设置有绝缘层33，即形成在第一触控电极层32和第二触控电极层34之间的绝缘层33，未在像素电极层31的垂直投影区域内形成。因此，当将阵列基板51和彩色滤光基板52相对贴合时，形成在第一触控电极层32和第二触控电极层34之间的绝缘层33的厚度不会对像素电极层31和彩色滤光基板52上的公共电极层之间的间距造成影响，也不会对像素电极层31和阵列基板51上的公共电极层之间的间距造成影响，由此当需要增加第一触控电极层32和第二触控电极层34之间的绝缘层33的厚度以降低触控电极层32、34之间的寄生电容时，可以避免对液晶电容和存储电容的大小产生影响，能够保证显示品质。
进一步地，阵列基板51还包括钝化层35。第一触控电极层32为阵列基板51的公共电极层。其中，像素电极层31与第二触控电极层34不重叠。像素电极层31与第一触控电极层32部分重叠，其位于第一触控电极层32上。绝缘层33包括多个间隔排列于第一触控电极层32上的绝缘层33，第二触控电极层34位于其中一个绝缘层33上，绝缘层33之间的第一触控电极层32上无绝缘层33。
其中，钝化层35设置在第二触控电极层34、绝缘层33之间的第一触控电极层32以及未被第二触控电极层34覆盖的绝缘层33上。像素电极层31包括多个像素电极条311，多个像素电极条311分别位于绝缘层33之间的钝化层35上，即多个像素电极条311位于直接覆盖在第一触控电极层32上的钝化层35上，且像素电极条311直接与钝化层35接触，从而使得像素电极套311的垂直投影区域内无绝缘层33。
其中，阵列基板51进一步还包括基底36以及依次形成于基底36上的栅极绝缘层37、ILD（Insulator layer，绝缘层）层38、源漏金属层39以及有机绝缘层40。第一触控电极层31形成于有机绝缘层40上。
其中，彩色滤光基板52包括玻璃基底521、形成于玻璃基底上的色阻层，所述色阻层包括红色色阻层、绿色色阻层、蓝色色阻层，每个色阻层对应阵列基板51上的一个像素单元，其中图中仅示出红色色阻层523和绿色色阻层524。彩色滤光基板52还包括位于色阻层之间的黑色矩阵522以及平坦层525。平坦层525为透明平坦层。其中，彩色滤光基板52上还设置有公共电极层（图中未示）。
其中，间隔物531位于黑色矩阵522的垂直投影区域内的液晶层53中。
其中，阵列基板51的第二触控电极层34位于黑色矩阵522的垂直投影区域内。
本实施方式的触摸屏，通过在像素电极层的垂直投影区域不设置有绝缘层33，从而当需要在第一触控电极层32和第二触控电极层34之间设置绝缘层33或者设置不同厚度的绝缘层33，以降低第一触控电极层32和第二触控电极层34之间的寄生电容时，可以避免绝缘层33对液晶电容和存储电容的大小的影响。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种用于触摸屏的阵列基板，其中，包括像素电极层、第一触控电极层以及依次层叠设置在所述第一触控电极层上的绝缘层、第二触控电极层；
    其中所述像素电极层与所述第一触控电极层、所述第二触控电极层中至少一个不重叠，并且至少在所述像素电极层的垂直投影区域无所述绝缘层；
    所述第一触控电极层为公共电极层，所述第二触控电极层位于黑色矩阵的垂直投影区域内。
  2. 根据权利要求1所述的阵列基板，其中，还包括钝化层；
    所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层包括多个间隔排列于所述第一触控电极层上的绝缘层，所述第二触控电极层位于其中一个所述绝缘层，所述钝化层设置在所述第二触控电极层以及绝缘层之间的第一触控电极层上，所述多个像素电极条分别设置在绝缘层之间的所述钝化层上，每个所述像素电极条的垂直投影区域无所述绝缘层。
  3. 根据权利要求1所述的阵列基板，其中，还包括钝化层；
    所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层覆盖部分所述第一触控电极层，所述钝化层设置在所述第二触控电极层以及未被所述绝缘层覆盖的所述第一触控电极层上，所述多个像素电极条设置在所述钝化层上，每个所述像素电极条的垂直投影区域以及像素电极条之间无所述绝缘层。
  4. 一种用于触摸屏的阵列基板，其中，包括像素电极层、第一触控电极层以及依次层叠设置在所述第一触控电极层上的绝缘层、第二触控电极层；
    其中所述像素电极层与所述第一触控电极层、所述第二触控电极层中至少一个不重叠，并且至少在所述像素电极层的垂直投影区域无所述绝缘层。
  5. 根据权利要求4所述的阵列基板，其中，还包括钝化层；
    所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层包括多个间隔排列于所述第一触控电极层上的绝缘层，所述第二触控电极层位于其中一个所述绝缘层，所述钝化层设置在所述第二触控电极层以及绝缘层之间的第一触控电极层上，所述多个像素电极条分别设置在绝缘层之间的所述钝化层上，每个所述像素电极条的垂直投影区域无所述绝缘层。
  6. 根据权利要求4所述的阵列基板，其中，还包括钝化层；
    所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层覆盖部分所述第一触控电极层，所述钝化层设置在所述第二触控电极层以及未被所述绝缘层覆盖的所述第一触控电极层上，所述多个像素电极条设置在所述钝化层上，每个所述像素电极条的垂直投影区域以及像素电极条之间无所述绝缘层。
  7. 根据权利要求4所述的阵列基板，其中，所述第一触控电极层为公共电极层。
  8. 根据权利要求4所述的阵列基板，其中，所述第二触控电极层位于黑色矩阵的垂直投影区域内。
  9. 一种触摸屏，其中，包括阵列基板、彩色滤光基板和位于所述阵列基板和所述彩色滤光基板之间的液晶层，所述阵列基板包括像素电极层、第一触控电极层以及依次层叠设置在所述第一触控电极层上的绝缘层、第二触控电极层；
    其中所述像素电极层与所述第一触控电极层、所述第二触控电极层中至少一个不重叠，并且至少在所述像素电极层的垂直投影区域无所述绝缘层。
  10. 根据权利要求9所述的触摸屏，其中，所述阵列基板还包括钝化层；
    所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层包括多个间隔排列于所述第一触控电极层上的绝缘层，所述第二触控电极层位于其中一个所述绝缘层，所述钝化层设置在所述第二触控电极层以及绝缘层之间的第一触控电极层上，所述多个像素电极条分别设置在绝缘层之间的所述钝化层上，每个所述像素电极条的垂直投影区域无所述绝缘层。
  11. 根据权利要求9所述的触摸屏，其中，所述阵列基板还包括钝化层；
    所述像素电极层与所述第二触控电极层不重叠，所述像素电极层包括多个像素电极条，所述绝缘层覆盖部分所述第一触控电极层，所述钝化层设置在所述第二触控电极层以及未被所述绝缘层覆盖的所述第一触控电极层上，所述多个像素电极条设置在所述钝化层上，每个所述像素电极条的垂直投影区域以及像素电极条之间无所述绝缘层。
  12. 根据权利要求9所述的触摸屏，其中，所述第一触控电极层为公共电极层。
  13. 根据权利要求9所述的触摸屏，其中，所述彩色滤光基板包括黑色矩阵，所述第二触控电极层位于所述黑色矩阵的垂直投影区域内。
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