WO2017119066A1 - 炭化珪素半導体装置 - Google Patents
炭化珪素半導体装置 Download PDFInfo
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- WO2017119066A1 WO2017119066A1 PCT/JP2016/050159 JP2016050159W WO2017119066A1 WO 2017119066 A1 WO2017119066 A1 WO 2017119066A1 JP 2016050159 W JP2016050159 W JP 2016050159W WO 2017119066 A1 WO2017119066 A1 WO 2017119066A1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 description 13
- 239000012535 impurity Substances 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device having a Schottky junction.
- the main part of the SBD has an n + substrate, an n-type buffer layer, an n-type drift layer, a Schottky electrode, and an ohmic electrode.
- the Schottky electrode is provided as an anode electrode on the n-type drift layer.
- the ohmic electrode is provided as a cathode electrode on the n + substrate.
- the present invention has been made to solve the above-described problems, and an object thereof is to provide a silicon carbide semiconductor device capable of further reducing the forward voltage while maintaining a sufficient withstand voltage. It is.
- the silicon carbide semiconductor device of the present invention has a silicon carbide substrate, a first anode electrode, a first cathode electrode, a second anode electrode, and a second cathode electrode.
- the silicon carbide substrate is provided with a first surface and a second surface opposite to the first surface.
- the silicon carbide substrate has an n-type region that connects the first surface and the second surface, and a p-type region that contacts the n-type region and connects the first surface and the second surface.
- the first anode electrode is Schottky joined to the n-type region on the first surface.
- the first cathode electrode is in ohmic contact with the n-type region on the second surface.
- the second anode electrode is in ohmic contact with the p-type region on the first surface.
- the second cathode electrode is Schottky joined to the p-type region on the second surface.
- the forward voltage can be further reduced while maintaining a sufficient withstand voltage.
- FIG. 1 is a cross sectional view schematically showing a configuration of a silicon carbide device in a first embodiment of the present invention. It is sectional drawing which shows schematically the structure of the silicon carbide apparatus in Embodiment 2 of this invention. It is sectional drawing which shows schematically the structure of the silicon carbide apparatus in Embodiment 3 of this invention. It is sectional drawing which shows schematically the structure of the silicon carbide apparatus in Embodiment 4 of this invention. It is sectional drawing which shows schematically the structure of the silicon carbide apparatus in Embodiment 5 of this invention.
- FIG. 1 is a circuit diagram schematically showing a configuration of an equivalent circuit of diode 91 (silicon carbide semiconductor device) of the present embodiment.
- the equivalent circuit of the diode 91 includes an anode terminal AD, a cathode terminal CD, a Schottky barrier diode SBp, and a Schottky barrier diode SBn.
- the anode side of each of Schottky barrier diode SBp and Schottky barrier diode SBn is connected to anode terminal AD.
- the cathode side of each of Schottky barrier diode SBp and Schottky barrier diode SBn is connected to cathode terminal CD.
- the Schottky barrier diode SBp and the Schottky barrier diode SBn are connected in parallel in the same forward direction.
- FIG. 2 is a cross-sectional view schematically showing the configuration of the diode 91.
- Diode 91 has silicon carbide substrate 50, first anode electrode 32, first cathode electrode 31, second anode electrode 41, second cathode electrode 42, and common anode electrode 60. ing.
- the silicon carbide substrate 50 is provided with a first surface S1 and a second surface S2 opposite to the first surface S1.
- the first surface S1 and the second surface S2 are surfaces substantially parallel to each other.
- Silicon carbide substrate 50 has n-type region 10 and p-type region 20.
- the n-type region 10 connects the first surface S1 and the second surface S2.
- n-type region 10 the n - has a region 11 and n + regions 12.
- the impurity concentration of n + region 12 is higher than the impurity concentration of n ⁇ region 11.
- the n ⁇ region 11 is disposed on the first surface S1.
- the n + region 12 is disposed on the second surface S2.
- the p-type region 20 connects the first surface S1 and the second surface S2.
- the p-type region 20 has a p ⁇ region 21 and a p + region 22.
- the impurity concentration of p + region 22 is higher than the impurity concentration of p ⁇ region 21.
- the p ⁇ region 21 is disposed on the second surface S2.
- the p + region 22 is disposed on the first surface S1.
- the p-type region 20 is in contact with the n-type region 10. Specifically, the p ⁇ region 21 is in contact with the n ⁇ region 11. Thereby, a pn junction by the n-type region 10 and the p-type region 20 is provided.
- the pn junction extends along a direction (vertical direction in FIG. 2) intersecting each of the first surface S1 and the second surface S2. As a result, the diode 91 is provided with a so-called super junction structure.
- the first anode electrode 32 is a Schottky electrode and is Schottky joined to the n ⁇ region 11 of the n-type region 10 on the first surface S1.
- the first anode electrode 32 is a conductor layer containing a first metal element, for example, Ti (titanium), and is, for example, a Ti layer.
- the second anode electrode 41 is an ohmic electrode, and is in ohmic contact with the p + region 22 of the p-type region 20 on the first surface S1.
- the second anode electrode 41 is preferably separated from the n-type region 10.
- the second anode electrode 41 is preferably silicided on the first surface S1 in order to obtain a good ohmic junction.
- the second anode electrode 41 may contain a second metal element different from the first metal element, for example, Pt (platinum).
- the second anode electrode 41 is a Pt layer.
- the common anode electrode 60 is in contact with each of the first anode electrode 32 and the second anode electrode 41. Thereby, the common anode electrode 60 has a function as the anode terminal AD (FIG. 1).
- the common anode electrode 60 can be omitted because each of them has a function as the anode terminal AD.
- the first cathode electrode 31 is an ohmic electrode, and is in ohmic contact with the n + region 12 of the n-type region 10 on the second surface S2.
- the first cathode electrode 31 is preferably separated from the p-type region 20.
- the first cathode electrode 31 is preferably silicided on the second surface S2 in order to obtain a good ohmic junction.
- the second cathode electrode 42 is a Schottky electrode and is Schottky joined to the p-type region 20 on the second surface S2.
- the first cathode electrode 31 and the second cathode electrode 42 may contain a common metal element.
- the first cathode electrode 31 may be a Ni (nickel) layer silicided on the second surface S2, and the second cathode electrode 42 may be a Ni layer.
- the first cathode electrode 31 and the second cathode electrode 42 may be connected to each other.
- the Schottky electrode described above can be formed by forming a layer to be a Schottky electrode and heat treatment for sintering of this layer.
- the ohmic electrode described above can be formed by forming a layer to be an ohmic electrode and heat treatment for silicidation of this layer.
- the temperature of the heat treatment for sintering is lower than the temperature of the heat treatment for silicidation.
- the former is about 400 ° C. and the latter is about 1100 ° C.
- the heat treatment for sintering of the layer serving as the Schottky electrode may be performed on both the layer serving as the Schottky electrode and the layer serving as the ohmic electrode.
- the heat treatment for silicidation of the layer serving as the ohmic electrode is performed only on the layer serving as the ohmic electrode and not performed on the layer serving as the Schottky electrode.
- a super junction structure with a pn junction between n-type region 10 and p-type region 20 is provided.
- the depletion layer can also extend in the lateral direction (the direction perpendicular to the thickness direction of silicon carbide substrate 50). Therefore, even if the impurity concentration of n-type region 10 and p-type region 20 as the drift layer, that is, n ⁇ region 11 and p ⁇ region 21 is increased to some extent, a sufficient withstand voltage can be ensured.
- the resistance (differential resistance) of the drift layer with respect to the forward current is reduced.
- Each of n-type region 10 and p-type region 20 constitutes Schottky barrier diode SBn and Schottky barrier diode SBp (FIG. 1).
- n-type region 10 and p-type region 20 constitutes Schottky barrier diode SBn and Schottky barrier diode SBp (FIG. 1).
- the second anode electrode 41 may contain a second metal element different from the first metal element contained in the first anode electrode 32.
- the physical properties of the material of the first anode electrode that requires a Schottky junction with the n-type semiconductor and the physical properties of the material of the second anode electrode that requires an ohmic junction with the n-type semiconductor are further improved. Can be optimized.
- the first cathode electrode 31 and the second cathode electrode 42 may contain a common metal element.
- the process for forming the first cathode electrode 31 and the second cathode electrode 42 is simplified. Specifically, the deposition process for forming the first cathode electrode 31 and the second cathode electrode 42 can be performed collectively.
- the first anode electrode 32 and the second anode electrode 41 are short-circuited with each other, and the first cathode electrode 31 and the second cathode electrode 42 are short-circuited with each other. ing.
- these short circuits may be ensured when the diode 91 is used. Since first anode electrode 32 and second anode electrode 41 are arranged on first surface S1 which is the same surface of the same silicon carbide substrate 50, they can be easily short-circuited. Since first cathode electrode 31 and second cathode electrode 42 are arranged on second surface S2 which is the same surface of the same silicon carbide substrate 50, they can be easily short-circuited.
- the electrodes separated from each other as described above can be short-circuited to each other by being mounted on a common conductor member.
- these electrodes can be short-circuited to each other by being electrically bonded to a common conductor member. Therefore, as a modification of the diode 91, the first anode electrode 32 and the second anode electrode 41 that are separated from each other may be provided while the common anode electrode 60 is omitted. Alternatively or simultaneously, the first cathode electrode 31 and the second cathode electrode 42 that are separated from each other may be provided. The same applies to other embodiments.
- FIG. 3 is a cross sectional view schematically showing a configuration of diode 92 (silicon carbide semiconductor device) of the present embodiment.
- Diode 92 has p-type well 14 in silicon carbide substrate 50.
- the p-type well 14 partially forms the first surface S1 on the n ⁇ region 11 of the n-type region 10. Therefore, the first anode electrode 32 is in contact with the p-type well 14 in addition to the n ⁇ region 11.
- the p-type well 14 can be formed by selective impurity implantation using an implantation mask on the n ⁇ region 11 of the n-type region 10.
- the impurity concentration profile of the p-type well 14 in the depth direction may be substantially the same as that of the p + region 22. In this case, the p-type well 14 and the p + region 22 can be formed collectively.
- FIG. 4 is a cross sectional view schematically showing a configuration of diode 93 (silicon carbide semiconductor device) of the present embodiment.
- Diode 93 has n-type well 24 in silicon carbide substrate 50.
- the n-type well 24 partially forms the second surface S2 on the p ⁇ region 21 of the p-type region 20. Therefore, the second cathode electrode 42 is in contact with the n-type well 24 in addition to the p ⁇ region 21.
- the n-type well 24 can be formed by selective impurity implantation using an implantation mask on the p ⁇ region 21 of the p-type region 20.
- the impurity concentration profile of the n-type well 24 in the depth direction may be substantially the same as that of the n + region 12. In this case, the n-type well 24 and the n + region 12 can be formed collectively.
- the n-type well 24 is used instead of the Schottky junction between the second cathode electrode 42 and the p ⁇ region 21. Current flows.
- the I 2 t resistance (inrush current resistance) determined by I F ⁇ V F can be increased.
- a p-type well 14 (FIG. 3: Embodiment 2) may be provided. In this case, the above-described effect is further enhanced.
- FIG. 5 is a cross sectional view schematically showing a configuration of diode 94 (silicon carbide semiconductor device) of the present embodiment.
- the p-type region 20 has a width smaller than the width of the n-type region 10 (the dimension in the horizontal direction in the drawing, in other words, the dimension in the direction orthogonal to the thickness direction).
- the p-type region 20 can have an area smaller than the area of the n-type region 10 in plan view. In other words, the effective area of the p-type region 20 is smaller than the effective area of the n-type region 10.
- the width of the p-type region 20 is not excessively small. Specifically, the width of the p-type region 20 is preferably larger than the distance that the depletion layer extends in the p ⁇ region 21 when a reverse bias is applied, and is more than about three times this distance in consideration of variation. Is more preferable.
- the width of the p-type region 20 is made smaller than the width of the n-type region 10.
- FIG. 6 is a cross sectional view schematically showing a configuration of diode 95 (silicon carbide semiconductor device) of the present embodiment.
- the second anode electrode 41 has an area larger than the area of the second cathode electrode 42. Since the other configuration is almost the same as the configuration of any of Embodiments 1 to 3 described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.
- the p + region 22 and the second anode electrode 41 in the p-type region 20 are compared to the Schottky connection region formed by the p ⁇ region 21 and the second cathode electrode 42 in the p-type region 20.
- the ohmic connection area by is wider.
- the area of the second cathode electrode 42 may be smaller than the area of the first anode electrode 32. In this case, recovery loss can be further reduced by the same operation as that described in the fourth embodiment.
Abstract
Description
図1は、本実施の形態のダイオード91(炭化珪素半導体装置)の等価回路の構成を概略的に示す回路図である。ダイオード91の等価回路は、アノード端子ADと、カソード端子CDと、ショットキーバリアダイオードSBpと、ショットキーバリアダイオードSBnとを有している。ショットキーバリアダイオードSBpおよびショットキーバリアダイオードSBnの各々のアノード側はアノード端子ADに接続されている。ショットキーバリアダイオードSBpおよびショットキーバリアダイオードSBnの各々のカソード側はカソード端子CDに接続されている。言い換えれば、ショットキーバリアダイオードSBpおよびショットキーバリアダイオードSBnは、同一の順方向で並列接続されている。
図3は、本実施の形態のダイオード92(炭化珪素半導体装置)の構成を概略的に示す断面図である。ダイオード92は、炭化珪素基板50中にp型ウェル14を有している。p型ウェル14は、n型領域10のn-領域11上において、第1の面S1を部分的になしている。よって第1のアノード電極32は、n-領域11に加えてp型ウェル14にも接している。p型ウェル14は、n型領域10のn-領域11上における、注入マスクを使用した選択的な不純物注入によって形成し得る。深さ方向におけるp型ウェル14の不純物濃度プロファイルは、p+領域22とほぼ同様であってもよい。この場合、p型ウェル14とp+領域22とを一括して形成し得る。
図4は、本実施の形態のダイオード93(炭化珪素半導体装置)の構成を概略的に示す断面図である。ダイオード93は、炭化珪素基板50中にn型ウェル24を有している。n型ウェル24は、p型領域20のp-領域21上において、第2の面S2を部分的になしている。よって第2のカソード電極42は、p-領域21に加えてn型ウェル24にも接している。n型ウェル24は、p型領域20のp-領域21上における、注入マスクを使用した選択的な不純物注入によって形成し得る。深さ方向におけるn型ウェル24の不純物濃度プロファイルは、n+領域12とほぼ同様であってもよい。この場合、n型ウェル24とn+領域12とを一括して形成し得る。
図5は、本実施の形態のダイオード94(炭化珪素半導体装置)の構成を概略的に示す断面図である。ダイオード94においては、p型領域20は、n型領域10の幅よりも小さい幅(図中の横方向における寸法、言い換えれば、厚み方向に直交する方向における寸法)を有している。この構成により、平面視において、p型領域20は、n型領域10の面積よりも小さい面積を有し得る。言い換えれば、p型領域20の有効面積は、n型領域10の有効面積よりも小さい。
図6は、本実施の形態のダイオード95(炭化珪素半導体装置)の構成を概略的に示す断面図である。ダイオード95においては、第2のアノード電極41は、第2のカソード電極42の面積よりも大きい面積を有している。なお、それ以外の構成については、上述した実施の形態1~3のいずれかの構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。
Claims (7)
- 第1の面(S1)と前記第1の面(S1)と反対の第2の面(S2)とが設けられ、前記第1の面(S1)と前記第2の面(S2)とをつなぐn型領域(10)と、前記n型領域(10)と接し前記第1の面(S1)と前記第2の面(S2)とをつなぐp型領域(20)と、を有する炭化珪素基板(50)と、
前記第1の面(S1)上で前記n型領域(10)にショットキー接合された第1のアノード電極(32)と、
前記第2の面(S2)上で前記n型領域(10)にオーミック接合された第1のカソード電極(31)と、
前記第1の面(S1)上で前記p型領域(20)にオーミック接合された第2のアノード電極(41)と、
前記第2の面(S2)上で前記p型領域(20)にショットキー接合された第2のカソード電極(42)と、
を備える、
炭化珪素半導体装置(91~95)。 - 前記n型領域(10)上において前記第1の面(S1)を部分的になすp型ウェル(14)をさらに備える、請求項1に記載の炭化珪素半導体装置(92)。
- 前記p型領域(20)上において前記第2の面(S2)を部分的になすn型ウェル(24)をさらに備える、請求項1または2に記載の炭化珪素半導体装置(93)。
- 前記p型領域(20)は、前記n型領域(10)の幅よりも小さい幅を有する、請求項1から3のいずれか1項に記載の炭化珪素半導体装置(94)。
- 前記第2のアノード電極は、前記第2のカソード電極の面積よりも大きい面積を有している、請求項1から4のいずれか1項に記載の炭化珪素半導体装置(95)。
- 前記第1のアノード電極(32)は第1の金属元素を含有しており、前記第2のアノード電極(41)は、前記第1の金属元素と異なる第2の金属元素を含有している、請求項1から5のいずれか1項に記載の炭化珪素半導体装置(91~95)。
- 前記第1のカソード電極(31)および前記第2のカソード電極(42)は共通の金属元素を含有している、請求項1から6のいずれか1項に記載の炭化珪素半導体装置(91~95)。
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