WO2017118092A1 - 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 - Google Patents

移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 Download PDF

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WO2017118092A1
WO2017118092A1 PCT/CN2016/099287 CN2016099287W WO2017118092A1 WO 2017118092 A1 WO2017118092 A1 WO 2017118092A1 CN 2016099287 W CN2016099287 W CN 2016099287W WO 2017118092 A1 WO2017118092 A1 WO 2017118092A1
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Prior art keywords
signal
transistor
control signal
terminal
node
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PCT/CN2016/099287
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English (en)
French (fr)
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孙拓
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京东方科技集团股份有限公司
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Priority to US15/520,789 priority Critical patent/US10109238B2/en
Publication of WO2017118092A1 publication Critical patent/WO2017118092A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a scan driving circuit, and a display device.
  • a typical active matrix light emitting diode (AMOLED) pixel circuit is shown in FIG.
  • the first scanning signal line S1 controls the transistor T1 to be turned on, and the data line Dm writes the data voltage to the gate of the driving transistor Td through the transistor T1.
  • the second scan signal line S2 supplies a single-pulse signal corresponding to the pulse width of the clock signal to the gate of the switching transistor T2 to drive the switching transistor T2 to be turned on for the time corresponding to the pulse width.
  • the current flowing through the driving transistor Td and the switching transistor T2 can drive the OLED to emit light.
  • the adjustment of the brightness gray scale can be achieved by adjusting the data voltage. However, there may be a large error between the adjusted grayscale value and the desired grayscale value, thereby affecting the display effect.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a scan driving circuit, and a display device.
  • the proposed scan driving circuit can be used to control the illumination duration of the OLED in the OLED display panel, thereby adjusting the brightness of the displayed image.
  • a shift register unit comprising: a first control signal end for receiving a first control signal; a second control signal end for receiving a second control signal; a first clock signal End, for receiving the first clock signal; the second clock signal end is for receiving the second clock signal; the first voltage end is for receiving the first voltage; the second voltage end is for receiving the second voltage; a signal output end and a second signal output terminal; the first control module operable to be responsive to the first control signal, the second control signal, the first clock signal, the second clock signal, and a first voltage and a) outputting a signal synchronized with the second clock signal to the second signal output during a duration, and b) generating a first internal control signal at the first node; the first output Mode a block operable to output the first voltage to the first signal output for the duration of time in response to the first internal control signal; the second control module operable to respond to a second control signal, the first clock signal, the second clock signal, the first voltage, and
  • the first control module is configured to adjust the duration according to a length of a time period in which the first control signal and the second control signal are active.
  • the first output module includes a first transistor having a gate connected to the first node, a first pole connected to the first voltage terminal, and a first signal coupled to the first signal The second pole of the output.
  • the second output module includes a second transistor having a gate coupled to the second node, a first pole coupled to the second voltage terminal, and coupled to the first signal The second pole of the output.
  • the first control module includes: a third transistor having a gate connected to the first clock signal end, a first pole connected to the first control signal end, and a third node connected a second transistor having a gate connected to the third node, a first pole connected to the first voltage terminal, and a second pole connected to the fourth node; and a sixth transistor having a connection a gate to the first clock signal terminal, a first pole connected to the second control signal terminal, and a second pole connected to the fourth node; a seventh transistor having a connection to the fourth node a gate, a first pole connected to the first voltage terminal, and a second pole connected to the second signal output; an eighth transistor having a gate connected to the third node, connected to the first a first pole of the second clock signal end and a second pole connected to the second signal output terminal; a ninth transistor having a gate connected to the second clock signal end and a first connected to the second signal output end pole And a second pole connected to the first node; a third capacitor having one end connected to the first clock
  • the second control module includes: a fourth transistor having a gate connected to the first clock signal terminal, a first pole connected to the second control signal terminal, and connected to the first a second pole of the two nodes; a tenth transistor having a gate connected to the first node, a first pole connected to the first voltage terminal, and a second pole connected to the second node; And a second capacitor having one end connected to the second clock signal end and the other end connected to the second node.
  • a scan driving circuit comprising a plurality of stages of shift register units as described in the first aspect.
  • a first control signal end of the first stage shift register unit is configured to receive a first start signal
  • a second control signal end of the first stage shift register unit is configured to receive a second start signal
  • a first control signal terminal of each stage shift register unit other than the first stage shift register unit is coupled to a second signal output terminal of the upper stage shift register unit; and in addition to the first stage shift register unit
  • the second control signal end of each stage of the shift register unit is connected to the first signal output end of the upper stage shift register unit.
  • a display device comprising: a display panel including a plurality of pixel units arranged in an array, each of the pixel units including a pixel circuit, the pixel circuit including a light emitting device And a switching transistor having a gate and configured to allow a driving current to flow through the light emitting device depending on a voltage applied to the gate; and a scan driving circuit as described in the second aspect.
  • a first signal output of each stage of the shift register unit in the scan drive circuit is coupled to a gate of a switch transistor in a corresponding row of pixel cells in the array.
  • a method of driving a shift register unit including a first signal output and a second signal output
  • the method comprising: responsive to the first control signal a second control signal, a first clock signal, a second clock signal, and a first voltage, outputting a signal synchronized with the second clock signal to the second signal output terminal and generating a first internal control signal; Outputting the first voltage to the first signal output terminal in response to the first internal control signal; responsive to the second control signal, the first clock signal, the second clock signal, the first Generating a second internal control signal with the voltage and the first internal control signal; and outputting a second voltage to the first signal output in response to the second internal control signal.
  • outputting a signal synchronized with the second clock signal to the second signal output and outputting the first voltage to the first signal output is simultaneous Start and terminate.
  • the output of the signal synchronized with the second clock signal to the output of the second signal and the output of the first voltage output to the first signal output are maintained for a duration.
  • the method further comprises adjusting the duration by changing a length of a time period in which the first control signal and the second control signal are active.
  • FIG. 1 is a schematic circuit diagram of a prior art pixel circuit
  • FIG. 2 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 3 is an exemplary circuit diagram of the shift register unit shown in FIG. 2;
  • FIG. 4 is a timing diagram of a circuit of the shift register unit shown in FIG. 3;
  • FIG. 5 is a schematic block diagram of a scan driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of a method of driving a shift register unit in accordance with an embodiment of the present disclosure.
  • FIG. 2 is a schematic block diagram of a shift register unit 200 in accordance with an embodiment of the present disclosure.
  • the shift register unit 200 includes a first control signal terminal STV1 for receiving a first control signal, a second control signal terminal STV2 for receiving a second control signal, and a second for receiving a first clock signal.
  • the shift register unit 200 further includes a first output module 10.
  • the first control module 30 is operable to output to the second signal output terminal OUTPUT2 during a duration in response to the first control signal, the second control signal, the first clock signal, the second clock signal, and the first voltage A signal synchronized with the second clock signal CKB, and b) a first internal control signal is generated at the first node (not shown in FIG. 2).
  • the first control module 30 is configured to adjust the duration according to the length of the time period in which the first control signal and the second control signal are active.
  • the first output module 10 is operative to output a first voltage to the first signal output terminal OUTPUT1 for the duration of time in response to the first internal control signal.
  • the second control module 40 is operative to be in the second node in response to the second control signal, the first clock signal, the second clock signal, the first voltage, and the first internal control signal A second internal control signal is generated at 2 not shown).
  • the second output module 20 is operative to output the second voltage to the first signal output terminal OUTPUT1 at the end of the duration in response to the second internal control signal.
  • shift register unit 200 The details of the shift register unit 200 are described in detail below with reference to FIGS. 3 and 4.
  • FIG. 3 is an exemplary circuit diagram of the shift register unit 200 shown in FIG. 2.
  • the first output module 10 includes a first transistor M1.
  • the first transistor M1 has a gate connected to the first node B, a first pole connected to the first voltage terminal VGH, and a second pole connected to the first signal output terminal OUTPUT1.
  • the voltage signal at the first node B is the first internal control signal.
  • the first output module 10 may further include one or more transistors in parallel with the first transistor M1, and/or one or more capacitors in parallel with the first capacitor C1.
  • the second output module 20 includes a second transistor M2.
  • the second transistor M2 has a gate connected to the second node C, a first pole connected to the second voltage terminal VGL, and a second pole connected to the first signal output terminal OUTPUT1.
  • the voltage signal at the second node C is a second internal control signal.
  • the second output module 20 may further include one or more transistors in parallel with the second transistor M2, and/or one or more capacitors in parallel with the second capacitor C2.
  • the first control module 30 includes a third transistor M3, a fifth transistor M5, and a sixth crystal
  • the third transistor M3 has a gate connected to the first clock signal terminal CK, a first pole connected to the first control signal terminal STV1, and a second pole connected to the third node D.
  • the fifth transistor M5 has a gate connected to the third node D, a first pole connected to the first voltage terminal VGH, and a second pole connected to the fourth node E.
  • the sixth transistor M6 has a gate connected to the first clock signal terminal CK, a first pole connected to the second control signal terminal STV2, and a second pole connected to the fourth node E.
  • the seventh transistor M7 has a gate connected to the fourth node E, a first pole connected to the first voltage terminal VGH, and a second pole connected to the second signal output terminal OUTPUT2.
  • the second signal output terminal OUTPUT2 is shown as being drawn from the node A.
  • the eighth transistor M8 has a gate connected to the third node D, a first pole connected to the second clock signal terminal CKB, and a second pole connected to the second signal output terminal OUTPUT2.
  • the ninth transistor M9 has a first pole connected to the second clock signal CKB gate, connected to the second signal output terminal OUTPUT2, and a second pole connected to the first node B.
  • the third capacitor C3 has one end connected to the third node D and the other end connected to the second signal output terminal OUTPUT2.
  • the fourth capacitor C4 has one end connected to the first voltage terminal VGH and the other end connected to the fourth node E.
  • the first capacitor C1 has one end connected to the first voltage terminal VGH and the other end connected to the first node B.
  • the first control module 30 may further include a plurality of transistors respectively connected in parallel with the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9, and/or A plurality of capacitors respectively connected in parallel with the third capacitor C3, the fourth capacitor C4, and the first capacitor C1.
  • the second control module 40 includes a fourth transistor M4, a tenth transistor M10, and a second capacitor C2.
  • the fourth transistor M4 has a gate connected to the first clock signal terminal CK, a first pole connected to the second control signal terminal STV2, and a second pole connected to the second node C.
  • the tenth transistor M10 has a gate connected to the first node B, a first pole connected to the first voltage terminal VGH, and a second pole connected to the second node C.
  • the second capacitor C2 has one end connected to the second clock signal terminal CKB and the other end connected to the second node C.
  • the second control module 40 may further include multiple A transistor in which the fourth transistor M4 and the tenth transistor M10 are connected in parallel.
  • each transistor is shown as a P-type transistor, and the first voltage terminal VGH is supplied with a high level and the second voltage terminal VGL is supplied with a low level.
  • the gate-on voltage for turning on the P-type transistor is a low level, and the gate-off voltage for turning off the P-type transistor is a high level.
  • each transistor can be an N-type transistor.
  • the gate-on voltage for turning on the N-type transistor is a high level, and the gate-off voltage for turning off the N-type transistor is a low level.
  • the transistors are typically fabricated such that their first and second poles are used interchangeably.
  • FIG. 4 is a timing diagram of a circuit of the shift register unit shown in FIG.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on.
  • the low level of the first control signal terminal STV1 is transmitted to the third node D through the third transistor M3.
  • the eighth transistor M8 and the fifth transistor M5 are turned on, and the third capacitor C3 stores the low level of the third node D.
  • the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5.
  • the high level of the second control signal terminal STV2 is transmitted to the gates of the fourth node E and the seventh transistor M7 through the sixth transistor M6, and thus the seventh transistor M7 is turned off.
  • the high level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
  • the ninth transistor M9 is turned off due to the high level of the second clock signal terminal CKB.
  • the first capacitor C1 outputs the high level stored at the end of the previous cycle to the gates of the first and third tenth transistors M1 and M10 and the first node B, and thus the first and fourth transistors M1 and M10 are turned off.
  • the fourth transistor M4 Since the fourth transistor M4 is turned on, the high level of the second control signal terminal STV2 is transmitted to the second node C through the fourth transistor M4, and is stored by the second capacitor C2. Under the control of the second node C, the second transistor M2 is turned off.
  • the first signal output terminal OUTPUT1 maintains a low level at the end of the previous cycle.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
  • the second capacitor C2 outputs the high level stored in the previous stage to the gate of the second transistor M2, and thus the second transistor M2 is turned off.
  • the low level stored in one stage of the third capacitor C3 causes the third node D to remain at a low level, and thus the fifth transistor M5 and the eighth transistor M8 remain in an on state.
  • the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5, and thus the seventh transistor M7 is turned off.
  • the low level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
  • the ninth transistor M9 is turned on, and the low level at the node A is transferred to the gate of the first transistor M1 and the first node B.
  • the first capacitor C1 stores the low level.
  • the first transistor M1 is turned on, and transmits a high level of the first voltage terminal VGH to the first signal output terminal OUTPUT1.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on.
  • the low level of the first control signal terminal STV1 is output to the third node D through the third transistor M3.
  • the eighth transistor M8 and the fifth transistor M5 are turned on.
  • the third capacitor C3 stores the low level of the third node D.
  • the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5.
  • the high level of the second control signal terminal STV2 is transmitted to the gates of M7 of the fourth node and the seventh transistor through the sixth transistor M6, and thus the seventh transistor M7 is turned off.
  • the high level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
  • the ninth transistor M9 is turned off due to the high level of the second clock signal terminal CKB.
  • Node B is at a low level due to the low level stored by the first capacitor C1.
  • the tenth transistor M10 and the first transistor M1 are turned on.
  • the high level of the first voltage terminal VGH is transmitted to the second node C through the tenth transistor M10, and is transmitted to the first signal output terminal OUTPUT1 through the first transistor M1.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
  • the low level stored by the third capacitor C3 causes the third node D to be at a low level.
  • the eighth transistor M8 and the fifth transistor M5 are turned on.
  • the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5, and thus the seventh transistor M7 is turned off.
  • the low level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
  • the ninth transistor M9 Since the second clock signal terminal CKB is at a low level, the ninth transistor M9 is turned on. The low level at the node A is caused to be transmitted through the ninth transistor M9 to the tenth transistor M10 and the gate of the first transistor M1 and the first node B. The first capacitor C1 stores the low level. The tenth transistor M10 is turned on, and transmits a high level of the first voltage terminal VGH to the gate of the second transistor M2, so that the second transistor M2 is turned off. The high level of the first voltage terminal VGH is transmitted to the first signal output terminal OUTPUT1 through the first transistor M1.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on.
  • the high level of the first control signal terminal STV1 is transmitted to the third node D through the third transistor M3.
  • the third capacitor C3 stores the high level.
  • the fifth transistor M5 and the eighth transistor M8 are turned off.
  • the sixth transistor M6 is turned on, the low level of the second control signal terminal STV2 is transmitted to the gates of the fourth node E and the seventh transistor M7 through the sixth transistor M6, and thus the seventh transistor M7 is turned on.
  • the fourth capacitor C4 stores the low level.
  • the high level of the first voltage terminal VGH is transmitted to the node A and the second signal output terminal OUTPUT2 through the seventh transistor M7.
  • the ninth transistor M9 Since the second clock signal terminal CKB is at the high level, the ninth transistor M9 is turned off.
  • the low level stored by the first capacitor C1 causes the tenth transistor M10 and the first transistor M1 to be turned on.
  • the high level of the first voltage terminal VGH is transmitted to the second node C through the tenth transistor M10, and the low level of the second signal control terminal STV2 is transmitted to the node C through the fourth transistor M4, so that the potential of the node C is located at the high voltage.
  • the high level of the first voltage terminal VGH is transmitted to the first signal output terminal OUTPUT1 through the first transistor M1.
  • the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
  • the high level stored by the third capacitor C3 causes the node D to be at a high level.
  • the fifth transistor M5 and the eighth transistor M8 are turned off.
  • the low level stored by the fourth capacitor C4 turns on the seventh transistor M7.
  • the high level of the first voltage terminal VGH is transmitted to the node A and the second signal output terminal OUTPUT2 through the seventh transistor M7.
  • the ninth transistor M9 Since the second clock signal terminal CKB is at a low level, the ninth transistor M9 is turned on, and the high level at the node A is transferred to the gates of the first transistor M1 and the tenth transistor M10, so that the first transistor M1 and The tenth transistor M10 is turned off.
  • the low level of the second clock signal terminal CKB is pulled down the potential of the node C to turn on the second transistor M2.
  • the low level of the second voltage terminal VGL is output through the second transistor M2 To the first signal output terminal OUTPUT1.
  • the first signal output terminal OUTPUT1 remains output low until the second phase of the next cycle.
  • the first signal output terminal OUTPUT1 outputs a high level signal
  • the second signal output terminal OUTPUT2 outputs a signal synchronized with the second clock signal CKB ( They have the same waveform). This is achieved by means of the operation of the first control module 30 of the shift register unit shown in FIG.
  • the operations of the second phase P2 and the third phase P3 may be alternately repeated such that the duration can be adjusted by changing the number of the second phase P2 and the third phase P3 included in the first control signal STV1 and the second control signal STV2 .
  • the first control signal STV1 and the second control signal STV2 can be considered to be valid during the period from the first phase P1 to the last third phase P3.
  • the effective first control signal STV1 is a square wave signal, and the effective second control signal STV2 is at the level of the first voltage.
  • the high level signal output by the first output terminal OUTPUT1 can be used to drive OLED illumination in the pixel circuit. That is, the luminescence duration of the OLED can be adjusted by changing the length of the period in which the first control signal STV1 and the second control signal STV2 are valid. The more the second phase P2 and the third phase P3 are repeated, the longer the duration of the first signal output terminal OUTPUT1 outputting the high level signal, and the longer the OLED is illuminated. Thereby, the image can be displayed with an adjustable brightness.
  • the adjustment of the duration of illumination can also be combined with the adjustment of the voltage to provide a flexible and fine adjustment of the brightness.
  • FIG. 5 is a schematic block diagram of a scan driving circuit 500 in accordance with an embodiment of the present disclosure.
  • the scan driving circuit 500 includes multi-stage shift register units SR1, SR2, ..., SRn-1, SRn, each of which may be the shift register unit 200 as described above.
  • the first signal output terminal OUTPUT1 of the shift register units SR1, SR2, ... SRn-1, SRn provides output signals to the control lines EM1, EM2, ..., EMn-1, EMn, respectively.
  • the details of the shift register unit 200 are described in detail in the above embodiments, and are omitted here for the sake of simplicity.
  • the first control signal terminal STV1 of the first stage shift register unit SR1 is for receiving the first start signal
  • the second control signal terminal STV2 of the first stage shift register unit SR1 For receiving the second control signal.
  • the first control signal terminal STV1 of each of the shift register units SR2...SRn-1, SRn other than the first stage shift register unit SR1 is connected to the second signal output terminal OUTPUT2 of the previous stage shift register unit .
  • the second control signal terminal STV2 of each of the shift register units SR2...SRn-1, SRn other than the first stage shift register unit SR1 is connected to the first signal output terminal OUTPUT1 of the shift register unit of the previous stage .
  • the second signal output terminal OUTPUT2 of the last stage shift register unit SRn is vacant.
  • FIG. 6 is a schematic diagram of a display device 600 in accordance with an embodiment of the present disclosure.
  • the display device 600 includes a display panel 610 including a plurality of pixel units 611.
  • Each of the pixel units 611 includes a light emitting device and a switching transistor having a gate and configured to allow a driving current to flow through the light emitting device depending on a voltage applied to the gate.
  • each of the pixel units 611 may include, for example, a pixel circuit as shown in FIG. 1.
  • the pixel circuit includes a driving transistor Td, a switching transistor T2, and a light emitting device OLED connected in series. In the example of FIG. 6, the remaining components within pixel unit 611 are not shown for simplicity.
  • Display device 600 also includes scan drive circuit 500 as described in the above embodiments.
  • the first signal output terminal OUTPUT1 of each of the shift register units SR1, SR2, ..., SRn-1, SRn in the scan driving circuit 500 is connected to the gate of the switching transistor T2 in the corresponding row of pixel cells.
  • the first signal output terminal OUTPUT1 of the first stage shift register unit SR1 is connected to the gate of the switching transistor T2 in the first row of pixel cells through the control line EM1, and the second stage shift register unit SR2
  • the first signal output terminal OUTPUT1 is connected to the gate of the switching transistor T2 in the second row of pixel cells through the control line EM2, and so on.
  • examples of the display device include any display device based on an organic light emitting diode, such as a television, a digital photo frame, a mobile phone, or a tablet.
  • FIG. 7 is a flow diagram of a method 700 of driving a shift register unit, which may be the shift register unit 200 described above in connection with FIGS. 2-4, in accordance with an embodiment of the present disclosure.
  • a signal synchronized with the second clock signal is output to the second signal output in response to the first control signal, the second control signal, the first clock signal, the second clock signal, and the first voltage And generating a first internal control signal.
  • the first voltage is output to the first signal output in response to the first internal control signal.
  • a second internal control signal is generated in response to the second control signal, the first clock signal, the second clock signal, the first voltage, and the first internal control signal.
  • a second voltage is output to the first signal output in response to the second internal control signal.

Abstract

一种移位寄存器单元（200）及其驱动方法、扫描驱动电路（500）和显示装置（600），移位寄存器单元（200）包括：第一控制模块（30），可操作用于a）在一持续时间期间向第二信号输出端（OUTPUT2）输出与第二时钟信号（CKB）同步的信号，并且b）生成第一内部控制信号；第一输出模块（10），可操作用于响应于所述第一内部控制信号而在所述持续时间内将第一电压（VGH）输出至第一信号输出端（OUTPUT1）；第二控制模块（40），可操作用于生成第二内部控制信号；以及第二输出模块（20），可操作用于响应于所述第二内部控制信号而在所述持续时间结束时将第二电压（VGL）输出至所述第一信号输出端（OUTPUT1）。

Description

移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法、扫描驱动电路、显示装置。
背景技术
一种典型的有源矩阵发光二极管(AMOLED)像素电路如图1所示。在数据写入阶段，第一扫描信号线S1控制晶体管T1导通，并且数据线Dm通过晶体管T1将数据电压写入驱动晶体管Td的栅极。在发光阶段，第二扫描信号线S2向开关晶体管T2的栅极提供一个与时钟信号的脉冲宽度相当的单脉冲信号，以驱动该开关晶体管T2在上述脉冲宽度对应的时间内导通。在此情况下，流过驱动晶体管Td和开关晶体管T2的电流能够驱动OLED发光。
可以通过调节数据电压来实现亮度灰阶的调节。然而，调节后的灰阶值与期望的灰阶值之间可能具有较大的误差，从而影响显示效果。
因此，需要一种用于调节显示面板所显示的图像的亮度的替换方案。
发明内容
本公开的实施例提供一种移位寄存器单元及其驱动方法、扫描驱动电路、显示装置。所提出的扫描驱动电路可以用于控制OLED显示面板中的OLED的发光时长，从而调节所显示图像的亮度。
根据本公开的第一方面，提供一种移位寄存器单元，包括：第一控制信号端，用于接收第一控制信号；第二控制信号端，用于接收第二控制信号；第一时钟信号端，用于接收第一时钟信号；第二时钟信号端，用于接收第二时钟信号；第一电压端，用于接收第一电压；第二电压端，用于接收第二电压；第一信号输出端和第二信号输出端；第一控制模块，可操作用于响应于所述第一控制信号、所述第二控制信号、所述第一时钟信号、所述第二时钟信号以及所述第一电压而a)在一持续时间期间向所述第二信号输出端输出与所述第二时钟信号同步的信号，并且b)在第一节点处生成第一内部控制信号；第一输出模 块，可操作用于响应于所述第一内部控制信号而在所述持续时间内将所述第一电压输出至所述第一信号输出端；第二控制模块，可操作用于响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而在第二节点处生成第二内部控制信号；以及第二输出模块，可操作用于响应于所述第二内部控制信号而在所述持续时间结束时将所述第二电压输出至所述第一信号输出端。
在一些实施例中，所述第一控制模块被配置成根据其中所述第一控制信号和所述第二控制信号为有效的时间段的长度来调节该持续时间。
在一些实施例中，所述第一输出模块包括第一晶体管，其具有连接到所述第一节点的栅极、连接到所述第一电压端的第一极、以及连接到所述第一信号输出端的第二极。
在一些实施例中，所述第二输出模块包括第二晶体管，其具有连接到所述第二节点的栅极、连接到所述第二电压端的第一极、以及连接到所述第一信号输出端的第二极。
在一些实施例中，所述第一控制模块包括：第三晶体管，具有连接到所述第一时钟信号端的栅极、连接到所述第一控制信号端的第一极、以及连接到第三节点的第二极；第五晶体管，具有连接到所述第三节点的栅极、连接到所述第一电压端的第一极、以及连接到第四节点的第二极；第六晶体管，具有连接到所述第一时钟信号端的栅极、连接到所述第二控制信号端的第一极、以及连接到所述第四节点的第二极；第七晶体管，具有连接到所述第四节点的栅极、连接到所述第一电压端的第一极、以及连接到所述第二信号输出端的第二极；第八晶体管，具有连接到所述第三节点的栅极、连接到所述第二时钟信号端的第一极、以及连接到所述第二信号输出端的第二极；第九晶体管，具有连接到所述第二时钟信号端的栅极、连接到所述第二信号输出端的第一极、以及连接到所述第一节点的第二极；第三电容，具有连接到所述第三节点的一端和连接到所述第二信号输出端的另一端；第四电容，具有连接到所述第一电压端的一端和连接到所述第四节点的另一端；以及第一电容，具有连接到所述第一电压端的一端和连接到所述第一节点的另一端。
在一些实施例中，所述第二控制模块包括：第四晶体管，具有连接到所述第一时钟信号端的栅极、连接到所述第二控制信号端的第一极、以及连接到所述第二节点的第二极；第十晶体管，具有连接到所述第一节点的栅极、连接到所述第一电压端第一极、以及连接到所述第二节点的第二极；以及第二电容，具有连接到所述第二时钟信号端的一端和连接到所述第二节点的另一端。
根据本公开的第二方面，提供了一种扫描驱动电路，包括多级如第一方面中所述的移位寄存器单元。第一级移位寄存器单元的第一控制信号端被配置用于接收第一起始信号，并且第一级移位寄存器单元的第二控制信号端被配置用于接收第二起始信号；除所述第一级移位寄存器单元以外的每一级移位寄存器单元的第一控制信号端连接上一级移位寄存器单元的第二信号输出端；并且除所述第一级移位寄存器单元以外的每一级移位寄存器单元的第二控制信号端连接上一级移位寄存器单元的第一信号输出端。
根据本公开的第三方面，提供了一种显示装置，包括：显示面板，包括布置在阵列中的多个像素单元，所述像素单元中的每个包括像素电路，所述像素电路包括发光器件和开关晶体管，所述开关晶体管具有栅极并且被配置成取决于施加到栅极的电压而允许驱动电流流过该发光器件；以及如第二方面中所述的扫描驱动电路。所述扫描驱动电路中的每一级移位寄存器单元的第一信号输出端与所述阵列中的相应一行像素单元中的开关晶体管的栅极相连接。
根据本公开的第四方面，提供了一种驱动移位寄存器单元的方法，所述移位寄存器单元包括第一信号输出端和第二信号输出端，所述方法包括：响应于第一控制信号、第二控制信号、第一时钟信号、第二时钟信号以及第一电压，向所述第二信号输出端输出与所述第二时钟信号同步的信号并且生成第一内部控制信号；响应于所述第一内部控制信号而将所述第一电压输出至所述第一信号输出端；响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而生成第二内部控制信号；以及响应于所述第二内部控制信号而将第二电压输出至所述第一信号输出端。
在一些实施例中，向所述第二信号输出端输出与所述第二时钟信号同步的信号以及将所述第一电压输出至所述第一信号输出端是同时 启动和终止的。
在一些实施例中，与所述第二时钟信号同步的信号向所述第二信号输出端的输出以及所述第一电压输出至所述第一信号输出端的输出被维持一持续时间。
在一些实施例中，所述的方法还包括通过改变其中所述第一控制信号和所述第二控制信号为有效的时间段的长度来调节该持续时间。根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1为一种现有技术像素电路的示意性电路图；
图2为根据本公开实施例的一种移位寄存器单元的示意性框图；
图3为图2所示的移位寄存器单元的示例性电路图；
图4为图3所示的移位寄存器单元的电路的时序图；
图5为根据本公开实施例的一种扫描驱动电路的示意性框图；
图6为根据本公开实施例的一种显示装置的示意图；并且
图7为根据本公开实施例的一种驱动移位寄存器单元的方法的流程图。
具体实施方式
下面将结合附图，对本公开实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。根据本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图2为根据本公开实施例的一种移位寄存器单元200的示意性框图。
参照图2，该移位寄存器单元200包括用于接收第一控制信号的第一控制信号端STV1、用于接收第二控制信号的第二控制信号端STV2、用于接收第一时钟信号的第一时钟信号端CK、用于接收第二时钟信号的第二时钟信号端CKB、用于接收第一电压的第一电压端VGH、用于接收第二电压的第二电压端VGL、第一信号输出端OUTPUT1以及第二信号输出端OUTPUT2。该移位寄存器单元200还包括第一输出模块 10、第二输出模块20、第一控制模块30以及第二控制模块40。
第一控制模块30可操作用于响应于第一控制信号、第二控制信号、第一时钟信号、第二时钟信号以及第一电压而a)在一持续时间期间向第二信号输出端OUTPUT2输出与第二时钟信号CKB同步的信号，并且b)在第一节点(图2中未示出)处生成第一内部控制信号。
如后面将描述的，第一控制模块30被配置成根据其中第一控制信号和第二控制信号为有效的时间段的长度来调节该持续时间。
第一输出模块10可操作用于响应于所述第一内部控制信号而在所述持续时间内将第一电压输出至第一信号输出端OUTPUT1。
第二控制模块40可操作用于响应于第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而在第二节点(图2中未示出)处生成第二内部控制信号。
第二输出模块20可操作用于响应于所述第二内部控制信号而在所述持续时间结束时将所述第二电压输出至所述第一信号输出端OUTPUT1。
以下参照图3和4对移位寄存器单元200的细节进行详细地描述。
图3为图2所示的移位寄存器单元200的示例性电路图。
参照图3，第一输出模块10包括第一晶体管M1。第一晶体管M1具有连接到第一节点B的栅极、连接到第一电压端VGH的第一极、以及连接到第一信号输出端OUTPUT1的第二极。在该示例中，第一节点B处的电压信号为第一内部控制信号。
本公开不限于此。例如，该第一输出模块10还可以包括一个或多个与第一晶体管M1并联的晶体管，和/或一个或多个与第一电容C1并联的电容。
第二输出模块20包括第二晶体管M2。第二晶体管M2具有连接到第二节点C的栅极、连接到第二电压端VGL的第一极、以及连接到第一信号输出端OUTPUT1的第二极。在该示例中，第二节点C处的电压信号为第二内部控制信号。
本公开不限于此。例如，该第二输出模块20还可以包括一个或多个与第二晶体管M2并联的晶体管，和/或一个或多个与第二电容C2并联的电容。
第一控制模块30包括第三晶体管M3、第五晶体管M5、第六晶体 管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第三电容C3、第四电容C4、以及第一电容C1。
第三晶体管M3具有连接到第一时钟信号端CK的栅极、连接到第一控制信号端STV1的第一极、以及连接到第三节点D的第二极。
第五晶体管M5具有连接到第三节点D的栅极、连接到第一电压端VGH的第一极、以及连接到第四节点E的第二极。
第六晶体管M6具有连接到第一时钟信号端CK的栅极、连接到第二控制信号端STV2的第一极、以及连接到第四节点E的第二极。
第七晶体管M7具有连接到第四节点E的栅极、连接到第一电压端VGH的第一极、以及连接到第二信号输出端OUTPUT2的第二极。在图3中，第二信号输出端OUTPUT2被示出为从节点A引出。
第八晶体管M8具有连接到第三节点D的栅极、连接到第二时钟信号端CKB的第一极、以及连接到第二信号输出端OUTPUT2的第二极。第九晶体管M9具有连接到第二时钟信号CKB栅极、连接到第二信号输出端OUTPUT2的第一极、以及连接到第一节点B的第二极。
第三电容C3具有连接到第三节点D的一端和连接到第二信号输出端OUTPUT2的另一端。第四电容C4具有连接到第一电压端VGH的一端和连接到第四节点E的另一端。第一电容C1具有连接到第一电压端VGH的一端和连接到第一节点B的另一端。
本公开不限于此。例如，第一控制模块30还可以包括多个分别与第三晶体管M3、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8以及第九晶体管M9并联的晶体管，和/或多个分别与第三电容C3、第四电容C4和第一电容C1并联的电容。
第二控制模块40包括第四晶体管M4、第十晶体管M10以及第二电容C2。
第四晶体管M4具有连接到第一时钟信号端CK的栅极、连接到第二控制信号端STV2的第一极、以及连接到第二节点C的第二极。
第十晶体管M10具有连接到第一节点B的栅极、连接到第一电压端VGH第一极、以及连接到第二节点C的第二极。
第二电容C2具有连接到第二时钟信号端CKB的一端和连接到第二节点C的另一端。
本公开不限于此。例如，第二控制模块40还可以包括多个分别与 第四晶体管M4和第十晶体管M10并联的晶体管。
在图3中，各晶体管被示出为P型晶体管，并且第一电压端VGH为供应高电平并且第二电压端VGL被供应低电平。用于开启P型晶体管的栅极导通电压为低电平，并且用于关断P型晶体管的栅极截止电压为高电平。
其他的实施例是可能。例如，各晶体管可以是N型晶体管。用于开启N型晶体管的栅极导通电压为高电平，并且用于关断N型晶体管的栅极截止电压为低电平。另外，各晶体管通常被制作使得它们的第一极和第二极可以互换地使用。
图4为图3所示的移位寄存器单元的电路的时序图。
在第一阶段P1，由于第一时钟信号端CK处于低电平，因此第三晶体管M3、第四晶体管M4以及第六晶体管M6导通。第一控制信号端STV1的低电平通过第三晶体管M3传送至第三节点D。在该第三节点D的控制下，第八晶体管M8和第五晶体管M5导通，并且第三电容C3对第三节点D的低电平进行存储。第一电压端VGH的高电平通过第五晶体管M5传送至第四节点E和第七晶体管M7的栅极。第二控制信号端STV2的高电平通过第六晶体管M6传送至第四节点E和第七晶体管的M7的栅极，并且因此第七晶体管M7截止。
第二时钟信号端CKB的高电平通过第八晶体管M8传送至节点A和第二信号输出端OUTPUT2。由于第二时钟信号端CKB的高电平，第九晶体管M9截止。第一电容C1将上一周期结束时存储的高电平输出至第一晶体管M1和第十晶体管M10的栅极以及第一节点B，并且因此第一晶体管M1和第十晶体管M10截止。
由于第四晶体管M4导通，因此第二控制信号端STV2的高电平通过第四晶体管M4传送至第二节点C，并通过第二电容C2进行存储。在第二节点C的控制下，第二晶体管M2截止。
由于第一晶体管M1和第二晶体管M2在该阶段均处于截止状态，因此第一信号输出端OUTPUT1保持上一周期结束时的低电平。
在第二阶段P2，由于第一时钟信号端CK处于高电平，因此第三晶体管M3、第四晶体管M4以及第六晶体管M6截止。第二电容C2将上一阶段存储的高电平输出至第二晶体管M2的栅极，并且因此第二晶体管M2截止。
第三电容C3上一阶段存储的低电平使得第三节点D保持低电平，并且因此第五晶体管M5和第八晶体管M8仍然保持开启状态。第一电压端VGH的高电平通过第五晶体管M5传送至第四节点E和第七晶体管M7的栅极，并且因此第七晶体管M7截止。第二时钟信号端CKB的低电平通过第八晶体管M8传送至节点A和第二信号输出端OUTPUT2。
由于第二时钟信号端CKB的低电平，第九晶体管M9导通，并且将节点A处的低电平传送至第一晶体管M1的栅极和第一节点B。第一电容C1将该低电平进行存储。第一晶体管M1导通，并将第一电压端VGH的高电平传送至第一信号输出端OUTPUT1。
在第三阶段P3，由于第一时钟信号端CK处于低电平，因此第三晶体管M3、第四晶体管M4以及第六晶体管M6导通。第一控制信号端STV1的低电平通过第三晶体管M3输出至第三节点D。在第三节点D的控制下，第八晶体管M8和第五晶体管M5导通。第三电容C3对第三节点D的低电平进行存储。第一电压端VGH的高电平通过第五晶体管M5传送至第四节点E和第七晶体管M7的栅极。第二控制信号端STV2的高电平通过第六晶体管M6传送至第四节点和第七晶体管的M7的栅极，并且因此第七晶体管M7截止。
第二时钟信号端CKB的高电平通过第八晶体管M8传送至节点A和第二信号输出端OUTPUT2。由于第二时钟信号端CKB的高电平，第九晶体管M9截止。由于第一电容C1存储的低电平，节点B处于低电平。在节点B的控制下，第十晶体管M10和第一晶体管M1导通。第一电压端VGH的高电平通过第十晶体管M10传送至第二节点C，并且通过第一晶体管M1传送至第一信号输出端OUTPUT1。
在第四阶段P4，由于第一时钟信号端CK处于高电平，因此第三晶体管M3、第四晶体管M4以及第六晶体管M6截止。第三电容C3存储的低电平使得第三节点D处于低电平。在第三节点D的控制下，第八晶体管M8和第五晶体管M5导通。第一电压端VGH的高电平通过第五晶体管M5传送至第四节点E和第七晶体管M7的栅极，并且因此第七晶体管M7截止。第二时钟信号端CKB的低电平通过第八晶体管M8传送至节点A以及第二信号输出端OUTPUT2。
由于第二时钟信号端CKB处于低电平，所以第九晶体管M9导通， 使得节点A处的低电平通过第九晶体管M9传送至第十晶体管M10和第一晶体管M1的栅极以及第一节点B。第一电容C1对该低电平进行存储。第十晶体管M10导通，并且将第一电压端VGH的高电平传送至第二晶体管M2的栅极，使得该第二晶体管M2截止。第一电压端VGH的高电平通过第一晶体管M1传送至第一信号输出端OUTPUT1。
在第五阶段P5，由于第一时钟信号端CK处于低电平，所以第三晶体管M3、第四晶体管M4以及第六晶体管M6导通。第一控制信号端STV1的高电平通过第三晶体管M3传送至第三节点D。第三电容C3对该高电平进行存储。在节点D的控制下，第五晶体管M5和第八晶体管M8截止。由于第六晶体管M6导通，因此第二控制信号端STV2的低电平通过第六晶体管M6传送至第四节点E和第七晶体管M7的栅极，并且因此第七晶体管M7导通。第四电容C4将该低电平进行存储。第一电压端VGH的高电平通过第七晶体管M7传送至节点A和第二信号输出端OUTPUT2。
由于第二时钟信号端CKB处于高电平，因此第九晶体管M9截止。第一电容C1存储的低电平使得第十晶体管M10和第一晶体管M1导通。第一电压端VGH的高电平通过第十晶体管M10传送至第二节点C，并且第二信号控制端STV2的低电平通过第四晶体管M4传送至节点C，使得节点C的电位位于高电平和低电平之间，并且足够高以使第二晶体管截止。第一电压端VGH的高电平通过第一晶体管M1传送至第一信号输出端OUTPUT1。
在第六阶段P6，由于第一时钟信号端CK处于高电平，因此第三晶体管M3、第四晶体管M4以及第六晶体管M6截止。第三电容C3存储的高电平使得节点D处于高电平。在节点D的控制下，第五晶体管M5和第八晶体管M8截止。第四电容C4存储的低电平将第七晶体管M7导通。此时，第一电压端VGH的高电平通过第七晶体管M7传送至节点A以及第二信号输出端OUTPUT2。
由于第二时钟信号端CKB处于低电平，因此第九晶体管M9导通，并且将节点A处的高电平传送至第一晶体管M1和第十晶体管M10的栅极，使得第一晶体管M1和第十晶体管M10截止。
第二时钟信号端CKB输的低电平将节点C的电位下拉，以使第二晶体管M2导通。第二电压端VGL的低电平通过第二晶体管M2输出 至第一信号输出端OUTPUT1。
此后，第一信号输出端OUTPUT1保持输出低电平直到下一周期的第二阶段为止。
可以看到，在从第二阶段P2到第五阶段P5的持续时间期间，第一信号输出端OUTPUT1输出高电平信号，并且第二信号输出端OUTPUT2输出与第二时钟信号CKB同步的信号(它们具有相同的波形)。这借助于图3中所示的移位寄存器单元的第一控制模块30的操作而被实现。
第二阶段P2和第三阶段P3的操作可以被交替重复，使得可以通过改变第一控制信号STV1和第二控制信号STV2所包含的第二阶段P2和第三阶段P3的数目来调节该持续时间。
在图4所示的时序中，第一控制信号STV1和第二控制信号STV2可以被认为在从第一阶段P1到最后一个第三阶段P3的时间段内是有效的。有效的第一控制信号STV1为方波信号，并且有效的第二控制信号STV2处于第一电压的电平。
如下面将描述的，第一输出端OUTPUT1输出的高电平信号可以用于驱动像素电路中的OLED发光。也就是说，可以通过改变其中第一控制信号STV1和第二控制信号STV2为有效的时间段的长度来调节OLED的发光时长。第二阶段P2和第三阶段P3重复次数越多，其中第一信号输出端OUTPUT1输出高电平信号的持续时间就越长，并且OLED的发光时间越长。由此，可以以可调节的亮度来显示图像。
在一些实施例中，发光时长的调节还可以与电压的调节相组合，从而提供对亮度的灵活和精细的调节。
图5为根据本公开实施例的一种扫描驱动电路500的示意性框图。
参照图5，扫描驱动电路500包括多级移位寄存器单元SR1，SR2，...SRn-1，SRn，其每一个可以是如上所述的移位寄存器单元200。移位寄存器单元SR1，SR2，...SRn-1，SRn的第一信号输出端OUTPUT1分别向控制线EM1，EM2，...，EMn-1，EMn提供输出信号。移位寄存器单元200的细节在上面的实施例中进行了详细地描述，此处为了简单起见而被省略。
第一级移位寄存器单元SR1的第一控制信号端STV1用于接收第一起始信号，并且第一级移位寄存器单元SR1的第二控制信号端STV2 用于接收第二控制信号。
除第一级移位寄存器单元SR1以外的移位寄存器单元SR2...SRn-1，SRn中的每一个的第一控制信号端STV1连接上一级移位寄存器单元的第二信号输出端OUTPUT2。
除第一级移位寄存器单元SR1以外的移位寄存器单元SR2...SRn-1，SRn中的每一个的第二控制信号端STV2连接上一级移位寄存器单元的第一信号输出端OUTPUT1。
最后一级移位寄存器单元SRn的第二信号输出端OUTPUT2空置。
图6为根据本公开实施例的一种显示装置600的示意图。
参照图6，显示装置600包括显示面板610，其包括多个像素单元611。每个像素单元611包括发光器件和开关晶体管，该开关晶体管具有栅极并且被配置成取决于施加到栅极的电压而允许驱动电流流过该发光器件。具体地，每个像素单元611可以包括例如如图1所示的像素电路。该像素电路包括串联的驱动晶体管Td、开关晶体管T2和发光器件OLED。在图6的示例中，像素单元611内的其余部件为了简单起见而未被示出。
显示装置600还包括如上面实施例中描述的扫描驱动电路500。扫描驱动电路500中的移位寄存器单元SR1，SR2，...SRn-1，SRn中的每个的第一信号输出端OUTPUT1与相应一行像素单元中的开关晶体管T2的栅极相连接。在图6的示例中，第一级移位寄存器单元SR1的第一信号输出端OUTPUT1通过控制线EM1连接到第一行像素单元中的开关晶体管T2的栅极，第二级移位寄存器单元SR2的第一信号输出端OUTPUT1通过控制线EM2连接到第二行像素单元中的开关晶体管T2的栅极，以此类推。
在该实施例中，显示装置的示例包括基于有机发光二极管的任何显示装置，例如电视、数码相框、手机或平板电脑。
图7为根据本公开实施例的一种驱动移位寄存器单元的方法700的流程图，其中移位寄存器单元可以是上面结合图2-4描述的移位寄存器单元200。
在框701处，响应于第一控制信号、第二控制信号、第一时钟信号、第二时钟信号以及第一电压，向所述第二信号输出端输出与所述第二时钟信号同步的信号并且生成第一内部控制信号。
在框702处，响应于所述第一内部控制信号而将所述第一电压输出至所述第一信号输出端。
在框703处，响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而生成第二内部控制信号。
在框704处，响应于所述第二内部控制信号而将第二电压输出至所述第一信号输出端。
返回参照图4，向所述第二信号输出端输出与所述第二时钟信号同步的信号以及将所述第一电压输出至所述第一信号输出端是同时启动和终止的。方法700的操作已经在上文结合图3和4进行了详细地描述，此处为了简单起见不再重复。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。本领域技术人员可轻易想到的变化或替换都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应由权利要求限定。

Claims (12)

  1. 一种移位寄存器单元，包括：
    第一控制信号端，用于接收第一控制信号；
    第二控制信号端，用于接收第二控制信号；
    第一时钟信号端，用于接收第一时钟信号；
    第二时钟信号端，用于接收第二时钟信号；
    第一电压端，用于接收第一电压；
    第二电压端，用于接收第二电压；
    第一信号输出端和第二信号输出端；
    第一控制模块，可操作用于响应于所述第一控制信号、所述第二控制信号、所述第一时钟信号、所述第二时钟信号以及所述第一电压而a)在一持续时间期间向所述第二信号输出端输出与所述第二时钟信号同步的信号，并且b)在第一节点处生成第一内部控制信号；
    第一输出模块，可操作用于响应于所述第一内部控制信号而在所述持续时间内将所述第一电压输出至所述第一信号输出端；
    第二控制模块，可操作用于响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而在第二节点处生成第二内部控制信号；以及
    第二输出模块，可操作用于响应于所述第二内部控制信号而在所述持续时间结束时将所述第二电压输出至所述第一信号输出端。
  2. 根据权利要求1所述的移位寄存器单元，其中所述第一控制模块被配置成根据其中所述第一控制信号和所述第二控制信号为有效的时间段的长度来调节该持续时间。
  3. 根据权利要求1所述的移位寄存器单元，其中所述第一输出模块包括第一晶体管，其具有连接到所述第一节点的栅极、连接到所述第一电压端的第一极、以及连接到所述第一信号输出端的第二极。
  4. 根据权利要求1所述的移位寄存器单元，其中所述第二输出模块包括第二晶体管，其具有连接到所述第二节点的栅极、连接到所述第二电压端的第一极、以及连接到所述第一信号输出端的第二极。
  5. 根据权利要求1所述的移位寄存器单元，其中所述第一控制模块包括：
    第三晶体管，具有连接到所述第一时钟信号端的栅极、连接到所述第一控制信号端的第一极、以及连接到第三节点的第二极；
    第五晶体管，具有连接到所述第三节点的栅极、连接到所述第一电压端的第一极、以及连接到第四节点的第二极；
    第六晶体管，具有连接到所述第一时钟信号端的栅极、连接到所述第二控制信号端的第一极、以及连接到所述第四节点的第二极；
    第七晶体管，具有连接到所述第四节点的栅极、连接到所述第一电压端的第一极、以及连接到所述第二信号输出端的第二极；
    第八晶体管，具有连接到所述第三节点的栅极、连接到所述第二时钟信号端的第一极、以及连接到所述第二信号输出端的第二极；
    第九晶体管，具有连接到所述第二时钟信号端的栅极、连接到所述第二信号输出端的第一极、以及连接到所述第一节点的第二极；
    第三电容，具有连接到所述第三节点的一端和连接到所述第二信号输出端的另一端；
    第四电容，具有连接到所述第一电压端的一端和连接到所述第四节点的另一端；以及
    第一电容，具有连接到所述第一电压端的一端和连接到所述第一节点的另一端。
  6. 根据权利要求1所述的移位寄存器单元，其中所述第二控制模块包括：
    第四晶体管，具有连接到所述第一时钟信号端的栅极、连接到所述第二控制信号端的第一极、以及连接到所述第二节点的第二极；
    第十晶体管，具有连接到所述第一节点的栅极、连接到所述第一电压端第一极、以及连接到所述第二节点的第二极；以及
    第二电容，具有连接到所述第二时钟信号端的一端和连接到所述第二节点的另一端。
  7. 一种扫描驱动电路，包括多级如权利要求1-6任一项所述的移位寄存器单元，其中：
    第一级移位寄存器单元的第一控制信号端被配置用于接收第一起始信号，并且第一级移位寄存器单元的第二控制信号端被配置用于接收第二起始信号；
    除所述第一级移位寄存器单元以外的每一级移位寄存器单元的第一控制信号端连接上一级移位寄存器单元的第二信号输出端；并且
    除所述第一级移位寄存器单元以外的每一级移位寄存器单元的第二控制信号端连接上一级移位寄存器单元的第一信号输出端。
  8. 一种显示装置，包括：
    显示面板，包括布置在阵列中的多个像素单元，所述像素单元中的每个包括像素电路，所述像素电路包括发光器件和开关晶体管，所述开关晶体管具有栅极并且被配置成取决于施加到栅极的电压而允许驱动电流流过该发光器件；以及
    如权利要求6所述的扫描驱动电路，
    其中，所述扫描驱动电路中的每一级移位寄存器单元的第一信号输出端与所述阵列中的相应一行像素单元中的开关晶体管的栅极相连接。
  9. 一种驱动移位寄存器单元的方法，所述移位寄存器单元包括第一信号输出端和第二信号输出端，所述方法包括：
    响应于第一控制信号、第二控制信号、第一时钟信号、第二时钟信号以及第一电压，向所述第二信号输出端输出与所述第二时钟信号同步的信号并且生成第一内部控制信号；
    响应于所述第一内部控制信号而将所述第一电压输出至所述第一信号输出端；
    响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而生成第二内部控制信号；以及
    响应于所述第二内部控制信号而将第二电压输出至所述第一信号输出端。
  10. 根据权利要求9所述的方法，其中向所述第二信号输出端输出与所述第二时钟信号同步的信号以及将所述第一电压输出至所述第一信号输出端是同时启动和终止的。
  11. 根据权利要求10所述的方法，其中与所述第二时钟信号同步的信号向所述第二信号输出端的输出以及所述第一电压输出至所述第一信号输出端的输出被维持一持续时间。
  12. 根据权利要求11所述的方法，还包括通过改变其中所述第一控制信号和所述第二控制信号为有效的时间段的长度来调节该持续时间。
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