WO2017045389A1 - 驱动电路及其驱动方法、触控显示面板和触控显示装置 - Google Patents

驱动电路及其驱动方法、触控显示面板和触控显示装置 Download PDF

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Publication number
WO2017045389A1
WO2017045389A1 PCT/CN2016/077192 CN2016077192W WO2017045389A1 WO 2017045389 A1 WO2017045389 A1 WO 2017045389A1 CN 2016077192 W CN2016077192 W CN 2016077192W WO 2017045389 A1 WO2017045389 A1 WO 2017045389A1
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Prior art keywords
transistor
signal
output
gate
gate driver
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PCT/CN2016/077192
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English (en)
French (fr)
Inventor
杨盛际
董学
王攀华
薛海林
陈小川
王海生
陈希
谢建云
刘英明
赵卫杰
刘红娟
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/326,766 priority Critical patent/US9966010B2/en
Publication of WO2017045389A1 publication Critical patent/WO2017045389A1/zh

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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
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    • G06F3/0412—Digitisers structurally integrated in a display
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit and a driving method thereof, a touch display panel, and a touch display device.
  • the working process of the existing touch display panel includes a display phase and a touch phase, wherein the touch phase is set in a blank time period between display phases of adjacent two frames of pictures.
  • the blank time period between the display phases of the adjacent two frames is shortened, and the blank time period between the display phases of the adjacent two frames cannot be satisfied.
  • the time required to perform the touch phase of the touch drive is shortened.
  • embodiments of the present invention provide a driving circuit and a driving method thereof, a touch display panel, and a touch display device, which are used to solve the problem that the touch display panel cannot meet the touch stage and the touch driving system is used in the prior art. Time required.
  • an embodiment of the present invention provides a driving circuit including a plurality of gate drivers and a delay unit, each of the plurality of gate drivers including at least one shift register.
  • Each of the delay units is disposed between two adjacent ones of the plurality of gate drivers, the first input of the delay unit and the adjacent two gate drivers The first gate driver is connected, the first output terminal of the delay unit is connected to the latter one of the two adjacent gate drivers, and the delay unit is provided with a first voltage terminal and The first control end.
  • the delay unit is configured to output a start signal to the subsequent gate driver after the output signal of the previous gate driver outputs a predetermined time to turn on the subsequent gate driver for the predetermined time Used for touch drive.
  • the delay unit may include an input module and an output module.
  • the input module respectively Connected to the first input end of the delay unit, the first voltage end, and the first node, for controlling the potential of the first node according to a signal input from the first input end and the first voltage end .
  • the output module is respectively connected to the first node, the first control end and the first output end of the delay unit, and is configured to be based on a signal input from the first control terminal under potential control of the first node Controlling the signal output by the first output.
  • the shift register may include a start signal input end and a signal output end, the signal output end performing an output according to a signal provided by the start signal input end, and in the adjacent two gate drivers
  • the signal output end of the shift register of the previous gate driver is connected to the first input end of the delay circuit corresponding to the adjacent two gate drivers, and the start signal of the shift register of the latter gate driver
  • the input is coupled to a first output of the delay circuit corresponding to the adjacent two gate drivers.
  • Each of the plurality of gate drivers may include a first output, a second output, and a third output, and a first output of the previous one of the two adjacent gate drivers is connected a first input to a delay circuit corresponding to the adjacent two gate drivers.
  • Each of the plurality of gate drivers is respectively configured to drive a pixel circuit, and the pixel circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second Capacitors and light-emitting devices.
  • a gate of the third transistor is connected to a second output end of each of the plurality of gate drivers, a first pole is connected to an initialization signal input end of the pixel circuit, and a second pole is connected To the second node of the pixel circuit.
  • a gate of the fourth transistor is coupled to a first output of each of the plurality of gate drivers, a first electrode is coupled to a second node of the pixel circuit, and a second electrode is coupled to the pixel circuit The sixth node.
  • a gate of the fifth transistor is coupled to a second node of the pixel circuit, a first pole is coupled to a fifth node of the pixel circuit, and a second pole is coupled to a sixth node of the pixel circuit.
  • a gate of the sixth transistor is coupled to a third output of each of the plurality of gate drivers, a first pole is coupled to the first power terminal of the pixel circuit, and a second pole is coupled to the pixel The fifth node of the circuit.
  • a gate of the seventh transistor is coupled to a first output of each of the plurality of gate drivers, a first electrode is coupled to a data input of the pixel circuit, and a second electrode is coupled to the pixel circuit The fifth node.
  • a gate of the eighth transistor is coupled to a third output of each of the plurality of gate drivers, a first pole is coupled to a sixth node of the pixel circuit, and a second pole is coupled to the light emitting device The first end.
  • the first end of the second capacitor is coupled to the second node of the pixel circuit, and the second end is coupled to the first power terminal of the pixel circuit.
  • the second end of the light emitting device is coupled to a second power terminal of the pixel circuit.
  • the first transistor to the eighth transistor may be P-type transistors.
  • the embodiment of the invention further provides a touch display panel comprising any of the above driving circuits.
  • the embodiment of the invention further provides a touch display device, comprising the above touch display panel.
  • An embodiment of the present invention further provides a driving method for a driving circuit, where the driving circuit includes any one of the driving circuits, and the first voltage terminal is at a low level.
  • the driving method includes the first stage to the third stage.
  • the previous gate driver outputs a low level, the first control terminal inputs a high level, and the latter gate driver outputs a high level.
  • the previous gate driver outputs a synchronous driving signal, the first control terminal inputs a low level, and the latter gate driver outputs a synchronous driving signal.
  • the previous gate driver outputs a high level, the first control terminal inputs a high level, and the latter gate driver outputs a low level.
  • a touch phase may also be included between the first phase and the second phase.
  • the previous gate driver outputs a synchronous driving signal
  • the first control terminal inputs
  • the latter gate driver outputs a synchronous driving signal
  • the duration of the touch phase is the predetermined time.
  • the synchronous driving signal and the touch driving signal may be the same.
  • the touch display panel and the touch display device provided by the embodiment of the invention, the first input end of the delay unit is connected with the corresponding previous gate driver, and the first output end of the delay unit Connected to the corresponding latter gate driver.
  • the delay unit outputs a start signal for turning on the latter gate driver to the subsequent gate driver after the previous gate driver outputs the driving signal for a predetermined time.
  • the delay unit provided by the embodiment of the invention implements a shift register with interval time between the previous gate driver and the latter gate driver to output the driving signal and the latter gate driver in the previous gate driver.
  • the touch time period is formed to ensure that the touch display panel can realize high-precision touch function under the premise of realizing high-resolution display function.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a timing chart showing the operation of the pixel circuit shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of a shift register according to Embodiment 1 of the present invention.
  • FIG. 6 is a flowchart of a driving method of a driving circuit according to Embodiment 4 of the present invention.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention.
  • the driving circuit includes a plurality of gate drivers GOA, and a delay unit 101 is disposed between adjacent two gate drivers GOA(Gn) and GOA(Gn+1), the gate The driver includes at least one shift register, and the first input terminal of the delay unit 101 is connected to a previous gate driver GOA (Gn) of the two adjacent gate drivers, and the delay unit 101 The first output terminal is connected to a subsequent gate driver GOA (Gn+1) of the two adjacent gate drivers, and the delay unit 101 is provided with a first voltage terminal VSS and a first control terminal PRE.
  • the delay unit 101 is configured to output the driving signal to the subsequent gate driver GOA (Gn+1) for turning on the latter one after the driving signal is outputted by the previous gate driver GOA (Gn)
  • the start signal of the gate driver GOA (Gn+1) is implemented with an interval time (ie, a predetermined time) between the previous gate driver GOA (Gn) and the latter gate driver GOA (Gn+1) Shift registering, which can form a touch time period between the output signal of the previous gate driver GOA (Gn) and the turn-on of the gate driver GOA (Gn+1), thereby ensuring high resolution of the touch display panel Under the premise of the rate display function, high-precision touch function can also be realized.
  • each of the gate drivers GOA includes only one shift register, that is, the delay unit 101 is disposed between adjacent shift registers. Compared with the case where a delay unit 101 is disposed between a plurality of shift registers, a delay unit 101 is disposed between adjacent shift registers to enable the touch display panel to have more touch driving time, thereby ensuring touch.
  • the display panel can also achieve higher-precision touch functions under the premise of realizing high-resolution display.
  • the gate driver GOA can also include multiple shift registers to suit the needs of different applications.
  • the delay unit 101 includes an input module 102 and an output module 103.
  • the input module 102 is respectively connected to a first input end of the delay unit 101, a first voltage end VSS, and a first node P1, and is used for The potential of the first node P1 is controlled according to a signal input from the first input terminal and the first voltage terminal VSS.
  • the output module 103 is respectively connected to the first node P1, the first control terminal PRE and the first output end of the delay unit 101, and is configured to be under the potential control of the first node P1 according to the first control terminal.
  • the signal input by the PRE controls the signal output by the first output.
  • the input module 102 includes a first transistor M1, a gate of the first transistor M1 is connected to a first input end of the delay unit 101, and a first pole of the first transistor M1 is The first voltage terminal VSS of the delay unit 101 is connected, and the second pole of the first transistor M1 is connected to the first node P1 of the delay unit 101.
  • the output module 103 includes a second transistor M2 and a first capacitor C1.
  • the gate of the second transistor M2 is connected to the first node P1 of the delay unit 101, and the first pole of the second transistor M2 is The first control terminal PRE of the delay unit 101 is connected, the second electrode of the second transistor M2 is connected to the first output end of the delay unit 101, and the first end of the first capacitor C1 is connected to The second transistor M2 has a second terminal connected to the second terminal of the second transistor M2.
  • the gate driver GOA in this embodiment is used to provide a gate drive signal of a pixel circuit.
  • 2 is a schematic structural diagram of a pixel circuit for providing a gate driving signal by a gate driver GOA in a driving circuit according to Embodiment 1 of the present invention
  • FIG. 3 is an operation timing chart of the pixel circuit shown in FIG.
  • the gate of the fifth transistor M5 is connected to the second node P2 of the pixel circuit, the first pole is connected to the fifth node P5 of the pixel circuit, and the second pole is connected to the sixth node P6 of the pixel circuit .
  • a gate of the sixth transistor M6 is connected to a third control terminal EM of the pixel circuit, a first electrode is connected to a first power terminal ELVDD of the pixel circuit, and a second electrode is connected to a fifth electrode of the pixel circuit Node P5.
  • a gate of the seventh transistor M7 is connected to a gate control terminal Gate of the pixel circuit, a first pole is connected to a data input terminal Vdata of the pixel circuit, and a second pole is connected to a fifth node of the pixel circuit P5.
  • a gate of the eighth transistor M8 is connected to a third control terminal EM of the pixel circuit, and a first electrode is connected to the pixel circuit
  • the sixth node P6 has a second pole connected to the first end of the light emitting device.
  • the first end of the second capacitor C2 is connected to the second node P2 of the pixel circuit, and the second end is connected to the first power terminal ELVDD of the pixel circuit.
  • the second end of the light emitting device is coupled to a second power supply terminal ELVSS of the pixel circuit.
  • the fifth transistor M5 is a driving transistor, and the other transistors are switching transistors.
  • the operation of the pixel circuit shown in Fig. 2 will be described below with reference to Figs. 2 and 3. Specifically, referring to FIG. 2 and FIG. 3, in the first stage, that is, when the signal on the reset control terminal Reset is low level, the signal on the gate control terminal Gate is high level, and the signal on the third control terminal EM is High level, the signal on the initialization signal input terminal Vint is low level, the signal on the first power supply terminal ELVDD is low level, the signal on the second power supply terminal ELVSS is low level, and the signal on the data input terminal Vdata is low level.
  • the third transistor M3 is turned on, and the voltage signal of the second node is reset.
  • the signal on the reset control terminal Reset is high, the signal on the gate control gate is low, the signal on the third control terminal EM is high, and the signal on the initialization signal input terminal Vint
  • the signal on the first power supply terminal ELVDD is low level
  • the signal on the second power supply terminal ELVSS is low level
  • the signal on the data input terminal Vdata is high level
  • the fourth transistor M4 the fifth transistor M5,
  • the seventh transistor M7 is turned on, and the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are turned off.
  • the signal on the data input terminal Vdata charges the second node P2 via the seventh transistor M7, the fifth transistor M5, and the fourth transistor M4.
  • the signal on the reset control terminal Reset is high level
  • the signal on the gate control terminal Gate is high level
  • the signal on the third control terminal EM is low level
  • the signal on the initialization signal input terminal Vint is initialized.
  • the signal on the first power supply terminal ELVDD is low level
  • the signal on the second power supply terminal ELVSS is low level
  • the fifth transistor M5 and the sixth transistor M6 is turned on, and the light emitting device OLED starts to emit light.
  • the operating current I OLED of the light emitting device OLED from the fifth transistor M5 i.e., a driving transistor
  • the voltage Vdd the voltage of the threshold voltage V th
  • the voltage Vdd the voltage of the signal only with the first power supply terminal supplied ELVDD input Vdata
  • the voltage of the signal is related, thereby solving the problem of the threshold voltage Vth drift of the driving transistor, eliminating the influence of the threshold voltage Vth of the driving transistor on the operating current IOLED of the OLED .
  • the touch phase when resetting the signal on the control terminal Reset, the signal on the gate control terminal Gate, the signal on the third control terminal EM, the signal on the initialization signal input terminal Vint, the first
  • the signal on the power supply ELVDD, the signal on the second power supply terminal ELVSS, and the signal on the data input terminal Vdata are synchronous driving signals
  • the above signals are synchronously driven with the touch electrodes to ensure the operating current and normal illumination of the light emitting device OLED.
  • the states are the same, and the touch driving in the touch phase is guaranteed to have no influence on the illumination of the OLED.
  • the gate driver GOA of this embodiment provides a control signal for the pixel circuit shown in FIG. 2 to implement the above-described operation.
  • the gate driver GOA may include a first output terminal, a second output terminal, and a third output terminal, wherein the first output terminal is connected to the gate control terminal Gate of the pixel circuit, and the second output terminal is connected to the The reset control terminal Reset of the pixel circuit is connected to the third control terminal EM of the pixel circuit.
  • the first output of the gate driver GOA is also connected to the first input of the corresponding delay circuit 101.
  • the gate driver GOA provided in the first embodiment of the present invention includes a shift register.
  • FIG. 4 is a schematic structural diagram of a shift register of a gate driver GOA according to Embodiment 1 of the present invention
  • FIG. 5 is a timing chart of operation of the shift register shown in FIG.
  • the shift register includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor.
  • M15 a third capacitor C3, and a fourth capacitor C4.
  • the gate of the ninth transistor M9 is connected to the clock signal terminal CK1, the first pole of the ninth transistor M9 is connected to the start signal input terminal STV1, and the second pole and the fourth node P4 of the ninth transistor M9 are connected. connection.
  • the gate of the tenth transistor M10 is connected to the fourth node P4, the first pole of the tenth transistor M10 is connected to the clock signal terminal CK1, and the second pole of the tenth transistor M10 is connected to the third node P3.
  • the gate of the eleventh transistor M11 is connected to the clock signal terminal CK1, the first electrode of the eleventh transistor M11 is connected to the second voltage terminal VGL, and the second electrode and the third electrode of the eleventh transistor M11 are connected. Node P3 is connected.
  • the gate of the twelfth transistor M12 is connected to the third node P3, the first pole of the twelfth transistor M12 is connected to the third voltage terminal VGH, and the second pole of the twelfth transistor M12 is connected with the signal End Gate Output connection.
  • a gate of the thirteenth transistor M13 is connected to the fourth node P4, the tenth The first pole of the three transistor M13 is connected to the signal output Gate Output, and the second pole of the thirteenth transistor M13 is connected to the second signal terminal CB1.
  • the operation of the shift register of the gate driver GOA includes at least Phase 1, Phase 2, Phase 3, Phase 4, and Phase 5-a and Phase 5-b.
  • phase 1 that is, when the signal on the start signal input terminal STV1 is low level, the signal on the clock signal terminal CK1 is low level, and the signal on the second signal terminal CB1 is high level
  • the signal output terminal is output on the gate output.
  • the output signal is high.
  • phase 2 that is, when the start signal input terminal STV1 is at a high level, the signal at the clock signal terminal CK1 is at a high level, and the signal at the second signal terminal CB1 is at a low level, the output signal at the signal output terminal output is Is low.
  • phase 3 that is, when the signal at the start signal input terminal STV1 is at a high level, the signal at the clock signal terminal CK1 is at a low level, and when the signal at the second signal terminal CB1 is at a high level, the output of the signal output is output at a gate output.
  • the signal is high.
  • phase 4 that is, when the signal at the start signal input terminal STV1 is at a high level, the signal at the clock signal terminal CK1 is at a high level, and when the signal at the second signal terminal CB1 is at a low level, the output of the signal output is output at a gate output.
  • the signal is high.
  • phase 5-a that is, when the signal at the start signal input terminal STV1 is at a high level, the signal at the clock signal terminal CK1 is at a high level, and when the signal at the second signal terminal CB1 is at a low level, the signal output terminal is output.
  • the upper output signal is a synchronous drive signal.
  • phase 5-b that is, when the signal at the start signal input terminal STV1 is at a high level, the signal at the clock signal terminal CK1 is at a high level, and when the signal at the second signal terminal CB1 is at a low level, the signal output terminal is output.
  • the upper output signal is a synchronous drive signal.
  • the shift register shown in Fig. 4 is used in the gate driver GOA of this embodiment. example
  • the signal output terminal of the shift register in the gate driver GOA(Gn) The Gate Output is connected to the first input terminal of the delay circuit 101, and the start signal input terminal STV1 of the shift register in the gate driver GOA (Gn+1) is connected to the first output terminal of the delay circuit 101.
  • the first to fifteenth transistors M1 to M15 are P-type transistors, but the present invention is not limited thereto.
  • the first input end of the delay unit is connected to the corresponding previous gate driver, and the first output end of the delay unit is connected to the corresponding latter gate driver.
  • the delay unit outputs a start signal for turning on the latter gate driver to the subsequent gate driver after the previous gate driver outputs the driving signal for a predetermined time.
  • the delay unit provided in this embodiment implements a shift register with an interval between the previous gate driver and the latter gate driver to be between the output signal of the previous gate driver and the turn-on of the gate driver.
  • the touch time period is formed, so that the touch display panel can realize the high-precision touch function under the premise of realizing the high-resolution display function.
  • the first input end of the delay unit is connected to the corresponding previous gate driver, and the first output end of the delay unit is connected to the corresponding latter gate driver.
  • the delay unit outputs a start signal for turning on the latter gate driver to the subsequent gate driver after the previous gate driver outputs the driving signal for a predetermined time.
  • the delay unit provided in this embodiment implements a shift register with an interval between the previous gate driver and the latter gate driver to be between the output signal of the previous gate driver and the turn-on of the gate driver. The touch time period is formed, so that the touch display panel can realize the high-precision touch function under the premise of realizing the high-resolution display function.
  • This embodiment provides a touch display device, which includes the touch display panel provided in the second embodiment.
  • a touch display device which includes the touch display panel provided in the second embodiment.
  • the first input end of the delay unit is connected to the corresponding previous gate driver, and the first output end of the delay unit is connected to the corresponding subsequent gate driver.
  • the delay unit outputs a start signal for turning on the latter gate driver to the subsequent gate driver after the previous gate driver outputs the driving signal for a predetermined time.
  • the delay unit provided in this embodiment implements a shift register with an interval between the previous gate driver and the latter gate driver to be between the output signal of the previous gate driver and the turn-on of the gate driver. The touch time period is formed, so that the touch display panel can realize the high-precision touch function under the premise of realizing the high-resolution display function.
  • the embodiment provides a driving method for the driving circuit, and the driving circuit includes the driving circuit provided in the first embodiment.
  • the driving circuit includes the driving circuit provided in the first embodiment.
  • step 1001 ie, the first stage
  • the previous gate driver outputs a low level
  • the first control terminal inputs a high level
  • the latter gate driver outputs a high level
  • step 1002 the previous gate driver outputs a synchronous drive signal
  • the first control terminal inputs a low level
  • the latter gate driver outputs a synchronous drive signal
  • step 1003 ie, the third stage
  • the previous gate driver outputs a high level
  • the first control terminal inputs a high level
  • the latter gate driver outputs a low level.
  • the touch phase is further included between the first phase and the second phase, wherein the previous gate driver outputs a synchronous driving signal, and the first control terminal inputs a high level.
  • the latter gate driver outputs a synchronous driving signal, and the touch
  • the duration of the phase is the predetermined time.
  • FIG. 7 is a timing chart showing an operation of a driving method for a driving circuit according to Embodiment 4 of the present invention.
  • the signal Gate n output by the previous gate driver is at a low level
  • the first control terminal signal PRE of the delay circuit corresponding to the previous gate driver is a high level
  • the first transistor M1 of the delay circuit is turned on
  • the first node P1 is at a low level
  • the second transistor M2 is turned on
  • the signal Gate n+1 output by the latter gate driver is high. level.
  • the signal Gate n output by the previous gate driver is a synchronous driving signal
  • the first control terminal signal PRE of the delay circuit corresponding to the previous gate driver is at a high level.
  • the signal Gate n output by the previous gate driver is a synchronous driving signal, and the first control terminal signal PRE of the delay circuit corresponding to the previous gate driver is low.
  • the output signal Gate n+1 is a synchronous drive signal.
  • the signal Gate n of the shift register of the previous gate driver is at a high level, and the first control terminal signal PRE of the delay circuit corresponding to the previous gate driver is high.
  • the shift register of the latter gate driver GOA (Gn+1) starts to operate, and outputs a low-level output signal Gate n+1.

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Abstract

一种驱动电路及其驱动方法、触控显示面板和触控显示装置，其中，延时单元（101）的第一输入端与对应的前一栅极驱动器连接，延时单元（101）的第一输出端与对应的后一栅极驱动器连接。所述延时单元（101）在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出起始信号，以开启所述后一栅极驱动器。该延时单元（101）在前一栅极驱动器与后一栅极驱动器之间实现移位寄存，以在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。

Description

驱动电路及其驱动方法、触控显示面板和触控显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种驱动电路及其驱动方法、触控显示面板和触控显示装置。
背景技术
现有的触控显示面板的工作过程包括显示阶段和触控阶段，其中，所述触控阶段被设置在相邻两帧画面的显示阶段之间的空白时间段内。在现有的显示面板中，为了提高显示面板的分辨率，缩短了相邻两帧画面的显示阶段之间的空白时间段，导致相邻两帧画面的显示阶段之间的空白时间段无法满足在其中进行触控驱动的触控阶段所需的时间。
发明内容
为解决上述问题，本发明实施例提供一种驱动电路及其驱动方法、触控显示面板和触控显示装置，用于解决现有技术中触控显示面板无法满足触控阶段进行触控驱动所需时间的问题。
为此，本发明实施例提供一种驱动电路，包括多个栅极驱动器和延时单元，所述多个栅极驱动器中的每一个包括至少一个移位寄存器。所述延时单元中的每一个设置在所述多个栅极驱动器中的相邻两个栅极驱动器之间，所述延时单元的第一输入端与所述相邻两个栅极驱动器中的前一栅极驱动器连接，所述延时单元的第一输出端与所述相邻两个栅极驱动器中的后一栅极驱动器连接，所述延时单元设置有第一电压端和第一控制端。所述延时单元用于在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出起始信号，以开启所述后一栅极驱动器，所述预定时间用于触控驱动。
所述延时单元可包括输入模块和输出模块。所述输入模块分别 与所述延时单元的第一输入端、第一电压端以及第一节点连接，用于根据从所述第一输入端和所述第一电压端输入的信号控制所述第一节点的电位。所述输出模块分别与所述延时单元的第一节点、第一控制端以及第一输出端连接，用于在所述第一节点的电位控制下根据从所述第一控制端输入的信号控制所述第一输出端输出的信号。
所述输入模块可包括第一晶体管。所述第一晶体管的栅极与所述延时单元的第一输入端连接，所述第一晶体管的第一极与所述延时单元的第一电压端连接，所述第一晶体管的第二极与所述延时单元的第一节点连接。
所述输出模块可包括第二晶体管和第一电容。所述第二晶体管的栅极与所述延时单元的第一节点连接，所述第二晶体管的第一极与所述延时单元的第一控制端连接，所述第二晶体管的第二极与所述延时单元的第一输出端连接。所述第一电容的第一端连接至所述第二晶体管的栅极，所述第一电容的第二端连接至所述第二晶体管的第二极。
所述移位寄存器可包括起始信号输入端和信号输出端，所述信号输出端根据所述起始信号输入端所提供的信号来执行输出，并且在所述相邻两个栅极驱动器中，前一栅极驱动器的移位寄存器的信号输出端连接至与所述相邻两个栅极驱动器对应的延时电路的第一输入端，后一栅极驱动器的移位寄存器的起始信号输入端连接至与所述相邻两个栅极驱动器对应的延时电路的第一输出端。
所述多个栅极驱动器中的每一个可包括第一输出端、第二输出端和第三输出端，所述相邻两个栅极驱动器中的前一栅极驱动器的第一输出端连接至与所述相邻两个栅极驱动器对应的延时电路的第一输入端。所述多个栅极驱动器中的每一个分别用于驱动像素电路，所述像素电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第二电容和发光器件。所述第三晶体管的栅极连接至所述多个栅极驱动器中的每一个的第二输出端，第一极连接至所述像素电路的初始化信号输入端，第二极连接 至所述像素电路的第二节点。所述第四晶体管的栅极连接至所述多个栅极驱动器中的每一个的第一输出端，第一极连接至所述像素电路的第二节点，第二极连接至所述像素电路的第六节点。所述第五晶体管的栅极连接至所述像素电路的第二节点，第一极连接至所述像素电路的第五节点，第二极连接至所述像素电路的第六节点。所述第六晶体管的栅极连接至所述多个栅极驱动器中的每一个的第三输出端，第一极连接至所述像素电路的第一电源端，第二极连接至所述像素电路的第五节点。所述第七晶体管的栅极连接至所述多个栅极驱动器中的每一个的第一输出端，第一极连接至所述像素电路的数据输入端，第二极连接至所述像素电路的第五节点。所述第八晶体管的栅极连接至所述多个栅极驱动器中的每一个的第三输出端，第一极连接至所述像素电路的第六节点，第二极连接至所述发光器件的第一端。所述第二电容的第一端连接至所述像素电路的第二节点，第二端连接至所述像素电路的第一电源端。所述发光器件的第二端连接至所述像素电路的第二电源端。
所述第一晶体管至所述第八晶体管可为P型晶体管。
本发明实施例还提供一种触控显示面板，包括上述任一驱动电路。
本发明实施例还提供一种触控显示装置，包括上述触控显示面板。
本发明实施例还提供一种针对驱动电路的驱动方法，所述驱动电路包括上述任一驱动电路，所述第一电压端为低电平。所述驱动方法包括第一阶段至第三阶段。在第一阶段，所述前一栅极驱动器输出低电平，所述第一控制端输入高电平，所述后一栅极驱动器输出高电平。在第二阶段，所述前一栅极驱动器输出同步驱动信号，所述第一控制端输入低电平，所述后一栅极驱动器输出同步驱动信号。在第三阶段，所述前一栅极驱动器输出高电平，所述第一控制端输入高电平，所述后一栅极驱动器输出低电平。
所述第一阶段与所述第二阶段之间还可包括触控阶段。在触控阶段，所述前一栅极驱动器输出同步驱动信号，所述第一控制端输 入高电平，所述后一栅极驱动器输出同步驱动信号，所述触控阶段的持续时间为所述预定时间。
所述同步驱动信号与触控驱动信号可以相同。
本发明具有下述有益效果：
本发明实施例提供的驱动电路及其驱动方法、触控显示面板和触控显示装置中，延时单元的第一输入端与对应的前一栅极驱动器连接，延时单元的第一输出端与对应的后一栅极驱动器连接。所述延时单元在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出用于开启所述后一栅极驱动器的起始信号。本发明实施例提供的延时单元在前一栅极驱动器与后一栅极驱动器之间实现具有间隔时间的移位寄存，以在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间段，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
附图说明
图1为本发明实施例一提供的一种驱动电路的结构示意图；
图2为本发明实施例一提供的一种像素电路的结构示意图；
图3为图2所示像素电路的工作时序图；
图4为本发明实施例一提供的一种移位寄存器的结构示意图；
图5为图4所示移位寄存器的工作时序图；
图6为本发明实施例四提供的一种驱动电路的驱动方法的流程图；
图7为本发明实施例四提供的一种驱动电路的工作时序图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的驱动电路及其驱动方法、触控显示面板和触控显示装置进行详细描述。
实施例一
图1为本发明实施例一提供的一种驱动电路的结构示意图。如图1所示，所述驱动电路包括多个栅极驱动器GOA，相邻的两个栅极驱动器GOA(Gn)与GOA(Gn+1)之间设置有延时单元101，所述栅极驱动器包括至少一个移位寄存器，所述延时单元101的第一输入端与所述相邻的两个栅极驱动器中的前一栅极驱动器GOA(Gn)连接，所述延时单元101的第一输出端与所述相邻的两个栅极驱动器中的后一栅极驱动器GOA(Gn+1)连接，所述延时单元101设置有第一电压端VSS和第一控制端PRE。所述延时单元101用于在所述前一栅极驱动器GOA(Gn)输出驱动信号经过预定时间之后，向所述后一栅极驱动器GOA(Gn+1)输出用于开启所述后一栅极驱动器GOA(Gn+1)的起始信号，以在前一栅极驱动器GOA(Gn)与后一栅极驱动器GOA(Gn+1)之间实现具有间隔时间(即，预定时间)的移位寄存，这样可以在前一栅极驱动器GOA(Gn)输出驱动信号与后一栅极驱动器GOA(Gn+1)开启之间形成触控时间段，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
本实施例中，每个所述栅极驱动器GOA只包括一个移位寄存器，也就是说，所述延时单元101设置在相邻的移位寄存器之间。相比于间隔多个移位寄存器设置一个延时单元101的情况，相邻的移位寄存器之间设置一个延时单元101使得触控显示面板具有更多的触控驱动时间，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现更高精度的触控功能。当然，所述栅极驱动器GOA也可以包括多个移位寄存器，以适应不同应用的需要。
参见图1，所述延时单元101包括输入模块102和输出模块103，所述输入模块102分别与延时单元101的第一输入端、第一电压端VSS以及第一节点P1连接，用于根据从所述第一输入端和所述第一电压端VSS输入的信号控制所述第一节点P1的电位。所述输出模块103分别与延时单元101的第一节点P1、第一控制端PRE以及第一输出端连接，用于在所述第一节点P1的电位控制下根据从所述第一控制端PRE输入的信号控制所述第一输出端输出的信号。
本实施例中，所述输入模块102包括第一晶体管M1，所述第一晶体管M1的栅极与所述延时单元101的第一输入端连接，所述第一晶体管M1的第一极与所述延时单元101的第一电压端VSS连接，所述第一晶体管M1的第二极与所述延时单元101的第一节点P1连接。所述输出模块103包括第二晶体管M2和第一电容C1，所述第二晶体管M2的栅极与所述延时单元101的第一节点P1连接，所述第二晶体管M2的第一极与所述延时单元101的第一控制端PRE连接，所述第二晶体管M2的第二极与所述延时单元101的第一输出端连接，所述第一电容C1的第一端连接至所述第二晶体管M2的栅极，第二端连接至所述第二晶体管M2的第二极。
本实施例中的栅极驱动器GOA用于提供像素电路的栅极驱动信号。图2为通过根据本发明实施例一的驱动电路中的栅极驱动器GOA来提供栅极驱动信号的一种像素电路的结构示意图，图3为图2所示像素电路的工作时序图。
如图2所示，所述像素电路包括第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第二电容C2以及发光器件。所述第三晶体管M3的栅极连接至所述像素电路的复位控制端Reset，第一极连接至所述像素电路的初始化信号输入端Vint，第二极连接至所述像素电路的第二节点P2。所述第四晶体管M4的栅极连接至所述像素电路的栅极控制端Gate，第一极连接至所述像素电路的第二节点P2，第二极连接至所述像素电路的第六节点P6。所述第五晶体管M5的栅极连接至所述像素电路的第二节点P2，第一极连接至所述像素电路的第五节点P5，第二极连接至所述像素电路的第六节点P6。所述第六晶体管M6的栅极连接至所述像素电路的第三控制端EM，第一极连接至所述像素电路的第一电源端ELVDD，第二极连接至所述像素电路的第五节点P5。所述第七晶体管M7的栅极连接至所述像素电路的栅极控制端Gate，第一极连接至所述像素电路的数据输入端Vdata，第二极连接至所述像素电路的第五节点P5。所述第八晶体管M8的栅极连接至所述像素电路的第三控制端EM，第一极连接至所述像素电路的 第六节点P6，第二极连接至所述发光器件的第一端。所述第二电容C2的第一端连接至所述像素电路的第二节点P2，第二端连接至所述像素电路的第一电源端ELVDD。所述发光器件的第二端连接至所述像素电路的第二电源端ELVSS。在本实施例中，第五晶体管M5为驱动晶体管，其它晶体管为开关晶体管。
下面结合图2和图3来描述图2所示的像素电路的工作过程。具体来说，参照图2和图3，在第一阶段，即，当复位控制端Reset上信号为低电平，栅极控制端Gate上信号为高电平，第三控制端EM上信号为高电平，初始化信号输入端Vint上信号为低电平，第一电源端ELVDD上信号为低电平，第二电源端ELVSS上信号为低电平，数据输入端Vdata上信号为低电平时，第三晶体管M3导通，第二节点的电压信号复位。在第二阶段，即，当复位控制端Reset上信号为高电平，栅极控制端Gate上信号为低电平，第三控制端EM上信号为高电平，初始化信号输入端Vint上信号为低电平，第一电源端ELVDD上信号为低电平，第二电源端ELVSS上信号为低电平，数据输入端Vdata上信号为高电平时，第四晶体管M4、第五晶体管M5、第七晶体管M7导通，第三晶体管M3、第六晶体管M6、第八晶体管M8截止。在此阶段，数据输入端Vdata上的信号经由第七晶体管M7、第五晶体管M5和第四晶体管M4对第二节点P2进行充电。
在第三阶段，即，当复位控制端Reset上信号为高电平，栅极控制端Gate上信号为高电平，第三控制端EM上信号为低电平，初始化信号输入端Vint上信号为低电平，第一电源端ELVDD上信号为低电平，第二电源端ELVSS上信号为低电平，数据输入端Vdata上信号为低电平时，第五晶体管M5、第六晶体管M6、第八晶体管M8导通，发光器件OLED开始发光。此时，发光器件OLED的工作电流IOLED不受第五晶体管M5(即，驱动晶体管)的阈值电压Vth的影响，只与第一电源端ELVDD提供的电压信号Vdd和数据输入端Vdata提供的信号的电压有关，从而解决了驱动晶体管的阈值电压Vth漂移的问题，消除了驱动晶体管的阈值电压Vth对发光器件OLED的工作电流IOLED的影响。在第四阶段(即，触控阶段)，当复位控制端Reset 上的信号、栅极控制端Gate上的信号、第三控制端EM上的信号、初始化信号输入端Vint上的信号、第一电源端ELVDD上的信号、第二电源端ELVSS上的信号以及数据输入端Vdata上的信号为同步驱动信号时，上述信号随着触控电极同步驱动，以保证发光器件OLED的工作电流与正常发光状态一致，进而保证触控阶段的触控驱动对发光器件OLED的发光没有任何影响。
本实施例的栅极驱动器GOA为图2所示的像素电路提供控制信号，以实现上述工作过程。具体而言，栅极驱动器GOA可包括第一输出端、第二输出端和第三输出端，其中第一输出端连接至所述像素电路的栅极控制端Gate，第二输出端连接至所述像素电路的复位控制端Reset，第三输出端连接至所述像素电路的第三控制端EM。栅极驱动器GOA的第一输出端还连接至相应的延时电路101的第一输入端。
如上所述，本发明实施例一提供的栅极驱动器GOA包括移位寄存器。图4为本发明实施例一提供的一种用于本发明实施例一的栅极驱动器GOA的移位寄存器的结构示意图，图5为图4所示移位寄存器的工作时序图。如图4所示，所述移位寄存器包括第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第三电容C3以及第四电容C4。所述第九晶体管M9的栅极与时钟信号端CK1连接，所述第九晶体管M9的第一极与起始信号输入端STV1连接，所述第九晶体管M9的第二极与第四节点P4连接。所述第十晶体管M10的栅极与第四节点P4连接，所述第十晶体管M10的第一极与时钟信号端CK1连接，所述第十晶体管M10的第二极与第三节点P3连接。所述第十一晶体管M11的栅极与时钟信号端CK1连接，所述第十一晶体管M11的第一极与第二电压端VGL连接，所述第十一晶体管M11的第二极与第三节点P3连接。所述第十二晶体管M12的栅极与第三节点P3连接，所述第十二晶体管M12的第一极与第三电压端VGH连接，所述第十二晶体管M12的第二极与信号输出端Gate Output连接。所述第十三晶体管M13的栅极与第四节点P4连接，所述第十 三晶体管M13的第一极与信号输出端Gate Output连接，所述第十三晶体管M13的第二极与第二信号端CB1连接。所述第十四晶体管M14的栅极与第三节点P3连接，所述第十四晶体管M14的第一极与第三电压端VGH连接，所述第十四晶体管M14的第二极与所述第十五晶体管M15的第一极连接。所述第十五晶体管M15的栅极与第二信号端CB1连接，所述第十五晶体管M15的第二极与第四节点P4连接。所述第三电容C3的第一端连接至所述第十三晶体管M13的栅极，第二端连接至所述第十三晶体管M13的第一极。所述第四电容C4的第一端连接至所述第十二晶体管M12的栅极，第二端连接至所述第十二晶体管M12的第一极。
参见图4和图5，所述栅极驱动器GOA的移位寄存器的工作过程至少包括阶段1、阶段2、阶段3、阶段4以及阶段5-a和阶段5-b。在阶段1，即，当起始信号输入端STV1上信号为低电平，时钟信号端CK1上信号为低电平，第二信号端CB1上信号为高电平时，信号输出端Gate output上的输出信号为高电平。在阶段2，即，当起始信号输入端STV1为高电平，时钟信号端CK1上信号为高电平，第二信号端CB1上信号为低电平时，信号输出端Gate output上的输出信号为低电平。在阶段3，即，当起始信号输入端STV1上信号为高电平，时钟信号端CK1上信号为低电平，第二信号端CB1上信号为高电平时，信号输出端Gate output上输出信号为高电平。在阶段4，即，当起始信号输入端STV1上信号为高电平，时钟信号端CK1上信号为高电平，第二信号端CB1上信号为低电平时，信号输出端Gate output上输出信号为高电平。在阶段5-a，即，当起始信号输入端STV1上信号为高电平，时钟信号端CK1上信号为高电平，第二信号端CB1上信号为低电平时，信号输出端Gate output上输出信号为同步驱动信号。在阶段5-b，即，当起始信号输入端STV1上信号为高电平，时钟信号端CK1上信号为高电平，第二信号端CB1上信号为低电平时，信号输出端Gate output上输出信号为同步驱动信号。
图4所示的移位寄存器用于本实施例的栅极驱动器GOA中。例 如，当图4所示的移位寄存器用于图1所示的栅极驱动器GOA(Gn)和GOA(Gn+1)时，栅极驱动器GOA(Gn)中的移位寄存器的信号输出端Gate Output连接至延时电路101的第一输入端，栅极驱动器GOA(Gn+1)中的移位寄存器的起始信号输入端STV1连接至延时电路101的第一输出端。
在本实施例中，第一晶体管M1至第十五晶体管M15为P型晶体管，但是本发明不限于此。
本实施例提供的驱动电路中，延时单元的第一输入端与对应的前一栅极驱动器连接，延时单元的第一输出端与对应的后一栅极驱动器连接。所述延时单元在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出用于开启所述后一栅极驱动器的起始信号。本实施例提供的延时单元在前一栅极驱动器与后一栅极驱动器之间实现具有间隔时间的移位寄存，以在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间段，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
实施例二
本实施例提供一种触控显示面板，包括实施例一提供的驱动电路，具体内容可参照实施例一的描述，此处不再赘述。
本实施例提供的触控显示面板中，延时单元的第一输入端与对应的前一栅极驱动器连接，延时单元的第一输出端与对应的后一栅极驱动器连接。所述延时单元在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出用于开启所述后一栅极驱动器的起始信号。本实施例提供的延时单元在前一栅极驱动器与后一栅极驱动器之间实现具有间隔时间的移位寄存，以在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间段，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
实施例三
本实施例提供一种触控显示装置，包括实施例二提供的触控显示面板，具体内容可参照实施例二的描述，此处不再赘述。
本实施例提供的触控显示装置中，延时单元的第一输入端与对应的前一栅极驱动器连接，延时单元的第一输出端与对应的后一栅极驱动器连接。所述延时单元在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出用于开启所述后一栅极驱动器的起始信号。本实施例提供的延时单元在前一栅极驱动器与后一栅极驱动器之间实现具有间隔时间的移位寄存，以在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间段，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
实施例四
本实施例提供一种针对驱动电路的驱动方法，所述驱动电路包括实施例一提供的驱动电路，具体内容可参照实施例一的描述，此处不再赘述。
图6为本发明实施例四提供的一种针对驱动电路的驱动方法的流程图。如图6所示，所述驱动方法包括步骤1001至步骤1003，其中，所述驱动电路的第一电压端VSS为低电平。
在步骤1001(即，第一阶段)，所述前一栅极驱动器输出低电平，所述第一控制端输入高电平，所述后一栅极驱动器输出高电平。
在步骤1002(即，第二阶段)，所述前一栅极驱动器输出同步驱动信号，所述第一控制端输入低电平，所述后一栅极驱动器输出同步驱动信号。
在步骤1003(即，第三阶段)，所述前一栅极驱动器输出高电平，所述第一控制端输入高电平，所述后一栅极驱动器输出低电平。
本实施例中，所述第一阶段与所述第二阶段之间还包括触控阶段，在其中所述前一栅极驱动器输出同步驱动信号，所述第一控制端输入高电平，所述后一栅极驱动器输出同步驱动信号，所述触控 阶段的持续时间为所述预定时间。
图7为本发明实施例四提供的一种针对驱动电路的驱动方法的工作时序图。如图7所示，在第一阶段T1，所述前一栅极驱动器输出的信号Gate n为低电平，与所述前一栅极驱动器对应的延时电路的第一控制端信号PRE为高电平，所述延时电路的第一晶体管M1导通，第一节点P1为低电平，第二晶体管M2导通，所述后一栅极驱动器输出的信号Gate n+1为高电平。在触控阶段Tc，所述前一栅极驱动器输出的信号Gate n为同步驱动信号，与所述前一栅极驱动器对应的延时电路的第一控制端信号PRE为高电平，所述后一栅极驱动器输出的信号Gate n+1为同步驱动信号，此时触控驱动电路向触控显示装置输出触控驱动信号，从而在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间，进而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。可选的，所述同步驱动信号与触控驱动信号相同。上述电压信号Gate n和电压信号Gate n+1随着触控电极同步驱动，以保证发光器件OLED的工作电流与正常发光状态一致，进而保证触控阶段的触控驱动对发光器件OLED的发光没有任何影响。
本实施例中，在第二阶段T2，所述前一栅极驱动器输出的信号Gate n为同步驱动信号，与所述前一栅极驱动器对应的延时电路的第一控制端信号PRE为低电平，此时延时单元的第一输出端向后一栅极驱动器GOA(Gn+1)的移位寄存器输出低电平，该低电平为用于开启后一栅极驱动器GOA(Gn+1)的移位寄存器的起始信号STV1，以使后一栅极驱动器GOA(Gn+1)的移位寄存器开始工作，此时后一栅极驱动器GOA(Gn+1)的移位寄存器输出的信号Gate n+1为同步驱动信号。在第三阶段T3，所述前一栅极驱动器的移位寄存器输出的信号Gate n为高电平，与所述前一栅极驱动器对应的延时电路的第一控制端信号PRE为高电平，后一栅极驱动器GOA(Gn+1)的移位寄存器开始工作，并且输出低电平的输出信号Gate n+1。
本实施例提供的驱动电路的驱动方法中，延时单元的第一输入端与对应的前一栅极驱动器连接，延时单元的第一输出端与对应的 后一栅极驱动器连接。所述延时单元在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出用于开启所述后一栅极驱动器的起始信号。本实施例提供的延时单元在前一栅极驱动器与后一栅极驱动器之间实现具有间隔时间的移位寄存，以在前一栅极驱动器输出驱动信号与后一栅极驱动器开启之间形成触控时间段，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种驱动电路，包括多个栅极驱动器和延时单元，所述多个栅极驱动器中的每一个包括至少一个移位寄存器，所述延时单元中的每一个设置在所述多个栅极驱动器中的相邻两个栅极驱动器之间，所述延时单元的第一输入端与所述相邻两个栅极驱动器中的前一栅极驱动器连接，所述延时单元的第一输出端与所述相邻两个栅极驱动器中的后一栅极驱动器连接，所述延时单元设置有第一电压端和第一控制端；
    所述延时单元用于在所述前一栅极驱动器输出驱动信号经过预定时间之后，向所述后一栅极驱动器输出起始信号，以开启所述后一栅极驱动器，所述预定时间用于触控驱动。
  2. 根据权利要求1所述的驱动电路，其中，所述延时单元包括输入模块和输出模块；
    所述输入模块分别与所述延时单元的第一输入端、第一电压端以及第一节点连接，用于根据从所述第一输入端和所述第一电压端输入的信号控制所述第一节点的电位；
    所述输出模块分别与所述延时单元的第一节点、第一控制端以及第一输出端连接，用于在所述第一节点的电位控制下根据从所述第一控制端输入的信号控制所述第一输出端输出的信号。
  3. 根据权利要求2所述的驱动电路，其中，所述输入模块包括第一晶体管；
    所述第一晶体管的栅极与所述延时单元的第一输入端连接，所述第一晶体管的第一极与所述延时单元的第一电压端连接，所述第一晶体管的第二极与所述延时单元的第一节点连接。
  4. 根据权利要求2所述的驱动电路，其中，所述输出模块包括第二晶体管和第一电容；
    所述第二晶体管的栅极与所述延时单元的第一节点连接，所述第二晶体管的第一极与所述延时单元的第一控制端连接，所述第二晶体管的第二极与所述延时单元的第一输出端连接；
    所述第一电容的第一端连接至所述第二晶体管的栅极，所述第一电容的第二端连接至所述第二晶体管的第二极。
  5. 根据权利要求1所述的驱动电路，其中，所述移位寄存器包括起始信号输入端和信号输出端，所述信号输出端根据所述起始信号输入端所提供的信号来执行输出，并且在所述相邻两个栅极驱动器中，前一栅极驱动器的移位寄存器的信号输出端连接至与所述相邻两个栅极驱动器对应的延时电路的第一输入端，后一栅极驱动器的移位寄存器的起始信号输入端连接至与所述相邻两个栅极驱动器对应的延时电路的第一输出端。
  6. 根据权利要求1所述的驱动电路，其中，所述多个栅极驱动器中的每一个包括第一输出端、第二输出端和第三输出端，所述相邻两个栅极驱动器中的前一栅极驱动器的第一输出端连接至与所述相邻两个栅极驱动器对应的延时电路的第一输入端，并且
    所述多个栅极驱动器中的每一个分别用于驱动像素电路，所述像素电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第二电容和发光器件，
    所述第三晶体管的栅极连接至所述多个栅极驱动器中的每一个的第二输出端，第一极连接至所述像素电路的初始化信号输入端，第二极连接至所述像素电路的第二节点；
    所述第四晶体管的栅极连接至所述多个栅极驱动器中的每一个的第一输出端，第一极连接至所述像素电路的第二节点，第二极连接至所述像素电路的第六节点；
    所述第五晶体管的栅极连接至所述像素电路的第二节点，第一极连接至所述像素电路的第五节点，第二极连接至所述像素电路的第六节点；
    所述第六晶体管的栅极连接至所述多个栅极驱动器中的每一个的第三输出端，第一极连接至所述像素电路的第一电源端，第二极连接至所述像素电路的第五节点；
    所述第七晶体管的栅极连接至所述多个栅极驱动器中的每一个的第一输出端，第一极连接至所述像素电路的数据输入端，第二极连接至所述像素电路的第五节点；
    所述第八晶体管的栅极连接至所述多个栅极驱动器中的每一个的第三输出端，第一极连接至所述像素电路的第六节点，第二极连接至所述发光器件的第一端；
    所述第二电容的第一端连接至所述像素电路的第二节点，第二端连接至所述像素电路的第一电源端；
    所述发光器件的第二端连接至所述像素电路的第二电源端。
  7. 根据权利要求3所述的驱动电路，其中，所述第一晶体管为P型晶体管。
  8. 根据权利要求4所述的驱动电路，其中，所述第二晶体管为P型晶体管。
  9. 根据权利要求6所述的驱动电路，其中，所述第三晶体管至所述第八晶体管为P型晶体管。
  10. 一种触控显示面板，包括权利要求1至9任一所述的驱动电路。
  11. 一种触控显示装置，包括权利要求10所述的触控显示面板。
  12. 一种针对驱动电路的驱动方法，所述驱动电路包括权利要求1至9任一所述的驱动电路，所述第一电压端为低电平，所述驱 动方法包括：
    在第一阶段，所述前一栅极驱动器输出低电平，所述第一控制端输入高电平，所述后一栅极驱动器输出高电平；
    在第二阶段，所述前一栅极驱动器输出同步驱动信号，所述第一控制端输入低电平，所述后一栅极驱动器输出同步驱动信号；
    在第三阶段，所述前一栅极驱动器输出高电平，所述第一控制端输入高电平，所述后一栅极驱动器输出低电平。
  13. 根据权利要求12所述的驱动电路的驱动方法，其中，所述第一阶段与所述第二阶段之间还包括：
    触控阶段，所述前一栅极驱动器输出同步驱动信号，所述第一控制端输入高电平，所述后一栅极驱动器输出同步驱动信号，所述触控阶段的持续时间为所述预定时间。
  14. 根据权利要求12或13所述的驱动电路的驱动方法，其中，所述同步驱动信号与触控驱动信号相同。
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