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  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
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  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
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  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02455—Group 13/15 materials
  • H01L21/02458—Nitrides
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  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02496—Layer structure
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  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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  • H10D64/00—Electrodes of devices having potential barriers
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  • H10D84/01—Manufacture or treatment
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  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
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  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/343—Gate regions of field-effect devices having PN junction gates
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs

Definitions

• This relates to Group IIIA-N (e.g., GaN) field effect transistors (FETs), and more particularly to buffer layers for such FETs.
• Group IIIA-N e.g., GaN
• FETs field effect transistors
• Gallium-nitride is a commonly used Group IIIA-N material, where Group IDA elements (such as Ga, boron, aluminum, indium, and thallium) are also sometimes referred to as Group 13 elements.
• Group IDA elements such as Ga, boron, aluminum, indium, and thallium
• GaN is a binary IIIA/V direct bandgap semiconductor that has a Wurtzite crystal structure. Its relatively wide band gap of 3.4 eV at room temperature (versus 1.1 eV for silicon) gives it special properties for a wide variety of applications in optoelectronics, high-power devices and high-frequency electronic devices.
• buffer layer(s) are commonly used between the silicon substrate and the GaN layer for strain management.
• This buffer technology forms the basis of most GaN-on-Si technology commonly used for high-electron-mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET) devices, which are field-effect transistors incorporating a junction between two materials with different band gaps (i.e. a heteroj unction) as the channel instead of a doped region (as is generally the case for a MOSFET).
• HEMT high-electron-mobility transistor
• HFET heterostructure FET
• MODFET modulation-doped FET
• Some buffer arrangements for such devices use either super lattice structures or a graded buffer structure.
• a GaN cap layer deposition follows the deposition of at least one buffer layer.
• Conventional buffer layer and cap layer deposition processes use NH 3 and H 2 during the cool down from their respective deposition temperatures.
• the H 2 volume flow rate is generally several times the NH 3 volume flow rate.
• a method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition, the gas mixture supplied to the deposition chamber includes NH 3 and at least one other gas.
• the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer, so that at a surface of the cap layer: (a) a root mean square (rms) roughness is ⁇ 10 A; and (b) a pit density for pits greater than (>) 2 nm deep is less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• a root mean square (rms) roughness is ⁇ 10 A
• a pit density for pits greater than (>) 2 nm deep is less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• FIG. 1 is a flow chart of steps in an example method of fabricating an epitaxial layer stack including at least one low defect density cap layer for a power group IIIA-N transistor, according to an example embodiment.
• FIG. 2 is a cross sectional depiction of an example device stack that includes a Group IIIA-N buffer layer with a low defect density cap layer thereon, according to an example embodiment.
• FIG. 3A is a cross sectional view of an example depletion-mode high-electron-mobility transistor (HEMT) with an epitaxial layer stack having a low defect density cap layer, according to an example embodiment.
• HEMT depletion-mode high-electron-mobility transistor
• FIG. 3B is a cross sectional view of an example enhancement-mode HEMT with a normally off gate with an epitaxial layer stack having a low defect density cap layer, according to an example embodiment.
• FIG. 3C is a cross sectional view of an example IC including the depletion mode HEMT power device shown in FIG. 3A and the enhancement-mode HEMT shown in FIG. 3B both on the same low defect density cap layers on a buffer stack.
• Example embodiments recognize that the conventional NH3 and H2 gas mixture supplied to the deposition chamber during the cool down after epitaxial Group IIIA-N cap layer depositions for Group IIIA-N devices results in pits in the cap layer upon the cooling, which can be worsened after subsequent etching/cleaning where preferential etching can take place.
• H2 can attack Group IIIA-N cap layers (such as GaN or AlGaN) causing pits.
• Defects (such as pits) in the cap layer result in defects in the power transistor and, if they exist in a high enough density, they can result in device failures.
• cap layer depositions follow the deposition of at least one buffer layer on a substrate with a cooling process that uses a supplied gas mixture including H3 and at least one other gas, where the gas mixture provides an ambient in the deposition chamber that is non-etching with respect to the first Group IIIA-N layer.
• non-etching refers a resulting surface of the cap layer having: (a) a root mean square (rms) roughness of ⁇ 10 A; and (b) a pit density for pits layer greater than (>) 2 nm deep less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• rms root mean square
• a pit density for pits layer greater than (>) 2 nm deep less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• One example uses a gas mixture during cooldown with only NH3 and N2.
• FIG. 1 is a flow chart of steps in an example method 100 of fabricating an epitaxial layer stack including a low defect density cap layer for a Group IIIA-N power transistor, according to an example embodiment.
• All respective buffer and Group IIIA-N cap layers can be epitaxially deposited in a single run using a metal-organic chemical vapor deposition (MOCVD) system, molecular beam epitaxy (MBE) system, or hydride vapor phase epitaxy (HVPE) system.
• MOCVD metal-organic chemical vapor deposition
• MBE molecular beam epitaxy
• HVPE hydride vapor phase epitaxy
• Step 101 comprises removing the native oxide if present on the surface of the substrate (e.g., wafer).
• the substrate can comprise sapphire, silicon or silicon carbide (SiC).
• Step 102 comprises depositing at least a first Group IIIA-N buffer layer on the substrate in a deposition chamber of a deposition system, using a deposition temperature generally from 1050 °C to 1300 °C.
• the buffer layer(s) can be 1 micron to 10 microns thick.
• the Group IIIA-N buffer layer(s) and cap layers described herein may be represented by the general formula AlxGaylnl-x-yN, where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ l, 0 ⁇ x+y ⁇ l .
• the Group IIIA-N layer can comprise at least one of A1N, AlGaN, AlInN, and AlInGaN.
• Group IIIA elements such as boron (B) may be included, and N may be partially replaced by phosphorus (P), arsenic (As), or antimony (Sb).
• Each of the Group IIIA nitride compound semiconductors may contain an optional dopant selected from Si, C, Ge, Se, O, Fe, Mn, Mg, Ca, Be, Cd, and Zn.
• the buffer layer deposition(s) can optionally be followed by a cooling process cooling from the higher buffer layer deposition temperature (e.g., 1250 °C) to the lower deposition temperature of the cap layer deposition, such as 900 °C to 1050 °C, that uses a gas mixture supplied to the deposition chamber including NH3 and at least one other gas, where the gas mixture provides an ambient in the deposition chamber that is non-etching with respect to the first Group IIIA-N buffer layer.
• the ramp down rate during this cooling process is generally 5 °C/min to 40 °C/min.
• the other gas can be N2, Ar, He, Ne, Kr and or a combination of such gases.
• H3 is supplied at 2 to 20 liters/min and N2 is supplied at 50 to 150 liters/min.
• Hydrogen (H2) may be provided up to about 40% by volume H2 provided the mixture remains non-etching.
• the method can comprise optionally depositing at least a second Group IIIA-N buffer layer on the first Group IIIA-N buffer layer to form a buffer stack.
• the other buffer layer deposition step(s) can use the same process low defect density deposition process as step 102 described hereinabove including the described cooling process.
• Step 103 comprises depositing at least one Group IIIA-N cap layer on the first Group IIIA-N buffer layer (or buffer stack).
• the cap layer deposition temperature is generally from 900 °C to 1050 °C.
• non-etching here refers to a resulting cap layer having: (a) a root mean square (rms) roughness of ⁇ 10 A; and (b) a pit density for pits layer greater than (>) 2 nm deep less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• Surface roughness may be measured by an atomic force microscopy (AFM) system, while the pit density may be measured by a defect analysis tool such as the KLA-Tencor CANDELA® 8620 Inspection System.
• AFM atomic force microscopy
• the other gas can be N2, Ar, He, Ne, Kr and or a combination of such gases.
• NH3 is supplied at 2 to 20 liters/min and N2 is supplied at 50 to 150 liters/min.
• Hydrogen (H2) may be provided up to about 40% by volume H2 provided the mixture remains non-etching.
• the ramp down rate during this cooling process is generally 5 °C/min to 40 °C/min, and as described hereinabove can cool down to a temperature of 300 °C to 550 °C, where the deposition chamber is vented to atmosphere and the boat of wafers is then generally removed from the deposition chamber.
• Step 104 comprises forming a gate dielectric layer (e.g., SiN, SiON, A1203, A1N, silicon oxide or combination of any of these layers) on the cap layer, forming a metal gate electrode on the gate dielectric layer, and a source having a source contact and a drain having a drain contact on the cap layer.
• the gate electrode can comprise a TiW alloy in one embodiment.
• the source and drain can be formed by sputtering a metal stack such as Ti/Al/TiN in one particular embodiment.
• FIG. 2 is a cross sectional depiction of an example device stack 200 that includes a multi-layer buffer stack (buffer layer stack) 220 comprising a first Group IIIA-N buffer layer 220a and a second group IIIA-N buffer layer 220b both shown as A1N layers on a substrate (e.g., silicon) 210, according to an example embodiment.
• a Group IIIA-N cap layer 230 shown as a GaN layer is on the second Group IIIA-N buffer layer 220b, where the Group IIIA-N cap layer 230 has a low defect density formed using a cap layer cool down process using an ambient in the deposition chamber during cooling that is non-etching with respect to the cap layer.
• the first Group IIIA-N buffer layer 220a comprises A1N
• the second group IIIA-N buffer layer 220b comprises GaN
• the Group IIIA-N cap layer 230 comprises AlGaN.
• Example thickness ranges for the Group IIIA-N cap layer 230 can be 5 A to 300 A which can be used as a HEMT layer, 5 ⁇ to 30 ⁇ for the second Group IIIA-N buffer layer 220b, and 0.1 ⁇ to 5 ⁇ for the first Group IIIA-N buffer layer 220a.
• Advantages of example embodiments include the ability to deposit an essentially void and crack-free epitaxial GaN film stack including an essentially void and crack-free cap layer to enable obtaining higher transistor breakdown voltage, lower leakage current, and reduced substrate bow/warp.
• power transistors can provide a breakdown voltage of at least of 100V at a leakage current density of 1 ⁇ amp per mm2.
• Examples of power semiconductor devices that can use described epitaxial stacks include HEMT, double heterostructure field effect transistors (DHFETs), heteroj unction bipolar transistors (HBTs) and bipolar junction transistors (BJTs).
• An HEMT also known as heterostructure FET (HFET) or modulation-doped FET (MODFET) is a field-effect transistor incorporating a junction between two semiconductor materials with different band gaps (i.e. a heteroj unction) as the two dimensional electron gas (2DEG) channel layer instead of a doped region (as is generally the case for a metal-oxide-semiconductor field-effect transistor (MOSFET)).
• HFET heterostructure FET
• MODFET modulation-doped FET
• the HEMT includes a compound semiconductor having a wide band gap such as GaN and AlGaN. Due to high electron saturation velocity in GaN and IIIA-N materials systems, the electron mobility in GaN HEMT is higher than that of other general transistors such as metal oxide semiconductor field effect transistors (MOSFET s).
• MOSFET s metal oxide semiconductor field effect transistors
• FIG. 3A is a cross sectional view of an example depletion-mode HEMT power device 300 with a described epitaxial stack shown including a Group IIIA-N cap layer 230' on a buffer layer stack 220 on a substrate 210, according to an example embodiment.
• HEMT power device 300 is shown having a gate dielectric layer 235 such as comprising silicon nitride or silicon oxynitride.
• the Group IIIA-N cap layer 230' is a low defect density cap layer, with a surface of the Group IIIA-N cap layer 230' having: (a) a root mean square (rms) roughness of ⁇ 10 A; and (b) a pit density for pits layer greater than (>) 2 nm deep less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• the Group IIIA-N cap layer 230' can comprise an AlGaN layer 230b sandwiched between a topmost (first) GaN layer 230c and bottommost (second) GaN layer 230a that is on the second Group IIIA-N buffer layer 220b.
• the topmost and bottommost GaN layers 230c, 230a generally each have a doping concentration between 1 x 1015 cm-3 and 1 x 1018 cm-3.
• the dopants can include carbon, magnesium, silicon, or zinc, or combination of such dopants.
• HEMT power device 300 can be a discrete device, or one of many devices on an IC. More generally, the Group IIIA-N cap layer 230' may include one or more of GaN, InN, A1N, AlGaN, AlInN, InGaN, and AlInGaN. As described hereinabove, the Group IIIA-N layers can include other Group IIIA elements such as B, and N may be partially replaced by P, As, or Sb, and may also contain an optional dopant. In another specific example, the Group IIIA-N cap layer 230' can comprise a GaN layer on top of an AlxGayN layer or an InxAlyN layer. Yet another specific example is the Group IIIA-N cap layer 230' being a tri-layer stack can comprise GaN on InAIN on AlGaN.
• HEMT power device 300 includes a source 241, a drain 242, and a gate electrode 240.
• Gate electrode 240 is positioned between the source 241 and drain 242, closer to the source 241 than the drain 242.
• the source 241, drain 242, and gate electrode 240 may be formed of metals and/or metal nitrides, but example embodiments are not limited thereto.
• FIG. 3B is a cross sectional view of an example enhancement-mode HEMT power device 350 with a normally off gate with a Group IIIA-N cap layer 230' on a buffer layer shown as a buffer layer stack 220 on a substrate 210, according to an example embodiment.
• the Group IIIA-N cap layer 230' is a low defect density cap layer, with a surface of the Group IIIA-N cap layer 230' having: (a) a root mean square (rms) roughness of ⁇ 10 A; and (b) a pit density for pits layer greater than (>) 2 nm deep less than ( ⁇ ) 10 pits per square ⁇ with an average pit diameter less than ( ⁇ ) 0.05 ⁇ .
• the gate electrode is a p-doped gate electrode 245 (shown as a p-GATE ELECTRODE) that is in direct contact with the Group IIIA-N cap layer 230c (e.g., GaN layer).
• FIG. 3C is a cross sectional view of an example IC 380 including the depletion mode HEMT power device 300 shown in FIG. 3A and the enhancement-mode HEMT shown in FIG. 3B both using the same cap layers and buffer stack.
• Example embodiments are further illustrated by the following examples.
• AFM data was taken for a cap layer on a Si substrate formed using a H3/N2 cap layer cooldown as compared to a known cap layer formed using a H3/H2 gas mixture for the cap layer cooldown.
• the H3/N2 flow ratios are 1 : 10 with flow ranging from 2 to 20 liters/min of H3 and N2 in the range of 50 tol50 liters/min.
• the wafers processed with the described NH3/N2 cap layer cool down consistently showed no surface pits with data from wafers from several different runs.
• the wafers processed with the known H3/H2 cap layer cool down consistently showed surface pits 1 x 1010 per cm2 with sizes ranging from 10 nm to 200 nm with data taken from wafers from several different runs.
• High-temperature-reverse-bias (HTRB) HEMT device data was obtained where the cap layer comprised GaN and the buffer layer comprised AlGaN formed using a N2/NH3 cap layer cooldown along with control GaN cap layer formed using a known NH3/H2 cap layer cooldown.
• HTRB High-temperature-reverse-bias
• HTRB failures were associated with reliability fails due to GaN cap layer pits.
• HEMTs having a control GaN cap layer formed using a known N2/H2 cap layer cooldown had a burn-in failure rate of 5 % to 10%, while HEMTs having a GaN cap layer formed using a NH3/N2 cap layer cool down had a failure rate of ⁇ 2% HTRB fails.
• Example embodiments are useful to form semiconductor die that may be integrated into a variety of assembly flows to form a variety of different devices and related products.
• the semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, and conductive vias.
• the semiconductor die can be formed from a variety of processes including bipolar, insulated gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

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