WO2017088267A1 - 液晶驱动电路与栅极驱动面板 - Google Patents

液晶驱动电路与栅极驱动面板 Download PDF

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Publication number
WO2017088267A1
WO2017088267A1 PCT/CN2015/099703 CN2015099703W WO2017088267A1 WO 2017088267 A1 WO2017088267 A1 WO 2017088267A1 CN 2015099703 W CN2015099703 W CN 2015099703W WO 2017088267 A1 WO2017088267 A1 WO 2017088267A1
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Prior art keywords
thin film
film transistor
auxiliary pull
gate
down circuits
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PCT/CN2015/099703
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English (en)
French (fr)
Inventor
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/905,764 priority Critical patent/US9959829B2/en
Publication of WO2017088267A1 publication Critical patent/WO2017088267A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to liquid crystal display driving technology, and more particularly to a liquid crystal driving circuit and a gate driving panel.
  • Array substrate gate drive technology (Gate Driver on Array, GOA), is to make a gate drive circuit directly on the array (Array) substrate (Gate driver ICs) can be directly around the panel, reducing the production process and reducing the cost of the product.
  • GOA Gate Driver on Array
  • the peripheral space of the panel design is gradually compressed.
  • each level of the GOA circuit The height of the wiring space and the corresponding pixel size are the same.
  • the size of the pixels is getting smaller and smaller, and the space height for routing the GOA circuit is also reduced. The height is limited, and it can only be compensated with a larger width when wiring, which is very disadvantageous for the design of the narrow bezel.
  • the conventional GOA circuit is composed of a basic circuit and an auxiliary pull-down circuit.
  • the auxiliary pull-down circuit is composed of two groups, and the pull-down operation is performed in different time periods to avoid the characteristic drift of the same group of circuits for a long time, resulting in a decrease in reliability. .
  • an object of the present invention is to provide a liquid crystal driving circuit and a gate driving panel capable of avoiding drift of characteristics of a same group of circuits for a long time.
  • An embodiment of the present invention provides a liquid crystal driving display device.
  • the liquid crystal driving device includes a display area and a liquid crystal driving circuit.
  • the liquid crystal driving circuit includes a multi-level GOA circuit, and each stage of the GOA circuit includes a gate line and an auxiliary pull-down.
  • the circuit is characterized in that the gate line is divided into an odd-array gate line and an even-array gate line, and the auxiliary pull-down circuit is divided into a first group of auxiliary pull-down circuits and a second group of auxiliary pull-down circuits;
  • the odd-array gate line and the even-array gate line are separately disposed on both sides of the display area, and the first group of auxiliary pull-down circuits and the second group of auxiliary pull-down circuits are also separately set. Any two adjacent GOA circuits of the multi-stage GOA circuit share the first set of auxiliary pull-down circuits and the second set of auxiliary pull-down circuits.
  • each of the auxiliary pull-down circuits of the first group and the second group of auxiliary pull-down circuits includes a first thin film transistor, a second thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, wherein a drain of the fifth thin film transistor is connected to a source of the sixth thin film transistor, a source of the fifth thin film transistor and the first a source of the seven thin film transistors is connected, a drain of the seventh thin film transistor is connected to a source of the eighth thin film transistor, a gate of the seventh thin film transistor and the fifth thin film transistor Connected to the drain, a gate of the first thin film transistor and a gate of the second thin film transistor are connected to the drain of the seventh thin film transistor, and a source of the first thin film transistor The pole is connected to a source of the second thin film transistor.
  • the GOA circuit further includes a third thin film transistor, a fourth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, and a capacitor, wherein the a drain of the nine thin film transistor is connected to a gate of the tenth thin film transistor and a gate of the eleventh thin film transistor, and a gate of the third thin film transistor and the fourth thin film transistor a gate connected, a source of the third thin film transistor, a source of the fourth thin film transistor, a drain of the eleventh thin film transistor, and a tenth thin film transistor The gates are connected.
  • the first group of auxiliary pull-down circuits and the second group of auxiliary pull-down circuits are respectively controlled by a first low frequency signal and a second low frequency signal.
  • the first group of auxiliary pull-down circuits when the first low frequency signal is high, the first group of auxiliary pull-down circuits perform a pull-down operation, and when the first low frequency signal is low, the first group of auxiliary pull-down circuits are not An action is performed; when the second low frequency signal is high, the second group of auxiliary pull-down circuits perform a pull-down operation, and when the second low frequency signal is low, the second group of auxiliary pull-down circuits are not Will act.
  • the first low frequency signal is inverted from the second low frequency signal.
  • a gate driving panel including a liquid crystal driving circuit, the liquid crystal driving circuit including a multi-stage GOA circuit, and each stage of the GOA circuit includes a gate line and an auxiliary pull-down circuit, wherein the The gate line is divided into an odd array gate line and an even array gate line, wherein the odd array gate line and the even array gate line are separately disposed, respectively located on both sides of the panel, and The first group of auxiliary pull-down circuits and the second group of auxiliary pull-down circuits are also separately disposed, respectively located on two sides of the panel, and any two adjacent GOA circuits in the multi-stage GOA circuit share the first group of auxiliary pull-downs And a second set of auxiliary pull-down circuits.
  • each of the auxiliary pull-down circuits of the first group and the second group of auxiliary pull-down circuits includes a first thin film transistor, a second thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, wherein a drain of the fifth thin film transistor is connected to a source of the sixth thin film transistor, a source of the fifth thin film transistor and the first a source of the seven thin film transistors is connected, a drain of the seventh thin film transistor is connected to a source of the eighth thin film transistor, a gate of the seventh thin film transistor and the fifth thin film transistor Connected to the drain, a gate of the first thin film transistor and a gate of the second thin film transistor are connected to the drain of the seventh thin film transistor, and a source of the first thin film transistor The pole is connected to a source of the second thin film transistor.
  • the GOA circuit further includes a third thin film transistor, a fourth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, and a capacitor, wherein the a drain of the nine thin film transistor is connected to a gate of the tenth thin film transistor and a gate of the eleventh thin film transistor, and a gate of the third thin film transistor and the fourth thin film transistor a gate connected, a source of the third thin film transistor, a source of the fourth thin film transistor, a drain of the eleventh thin film transistor, and a tenth thin film transistor The gates are connected.
  • the first group of auxiliary pull-down circuits and the second group of auxiliary pull-down circuits are respectively controlled by a first low frequency signal and a second low frequency signal.
  • the first group of auxiliary pull-down circuits when the first low frequency signal is high, the first group of auxiliary pull-down circuits perform a pull-down operation, and when the first low frequency signal is low, the first group of auxiliary pull-down circuits are not An action is performed; when the second low frequency signal is high, the second group of auxiliary pull-down circuits perform a pull-down operation, and when the second low frequency signal is low, the second group of auxiliary pull-down circuits are not Will act.
  • the first low frequency signal is inverted from the second low frequency signal.
  • the wiring space height of each stage of the GOA circuit is large, and the width of the wiring can be reduced, and after the average, each stage of the GOA circuit has only one set of auxiliary pull-down circuits, and the space occupied by the GOA circuit itself is also reduced.
  • the design of the border is very advantageous.
  • FIG. 1 is a schematic diagram of a GOA architecture of a gate driving panel according to an embodiment of the invention
  • Figure 2 is an equivalent circuit diagram of a GOA circuit of Figure 1;
  • FIG. 3 is an equivalent circuit diagram of another GOA circuit of Figure 1;
  • FIG. 4 is a waveform diagram of the GOA architecture of the gate driving panel of FIG. 1;
  • Figure 5 is an equivalent circuit diagram of a GOA circuit of a second embodiment of the present invention.
  • the GOA architecture of the gate driving panel is shown in FIG. 1.
  • the gate lines are divided into an odd-array gate line 101 and an even-array gate line 102, which are respectively located on the panel 1.
  • the two sides alternately enter the display area 10 of the panel 1.
  • the adjacent two-stage GOA circuits 1011 and 1012 use the first set of auxiliary pull-down circuits 1001 and the second set of auxiliary pull-down circuits 1002, respectively.
  • the first set of auxiliary pull-down circuits 1001 and the second set of auxiliary pull-down circuits 1002 are controlled by two low frequency signals LC1 and LC2, alternately performing pull-down operations in different time periods.
  • FIG. 2 is an equivalent circuit diagram of the GOA circuit 1011 of FIG. 1.
  • the GOA circuit 1011 includes a third thin film transistor T3, a fourth thin film transistor T4, a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, and a capacitor C12.
  • the drain of the ninth thin film transistor T9 and the gate of the tenth thin film transistor T10 are connected to the gate of the eleventh thin film transistor T11, and the gate of the third thin film transistor T3 is connected to the gate of the fourth thin film transistor T4.
  • the source of the third thin film transistor T3 and the source of the fourth thin film transistor T4 are connected to the drain of the eleventh thin film transistor T11 and the gate of the tenth thin film transistor T10, respectively.
  • the first group of auxiliary pull-down circuits 1001 of FIG. 2 includes a first thin film transistor T1, a second thin film transistor T2, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8, wherein A drain of the fifth thin film transistor T5 is connected to a source of the sixth thin film transistor T6, and a source of the fifth thin film transistor T5 is connected to a source of the seventh thin film transistor T7. a drain of the seventh thin film transistor T7 is connected to a source of the eighth thin film transistor T8, and a gate of the seventh thin film transistor T7 is connected to the drain of the fifth thin film transistor T5.
  • a gate of the first thin film transistor T1 is connected to a gate of the second thin film transistor T2 and the drain of the seventh thin film transistor T7, and a source of the first thin film transistor T1 is A source of the second thin film transistor T2 is connected, and a capacitor C12 is connected to the source of the ninth thin film transistor T9 and the gate of the tenth thin film transistor T10.
  • the first group of auxiliary pull-down circuits 1001 is controlled by a low frequency signal LC1. When LC1 is high, the first group of auxiliary pull-down circuits 1001 perform a pull-down operation. When LC1 is low, the first group of auxiliary pull-down circuits 1001 does not work.
  • the corresponding action is performed by the second set of auxiliary pull-down circuits 1002 located on the other side of the panel 1.
  • the Q point of the GOA circuit 1011 is controlled to be pulled low by the output G_1014 of the GOA circuit 1014, and the outputs G_1011 and G_1012 of the GOA circuit 1011 and the GOA circuit 1012 are the first set of auxiliary pull-down circuits in FIG.
  • the two thin film transistors T1 and T2 in 1001 are performed, so that the auxiliary pull-down circuit 1001 can be shared by the GOA circuit 1011 and the GOA circuit 1012.
  • the GOA circuit 1012 includes a third thin film transistor T3', a fourth thin film transistor T4', a ninth thin film transistor T9', a tenth thin film transistor T10', an eleventh thin film transistor T11', and a capacitor.
  • auxiliary pull-down circuits 1002 including a first thin film transistor T1', a second thin film transistor T2', a fifth thin film transistor T5', and a sixth thin film transistor T6'.
  • a seventh thin film transistor T7', an eighth thin film transistor T8' wherein a drain of the fifth thin film transistor T5' is connected to a source of the sixth thin film transistor T6', and the fifth thin film transistor T5 a source of the seventh thin film transistor T7' is connected to a source of the seventh thin film transistor T7', and a drain of the seventh thin film transistor T7' is connected to a source of the eighth thin film transistor T8'.
  • a gate of the transistor T7' is connected to the drain of the fifth thin film transistor T5', a gate of the first thin film transistor T1' and a gate of the second thin film transistor T2'
  • the drain of the seventh thin film transistor T7' is connected, and a source of the first thin film transistor T1' is connected to a source of the second thin film transistor T2'.
  • the auxiliary pull-down circuit 1002 is controlled by the low frequency signal LC2, and LC1 and LC2 are mutually inverted signals, so at the same time point, only one of the circuits in Fig. 2 and Fig. 3 is performing the operation, avoiding They are electrically drifted due to squeezing for a long time in working condition.
  • the Q' point of the GOA circuit 1012 is also controlled to be pulled low by the output G_1014 of the GOA circuit 1014.
  • the auxiliary pull-down circuit 1002 can be pulled low by the GOA circuit 1011 and the GOA circuit 1012 during operation to ensure a state of being in a low potential when the corresponding gate lines GL_1 and GL_2 are turned off.
  • Figure 4 is a waveform diagram of the architecture of Figure 1 during normal operation.
  • the CK signal corresponding to the output G_1011 is already outputting a low potential signal, and it does not need to be pulled down again; for the GOA circuit 1012
  • the thin film transistor in the auxiliary pull-down circuit 1002 is also sufficient to pull down the output G_1012.
  • Fig. 5 is an equivalent circuit diagram of a GOA circuit 1011' according to a second embodiment of the present invention.
  • the auxiliary pull-down circuit shown in FIG. 5 does not include the third thin film transistor T3. Because the first thin film transistor T1 and the second thin film transistor T2 in the auxiliary pull-down circuit in FIG. 2 are enough to pull down the output G_1012, the role of the third thin film transistor T3 is repeated, and can be deleted when a design with a narrower bezel is required. .
  • the wiring space height of each stage of the GOA circuit is large, and the width of the wiring can be reduced, and after the average, each stage of the GOA circuit has only one set of auxiliary pull-down circuits, and the space occupied by the GOA circuit itself is also reduced.
  • the design of the border is very advantageous.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶驱动显示装置，包括显示区（10）与液晶驱动电路，所述液晶驱动电路包括多级GOA电路（1011，1012），每级GOA电路包括栅极线（101，102）及辅助下拉电路（1001，1002），所述栅极线（101，102）分为一奇数组栅极线（101）与一偶数组栅极线（102），所述辅助下拉电路（1001，1002）分为一第一组辅助下拉电路（1001）与一第二组辅助下拉电路（1002）；其中，所述奇数组栅极线（101）与所述偶数组栅极线（102）被分开设置于显示区（10）两侧，且所述第一组辅助下拉电路（1001）与所述第二组辅助下拉电路（1002）也是被分开设置于显示区（10）两侧，所述多级GOA电路（1011，1012）中的任相邻两级GOA电路共享所述第一组辅助下拉电路（1001）与所述第二组辅助下拉电路（1002）。

Description

液晶驱动电路与栅极驱动面板 技术领域
本发明涉及液晶显示驱动技术，特别是关于一种液晶驱动电路与栅极驱动面板。
 背景技术
阵列基板栅驱动技术(Gate Driver on Array, GOA)，是直接在阵列(Array)基板上制作栅极驱动电路(Gate driver ICs)，可直接做在面板周围，减少制作程序并降低产品成本，随着窄边框设计的日益流行，面板设计的周边空间被逐渐压缩，在传统的GOA电路设计中，每一级GOA电路的布线空间高度和对应的像素尺寸是一致的，现在4K或者更高ppi分辨率的产品的逐渐普及，像素的尺寸越来越小，留给GOA电路进行布线的空间高度也随之减小，由于高度收到限制，在布线时只能用更大的宽度来进行弥补，对窄边框的设计非常不利。
传统的GOA电路由基本电路和辅助下拉电路构成，通常辅助下拉电路由两组构成，分别在不同的时间段内进行下拉动作，避免同一组电路长时间受到挤压发生特性漂移，导致可靠度下降。
 技术问题
鉴于以上问题，本发明的目的在于提供一种能够避免同一组电路长时间受到挤压发生特性漂移的液晶驱动电路与栅极驱动面板。
 技术解决方案
本发明一实施例提出一种液晶驱动显示设备，所述液晶驱动装置包括一显示区及一液晶驱动电路，所述液晶驱动电路包括多级GOA电路，每级GOA电路包括栅极线及辅助下拉电路，其特征在于，所述栅极线分为一奇数组栅极线与一偶数组栅极线，所述辅助下拉电路分为一第一组辅助下拉电路与一第二组辅助下拉电路；其中，所述奇数组栅极线与所述偶数组栅极线被分开设置于所述显示区两侧，且所述第一组辅助下拉电路与所述第二组辅助下拉电路也是被分开设置，所述多级GOA电路中的任相邻两级GOA电路共享所述第一组辅助下拉电路与所述第二组辅助下拉电路。
较佳地，所述第一组与所述第二组辅助下拉电路中的每一辅助下拉电路包括一第一薄膜晶体管、一第二薄膜晶体管、一第五薄膜晶体管、一第六薄膜晶体管、一第七薄膜晶体管、一第八薄膜晶体管，其中所述第五薄膜晶体管的一漏极与所述第六薄膜晶体管的一源极相连，所述第五薄膜晶体管的一源极与所述第七薄膜晶体管的一源极相连，所述第七薄膜晶体管的一漏极与所述第八薄膜晶体管的一源极相连，所述第七薄膜晶体管的一栅极与所述第五薄膜晶体管的所述漏极相连，所述第一薄膜晶体管的一栅极与所述第二薄膜晶体管的一栅极与所述第七薄膜晶体管的所述漏极相连，所述第一薄膜晶体管的一源极与所述第二薄膜晶体管的一源极相连。
较佳地，所述GOA电路另包括一第三薄膜晶体管、一第四薄膜晶体管、一第九薄膜晶体管、一第十薄膜晶体管、一第十一薄膜晶体管、以及一电容，其中，所述第九薄膜晶体管的一漏极与所述第十薄膜晶体管的一栅极与所述第十一薄膜晶体管的一栅极相连，所述第三薄膜晶体管的一栅极与所述第四薄膜晶体管的一栅极相连，所述第三薄膜晶体管的一源极，与所述第四薄膜晶体管的一源极，分别与所述第十一薄膜晶体管的一漏极，以及所述第十薄膜晶体管的所述栅极相连。
较佳地，所述第一组辅助下拉电路与所述第二组辅助下拉电路是分别由一第一低频信号与一第二低频信号来控制。
较佳地，当所述第一低频信号为高电位时，所述第一组辅助下拉电路会进行下拉动作，当所述第一低频信号为低电位时，所述第一组辅助下拉电路不会进行动作；当所述第二低频信号为高电位时，所述第二组辅助下拉电路会进行下拉动作，当所述第二低频信号为低电位时，所述第二组辅助下拉电路不会进行动作。
较佳地，所述第一低频信号与所述第二低频信号反相。
本发明另一实施例提出一种栅极驱动面板，包括一液晶驱动电路，所述液晶驱动电路包括多级GOA电路，每级GOA电路包括栅极线及辅助下拉电路，其特征在于，所述栅极线分为一奇数组栅极线与一偶数组栅极线，其中，所述奇数组栅极线与所述偶数组栅极线被分开设置，分别位于所述面板两侧，且所述第一组辅助下拉电路与所述第二组辅助下拉电路也是被分开设置，分别位于所述面板两侧，所述多级GOA电路中的任相邻两级GOA电路共享所述第一组辅助下拉电路与所述第二组辅助下拉电路。
较佳地，所述第一组与所述第二组辅助下拉电路中的每一辅助下拉电路包括一第一薄膜晶体管、一第二薄膜晶体管、一第五薄膜晶体管、一第六薄膜晶体管、一第七薄膜晶体管、一第八薄膜晶体管，其中所述第五薄膜晶体管的一漏极与所述第六薄膜晶体管的一源极相连，所述第五薄膜晶体管的一源极与所述第七薄膜晶体管的一源极相连，所述第七薄膜晶体管的一漏极与所述第八薄膜晶体管的一源极相连，所述第七薄膜晶体管的一栅极与所述第五薄膜晶体管的所述漏极相连，所述第一薄膜晶体管的一栅极与所述第二薄膜晶体管的一栅极与所述第七薄膜晶体管的所述漏极相连，所述第一薄膜晶体管的一源极与所述第二薄膜晶体管的一源极相连。
较佳地，所述GOA电路另包括一第三薄膜晶体管、一第四薄膜晶体管、一第九薄膜晶体管、一第十薄膜晶体管、一第十一薄膜晶体管、以及一电容，其中，所述第九薄膜晶体管的一漏极与所述第十薄膜晶体管的一栅极与所述第十一薄膜晶体管的一栅极相连，所述第三薄膜晶体管的一栅极与所述第四薄膜晶体管的一栅极相连，所述第三薄膜晶体管的一源极，与所述第四薄膜晶体管的一源极，分别与所述第十一薄膜晶体管的一漏极，以及所述第十薄膜晶体管的所述栅极相连。
较佳地，所述第一组辅助下拉电路与所述第二组辅助下拉电路是分别由一第一低频信号与一第二低频信号来控制。
较佳地，当所述第一低频信号为高电位时，所述第一组辅助下拉电路会进行下拉动作，当所述第一低频信号为低电位时，所述第一组辅助下拉电路不会进行动作；当所述第二低频信号为高电位时，所述第二组辅助下拉电路会进行下拉动作，当所述第二低频信号为低电位时，所述第二组辅助下拉电路不会进行动作。
较佳地，所述第一低频信号与所述第二低频信号反相。
 有益效果
本发明中每一级GOA电路的布线空间高度较大，可以减小布线的宽度，而且平均之后每一级GOA电路只有一组辅助下拉电路，GOA电路本身所占的空间也减小，对窄边框的设计是非常有利的。
 附图说明
图1是依据本发明一实施例的栅极驱动面板的GOA架构示意图；
图2是图1中一GOA电路的等效电路图；
图3是图1中另一GOA电路的等效电路图；
图4是图1中的栅极驱动面板的GOA架构工作时的波形图；以及
图5是本发明第二实施例的GOA电路的等效电路图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明一实施例提出的栅极驱动面板的GOA架构如图1所示，在图1中，栅极线被分为奇数组栅极线101和偶数组栅极线102，它们分别位于面板1的两侧，交替进入面板1的显示区10。相邻两级GOA电路1011与1012分别使用第一组辅助下拉电路1001与第二组辅助下拉电路1002。第一组辅助下拉电路1001与第二组辅助下拉电路1002是由两个低频信号LC1和LC2来控制，在不同的时间段内交替进行下拉动作。
图2是图1中GOA电路1011的等效电路图。GOA电路1011包括第三薄膜晶体管T3、第四薄膜晶体管T4、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11以及电容C12。所述第九薄膜晶体管T9的漏极与第十薄膜晶体管T10的栅极与第十一薄膜晶体管T11的栅极相连，第三薄膜晶体管T3的栅极与第四薄膜晶体管T4的栅极相连，第三薄膜晶体管T3的源极与第四薄膜晶体管T4的源极分别与第十一薄膜晶体管T11的漏极以及第十薄膜晶体管T10的栅极相连。图2的第一组辅助下拉电路1001包括第一薄膜晶体管T1、第二薄膜晶体管T2、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8，其中所述第五薄膜晶体管T5的一漏极与所述第六薄膜晶体管T6的一源极相连，所述第五薄膜晶体管T5的一源极与所述第七薄膜晶体管T7的一源极相连，所述第七薄膜晶体管T7的一漏极与所述第八薄膜晶体管T8的一源极相连，所述第七薄膜晶体管T7的一栅极与所述第五薄膜晶体管T5的所述漏极相连，所述第一薄膜晶体管T1的一栅极与所述第二薄膜晶体管T2的一栅极与所述第七薄膜晶体管T7的所述漏极相连，所述第一薄膜晶体管T1的一源极与所述第二薄膜晶体管T2的一源极相连，电容C12连接于所述第九薄膜晶体管T9的源极与所述第十薄膜晶体管T10的栅极。第一组辅助下拉电路1001由一个低频信号LC1控制，当LC1为高电位时，第一组辅助下拉电路1001进行下拉动作，当LC1为低电位时，第一组辅助下拉电路1001不工作，此时是由位于面板1另外一侧的第二组辅助下拉电路1002来进行相应动作。在图2中，GOA电路1011的Q点是由GOA电路1014的输出G_1014来控制进行拉低，GOA电路1011和GOA电路1012的输出G_1011与G_1012则是由图2中的第一组辅助下拉电路1001中的两个薄膜晶体管T1与T2来进行，因此可以让辅助下拉电路1001被GOA电路1011和GOA电路1012所共享。
图3是图1中GOA电路1012的等效电路图。所述GOA电路1012包括一第三薄膜晶体管T3’、一第四薄膜晶体管T4’、一第九薄膜晶体管T9’、一第十薄膜晶体管T10’、一第十一薄膜晶体管T11’、以及一电容C12’，其中，所述第九薄膜晶体管T9’的一漏极与所述第十薄膜晶体管T10’的一栅极与所述第十一薄膜晶体管T11’的一栅极相连，所述第三薄膜晶体管T3’的一栅极与所述第四薄膜晶体管T4’的一栅极相连，所述第三薄膜晶体管T3’的一源极，与第四薄膜晶体管T4’的一源极，分别与第十一薄膜晶体管T11’的一漏极，以及第十薄膜晶体管T10’的所述栅极相连，电容C12’连接于所述第九薄膜晶体管T9’的源极与所述第十薄膜晶体管T10’的栅极。图3的虚线框中的部分就是第一组辅助下拉电路1002，其包括一第一薄膜晶体管T1’、一第二薄膜晶体管T2’、一第五薄膜晶体管T5’、一第六薄膜晶体管T6’、一第七薄膜晶体管T7’、一第八薄膜晶体管T8’，其中所述第五薄膜晶体管T5’的漏极与所述第六薄膜晶体管T6’的源极相连，所述第五薄膜晶体管T5’的源极与所述第七薄膜晶体管T7’的源极相连，所述第七薄膜晶体管T7’的一漏极与所述第八薄膜晶体管T8’的一源极相连，所述第七薄膜晶体管T7’的一栅极与所述第五薄膜晶体管T5’的所述漏极相连，所述第一薄膜晶体管T1’的一栅极与所述第二薄膜晶体管T2’的一栅极与所述第七薄膜晶体管T7’的所述漏极相连，所述第一薄膜晶体管T1’的一源极与所述第二薄膜晶体管T2’的一源极相连。与图2相同，辅助下拉电路1002由低频信号LC2进行控制，LC1和LC2互为反相信号，所以在同一时间点，图2和图3中的电路只会有一组在进行下来动作，避免了它们长时间处于工作状态受到挤压而导致的电性漂移。GOA电路1012的Q’点同样是由GOA电路1014的输出G_1014控制进行拉低。辅助下拉电路1002在工作时可由GOA电路1011和GOA电路1012进行拉低，确保在对应栅极线GL_1与GL_2关闭时处于低电位的状态。
图4是图1中的架构在正常工作时的波形图。从图中可以看到，对第n级电路来说，当输出G_1014开始输出时，输出G_1011对应的CK信号已经在输出低电位信号了，它本身不需要再进行下拉；对于GOA电路1012来讲，辅助下拉电路1002中的薄膜晶体管也已经足够对输出G_1012进行下拉动作。
请参阅图5，图5是本发明第二实施例的GOA电路1011’的等效电路图。相较于图2，图5所示的辅助下拉电路不包含第三薄膜晶体管T3。因为图2中辅助下拉电路中的第一薄膜晶体管T1与第二薄膜晶体管T2已经足够对输出G_1012进行下拉动作，所以第三薄膜晶体管T3的作用重复，在需要更窄边框的设计时可以删去。
本发明中每一级GOA电路的布线空间高度较大，可以减小布线的宽度，而且平均之后每一级GOA电路只有一组辅助下拉电路，GOA电路本身所占的空间也减小，对窄边框的设计是非常有利的。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种液晶驱动显示装置，所述液晶驱动装置包括一显示区及一液晶驱动电路，所述液晶驱动电路包括多级GOA电路，每级GOA电路包括栅极线及辅助下拉电路，其中，所述栅极线分为奇数组栅极线与偶数组栅极线，所述辅助下拉电路分为第一组辅助下拉电路与第二组辅助下拉电路；其中，所述奇数组栅极线与所述偶数组栅极线被分开设置于所述显示区两侧，且所述第一组辅助下拉电路与所述第二组辅助下拉电路也是被分开设置于所述显示区两侧，所述多级GOA电路中的任相邻两级GOA电路共享所述第一组辅助下拉电路与所述第二组辅助下拉电路；当所述第一组辅助下拉电路进行下拉动作时，所述第二组辅助下拉电路不会进行动作，而当所述第二组辅助下拉电路进行下拉动作时，所述第一组辅助下拉电路不会进行动作。
  2. 一种液晶驱动显示装置，所述液晶驱动装置包括一显示区及一液晶驱动电路，所述液晶驱动电路包括多级GOA电路，每级GOA电路包括栅极线及辅助下拉电路，其中，所述栅极线分为奇数组栅极线与偶数组栅极线，所述辅助下拉电路分为第一组辅助下拉电路与第二组辅助下拉电路；其中，所述奇数组栅极线与所述偶数组栅极线被分开设置于所述显示区两侧，且所述第一组辅助下拉电路与所述第二组辅助下拉电路也是被分开设置于所述显示区两侧，所述多级GOA电路中的任相邻两级GOA电路共享所述第一组辅助下拉电路与所述第二组辅助下拉电路。
  3. 根据权利要求2所述的液晶驱动显示装置，其中，每一辅助下拉电路包括：
    第一薄膜晶体管；
    第二薄膜晶体管，所述第二薄膜晶体管的源极与所述第一薄膜晶体管的源极相连；
    第五薄膜晶体管；
    第六薄膜晶体管，所述第六薄膜晶体管的源极与所述第五薄膜晶体管的漏极相连；
    第七薄膜晶体管，所述第七薄膜晶体管的源极与所述第五薄膜晶体管的源极相连，且所述第七薄膜晶体管的所述漏极与所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极相连；以及
    第八薄膜晶体管，所述第八薄膜晶体管的源极与所述第七薄膜晶体管的漏极相连。
  4. 根据权利要求3所述的液晶驱动显示设备，其中，所述GOA电路另包括：
    第三薄膜晶体管；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连；
    第九薄膜晶体管；
    第十薄膜晶体管，所述第十薄膜晶体管的栅极与所述第四薄膜晶体管的源极以及所述第九薄膜晶体管的漏极相连；
    第十一薄膜晶体管，所述第十一薄膜晶体管的栅极与所述第九薄膜晶体管的漏极相连，且所述第十一薄膜晶体管的漏极与所述第三薄膜晶体管的源极相连；以及
    电容，连接于所述第九薄膜晶体管的源极与所述第十薄膜晶体管的栅极。
  5. 根据权利要求4所述的液晶驱动显示设备，其中，所述第一组辅助下拉电路与所述第二组辅助下拉电路是分别由一第一低频信号与一第二低频信号来控制。
  6. 根据权利要求4所述的液晶驱动显示设备，其中，当所述第一低频信号为高电位时，所述第一组辅助下拉电路会进行下拉动作，当所述第一低频信号为低电位时，所述第一组辅助下拉电路不会进行动作；当所述第二低频信号为高电位时，所述第二组辅助下拉电路会进行下拉动作，当所述第二低频信号为低电位时，所述第二组辅助下拉电路不会进行动作。
  7. 根据权利要求5所述的液晶驱动显示设备，其中，所述第一低频信号与所述第二低频信号反相。
  8. 一种栅极驱动面板，包括一液晶驱动电路，所述液晶驱动电路包括多级GOA电路，每级GOA电路包括栅极线及辅助下拉电路，其中，所述栅极线分为一奇数组栅极线与一偶数组栅极线，其中，所述奇数组栅极线与所述偶数组栅极线被分开设置，分别位于所述面板两侧，且所述第一组辅助下拉电路与所述第二组辅助下拉电路也是被分开设置，分别位于所述面板两侧，所述多级GOA电路中的任相邻两级GOA电路共享所述第一组辅助下拉电路与所述第二组辅助下拉电路。
  9. 根据权利要求8所述的栅极驱动面板，其中，所述第一组与所述第二组辅助下拉电路中的每一辅助下拉电路包括：
    第一薄膜晶体管；
    第二薄膜晶体管，所述第二薄膜晶体管的源极与所述第一薄膜晶体管的源极相连；
    第五薄膜晶体管；
    第六薄膜晶体管，所述第六薄膜晶体管的源极与所述第五薄膜晶体管的漏极相连；
    第七薄膜晶体管，所述第七薄膜晶体管的源极与所述第五薄膜晶体管的源极相连，且所述第七薄膜晶体管的所述漏极与所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极相连；以及
    第八薄膜晶体管，所述第八薄膜晶体管的源极与所述第七薄膜晶体管的漏极相连。
  10. 根据权利要求9所述的栅极驱动面板，其中，所述GOA电路另包括：
    第三薄膜晶体管；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连；
    第九薄膜晶体管；
    第十薄膜晶体管，所述第十薄膜晶体管的栅极与所述第四薄膜晶体管的源极以及所述第九薄膜晶体管的漏极相连；
    第十一薄膜晶体管，所述第十一薄膜晶体管的栅极与所述第九薄膜晶体管的漏极相连，且所述第十一薄膜晶体管的漏极与所述第三薄膜晶体管的源极相连；以及
    电容，连接于所述第九薄膜晶体管的源极与所述第十薄膜晶体管的栅极。
  11. 根据权利要求10所述的栅极驱动面板，其中，所述第一组辅助下拉电路与所述第二组辅助下拉电路是分别由一第一低频信号与一第二低频信号来控制。
  12. 根据权利要求10所述的栅极驱动面板，其中，当所述第一低频信号为高电位时，所述第一组辅助下拉电路会进行下拉动作，当所述第一低频信号为低电位时，所述第一组辅助下拉电路不会进行动作；当所述第二低频信号为高电位时，所述第二组辅助下拉电路会进行下拉动作，当所述第二低频信号为低电位时，所述第二组辅助下拉电路不会进行动作。
  13. 根据权利要求11所述的栅极驱动面板，其中，所述第一低频信号与所述第二低频信号反相。
PCT/CN2015/099703 2015-11-24 2015-12-30 液晶驱动电路与栅极驱动面板 WO2017088267A1 (zh)

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