WO2017107258A1 - 栅极驱动架构及其阵列基板 - Google Patents

栅极驱动架构及其阵列基板 Download PDF

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Publication number
WO2017107258A1
WO2017107258A1 PCT/CN2016/070625 CN2016070625W WO2017107258A1 WO 2017107258 A1 WO2017107258 A1 WO 2017107258A1 CN 2016070625 W CN2016070625 W CN 2016070625W WO 2017107258 A1 WO2017107258 A1 WO 2017107258A1
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Prior art keywords
gate
sub
drain
pixels
source
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PCT/CN2016/070625
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English (en)
French (fr)
Inventor
王笑笑
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/907,930 priority Critical patent/US10297216B2/en
Publication of WO2017107258A1 publication Critical patent/WO2017107258A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display

Definitions

  • the present patent application relates to the field of liquid crystal display technologies, and in particular to a gate driving architecture and an array substrate thereof for use in a liquid crystal display.
  • liquid crystal display liquid crystal display, LCD
  • LCD liquid crystal display
  • cathode ray tube, CRT cathode ray tube
  • the display array under the tri-gate mode driving architecture has the following technical problems: a chip on film on a thin film.
  • the number of COF) is reduced, the corresponding source side fanout line becomes longer, and the fanout resistance/capacitor delay (fanout RC) Delay) becomes serious, the data signal on both sides of the display panel is due to RC
  • the delay is the largest and the waveform distortion is the most serious, causing insufficient charging on both sides of the panel, causing color shift problems on both sides of the panel.
  • red and green (R and G) are required to turn on the brightness of L255.
  • red color If the red color is turned on first, then the green color is turned on, and the red data signal is driven due to waveform distortion. As a result, the red charging is insufficient, and the brightness required by the 255th order (L255) cannot be achieved, and the yellow screen obtained on both sides will be greenish. If you turn on green first, then turn on red, green will be distorted and undercharged, resulting in a reddish yellow on both sides of the displayed yellow screen.
  • the source driving waveform signal is a data signal transmitted to the display area on both sides of the tri-gate panel. Because the signal delay is large, the signal waveform that is first turned on is distorted.
  • a row driving method is taken as an example. If the yellow L255 screen is displayed, red and green should be opened to L255 at the same time. If the red color is written first and then the green color is written, the red color will be greenish due to insufficient writing, and the yellow color will be green first. Write red again, green will be too red, the displayed yellow will be reddish. Therefore, it is necessary to develop a new type of gate driving architecture to solve the above problem of color shift.
  • the purpose of this patent application is to provide a gate driving architecture and an array substrate thereof, which can control the high scan signal of the scan output by pulling up and lowering the level of the node in a frame display screen.
  • the potential and the low potential are sequentially written to all the first column pixels, all the second column sub-pixels and all the third column sub-pixels in one frame of the display screen, thereby preventing the sub-pixel unit from generating resistance/capacitance delay and preventing The color deviation phenomenon improves the display quality of the liquid crystal panel.
  • the first embodiment of the present application provides a gate driving structure, which is disposed on an array substrate of a liquid crystal panel, the array substrate includes a frame display screen, and the frame display screen includes a plurality of first a row of sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, each of the first sub-pixels, each of the second sub-pixels, and each of the third sub-pixels are electrically connected to each of the scan lines
  • Each of the scan lines corresponds to a gate drive architecture, wherein the gate drive architecture includes: a first driver module for receiving a clock signal, the first driver module including a node and a scan output terminal The scan output end is connected to a scan line; a second drive module is electrically connected to the first drive module for receiving the pre-stage control signal and the first voltage signal, when the pre-stage control signal is enabled When the second driving module is described, the second driving module outputs the first voltage signal to the first driving module to raise the potential of the
  • the frame display screen is arranged in a sequence of different types of first column sub-pixels, second column sub-pixels, and third column sub-pixels, so that the first column sub-pixels and the plurality of The two columns of sub-pixels and the plurality of third column of sub-pixels form the frame display screen.
  • the three types of the first column sub-pixel, the second column sub-pixel, and the third column sub-pixel are composed of a red column sub-pixel, a green column sub-pixel, and a blue column sub-pixel.
  • the first voltage signal is greater than the second voltage signal, and the first voltage signal is a positive voltage signal and the second voltage signal is a negative voltage signal.
  • the driving order of the frame display screen is sequentially the plurality of first column sub-pixels, the plurality of second column sub-pixels, and the plurality of third column sub-pixels.
  • the first driving module includes: a first transistor, a first source, a first gate, and a first drain, wherein the first source receives the clock signal, a first gate is connected to the node, the first drain is connected to the scan output end to correspondingly output the first scan signal according to a period of the clock signal; and a second transistor is provided with a second source a second source connected to the first source and receiving the clock signal, and a second gate connecting the first gate and the node, The second drain outputs a current control signal, the current control signal is the same as the first scan signal, and a capacitor, the two ends of the capacitor are respectively connected to the node and the scan output end.
  • the second driving module includes: a third transistor, a third source, a third gate, and a third drain, wherein the third source receives the first voltage signal, The third gate receives the pre-stage control signal, the third drain is connected to the node, and a fourth transistor is provided with a fourth source, a fourth gate, and a fourth drain, The fourth source and the second gate receive the first voltage signal, the fourth drain is connected to the third driving module, and a fifth transistor is provided with a fifth source and a fifth gate a fifth drain, the fifth source is connected to the fourth source, the fifth gate is connected to the node, and the fifth drain is connected to the second driving module and the third driving module .
  • the third driving module includes: a sixth transistor, a sixth source, a sixth gate, and a sixth drain, wherein the sixth source is connected to the second driving module, The sixth gate is connected to the node, the sixth drain receives the second voltage signal, and a seventh transistor is provided with a seventh source, a seventh gate, and a seventh drain, a seventh source is connected to the first driving module and the second driving module, the seventh gate is connected to the sixth source, and the seventh drain is connected to the sixth drain and receiving the a second voltage signal; an eighth transistor having an eighth source, an eighth gate, and an eighth drain, wherein the eighth source is connected to the node, and the eighth gate receives the rear control signal
  • the eighth drain connects the sixth drain and the seventh drain and receives the second voltage signal; and the ninth transistor is provided with a ninth source, a ninth gate, and a ninth drain, The ninth source is connected to the scan output, the ninth gate is connected to the eighth gate and receiving After the stage control signal, said ninth drain connected to the drain of the sixth, seventh,
  • the first scan signal of the gate driving architecture and the second scan signal of another gate driving architecture are overlapped in a period of the clock signal to form a scan for the subsequent stage.
  • the line is pre-charged.
  • an array substrate including a gate driving architecture, wherein the gate driving architecture adopts the above-described gate driving architecture.
  • the patent provides a gate driving architecture and an array substrate thereof.
  • a frame display screen by pulling and lowering the level of the node, the high potential and the low potential of the scanning signal at the scanning output end are controlled to be sequentially written.
  • FIG. 1 is a schematic view showing a display area of a pixel array having a triple gate in accordance with an embodiment of the present patent application.
  • FIG. 2 is a circuit diagram of a gate drive architecture in accordance with an embodiment of the present patent application.
  • 3A and 3B are schematic diagrams showing the sequence of transmission of gate signals of sub-pixels for driving gate lines in a gate driving architecture according to an embodiment of the present patent application.
  • FIG. 4 is a timing diagram of waveform signals of a gate drive architecture and data signals in accordance with an embodiment of the present patent application.
  • FIG. 1 is a schematic diagram of a display area of a pixel arrangement having a triple gate in accordance with an embodiment of the present patent application.
  • the frame display screen 100 of the display area includes a plurality of first column sub-pixels 102RL, a plurality of second column sub-pixels 102GL, and a plurality of third column sub-pixels 102BL, each column of sub-pixels.
  • 102RL, 102GL, and 102BL are respectively composed of a plurality of sub-pixel units 102R, 102G, and 102B, and each of the first sub-pixels 102RL, each of the second sub-pixels 102GL, and each of the third sub-pixels 102BL are respectively electrically connected.
  • One scanning line G(1) ⁇ G(6) for example, six scanning lines shown in FIG. 1, but the number is not limited thereto, and each column of sub-pixels is connected to a gate circuit (not shown).
  • Each row of sub-pixels D(1) ⁇ D(6) sequentially includes a plurality of sub-pixel units 102R, 102G, 102B, for example, each row of sub-pixels D(1) ⁇ D(6) includes six sub-pixel units 102R, 102G, 102B, but the number is not limited thereto, and each row of sub-pixels is connected to a source circuit (not shown).
  • Each of the sub-pixel units 102R, 102G, 102B includes a transistor 104, a liquid crystal capacitor that connects the transistor 104, and a holding capacitor that connects the transistor 104.
  • a gate driving structure is disposed between each of the scanning lines G(1) to G(6) and one of the sub-pixels 102RL, 102GL, and 102BL.
  • FIG. 2 is a schematic circuit diagram of a gate driving architecture according to an embodiment of the present patent application.
  • the gate driving architecture includes a first driving module 200, a second driving module 202, and a third driving module 204.
  • the first driving module 200, the second driving module 202, and the third driving module 204 are electrically connected to each other.
  • the first driving module 200 is configured to receive a clock signal CK1, for example, a square wave signal with a duty cycle of 50%, the first driving module 200 includes a node Q(n) and a scan output terminal G(n), and the scan output terminal G (n) A scan line G(1) ⁇ G(6) is connected.
  • the scan output terminal G(n) correspondingly outputs a first scan signal having a high level to a scan line G(1) ⁇ G(6) according to a period of the clock signal CK1 to drive the first column of sub-pixels 102RL.
  • the third driving module 204 is electrically connected to the first driving module 202 and the second driving module 204, and the third driving module 204 is configured to receive the second-level control signal ST(n+9) and the second voltage signal V2.
  • the third driving module 204 outputs the second voltage signal V2 (for example, a negative voltage level signal VSS) to the
  • the second driving module 202 is configured to pull down the potential of the node Q(n) and the scan output terminal G(n) to a low level, and when the node Q(n) is at a low level,
  • the scan output terminal G(n) correspondingly outputs the first scan signal having a low level to a corresponding one of the scan lines G(1) G(6) according to the period of the clock signal CK1 until different
  • the gate drive architecture performs the driving of the plurality of first column sub-pixels.
  • each gate drive architecture generates a first scan signal to drive each first column of sub-pixels 102RL, the first sub-pixel unit 102R of each first sub-pixel 102RL is written with data data; then a second scan signal is generated by each gate driving architecture to drive each second sub-pixel 102GL to enable data Data is written to the second sub-pixel unit 102G of each second sub-pixel 102GL; finally, a third scan signal is generated by each gate driving architecture to drive each third sub-pixel 102BL to write data data.
  • the third sub-pixel unit 102B of each third column of sub-pixels 102BL are examples of each third column of sub-pixels 102BL.
  • the arrangement manner of the frame display screen 100 is sequentially different types of the first column sub-pixel 102RL, the second column sub-pixel 102GL, and the third column sub-pixel 102BL.
  • the column display screen 100 is formed by a column of sub-pixels 102RL, a plurality of second column sub-pixels 102GL, and a plurality of third column sub-pixels 102BL.
  • the first column sub-pixel 102RL, the second column sub-pixel 102GL, and the third column sub-pixel 102BL are composed of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. .
  • the driving order of the frame display screen 100 is sequentially the plurality of first column sub-pixels 102RL, the plurality of second column sub-pixels 102GL, and the plurality of third column sub-pixels 102BL.
  • the first voltage signal V1 eg, a positive voltage VDD
  • the second voltage signal V2 eg, a negative voltage VSS
  • a first voltage signal V1 and a second voltage signal V2 generated by a DC power converter.
  • the first driving module 200 includes a first transistor T1 and a second transistor T2.
  • the first transistor T1 is provided with a first source S1, a first gate G1 and a first drain D1.
  • the first source S1 receives the clock signal CK1, and the first gate G1 is connected to the node Q. (n), the first drain D1 is connected to the scan output terminal G(n) to output the first scan signal according to a period of the clock signal CK1, where "n" represents a positive integer and is The number of levels of scan lines and/or column sub-pixels.
  • the second transistor T2 is provided with a second source S2, a second gate G2, and a second drain D2.
  • the second source S2 is connected to the first source S1 and receives the clock signal CK1.
  • a second gate G2 connected to the first gate G1 and the node Q(n), the second drain D2 outputs a current control signal ST(n), the current control signal ST(n) and the The first scan signal of the scan output G(n) is the same.
  • Both ends of the capacitor C are connected to the node Q(n) and the scan output terminal G(n), respectively.
  • Capacitor C is used to pull the node Q(n) potential a second time.
  • the second driving module 204 includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the third transistor T3 is provided with a third source S3, a third gate G3, and a third drain D3.
  • the third source S3 receives the first voltage signal V1, and the third gate G3 receives the The front stage control signal ST(n-9), the third drain D3 is connected to the node Q(n).
  • the fourth transistor T4 is provided with a fourth source S4, a fourth gate G4 and a fourth drain D4, and the fourth source S4 and the second gate G2 receive the first voltage signal V1,
  • the fourth drain D4 is connected to the third driving module 204.
  • the fifth transistor T5 is provided with a fifth source S5, a fifth gate G5 and a fifth drain D5, the fifth source S5 is connected to the fourth source S4, and the fifth gate G5 is connected to the The node Q(n), the fifth drain D5 is connected to the second driving module 202 and the third driving module 204.
  • the third driving module includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the sixth transistor T6 is provided with a sixth source S6, a sixth gate G6 and a sixth drain D6, the sixth source D6 is connected to the second driving module 202, and the sixth gate G6 is connected to the Node Q(n), the sixth drain D6 receives the second voltage signal V2.
  • the seventh transistor T7 is provided with a seventh source S7, a seventh gate G7 and a seventh drain D7, and the seventh source S7 is connected to the first driving module 200 and the second driving module 202,
  • the seventh gate G7 is connected to the sixth source S6, and the seventh drain D7 is connected to the sixth drain D6 and receives the second voltage signal V2.
  • the eighth transistor T8 is provided with an eighth source S8, an eighth gate G8 and an eighth drain D8, the eighth source S8 is connected to the node Q(n), and the eighth gate G8 receives the The latter stage control signal ST(n+9), the eighth drain D8 is connected to the sixth drain D6 and the seventh drain D7 and receives the second voltage signal V2.
  • the ninth transistor T9 is provided with a ninth source S9, a ninth gate G9 and a ninth drain D9.
  • the ninth source S9 is connected to the scan output terminal G(n), and the ninth gate G9 is connected.
  • the eighth gate G8 receives the post-stage control signal ST(n+9), and the ninth drain G9 connects the sixth drain D6, the seventh drain D7, and the eighth drain D8 and The second voltage signal V2 is received.
  • the source and drain of the transistors of the present patent application are interchangeable.
  • the nodes Q(n) to which the gates of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are connected have the same level.
  • FIG. 3A and FIG. 3B are schematic diagrams showing the transfer sequence of the gate signals of the sub-pixels for driving the gate lines in the gate driving architecture according to the embodiment of the present application.
  • Figure 3A and Figure 3B is full HD (full High definition, For example, the resolution of FHD is that the number of sub-pixels in one column is 3240 (equal to 1080 pixel columns *3, and three columns of sub-pixels constitute one pixel column).
  • six clock signals CK1 ⁇ CK6 are included, for example, clock signals CK1 ⁇ CK6 are generated by the timing controller, and six gate drive architectures 3223(R), 3226(R), 3229(R), 3232(R) are provided.
  • 3A shows the red sub-pixels written in the first frame display screen 100, and waits for the data of all the red sub-pixels of the frame display screen 100 to be written, and then writes all the green of the frame display screen 100.
  • Column sub-pixel data In the embodiment shown in FIG. 3A, the data of the red column sub-pixels is sequentially written from bottom to top in one frame of the display screen 100, and then the data of the green sub-pixels is written.
  • FIG. 3B six clock signals CK1 CK CK6 are included, and six gate drive architectures 17 (G), 14 (G), 11 (G), 8 (G), 5 (G), 2 (G), respectively.
  • FIG. 3A shows the green sub-pixels written in one frame display screen 100 first, and after all the data of the green sub-pixels are written, the data of all the blue sub-pixels is written.
  • the data of the green column sub-pixels is sequentially written from top to bottom in one frame display screen 100, and then the data of the blue column sub-pixels is written.
  • FIG. 4 it is a waveform signal timing diagram of a gate driving architecture and a data signal according to an embodiment of the present patent application.
  • G(1), G(4), G(7), G(10), G(13), G(16), and data signals, the six clock signals CK1 ⁇ CK6 are, for example, square wave signals having a phase difference Corresponding to the scanning signals G(1), G(4), G(7), G(10), G(13), G(16), respectively.
  • the data signal will first display 1/3 frame red sub-pixel 400R according to the scan signal, and then display 1/3 frame.
  • the first scan signal G(1) of the gate driving architecture and the second scan signal G(4) of another gate driving architecture are overlapped in a period of the clock signal CK1 to form
  • the scanning line G(4) of the subsequent stage is precharged to maintain the charging signal level of the scanning line at a sufficient level.
  • the signals of the nodes Q(1), Q(4), and Q(7) are the same as the waveform signals of the enable signal STV, as shown in FIG. 4, the start signal STV, and the remaining levels are each The superposition of the level G(n) signal and the ST(n-9) signal.
  • the gate driving architecture and the array substrate thereof of the patent application in a frame display screen, control the high potential and the low potential of the scan signal at the scan output by pulling up and lowering the level of the node, and sequentially writing Data to all the first column pixels, all the second column sub-pixels and all the third column sub-pixels in one frame display screen, avoiding resistance/capacitance delay of sub-pixel unit, preventing color deviation phenomenon, improving display quality of liquid crystal panel .

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Abstract

一种栅极驱动架构及其阵列基板，在一帧显示画面中，通过第二驱动模块（202）的第一电压信号（V1）以及第三驱动模块（204）的第二电压信号（V2）分别拉高以及拉低节点（Q(n)）的电平，以控制扫描输出端（G(n)）的扫描信号的高电位以及低电位，以依序写入数据至一帧显示画面中全部的第一列次像素（102RL）、全部第二列次像素（102GL）以及全部第三列次像素（102BL），避免次像素单元（102R、102G、102B）产生电阻/电容延迟，防止色彩偏离现象，提高液晶面板的显示品质。

Description

栅极驱动架构及其阵列基板 技术领域
本专利申请涉及一种液晶显示器技术领域，且特别是涉及一种栅极驱动架构及其阵列基板，用于液晶显示器。
 背景技术
由于液晶显示器(liquid crystal display, LCD)具有低辐射、体积小及低耗能等优点，因此逐渐取代传统的阴极射线管(cathode ray tube, CRT)显示器，广泛地应用在笔记型计算机、个人数字助理(personal digital assistant, PDA)、平面电视，或行动电话等信息产品上。
现有技术中，三栅极(tri-gate)模式驱动架构下的显示阵列存在以下技术问题：薄膜上源极驱动芯片(chip on film, COF)数量减少，对应的源极(source)侧扇出区域(fanout)走线变长，扇出电阻/电容延迟(fanout RC delay)变得严重，显示面板两侧数据(data)信号因RC delay最大而波形失真最严重，造成面板两侧充电不足，使得面板两侧出现色偏问题。例如以行(column)方式为例，当显示纯色L255黄色画面，需红色以及绿色(R及G)都开启到L255的亮度，如果先打开红色，后打开绿色，驱动红色的data讯号因波形失真，导致红色充电不足，无法达到255阶(L255)要求的亮度，得到的黄色画面两侧会偏绿。如果先打开绿色，后打开红色，绿色会波形失真而充电不足，从而导致显的黄色画面两侧偏红。
源极驱动波形信号为传输到三栅极(tri-gate)面板两侧显示区域的数据信号，因信号延迟较大，先打开的讯号波形会失真，这里以行行(column)驱动方式为例，若显示黄色L255画面，则要红色和绿色同时开到L255，若是先写入红色，再写入绿色，红色会因写入不足，最后呈现出的黄色偏绿，反之若是先写入绿色，再写入红色，绿色会因写入不足，显示的黄色会偏红。因此需要发展一种新式的栅极驱动架构，以解决上述色偏的问题。
 技术问题
有监于此，本专利申请的目的在于提供一种栅极驱动架构及其阵列基板，在一帧显示画面中，通过拉高以及拉低节点的电平，以控制扫描输出端的扫描信号的高电位以及低电位，以依序写入数据至一帧显示画面中全部的第一次列像素、全部第二列次像素以及全部第三列次像素，避免次像素单元产生电阻/电容延迟，防止色彩偏离现象，提高液晶面板的显示品质。
技术解决方案
为达到上述发明目的，本专利申请第一实施例中提供一种栅极驱动架构，设置于液晶面板的阵列基板上，所述阵列基板包括一帧显示画面，所述帧显示画面包括若干第一列次像素、若干第二列次像素以及若干第三列次像素，每一第一列次像素、每一第二列次像素以及每一第三列次像素分别相对应电性连接一条扫描线，每一扫描线相对应一栅极驱动架构，其中所述栅极驱动架构包括：一第一驱动模块，用以接收时钟信号，所述第一驱动模块包括一节点以及一扫描输出端，所述扫描输出端相对应连接一条扫描线；一第二驱动模块，电性连接所述第一驱动模块，用以接收前级控制信号以及第一电压信号，当所述前级控制信号致能所述第二驱动模块时，所述第二驱动模块输出所述第一电压信号至所述第一驱动模块，以拉高所述节点的电位至高电平，并且当所述节点处于高电平时，使所述扫描输出端依据所述时钟信号的周期相对应输出具有高电平的一第一扫描信号至一条扫描线，以驱动所述第一列次像素；以及一第三驱动模块，电性连接所述第一驱动模块以及所述第二驱动模块，用以接收后级控制信号以及第二电压信号，当所述后级控制信号致能所述第三驱动模块时，所述第三驱动模块输出所述第二电压信号至所述第二驱动模块，以拉低所述节点以及所述扫描输出端的电位至低电平，并且当所述节点处于低电平时，使所述扫描输出端依据所述时钟信号的周期相对应输出具有低电平的所述第一扫描信号至所述扫描线，直至以不同的栅极驱动架构完成所述若干第一列次像素的驱动。
在一实施例中，所述帧显示画面的配置方式依序为不同类型的第一列次像素、第二列次像素以及第三列次像素，使所述若干第一列次像素、若干第二列次像素以及若干第三列次像素形成所述帧显示画面。
在一实施例中，所述第一列次像素、第二列次像素以及第三列次像素三种类型是由红色列次像素、绿色列次像素以及蓝色列次像素所组成。
在一实施例中，所述第一电压信号的大于所述第二电压信号，并且所述第一电压信号是正电压信号，所述第二电压信号是负电压信号。
在一实施例中，所述帧显示画面的驱动顺序依序为所述若干第一列次像素、所述若干第二列次像素以及所述若干第三列次像素。
在一实施例中，所述第一驱动模块包括：一第一晶体管，设有第一源极、第一栅极以及第一漏极，所述第一源极接收所述时钟信号，所述第一栅极连接所述节点，所述第一漏极连接所述扫描输出端，以依据所述时钟信号的周期相对应输出所述第一扫描信号；一第二晶体管，设有第二源极、第二栅极以及第二漏极，所述第二源极连接所述第一源极并且接收所述时钟信号，所述第二栅极连接所述第一栅极以及所述节点，所述第二漏极输出一目前控制信号，所述目前控制信号与所述第一扫描信号相同；以及一电容，所述电容的两端部分别连接所述节点以及所述扫描输出端。
在一实施例中，所述第二驱动模块包括：一第三晶体管，设有第三源极、第三栅极以及第三漏极，所述第三源极接收所述第一电压信号，所述第三栅极接收所述前级控制信号，所述第三漏极连接所述节点；一第四晶体管，设有第四源极、第四栅极以及第四漏极，所述第四源极以及所述第二栅极接收所述第一电压信号，所述第四漏极连接所述第三驱动模块；以及一第五晶体管，设有第五源极、第五栅极以及第五漏极，所述第五源极连接所述第四源极，所述第五栅极连接所述节点，所述第五漏极连接所述第二驱动模块以及所述第三驱动模块。
在一实施例中，所述第三驱动模块包括：一第六晶体管，设有第六源极、第六栅极以及第六漏极，所述第六源极连接所述第二驱动模块，所述第六栅极连接所述节点，所述第六漏极接收所述第二电压信号；一第七晶体管，设有第七源极、第七栅极以及第七漏极，所述第七源极连接所述第一驱动模块以及所述第二驱动模块，所述第七栅极连接所述第六源极，所述第七漏极连接所述第六漏极并且接收所述第二电压信号；一第八晶体管，设有第八源极、第八栅极以及第八漏极，所述第八源极连接所述节点，所述第八栅极接收所述后级控制信号，所述第八漏极连接所述第六漏极以及第七漏极并且接收所述第二电压信号；以及第九晶体管，设有第九源极、第九栅极以及第九漏极，所述第九源极连接所述扫描输出端，所述第九栅极连接所述第八栅极并且接收所述后级控制信号，所述第九漏极连接所述第六漏极、第七漏极以及第八漏极并且接收所述第二电压信号。
在一实施例中，所述栅极驱动架构的所述第一扫描信号与另一栅极驱动架构的第二扫描信号在所述时钟信号的周期为重迭状态，以形成对后级的扫描线作预先充电。
本专利申请第一实施例中提供一种阵列基板，包括栅极驱动架构，其中所述栅极驱动架构采用上述之栅极驱动架构。
 有益效果
本专利提供一种栅极驱动架构及其阵列基板，在一帧显示画面中，通过拉高以及拉低节点的电平，以控制扫描输出端的扫描信号的高电位以及低电位，以依序写入数据至一帧显示画面中全部的第一次列像素、全部第二列次像素以及全部第三列次像素，避免次像素单元产生电阻/电容延迟，防止色彩偏离现象，提高液晶面板的显示品质。
附图说明
图1:为根据本专利申请实施例中具备三栅极的像素排列的显示区域之示意图。
图2:为根据本专利申请实施例中栅极驱动架构的电路示意图。
图3A、3B:为根据本专利申请实施例中栅极驱动架构用以驱动各条栅极线的次像素之栅极信号的传递顺序示意图。
图4:为根据本专利申请实施例中栅极驱动架构以及数据信号的波形信号时序图。
 本发明的最佳实施方式
本专利申请说明书提供不同的实施例来说明本专利申请不同实施方式的技术特征。实施例中的各组件的配置是为了清楚说明本专利申请揭示的内容，并非用以限制本专利申请。在不同的图式中，相同的组件符号表示相同或相似的组件。
参考图1，其为根据本专利申请实施例中具备三栅极的像素排列的显示区域之示意图。如图1所示，液晶面板的阵列基板中，显示区域的帧显示画面100包括包括若干第一列次像素102RL、若干第二列次像素102GL以及若干第三列次像素102BL，每一列次像素102RL、102GL、102BL分别由若干次像素单元102R、102G、102B组成，每一第一列次像素102RL、每一第二列次像素102GL以及每一第三列次像素102BL分别相对应电性连接一条扫描线G(1)~G(6)，例如图1所示的6条扫描线，但是其数量不限于此，每一列次像素连接栅极电路(未图标)。每一行次像素D(1)~D(6)依序包括若干次像素单元102R、102G、102B，例如每一行次像素D(1)~D(6)包括六个次像素单元102R、102G、102B，但是其数量不限于此，每一行次像素连接一源极电路(未图标)。每个次像素单元102R、102G、102B包括一个晶体管104、连接晶体管104的液晶电容、以及连接晶体管104的保持电容。在每一条扫描线G(1)~G(6)与一列次像素102RL、102GL、102BL之间设有一栅极驱动架构。
参考图1及图2，图2为根据本专利申请实施例中栅极驱动架构的电路示意图。所述栅极驱动架构包括第一驱动模块200、第二驱动模块202以及第三驱动模块204。第一驱动模块200、第二驱动模块202以及第三驱动模块204彼此互相电性连接。第一驱动模块200用以接收时钟信号CK1例如责任周期是50%的方波信号，所述第一驱动模块200包括节点Q(n)以及扫描输出端G(n)，所述扫描输出端G(n)相对应连接一条扫描线G(1)~G(6)。第二驱动模块202电性连接所述第一驱动模块202，用以接收前级控制信号ST(n-9)(例如n=10，ST(n-9)是來自G(1)的信號)以及第一电压信号V1(例如是正电压电平信号VDD)，当所述前级控制信号ST(n-9)致能(enable)所述第二驱动模块202时，所述第二驱动模块202输出所述第一电压信号V1至所述第一驱动模块200，以拉高所述节点Q(n)的电位至高电平，并且当所述节点Q(n)处于高电平时，使所述扫描输出端G(n)依据所述时钟信号CK1的周期相对应输出具有高电平的第一扫描信号至一条扫描线G(1)~G(6)，以驱动所述第一列次像素102RL。
第三驱动模块204电性连接所述第一驱动模块202以及所述第二驱动模块204，第三驱动模块204用以接收后级控制信号ST(n+9)以及第二电压信号V2，当所述后级控制信号ST(n+9)致能所述第三驱动模块204时，所述第三驱动模块204输出所述第二电压信号V2(例如是负电压电平信号VSS)至所述第二驱动模块202，以拉低所述节点Q(n)以及所述扫描输出端G(n)的电位至低电平，并且当所述节点Q(n)处于低电平时，使所述扫描输出端G(n)依据所述时钟信号CK1的周期相对应输出具有低电平的所述第一扫描信号至相对应的一条扫描线G(1)~G(6)，直至以不同的栅极驱动架构完成所述若干第一列次像素的驱动。本专利申请在一帧显示画面100中，通过拉高(pull up)以及拉低(pull down)节点Q(n)的电平，以控制扫描输出端G(n)的扫描信号的高电位以及低电位，每一栅极驱动架构产生第一扫描信号以驱动每一第一列次像素102RL，使数据数据写入的每个第一列次像素102RL的第一次像素单元102R；然后以每一栅极驱动架构产生第二扫描信号以驱动每一第二列次像素102GL，使数据数据写入的每个第二列次像素102GL的第二次像素单元102G；最后以每一栅极驱动架构产生第三扫描信号以驱动每一第三列次像素102BL，使数据数据写入的每个第三列次像素102BL的第三次像素单元102B。
如图1及图2所示，所述帧显示画面100的配置方式依序为不同类型的第一列次像素102RL、第二列次像素102GL以及第三列次像素102BL，使所述若干第一列次像素102RL、若干第二列次像素102GL以及若干第三列次像素102BL形成所述帧显示画面100。在一实施例中，所述第一列次像素102RL、第二列次像素102GL以及第三列次像素102BL三种类型是由红色列次像素、绿色列次像素以及蓝色列次像素所组成。所述帧显示画面100的驱动顺序依序为所述若干第一列次像素102RL、所述若干第二列次像素102GL以及所述若干第三列次像素102BL。所述第一电压信号V1(例如是正电压VDD)的大于所述第二电压信号V2(例如是负电压VSS)，例如由直流电源转换器产生第一电压信号V1以及第二电压信号V2。
如图1及图2所示，所述第一驱动模块200包括第一晶体管T1以及第二晶体管T2。第一晶体管T1设有第一源极S1、第一栅极G1以及第一漏极D1，所述第一源极S1接收所述时钟信号CK1，所述第一栅极G1连接所述节点Q(n)，所述第一漏极D1连接所述扫描输出端G(n)，以依据所述时钟信号CK1的周期相对应输出所述第一扫描信号，其中”n”表示正整数且为扫描线及/或是列次像素的级数。第二晶体管T2设有第二源极S2、第二栅极G2以及第二漏极D2，所述第二源极S2连接所述第一源极S1并且接收所述时钟信号CK1，所述第二栅极G2连接所述第一栅极G1以及所述节点Q(n)，所述第二漏极D2输出一目前控制信号ST(n)，所述目前控制信号ST(n)与所述扫描输出端G(n)的第一扫描信号相同。电容C的两端部分别连接所述节点Q(n)以及所述扫描输出端G(n)。电容C用以第二次拉高节点Q(n)电位。
如图1及图2所示，所述第二驱动模块204包括第三晶体管T3、第四晶体管T4以及第五晶体管T5。第三晶体管T3设有第三源极S3、第三栅极G3以及第三漏极D3，所述第三源极S3接收所述第一电压信号V1，所述第三栅极G3接收所述前级控制信号ST(n-9)，所述第三漏极D3连接所述节点Q(n)。第四晶体管T4设有第四源极S4、第四栅极G4以及第四漏极D4，所述第四源极S4以及所述第二栅极G2接收所述第一电压信号V1，所述第四漏极D4连接所述第三驱动模块204。第五晶体管T5设有第五源极S5、第五栅极G5以及第五漏极D5，所述第五源极S5连接所述第四源极S4，所述第五栅极G5连接所述节点Q(n)，所述第五漏极D5连接所述第二驱动模块202以及所述第三驱动模块204。
如图1及图2所示，所述第三驱动模块包括第六晶体管T6、第七晶体管T7、第八晶体管T8以及第九晶体管T9。第六晶体管T6设有第六源极S6、第六栅极G6以及第六漏极D6，所述第六源极D6连接所述第二驱动模块202，所述第六栅极G6连接所述节点Q(n)，所述第六漏极D6接收所述第二电压信号V2。第七晶体管T7设有第七源极S7、第七栅极G7以及第七漏极D7，所述第七源极S7连接所述第一驱动模块200以及所述第二驱动模块202，所述第七栅极G7连接所述第六源极S6，所述第七漏极D7连接所述第六漏极D6并且接收所述第二电压信号V2。第八晶体管T8设有第八源极S8、第八栅极G8以及第八漏极D8，所述第八源极S8连接所述节点Q(n)，所述第八栅极G8接收所述后级控制信号ST(n+9)，所述第八漏极D8连接所述第六漏极D6以及第七漏极D7并且接收所述第二电压信号V2。第九晶体管T9设有第九源极S9、第九栅极G9以及第九漏极D9，所述第九源极S9连接所述扫描输出端G(n)，所述第九栅极G9连接所述第八栅极G8并且接收所述后级控制信号ST(n+9)，所述第九漏极G9连接所述第六漏极D6、第七漏极D7以及第八漏极D8并且接收所述第二电压信号V2。应注意的是，本专利申请的晶体管的源极以及漏极可以互换。在图2中，第一晶体管T1、第二晶体管T2、第五晶体管T5以及第六晶体管T6的栅极所连接的节点Q(n)具有相同的电平。
图3A以及图3B为根据本专利申请实施例中栅极驱动架构用以驱动各条栅极线的次像素之栅极信号的传递顺序示意图。在图3A以及图3B中是全高清(full high definition, FHD)分辨率为例，其一条列次像素的数量为3240(等于1080条像素列*3，三条列次像素组成一像素列)。在图3A中，包括六条时钟信号CK1~CK6，例如由时序控制器产生时钟信号CK1~CK6，六个栅极驱动架构3223(R)、3226(R)、3229(R)、3232(R)、3235(R)、3238(R)，分别连接六条时钟信号CK1~CK6；六个栅极驱动架构3239(G)、3236(G)、3233(G)、3230(G)、3227(G)、3224(G)，分别连接六条时钟信号CK1~CK6，栅极驱动架构3223(R)与栅极驱动架构3232(R)之间的前级控制信号ST(3223)以及后级控制信号ST(3232)；栅极驱动架构3226(R)与栅极驱动架构3235(R)之间的前级控制信号ST(3226)以及后级控制信号ST(3235)；栅极驱动架构3229(R)与栅极驱动架构3238(R)之间的前级控制信号ST(3229)以及后级控制信号ST(3238)。同样地，栅极驱动架构3239(G)与栅极驱动架构3230(G)之间的前级控制信号ST(3239)以及后级控制信号ST(3230)；栅极驱动架构3236(G)与栅极驱动架构3227(G)之间的前级控制信号ST(3236)以及后级控制信号ST(3227)；栅极驱动架构3233(G)与栅极驱动架构3224(G)之间的前级控制信号ST(3233)以及后级控制信号ST(3224)。图3A表示先写入在一帧显示画面100中的红色列次像素，等待所述帧显示画面100全部的红色列次像素的数据写完之后，接着写入所述帧显示画面100全部的绿色列次像素的数据。如图3A所示的实施例中，在一帧显示画面100是从下至上依序写入红色列次像素的数据，然后写入绿色列次像素的数据。
在图3B中，包括六条时钟信号CK1~CK6，六个栅极驱动架构17(G)、14(G)、11(G)、8(G)、5(G)、2(G)，分别连接六条时钟信号CK1~CK6；六个栅极驱动架构3(B)、6(B)、9(B)、12(B)、15(B)、18(B)，分别连接六条时钟信号CK1~CK6，栅极驱动架构17(G)与栅极驱动架构8(G)之间的前级控制信号ST(17)以及后级控制信号ST(8)；栅极驱动架构14(G)与栅极驱动架构5(G)之间的前级控制信号ST(14)以及后级控制信号ST(5)；栅极驱动架构11(G)与栅极驱动架构2(G)之间的前级控制信号ST(11)以及后级控制信号ST(2)。同样地，栅极驱动架构3(B)与栅极驱动架构12(B)之间的前级控制信号ST(3)以及后级控制信号ST(12)；栅极驱动架构6(B)与栅极驱动架构15(B)之间的前级控制信号ST(6)以及后级控制信号ST(15)；栅极驱动架构9(B)与栅极驱动架构18(B)之间的前级控制信号ST(9)以及后级控制信号ST(18)。图3A表示先写入在一帧显示画面100中的绿色列次像素，等待全部的绿色列次像素的数据写完之后，接着写入全部的蓝色列次像素的数据。如图3B所示的实施例中，在一帧显示画面100是从上至下依序写入绿色列次像素的数据，然后写入蓝色列次像素的数据。
参考图4，其为根据本专利申请实施例中栅极驱动架构以及数据信号的波形信号时序图。一帧显示画面100的启动信号STV、六条时钟信号CK1~CK6、第一电压信号V1(例如是正电压电平信号VDD)、第二电压信号V2(例如是负电压电平信号VSS)、扫描信号G(1)、G(4)、G(7)、G(10)、G(13)、G(16)、以及数据信号，六条时钟信号CK1~CK6例如是具有一相位差的方波信号，分别相对应于扫描信号G(1)、G(4)、G(7)、G(10)、G(13)、G(16)。在一帧显示画面100内，先全部写入红色，再全部写入绿色，最后是蓝色，所以在一帧显示画面内红、绿、蓝都是只在第一条扫描线(例如红色列次像素G(1))打开时受数据延迟的影响，其余同一种类的次像素单元(例如红色列次像素G(4)、G(7)、G(10)、G(13)、G(16))不受数据延迟的影响，故可改善色偏的问题，例如在一帧显示画面中，数据信号依据扫描信号将先显示1/3帧红色列次像素400R，接着显示1/3帧绿色列次像素400G，最后1/3帧蓝色列次像素400B。此外，所述栅极驱动架构的所述第一扫描信号G(1)与另一栅极驱动架构的第二扫描信号G(4)在所述时钟信号CK1的周期为重迭状态，以形成对后级的扫描线G(4)作预先充电，使扫描线的充电信号电平维持在足够的准位。在图4的实施例中，节点Q(1)、Q(4)、Q(7)的信号与启动信号STV的波形信号相同，如图4所示的启动信号STV，其余各级为各该级G(n)信号与ST(n-9)信号的迭加。
本专利申请之栅极驱动架构及其阵列基板，在一帧显示画面中，通过拉高以及拉低节点的电平，以控制扫描输出端的扫描信号的高电位以及低电位，以依序写入数据至一帧显示画面中全部的第一次列像素、全部第二列次像素以及全部第三列次像素，避免次像素单元产生电阻/电容延迟，防止色彩偏离现象，提高液晶面板的显示品质。
虽然本专利申请已用较佳实施例揭露如上，然其并非用以限定本专利申请，本专利申请所属技术领域中具有通常知识者，在不脱离本专利申请的精神和范围内，当可作各种的更动与润饰，因此本专利申请的保护范围当视后附的权利要求范围所界定者为准。

Claims (10)

  1. 一种栅极驱动架构，设置于液晶面板的阵列基板上，所述阵列基板包括一帧显示画面，所述帧显示画面包括若干第一列次像素、若干第二列次像素以及若干第三列次像素，每一第一列次像素、每一第二列次像素以及每一第三列次像素分别相对应电性连接一条扫描线，每一扫描线相对应一栅极驱动架构，其中所述栅极驱动架构包括：
    一第一驱动模块，用以接收时钟信号，所述第一驱动模块包括一节点以及一扫描输出端，所述扫描输出端相对应连接一条扫描线；
    一第二驱动模块，电性连接所述第一驱动模块，用以接收前级控制信号以及第一电压信号，当所述前级控制信号致能所述第二驱动模块时，所述第二驱动模块输出所述第一电压信号至所述第一驱动模块，以拉高所述节点的电位至高电平，并且当所述节点处于高电平时，使所述扫描输出端依据所述时钟信号的周期相对应输出具有高电平的一第一扫描信号至一条扫描线，以驱动所述第一列次像素；以及
    一第三驱动模块，电性连接所述第一驱动模块以及所述第二驱动模块，用以接收后级控制信号以及第二电压信号，当所述后级控制信号致能所述第三驱动模块时，所述第三驱动模块输出所述第二电压信号至所述第二驱动模块，以拉低所述节点以及所述扫描输出端的电位至低电平，并且当所述节点处于低电平时，使所述扫描输出端依据所述时钟信号的周期相对应输出具有低电平的所述第一扫描信号至所述扫描线，直至以不同的栅极驱动架构完成所述若干第一列次像素的驱动。
  2. 根据权利要求1所述的栅极驱动架构，其中所述帧显示画面的配置方式依序为不同类型的第一列次像素、第二列次像素以及第三列次像素，使所述若干第一列次像素、若干第二列次像素以及若干第三列次像素形成所述帧显示画面。
  3. 根据权利要求2所述的栅极驱动架构，其中所述第一列次像素、第二列次像素以及第三列次像素三种类型是由红色列次像素、绿色列次像素以及蓝色列次像素所组成。
  4. 根据权利要求1所述的栅极驱动架构，其中所述第一电压信号的大于所述第二电压信号，并且所述第一电压信号是正电压信号，所述第二电压信号是负电压信号。
  5. 根据权利要求1所述的栅极驱动架构，其中所述帧显示画面的驱动顺序依序为所述若干第一列次像素、所述若干第二列次像素以及所述若干第三列次像素。
  6. 根据权利要求1所述的栅极驱动架构，其中所述第一驱动模块包括：
    一第一晶体管，设有第一源极、第一栅极以及第一漏极，所述第一源极接收所述时钟信号，所述第一栅极连接所述节点，所述第一漏极连接所述扫描输出端，以依据所述时钟信号的周期相对应输出所述第一扫描信号；
    一第二晶体管，设有第二源极、第二栅极以及第二漏极，所述第二源极连接所述第一源极并且接收所述时钟信号，所述第二栅极连接所述第一栅极以及所述节点，所述第二漏极输出一目前控制信号，所述目前控制信号与所述第一扫描信号相同；以及
    一电容，所述电容的两端部分别连接所述节点以及所述扫描输出端。
  7. 根据权利要求1所述的栅极驱动架构，其中所述第二驱动模块包括：
    一第三晶体管，设有第三源极、第三栅极以及第三漏极，所述第三源极接收所述第一电压信号，所述第三栅极接收所述前级控制信号，所述第三漏极连接所述节点；
    一第四晶体管，设有第四源极、第四栅极以及第四漏极，所述第四源极以及所述第二栅极接收所述第一电压信号，所述第四漏极连接所述第三驱动模块；以及
    一第五晶体管，设有第五源极、第五栅极以及第五漏极，所述第五源极连接所述第四源极，所述第五栅极连接所述节点，所述第五漏极连接所述第二驱动模块以及所述第三驱动模块。
  8. 根据权利要求1所述的栅极驱动架构，其中所述第三驱动模块包括：
    一第六晶体管，设有第六源极、第六栅极以及第六漏极，所述第六源极连接所述第二驱动模块，所述第六栅极连接所述节点，所述第六漏极接收所述第二电压信号；
    一第七晶体管，设有第七源极、第七栅极以及第七漏极，所述第七源极连接所述第一驱动模块以及所述第二驱动模块，所述第七栅极连接所述第六源极，所述第七漏极连接所述第六漏极并且接收所述第二电压信号；
    一第八晶体管，设有第八源极、第八栅极以及第八漏极，所述第八源极连接所述节点，所述第八栅极接收所述后级控制信号，所述第八漏极连接所述第六漏极以及第七漏极并且接收所述第二电压信号；以及
    一第九晶体管，设有第九源极、第九栅极以及第九漏极，所述第九源极连接所述扫描输出端，所述第九栅极连接所述第八栅极并且接收所述后级控制信号，所述第九漏极连接所述第六漏极、第七漏极以及第八漏极并且接收所述第二电压信号。
  9. 根据权利要求1所述的栅极驱动架构，其中所述栅极驱动架构的所述第一扫描信号与另一栅极驱动架构的第二扫描信号在所述时钟信号的周期为重迭状态，以形成对后级的扫描线作预先充电。
  10. 一种阵列基板，包括栅极驱动架构，其中所述栅极驱动架构采用权利要求1所述的栅极驱动架构。
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