WO2015032238A1 - 栅极驱动单元、栅极驱动电路和显示装置 - Google Patents

栅极驱动单元、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2015032238A1
WO2015032238A1 PCT/CN2014/081116 CN2014081116W WO2015032238A1 WO 2015032238 A1 WO2015032238 A1 WO 2015032238A1 CN 2014081116 W CN2014081116 W CN 2014081116W WO 2015032238 A1 WO2015032238 A1 WO 2015032238A1
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WIPO (PCT)
Prior art keywords
transistor
circuit
gate
signal
gate driving
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PCT/CN2014/081116
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English (en)
French (fr)
Inventor
徐向阳
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US14/422,219 priority Critical patent/US9721510B2/en
Publication of WO2015032238A1 publication Critical patent/WO2015032238A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • Gate drive unit gate drive circuit and display device
  • the present invention relates to the field of display technologies, and in particular, to a gate driving unit, a gate driving circuit, and a display device. Background technique
  • liquid crystal display devices LCDs
  • organic electroluminescent diode (OLED) display devices are still the mainstream products for flat panel displays.
  • a thin film transistor (TFT) is generally used to control each pixel unit, thereby realizing image display.
  • the control of the pixel unit includes row control and column control.
  • the row control usually uses a gate drive circuit to realize progressive scan of the pixel unit.
  • the gate drive circuit eg, Gate driver On Array, GO A
  • the column control usually uses a data driving circuit to realize column-by-column scanning of pixel units, thereby realizing the transmission of display data.
  • the conventional gate driving circuit is composed of a plurality of gate driving units cascaded, each of the gate driving units has the same circuit structure, and is composed of four thin film transistors and one capacitor, that is, a 4T1C structure; each gate driving unit has The working process is the same, only the input and output signals are different.
  • the circuit structure of a typical gate driving unit is shown in FIG. 1.
  • the circuit interface of the gate driving unit is shown in FIG. 2, wherein Vclk is a clock signal input end, and Clock is a clock signal input from a clock signal input end.
  • Vss is the low-potential signal input terminal
  • Output[nl], Output[n], and Output[n+l] are the gate drive signals of the pixel cells of the n-1th row, the nth row, and the n+1th row, respectively.
  • the operation process of the gate driving unit is: first, the gate driving signal Output[nl] of the n-1th row outputs a high level pulse signal, turns on the thin film transistor TFT4 and charges the capacitor Cd, and simultaneously gates the thin film transistor TFT1.
  • the gate drive signal of the nth row Output[n] outputs a high-level pulse signal with the clock signal Clock, thus turning on the nth row of pixel units, and then the gate drive signal Output [n+ 1 ] of the n+1th row outputs a high-level pulse signal.
  • the thin film transistor TF T2 and the thin film transistor TFT3 are turned on, so that the capacitor Cd and the gate drive signal Output[n] of the nth row are pulled low by the low potential signal input from the low potential input terminal Vss, so that the thin film transistor TFT1 is turned off. And keeping the gate drive signal Output[n] of the nth row at a low potential, thereby turning off the nth row of pixel cells.
  • the gate driving circuit is composed of n gate driving units, the circuit connection is complicated, and the entire gate driving circuit has a large area, so the area occupied by the substrate is also large, which is disadvantageous for the development of the display panel in the direction of miniaturization and low cost.
  • the gate driving circuit With the development of flat panel display technology, narrow bezel, thinness and low cost have become the trend of flat panel display, especially for small size and high resolution products, simplifying the gate drive circuit and reducing the gate drive circuit area.
  • the present invention is directed to the above technical problems existing in the prior art, and provides a gate driving unit, a gate driving circuit, and a display device.
  • the gate driving unit can output the gate driving signals of the two rows of pixel units, and the use efficiency is high; when the number of gate rows of the pixel unit to be driven is the same, the gate driving circuit composed of the gate driving unit is used, The number of pole drive units can be reduced by half, correspondingly reducing the footprint of the gate drive circuit; and also improving the drive efficiency of the gate drive circuit.
  • the present invention provides a gate driving unit including: an input circuit, a pull-up circuit, a reset circuit, and an output circuit, the input circuit being respectively connected to the pull-up circuit and the reset circuit, the pull-up circuit and the The reset circuit is respectively connected to the output circuit;
  • the input circuit is configured to receive a pull-up driving signal, and input the pull-up driving signal to the pull-up circuit;
  • the pull-up circuit is configured to receive the pull-up driving signal, and output a high-level signal to an input end of the output circuit;
  • the reset circuit is configured to receive a reset driving signal, and to output the output circuit
  • the high level signal of the input terminal is reset to a low level signal
  • the output circuit is configured to receive an output signal of the pull-up circuit and an output signal of the reset circuit, and output a gate drive signal under control of the clock signal;
  • the pull-up drive signal received in the input circuit includes The gate driving signals of the n-2 row pixel unit and the n+4th row pixel unit;
  • the reset driving signal received in the reset circuit includes an n+2th row pixel unit and an n+8th row pixel unit
  • the gate driving signal outputted by the output circuit includes the gate driving signals of the nth row of pixel cells and the n+6th row of pixel cells, n being a positive integer, and ne [3, Oo ).
  • the input circuit comprises a first transistor, a second transistor and a fifth transistor, wherein the gates of the first transistor and the second transistor are respectively connected to respective sources, and the drains are simultaneously connected to the fifth a gate of the transistor is connected to the drain, a source of the fifth transistor is simultaneously connected to the pull-up circuit and the reset circuit, and a gate driving signal of the n-2th row of pixel units is input to the first a gate of a transistor, a gate drive signal of the n+4th row of pixel cells is input to a gate of the second transistor;
  • the pull-up circuit includes a sixth transistor and a capacitor connected between a gate and a source of the sixth transistor, and a gate of the sixth transistor is further connected to a source of a fifth transistor in the input circuit a pole and a drain are connected to the high potential end, and a source is further connected to the input end of the output circuit;
  • the reset circuit includes a third transistor, a fourth transistor, a seventh transistor, and an eighth transistor, wherein the gates of the third transistor and the fourth transistor are respectively connected to respective sources, and the drains are simultaneously a seventh transistor connected to a gate of the eighth transistor, a gate of the seventh transistor and a gate of the eighth transistor, a source of the seventh transistor and the first of the input circuits a source of five transistors is connected, a source of the eighth transistor is connected to a source of the sixth transistor in the pull-up circuit, and a drain of the seventh transistor and the eighth transistor are simultaneously connected to At the low potential end, the gate drive signal of the n+2th pixel unit is driven
  • the output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, and a gate of the eleventh transistor is connected to a first clock signal or a second clock signal, the twelfth transistor The gate is connected to the third clock signal or the fourth clock signal, and the sources of the eleventh transistor and the
  • the pulse widths of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all equal, and the duty ratio is 1/2, the first clock The signal is advanced by 1/2 cycle than the third clock signal, and the second clock signal is advanced by 1/2 cycle than the fourth clock signal.
  • the gate driving signal of the pixel unit of the first row or the second row received by the input circuit is a 1/2 frame start signal.
  • the gate drive signals of two adjacent odd-numbered rows or adjacent two even-numbered rows of pixel cells are separated by 1/2 cycle.
  • the gate driving unit inputs the gate driving signals of the n-2th row pixel unit and the n+4th row pixel unit through the input circuit to precharge the pull-up circuit ;
  • a high-level signal can be output, and the high-level signal causes the output circuit to output the n-th row of pixel units under the control of the first to fourth clock signals.
  • the gate driving unit inputs the gate driving signals of the n+2th row pixel unit and the n+8th row pixel unit through the reset circuit, so that the outputted nth row of pixel units and The gate driving signal of the n+6th pixel unit is reset to a low level signal by a high level signal.
  • the present invention also provides a gate driving circuit including the plurality of gate driving units, wherein the plurality of gate driving units are sequentially cascaded.
  • the respective clock signals used by two adjacent ones of the plurality of gate driving units are sequentially spaced by 1/4 cycle.
  • the gate driving circuit includes two 1/2 frame start signals and two 1/2 frame reset signals, and the two 1/2 frame start signals are respectively used as the first row and the second row of pixels.
  • a pull-up driving signal of a gate driving signal of the cell wherein the two 1/2-frame reset signals respectively serve as reset driving signals of gate driving signals of the last two rows of pixel units, and the two 1/2 frame starts
  • the interval between the signals is 1/4 cycle of the clock signal, and the interval between the two 1/2 frame reset signals is 1/4 cycle of the clock signal.
  • the present invention also provides a display device including the above-described gate driving circuit.
  • Advantageous Effects of Invention The gate driving unit provided by the present invention respectively inputs gate driving signals of two rows of pixel units at input terminals of the input circuit and the reset circuit, and outputs two rows of pixel units at an output end of the output circuit.
  • the gate driving signal is more efficient in the gate driving unit of the present invention than the gate driving unit in the prior art which can output only the gate driving signals of one row of pixel cells.
  • the gate driving circuit provided by the present invention reduces the area occupied by the entire gate driving circuit by reducing the number of gate driving units; in addition, the adjacent two rows of the output of the adjacent two gate driving units
  • the gate driving signals of the pixel unit are spaced apart by 1/4 cycle, which shortens the charging time and improves the charging efficiency, thereby improving the driving efficiency of the entire gate driving circuit.
  • FIG. 1 is a circuit diagram of a gate driving unit in the prior art
  • FIG. 2 is a schematic diagram of a circuit interface of the gate driving unit of FIG. 1;
  • FIG. 3 is a circuit diagram of a gate driving unit according to Embodiment 1 of the present invention
  • FIG. 4 is a timing chart of driving of a gate driving unit according to Embodiment 1 of the present invention
  • FIG. 5 is a circuit diagram of a gate driving circuit according to Embodiment 2 of the present invention
  • Fig. 6 is a timing chart showing the driving of the gate driving circuit in the second embodiment of the present invention.
  • the reference numerals are as follows:
  • the embodiment provides a gate driving unit.
  • the gate driving unit includes: an input circuit 1, a pull-up circuit 2, a reset circuit 3, and an output circuit 4.
  • the input circuit 1 and the pull-up circuit 2 are respectively The reset circuit 3 is connected, and the pull-up circuit 2 and the reset circuit 3 are connected to the output circuit 4, respectively. among them,
  • the input circuit 1 is configured to receive a pull-up drive signal, and the pull-up circuit 2 inputs the pull-up drive signal;
  • a pull-up circuit 2 configured to receive the pull-up driving signal, and output a high-level signal to an input terminal PU of the output circuit 4;
  • a reset circuit 3 configured to receive a reset driving signal, and reset a high level signal of the input terminal PU of the output circuit 4 to a low level signal;
  • the output circuit 4 is configured to receive an output signal of the pull-up circuit 2 and an output signal of the reset circuit 3, and output a gate drive signal under the control of the clock signal.
  • the pull-up driving signal received in the input circuit 1 includes the gate driving signals of the n-2th row and the n+th row of pixel cells; the reset driving signal received in the reset circuit 3 includes the n+2th row. And a gate driving signal of the pixel unit of the n+8th row; the gate driving signal output by the output circuit 4 includes a gate driving signal of the pixel row of the nth row and the n+th row, n is a positive integer, and ne [3 , oo ).
  • the specific circuit of the gate drive unit is:
  • the input circuit 1 includes a first transistor M1, a second transistor M2, and a fifth transistor M5.
  • the gates of the first transistor M1 and the second transistor M2 are respectively connected to respective sources, and the drain is simultaneously connected to the gate of the fifth transistor M5.
  • the source of the five-transistor M5 is simultaneously connected to the pull-up circuit 2 and the reset circuit 3.
  • the gate drive signal of the n-2th pixel unit is input to the gate of the first transistor M1, and the gate of the n+4th pixel unit
  • the drive signal is input to the gate of the second transistor M2.
  • the pull-up circuit 2 includes a sixth transistor M6 and a capacitor Cb connected between the gate and the source of the sixth transistor M6, and the gate of the sixth transistor M6 is also connected to the source of the fifth transistor M5 in the input circuit 1.
  • the drain is connected to the high potential terminal Vgh, and the source is also connected to the input terminal PU of the output circuit 4.
  • the reset circuit 3 includes a third transistor M3, a fourth transistor M4, a seventh transistor M7, and an eighth transistor M8.
  • the gates of the third transistor M3 and the fourth transistor M4 are respectively connected to respective sources, and the drains are simultaneously and seventh.
  • the gate of the transistor M7 and the eighth transistor M8 are connected, the gate of the seventh transistor M7 is connected to the gate of the eighth transistor M8, and the source of the seventh transistor M7 is connected to the source of the fifth transistor M5 in the input circuit 1.
  • the source of the eighth transistor M8 is connected to the source of the sixth transistor M6 in the pull-up circuit 2, and the drains of the seventh transistor M7 and the eighth transistor M8 are simultaneously connected to the low potential terminal Vss, the n+2th row of pixels
  • the gate drive signal of the cell is input to the gate of the third transistor M3, and the gate drive signal of the n+8th row of pixel cells is input to the gate of the fourth transistor M4.
  • the output circuit 4 includes a ninth transistor M9, a tenth transistor M10, a first transistor Mi l and a twelfth transistor M12.
  • the gate of the first transistor Mi l is connected to the first clock signal CLKA or the second clock signal CLKB.
  • the gate of the twelve transistor M12 is connected to the third clock signal CLKC or the fourth clock signal CLKD, and the sources of the first transistor Mi1 and the twelfth transistor M12 are simultaneously connected to the source of the sixth transistor M6 in the pull-up circuit 2.
  • the gates of the ninth transistor M9 and the tenth transistor M10 are simultaneously connected to the gate of the seventh transistor M7 in the reset circuit 3, and the drain of the first transistor Mi1 is connected to the source of the ninth transistor M9, and Outputting a gate driving signal of the pixel unit of the nth row, a drain of the twelfth transistor M12 is connected to a source of the tenth transistor M10, and outputting a gate driving signal of the pixel unit of the n+6th row, the ninth transistor M9 and The drain of the tenth transistor M10 is simultaneously connected to the low potential terminal Vss.
  • the two adjacent gate driving units respectively use two clock signals spaced apart from each other by 1/2 cycle, gp, and two clock signals used by one of the two adjacent gate driving units are mutually At intervals of 1/2 cycle, the two clock signals used by the other gate drive unit are also spaced apart by 1/2 cycle.
  • the first clock signal CLKA and the third clock signal CLKC adopts the first clock signal CLKA and the third clock signal CLKC
  • another gate driving unit adjacent thereto adopts the second clock signal CLKB and the fourth clock signal CLKD
  • the first clock signal CLKA And the third clock signal CLKC is two clock signals spaced apart by 1/2 cycle
  • the second clock signal CLKB and the fourth clock signal CLKD are two clock signals separated by 1/2 cycle.
  • the tenth transistor M10, the first transistor Mi l and the twelfth transistor M12 are preferably thin film transistors.
  • other types of transistors having a gate switching function can also be selected.
  • the gate of the thin film transistor When the gate of the thin film transistor is turned on and the voltage difference between the source and the drain satisfies the on condition, the thin film transistor is turned on.
  • the source is the signal input end of the thin film transistor
  • the drain is the signal output end of the thin film transistor, and vice versa.
  • the voltage of the source of the thin film transistor is high, current flows from the source to the drain; when the voltage of the drain of the thin film transistor is high, current flows from the drain to the source, that is, the source and the drain are interchangeable. .
  • the pulse widths of the first clock signal CLKA, the second clock signal CLKB, the third clock signal CLKC, and the fourth clock signal CLKD are all equal, and the duty ratio is 1/2, and the first clock signal CLKA is equal to
  • the three clock signal CLKC is advanced by 1/2 cycle
  • the second clock signal CLKB is advanced by 1/2 cycle than the fourth clock signal CLKD.
  • the gate drive signal (pull pull drive signal) of the pixel unit of the first row or the second row received by the input circuit 1 is a 1/2 frame start signal as an initial trigger signal.
  • the gate driving signals of two adjacent odd-numbered rows or adjacent two even-numbered row pixel cells are separated by 1/2 cycle. With this arrangement, it is possible to ensure that adjacent odd-numbered rows or adjacent even-numbered rows of pixel cells can output gate drive signals row by row.
  • the embodiment further provides a gate driving method.
  • a specific driving process of the gate driving unit will be described by taking a gate driving unit using the first clock signal CLKA and the third clock signal CLKC as an example.
  • the driving timing of the gate driving method is as shown in FIG. 4 , and the gate driving method specifically includes the following steps, wherein the gate driving signal of the pixel unit of the n-2th row is taken as an example to illustrate the gate driving unit. work process.
  • Step S1 is the first stage in the gate driving process: when the first 1/2 period of the first clock signal CLKA is a low level signal, and the first 1/2 period of the third clock signal CLKC is a high level signal,
  • the input circuit 1 inputs a gate driving signal of the n-2th pixel unit, the gate driving signal of the n-2th pixel unit is a high level pulse signal; and the gate driving signal of the n-2th pixel unit is used as The pull-up drive signal pre-charges the capacitor Cb through the fifth transistor M5.
  • the input gate drive signal is an initial trigger signal whose magnitude and period are the same as the high-level pulse signal.
  • the initial trigger signal is provided by an external trigger circuit that initiates the driving of the gate drive unit.
  • Pull-up circuit 2 outputs a high-level signal after pre-charging is completed, and the high-level signal causes output circuit 4 to output the gate of pixel row of nth row under the control of first clock signal CLKA and third clock signal CLKC Drive signal.
  • step S1 after the first 1/2 period of the first clock signal CLKA, the gate driving signal of the pixel unit of the n-2th row is used as the precharge voltage signal of the gate driving signal of the pixel row of the nth row, to the capacitor Cb is precharged, and at the same time as the first 1/2 period of the first clock signal CLKA ends, the precharge of the capacitor Cb is completed, that is, the precharge of the pull-up circuit 2 is completed, so that the gate of the sixth transistor M6 in the pull-up circuit 2 Extremely high.
  • Step S2 is the second phase in the gate driving process: at the beginning of the second 1/2 cycle of the first clock signal CLKA, the first clock signal CLKA jumps to a high level signal, and the third clock signal CLKC jumps Becomes a low level signal at high potential
  • the output terminal PD of the pull-up circuit 2 outputs a high level signal
  • the high level signal causes the output circuit 4 to output the gate driving signal of the pixel unit of the nth row under the control of the first clock signal CLKA.
  • the signal is a high level pulse signal for turning on the nth row of pixel units; meanwhile, the gate drive signal of the nth row of pixel units is also used as the gate drive of the n+2th row of pixel units
  • the precharge voltage signal of the signal, and the reset drive signal as the gate drive signal of the n-2th pixel unit, that is, the gate drive signal of the n-2th pixel unit are reset.
  • Step S3 is the third stage in the gate driving process: in the first 1/2 period of the next period of the first clock signal CLKA, the gate driving signal of the pixel unit of the nth row is used as the n+2th row pixel unit
  • the precharge voltage signal of the gate drive signal precharges the capacitor Cb; meanwhile, the gate drive signal of the n+2th row of pixel cells resets the gate drive signal of the nth row of pixel cells.
  • the reset circuit 3 inputting a gate driving signal Output[n+2] of the pixel unit of the n+2th row, a gate driving signal of the pixel node of the n+2th row is a high level pulse signal, and the n+2th row of pixel units
  • the gate driving signal turns on the seventh transistor M7 and the eighth transistor M8.
  • the sixth transistor M6 Under the pulling of the low potential terminal Vss, the two plates in the capacitor Cb and the high level signal output from the output terminal PD of the pull-up circuit 2 Pulled low, the sixth transistor M6 is turned off, and the gate driving signal of the n+2th pixel unit further turns on the ninth transistor M9, so that the gate driving signal Output[n] of the nth row of pixel units
  • the low potential terminal Vss is pulled low and remains low, that is, the gate driving signal of the pixel unit of the nth row is reset to a low level signal.
  • the gate driving unit completes the output and reset of the gate driving signal of the pixel unit of the nth row.
  • the gate drive signal Output[n+6] of the pixel unit of the n+6th row Output and reset the gate drive signal Output[n+4] (pull drive signal) of the pixel unit in the n+4th row
  • the gate drive signal Output[n+8] of the n+8th pixel unit (reset drive) The signal), the first clock signal CLKA, and the third clock signal CLKC are combined in accordance with the above driving method.
  • the gate driving unit in this embodiment respectively inputs the gate driving signals of the two rows of pixel cells at the input ends of the input circuit 1 and the reset circuit 3, and outputs the gates of the two rows of pixel cells at the output terminal of the output circuit 4. Driving the signal, thereby improving the use efficiency of the gate driving unit.
  • the number of gate rows of the pixel unit to be driven is the same, using the gate driving circuit composed of the gate driving unit, the number of the gate driving unit may be By halving, the footprint of the gate drive circuit is correspondingly reduced.
  • the present embodiment provides a gate driving circuit, as shown in FIG. 5, including the above-described gate driving unit GOA, which is formed by sequentially cascading a plurality of the gate driving units GOA.
  • the plurality of gate driving units GOA sequentially alternately adopt a first clock signal CLKA and a third clock signal CLKC, and a second clock signal CLKB and a fourth clock signal CLKD, that is, adjacent two gates
  • One gate driving unit in the driving unit adopts a first clock signal CLKA and a third clock signal CLKC, and the other gate driving unit adopts a second clock signal CLKB and a fourth clock signal CLKD.
  • the four clock signals used by the adjacent two gate driving units GOA are sequentially spaced by 1/4 cycle, gp, and the first clock signal CLKA and the second clock signal CLKB are separated by 1/4 cycle.
  • the second clock signal CLKB is spaced apart from the third clock signal CLKC by 1/4 cycle, and the third clock signal CLKC and the fourth clock signal CLKD are separated by 1/4 cycle.
  • the gate driving circuit includes two 1/2 frame start signals and two 1/2 frame reset signals, wherein “frame” is a time parameter when the display screen is displayed, "1"
  • the frame is the time taken to scan from the first row of pixel cells to the last row of pixel cells, that is, the time taken to drive the entire screen once; for the same reason, "1/2 frame” is the time used for half-screen driving; "1/2 frame
  • the start signal is a signal sent at intervals of 1/2 frame.
  • the two 1/2 frame start signals are used as pull-up drive signals for the gate drive signals of the pixel units of the first and second rows, respectively, and two The interval between the start signals of the 1/2 frames is 1/4 cycle of the clock signal.
  • the first odd gate drive unit and the first even gate drive unit in the drive order (usually corresponding The first gate driving unit and the second gate driving unit respectively need an initial trigger signal, and the two initial trigger signals are both 1/2 frame start signals.
  • the odd-numbered gate driving units respectively Driving the gates of the odd-line pixel units
  • the even-numbered gate drive units respectively drive the gates of the even-numbered rows of pixel units.
  • the "1/2 frame reset signal” refers to a reset signal at intervals of 1/2 frame. 1/2 frame reset signal as the most The reset signal driving the gate driving signal lines of the two pixel units, and an interval between two reset signals 1/2 1/4 cycles of the clock signal.
  • the four gate driving units are respectively a first gate driving unit and a second a gate driving unit, a third gate driving unit, and a fourth gate driving unit, and sequentially outputting the first clock signal CLKA, the second clock signal CLKB, the third clock signal CLKC, and the fourth clock signal CLKD Gate drive signals for n-2 rows, n-1th rows, nth rows, and n+1th rows of pixel cells.
  • the driving process of the above gate driving circuit is:
  • the first stage is a first stage
  • the first pull-up driving is provided for the gate driving signal of the n-2th row pixel unit through the input circuit of the first gate driving unit a signal, the first pull-up driving signal pre-charging a gate driving signal of the n-2th pixel unit; while the first 1/4 period ends, the first clock signal CLKA becomes a high level signal , output gate driving signal output circuit outputs a first gate driving unit of a pixel row n-2 cells [n-2] 0 a gate drive signal to the n-2-th pixel units output [n-2] Is a high level signal.
  • the second clock signal CLKB is a low level signal
  • the second pull-up driving signal is provided by the input circuit of the second gate driving unit for the gate driving signal of the n-1th row pixel unit.
  • the gate driving signal of the pixel unit of the n-1th row is precharged; at the same time as the end of the second 1/4 period, the second clock signal CLKB becomes a high level signal, and the output circuit output of the second gate driving unit
  • the gate drive signal Output[n-1] of the n-1th row pixel unit is a high level signal.
  • the third stage is the third stage.
  • the third The clock signal CLKC is a low level signal
  • the gate driving signal Output[n-2] of the n-2th pixel unit provides a third pull-up driving signal for the gate driving signal of the n-th pixel unit, the third upper Pulling the driving signal to precharge the gate driving signal of the pixel row of the nth row; at the end of charging, the gate driving signal of the pixel cell of the n-2th row is reset to a low level signal; in the third quarter cycle
  • the third clock signal CLKC becomes a high level signal
  • the output circuit of the third gate driving unit outputs a gate driving signal Output[n] 0 of the nth row of pixel units.
  • the drive signal Output[n] is a high level signal.
  • the gate driving signal Output[n] of the nth row of pixel cells that is, at the beginning of the fourth 1/4 cycle immediately thereafter, the fourth clock signal CLKD is a low level signal
  • the gate driving signal Output[nl] of the pixel unit of the n-1th row provides a fourth pull-up driving signal for the gate driving signal of the n+1th row pixel unit, and the fourth pull-up driving
  • the signal precharges the gate driving signal of the pixel cell of the n+1th row; at the end of charging, the gate of the n-1th row
  • the pole drive signal is reset to a low level signal; at the same time as the end of the fourth quarter period, the fourth clock signal CLKD becomes a high level signal, and the output circuit of the fourth gate drive unit outputs the n+1th line
  • the gate drive signal Output[n+l] of the pixel unit is a high level signal.
  • the first pull-up driving signal, the second pull-up driving signal, the third pull-up driving signal, and the fourth pull-up driving signal are sequentially spaced apart by 1/4 cycle of the first clock signal CLKA.
  • the entire gate driving circuit is cyclically driven in accordance with the above-described driving process from the first stage to the fourth stage, thereby driving the entire gate driving circuit.
  • the gate driving signals of the n-2th to n+1th row pixel units respectively outputted by the output circuits of the first to fourth gate driving units are 1/1 of the first clock signal CLKA.
  • the shaded portions of the four pulse signals respectively correspond to a quarter cycle of the first clock signal CLKA, the second clock signal CLKB, the third clock signal CLKC, and the fourth clock signal CLKD, and the four
  • the shaded portions of the pulse signals respectively correspond to the high-level signal phases of the four clock signals, that is, the first to fourth gate drive units respectively output the nth in the pulse time of the gate drive signal corresponding to the shaded portion.
  • the gate drive signals of the pixel cells of the -2th row to the n+1th row are refreshed once.
  • the blank portions of the four pulse signals also respectively correspond to a quarter cycle of the first clock signal CLKA, the second clock signal CLKB, the third clock signal CLKC, and the fourth clock signal CLKD, and the blank of the four pulse signals Part of the low-level signal phase corresponding to the four clock signals respectively, the blank portion indicating the pre-charging time of the gate driving signal of the adjacent next row of pixel units relative to the gate driving signal of the previous row of pixel units, that is, the four
  • the first to fourth gate driving units do not respectively output the gate driving signals of the n-2th to n+1th pixel units in the pulse time corresponding to the blank portion of the pulse signals.
  • the gate driving signals of any two adjacent rows of pixel units of the entire gate driving circuit do not crosstalk, and at the same time, the pre-charging time (corresponding to the gate driving signal) of the gate driving signals of the adjacent two rows of pixel units
  • the blank portion) and the output time of the gate drive signal are separated by 1/4 cycle, respectively.
  • the output time of the gate drive signals of the conventional adjacent two rows of pixel units is separated by
  • the 1/2 cycle gate drive circuit not only shortens the charging time, improves the charging efficiency, but also improves the driving efficiency of the entire gate driving circuit.
  • the first pull-up driving signal and the second pull-up driving signal All are initial trigger signals, which are provided by an external trigger circuit.
  • the initial trigger signal of the pixel unit of the first row is used to start the driving of the odd-numbered gate driving unit
  • the initial trigger signal of the pixel unit of the second row is used to start the driving of the even-numbered gate driving unit, for refreshing one frame
  • two The initial trigger signals are spaced apart from each other by a 1/2 frame start signal.
  • the refresh rate of one frame is increased, thereby improving the driving efficiency of the gate driving circuit.
  • the n+6th pixel unit is the last row of pixel units
  • the n+5th row of pixel units is the penultimate row of pixel units
  • the reset driving signals of the gate driving signals of the two rows of pixel units also need to be externally
  • the trigger circuit is provided.
  • the reset driving signal of the gate driving signal of the pixel unit of the n+5th row is used to start the reset of the last even gate driving unit
  • the reset driving signal of the gate driving signal of the pixel unit of the n+6th row is used to start the last one Reset of the odd gate drive unit.
  • the interval between the reset drive signals of the gate drive signals of the last two rows of pixel cells is a 1/2 frame start signal, and the interval between the reset drive signals of the gate drive signals of the last two rows of pixel cells is the first clock 1/4 cycle of the signal.
  • the embodiment provides a display device including the gate driving circuit in Embodiment 2.

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Abstract

一种栅极驱动单元、栅极驱动电路和显示装置。该栅极驱动单元包括输入电路（1）、上拉电路（2）、复位电路（3）和输出电路（4）；输入电路（1）中接收的上拉驱动信号包括第n-2行和第n+4行像素单元的栅极驱动信号；复位电路（3）中接收的复位驱动信号包括第n+2行和第n+8行像素单元的栅极驱动信号；输出电路（4）输出的栅极驱动信号包括第n行和第n+6行像素单元的栅极驱动信号，n为正整数，且n∈[3，∞）。该栅极驱动单元能够输出两行像素单元的栅极驱动信号，使用效率高；在待驱动像素单元的栅极行数相同的情况下，利用该栅极驱动单元组成的栅极驱动电路，栅极驱动单元的数量可减少一半，相应地减少了栅极驱动电路所占用的面积，同时提高了栅极驱动电路的驱动效率。

Description

栅极驱动单元、 栅极驱动电路和显示装 技术领域
本发明涉及显示技术领域，具体地，涉及一种栅极驱动单元、 栅极驱动电路和显示装置。 背景技术
目前，液晶显示装置（LCD )和有机电致发光二极管（OLED ) 显示装置仍为平板显示的主流产品。在液晶显示装置和有源驱动 OLED显示装置中， 通常采用薄膜晶体管（Thin Film Transistor: 简称 TFT )对各个像素单元进行控制， 从而实现图像显示。 对像 素单元的控制包括行控制和列控制，行控制通常为采用栅极驱动 电路实现像素单元的逐行扫描， 目前栅极驱动电路 （如， Gate driver On Array, GO A) 的发展已经比较完善； 列控制通常采用 数据驱动电路实现像素单元的逐列扫描，从而实现显示数据的传 送。
传统的栅极驱动电路由多个栅极驱动单元级联组成，每个栅 极驱动单元的电路结构相同，由 4个薄膜晶体管和 1个电容器构 成， 即 4T1C结构； 每个栅极驱动单元的工作过程也相同， 只有 输入和输出信号不同。一个典型的栅极驱动单元的电路结构如图 1所示， 该栅极驱动单元的电路接口如图 2所示， 其中 Vclk为 时钟信号输入端， Clock为从时钟信号输入端输入的时钟信号， Vss为低电位信号输入端， Output[n-l]、 Output[n]和 Output[n+l] 分别为第 n-1行、 第 n行和第 n+1行像素单元的栅极驱动信号。 栅极驱动单元的工作过程为： 首先第 n-1 行栅极驱动信号 Output[n-l]输出一个高电平脉冲信号， 导通薄膜晶体管 TFT4并 对电容器 Cd进行充电， 同时使薄膜晶体管 TFT1 的栅极处于高 电位， 以导通薄膜晶体管 TFT1 , 然后第 n 行的栅极驱动信号 Output[n]随时钟信号 Clock同歩输出一个高电平脉冲信号，从而 将第 n 行像素单元打开， 之后第 n+1 行的栅极驱动信号 Output [n+ 1 ]输出高电平脉冲信号使薄膜晶体管 TF T2和薄膜晶体 管 TFT3 导通， 从而使电容器 Cd 和第 n 行的栅极驱动信号 Output[n]被从低电位输入端 Vss输入的低电位信号拉低，使得薄 膜晶体管 TFT1被关断，以及使得第 n行的栅极驱动信号 Output[n] 保持在低电位， 从而将第 n行像素单元关闭。
上述栅极驱动电路由 n 个栅极驱动单元组成， 电路连接复 杂， 整个栅极驱动电路面积较大， 所以占用基板的面积也大， 不 利于显示面板向小型化和低成本的方向发展。随着平板显示技术 的发展， 窄边框、 薄型化和低成本已成为平板显示发展趋势， 尤 其是对于小尺寸和高分辨率产品，简化栅极驱动电路和缩小栅极 驱动电路面积已非常重要。 发明内容
本发明针对现有技术中存在的上述技术问题，提供一种栅极 驱动单元、栅极驱动电路和显示装置。该栅极驱动单元能够输出 两行像素单元的栅极驱动信号， 使用效率高； 在待驱动像素单元 的栅极行数相同的情况下，利用该栅极驱动单元组成的栅极驱动 电路， 栅极驱动单元的数量可减少一半， 相应地减少了栅极驱动 电路的占用面积； 同时还提高了栅极驱动电路的驱动效率。
本发明提供一种栅极驱动单元，包括：输入电路、上拉电路、 复位电路和输出电路，所述输入电路分别与所述上拉电路和所述 复位电路连接，所述上拉电路和所述复位电路分别与所述输出电 路连接；
所述输入电路用于接收上拉驱动信号，以及向所述上拉电路 输入所述上拉驱动信号；
所述上拉电路用于接收所述上拉驱动信号，以及向所述输出 电路的输入端输出高电平信号；
所述复位电路用于接收复位驱动信号，以及将所述输出电路 的输入端的高电平信号复位为低电平信号；
所述输出电路用于接收所述上拉电路的输出信号和复位电 路的输出信号， 以及在时钟信号的控制下输出栅极驱动信号； 所述输入电路中接收的所述上拉驱动信号包括第 n-2 行像 素单元和第 n+4行像素单元的所述栅极驱动信号；所述复位电路 中接收的所述复位驱动信号包括第 n+2行像素单元和第 n+8行 像素单元的所述栅极驱动信号；所述输出电路输出的栅极驱动信 号包括第 n行像素单元和第 n+6行像素单元的所述栅极驱动信 号， n为正整数， 且 n e [3,oo ) 。
优选的，所述输入电路包括第一晶体管、第二晶体管和第五 晶体管，所述第一晶体管和所述第二晶体管的栅极分别与各自的 源极连接、漏极同时与所述第五晶体管的栅极和漏极连接， 所述 第五晶体管的源极同时与所述上拉电路和所述复位电路连接，所 述第 n-2 行像素单元的栅极驱动信号输入到所述第一晶体管的 栅极，所述第 n+4行像素单元的栅极驱动信号输入到所述第二晶 体管的栅极；
所述上拉电路包括第六晶体管和连接于所述第六晶体管的 栅极与源极之间的电容器，所述第六晶体管的栅极还连接至所述 输入电路中的第五晶体管的源极、漏极连接至高电位端、源极还 连接至所述输出电路的输入端；
所述复位电路包括第三晶体管、第四晶体管、第七晶体管和 第八晶体管，所述第三晶体管和所述第四晶体管的栅极分别与各 自的源极连接、漏极同时与所述第七晶体管和所述第八晶体管的 栅极连接， 所述第七晶体管的栅极和所述第八晶体管的栅极连 接，所述第七晶体管的源极与所述输入电路中的所述第五晶体管 的源极连接，所述第八晶体管的源极与所述上拉电路中的所述第 六晶体管的源极连接，所述第七晶体管和所述第八晶体管的漏极 同时连接至低电位端，所述第 n+2行像素单元的栅极驱动信号输 所述输出电路包括第九晶体管、第十晶体管、第十一晶体管 和第十二晶体管，所述第十一晶体管的栅极连接第一时钟信号或 第二时钟信号，所述第十二晶体管的栅极连接第三时钟信号或第 四时钟信号，所述第十一晶体管和所述第十二晶体管的源极同时 与所述上拉电路中的第六晶体管的源极连接，所述第九晶体管和 所述第十晶体管的栅极同时与所述复位电路中的第七晶体管的 栅极连接，所述第十一晶体管的漏极与所述第九晶体管的源极连 接， 并输出所述第 n行像素单元的所述栅极驱动信号， 所述第十 二晶体管的漏极与所述第十晶体管的源极连接， 并输出所述第 n+6行像素单元的所述栅极驱动信号，所述第九晶体管和所述第 十晶体管的漏极同时连接至所述低电位端。
优选的， 所述第一时钟信号、 所述第二时钟信号、 所述第三 时钟信号和所述第四时钟信号的脉宽均相等、 且占空比为 1/2， 所述第一时钟信号比所述第三时钟信号超前 1/2周期， 所述第二 时钟信号比所述第四时钟信号超前 1/2周期。
优选的，所述输入电路接收的第 1行或第 2行像素单元的栅 极驱动信号为 1/2帧起始信号。
优选的，相邻的两奇数行或相邻的两偶数行像素单元的所述 栅极驱动信号之间间隔 1/2周期。
优选的， 所述栅极驱动单元通过所述输入电路输入所述第 n-2行像素单元和所述第 n+4行像素单元的所述栅极驱动信号， 使所述上拉电路预充电；
所述上拉电路预充电完成后能输出高电平信号，且所述高电 平信号在所述第一至第四时钟信号的控制下，使所述输出电路输 出所述第 n行像素单元和所述第 n+6行像素单元的栅极驱动信 号；
所述栅极驱动单元通过所述复位电路输入所述第 n+2 行像 素单元和所述第 n+8行像素单元的所述栅极驱动信号，使输出的 所述第 n行像素单元和所述第 n+6行像素单元的所述栅极驱动信 号由高电平信号复位为低电平信号。 本发明还提供一种栅极驱动电路，包括上述多个栅极驱动单 元， 所述多个栅极驱动单元依次级联。
优选的，所述多个栅极驱动单元中相邻的两个所采用的各个 时钟信号依次间隔 1/4周期。
优选的，所述栅极驱动电路包括两个 1/2帧起始信号和两个 1/2帧复位信号， 所述两个 1/2帧起始信号分别作为第 1行和第 2行像素单元的栅极驱动信号的上拉驱动信号， 所述两个 1/2帧 复位信号分别作为最后两行像素单元的栅极驱动信号的复位驱 动信号， 且所述两个 1/2帧起始信号之间的间隔是所述时钟信号 的 1/4周期， 所述两个 1/2帧复位信号之间的间隔是所述时钟信 号的 1/4周期。
本发明还提供一种显示装置， 包括上述栅极驱动电路。 本发明的有益效果：本发明所提供的栅极驱动单元通过在输 入电路和复位电路的输入端分别接入两行像素单元的栅极驱动 信号， 并在输出电路的输出端输出两行像素单元的栅极驱动信 号，与现有技术中只能输出一行像素单元的栅极驱动信号的栅极 驱动单元相比， 本发明中栅极驱动单元的效率更高。本发明所提 供的栅极驱动电路， 由于减少了栅极驱动单元的数量， 从而减少 了整个栅极驱动电路所占用的面积； 另外， 由于相邻两个栅极驱 动单元输出的相邻两行像素单元的栅极驱动信号之间间隔 1/4周 期， 缩短了充电时间， 提高了充电效率， 从而提高了整个栅极驱 动电路的驱动效率。 附图说明
图 1为现有技术中栅极驱动单元的电路图；
图 2为图 1中栅极驱动单元的电路接口示意图；
图 3为本发明实施例 1中栅极驱动单元的电路图； 图 4为本发明实施例 1中栅极驱动单元的驱动时序图； 图 5为本发明实施例 2中栅极驱动电路的电路图； 图 6为本发明实施例 2中栅极驱动电路的驱动时序图。 其中的附图标记说明：
1.输入电路； 2.上拉电路； 3.复位电路； 4.输出电路。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面 结合附图和具体实施方式对本发明栅极驱动单元、栅极驱动电路 和显示装置作进一歩详细描述。 实施例 1 :
本实施例提供一种栅极驱动单元， 如图 3所示， 该栅极驱动 单元包括： 输入电路 1、 上拉电路 2、 复位电路 3和输出电路 4， 输入电路 1 分别与上拉电路 2和复位电路 3连接， 上拉电路 2 和复位电路 3分别与输出电路 4连接。 其中，
输入电路 1， 用于接收上拉驱动信号， 以及向上拉电路 2输 入所述上拉驱动信号；
上拉电路 2， 用于接收所述上拉驱动信号， 以及向输出电路 4的输入端 PU输出高电平信号；
复位电路 3， 用于接收复位驱动信号， 以及将输出电路 4的 输入端 PU的高电平信号复位为低电平信号；
输出电路 4， 用于接收上拉电路 2的输出信号和复位电路 3 的输出信号， 以及在时钟信号的控制下， 输出栅极驱动信号。
本实施例中， 输入电路 1中接收的上拉驱动信号包括第 n-2 行和第 n+4行像素单元的栅极驱动信号；复位电路 3中接收的复 位驱动信号包括第 n+2行和第 n+8行像素单元的栅极驱动信号； 输出电路 4输出的栅极驱动信号包括第 n行和第 n+6行像素单元 的栅极驱动信号， n为正整数， 且 n e [3,oo ) 。
如图 3所示， 栅极驱动单元的具体电路为：
输入电路 1包括第一晶体管 Ml、 第二晶体管 M2和第五晶 体管 M5， 第一晶体管 Ml和第二晶体管 M2的栅极分别与各自 的源极连接、 漏极同时与第五晶体管 M5的栅极和漏极连接， 第 五晶体管 M5 的源极同时与上拉电路 2和复位电路 3 连接， 第 n-2行像素单元的栅极驱动信号输入到第一晶体管 Ml 的栅极， 第 n+4 行像素单元的栅极驱动信号输入到第二晶体管 M2 的栅 极。
上拉电路 2包括第六晶体管 M6和连接于第六晶体管 M6的 栅极与源极之间的电容器 Cb， 第六晶体管 M6 的栅极还连接至 输入电路 1 中的第五晶体管 M5 的源极、 漏极连接至高电位端 Vgh、 源极还连接至输出电路 4的输入端 PU。
复位电路 3包括第三晶体管 M3、 第四晶体管 M4、 第七晶 体管 M7和第八晶体管 M8 , 第三晶体管 M3和第四晶体管 M4 的栅极分别与各自的源极连接、漏极同时与第七晶体管 M7和第 八晶体管 M8的栅极连接， 第七晶体管 M7的栅极和第八晶体管 M8的栅极连接， 第七晶体管 M7的源极与输入电路 1 中的第五 晶体管 M5的源极连接， 第八晶体管 M8的源极与上拉电路 2中 的第六晶体管 M6 的源极连接， 第七晶体管 M7 和第八晶体管 M8的漏极同时连接至低电位端 Vss， 第 n+2行像素单元的栅极 驱动信号输入到第三晶体管 M3的栅极，第 n+8行像素单元的栅 极驱动信号输入到第四晶体管 M4的栅极。
输出电路 4包括第九晶体管 M9、 第十晶体管 M10、 第 ^一 晶体管 Mi l和第十二晶体管 M12 ,第 ^一晶体管 Mi l的栅极连 接第一时钟信号 CLKA或第二时钟信号 CLKB , 第十二晶体管 M12 的栅极连接第三时钟信号 CLKC或第四时钟信号 CLKD, 第 ^一晶体管 Mi l和第十二晶体管 M12的源极同时与上拉电路 2中的第六晶体管 M6的源极连接， 第九晶体管 M9和第十晶体 管 M10的栅极同时与复位电路 3 中的第七晶体管 M7的栅极连 接， 第 ^一晶体管 Mi l 的漏极与第九晶体管 M9 的源极连接， 并输出第 n行像素单元的栅极驱动信号， 第十二晶体管 M12的 漏极与第十晶体管 M10的源极连接， 并输出第 n+6行像素单元 的栅极驱动信号， 第九晶体管 M9和第十晶体管 M10 的漏极同 时连接至低电位端 Vss。 其中， 相邻的两个栅极驱动单元分别采用两个相互间隔 1/2 周期的时钟信号， gp， 相邻的两个栅极驱动单元中的一个栅极驱 动单元采用的两个时钟信号相互间隔 1/2周期， 另一个栅极驱动 单元采用的两个时钟信号也相互间隔 1/2周期。 例如， 如果一个 栅极驱动单元采用第一时钟信号 CLKA和第三时钟信号 CLKC, 与其相邻的另一个栅极驱动单元采用第二时钟信号 CLKB 和第 四时钟信号 CLKD , 则第一时钟信号 CLKA 和第三时钟信号 CLKC为间隔 1/2周期的两个时钟信号， 第二时钟信号 CLKB和 第四时钟信号 CLKD为间隔 1/2周期的两个时钟信号。
需要说明的是， 第一晶体管 Ml、 第二晶体管 M2、 第三晶 体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第六晶体管 M6、 第七晶体管 M7、 第八晶体管 M8、 第九晶体管 M9、 第十晶体管 M10、 第 ^一晶体管 Mi l和第十二晶体管 M12优选均为薄膜晶 体管， 当然， 也可选用具有选通开关功能的其他类型的晶体管。 当薄膜晶体管的栅极开启，且其源极和漏极之间的压差满足导通 条件时， 薄膜晶体管导通。 其中， 源极为薄膜晶体管的信号输入 端， 漏极为薄膜晶体管的信号输出端， 反之亦可。 具体地， 当薄 膜晶体管的源极的电压高时， 电流从源极流向漏极； 当薄膜晶体 管的漏极的电压高时， 电流从漏极流向源极， 即源极和漏极可以 互换。
本实施例中， 第一时钟信号 CLKA、 第二时钟信号 CLKB、 第三时钟信号 CLKC和第四时钟信号 CLKD的脉宽均相等、 且 占空比为 1/2，第一时钟信号 CLKA比第三时钟信号 CLKC超前 1/2周期， 第二时钟信号 CLKB比第四时钟信号 CLKD超前 1/2 周期。其中， 输入电路 1接收的第 1行或第 2行像素单元的栅极 驱动信号 （上拉驱动信号） 为 1/2帧起始信号， 以作为初始触发 信号。相邻的两奇数行或相邻的两偶数行像素单元的栅极驱动信 号之间间隔 1/2周期。 如此设置， 能够确保相邻的奇数行或相邻 的偶数行像素单元能够逐行输出栅极驱动信号。
基于上述栅极驱动单元， 本实施例还提供一种栅极驱动方 法， 下面以采用第一时钟信号 CLKA和第三时钟信号 CLKC的 一个栅极驱动单元为例来说明该栅极驱动单元的具体驱动过程。 该栅极驱动方法的驱动时序如图 4所示，该栅极驱动方法具体包 括如下歩骤， 其中， 以输入第 n-2行像素单元的栅极驱动信号为 例说明该栅极驱动单元的工作过程。
S1 :通过输入电路 1输入第 n-2行像素单元的栅极驱动信号 作为上拉驱动信号， 使上拉电路 2预充电。
歩骤 S1 即栅极驱动过程中的第一阶段： 当第一时钟信号 CLKA 的前 1/2周期为低电平信号， 第三时钟信号 CLKC 的前 1/2周期为高电平信号时， 输入电路 1输入第 n-2行像素单元的 栅极驱动信号，该第 n-2行像素单元的栅极驱动信号为高电平脉 冲信号； 第 n-2行像素单元的栅极驱动信号作为上拉驱动信号， 通过第五晶体管 M5对电容器 Cb进行预充电。
其中，如果输入电路 1输入的是第 1行或第 2行像素单元的 栅极驱动信号，则输入的栅极驱动信号为大小和周期均与上述高 电平脉冲信号相同的一个初始触发信号，该初始触发信号由外部 触发电路提供， 由该初始触发信号来启动该栅极驱动单元的驱 动。
S2: 上拉电路 2 预充电完成后输出高电平信号， 该高电平 信号在第一时钟信号 CLKA和第三时钟信号 CLKC的控制下， 使输出电路 4输出第 n行像素单元的栅极驱动信号。
在歩骤 S1中， 经过第一时钟信号 CLKA的前 1/2周期， 第 n-2行像素单元的栅极驱动信号作为第 n行像素单元的栅极驱动 信号的预充电电压信号， 对电容器 Cb进行预充电， 在该第一时 钟信号 CLKA的前 1/2周期结束的同时， 电容器 Cb的预充电完 成， 即上拉电路 2预充电完成， 使得上拉电路 2 中第六晶体管 M6的栅极处于高电位。
歩骤 S2 即栅极驱动过程中的第二阶段： 在第一时钟信号 CLKA的后 1/2周期的起始时刻，第一时钟信号 CLKA跳变为高 电平信号， 第三时钟信号 CLKC 跳变为低电平信号， 在高电位 端 Vgh的拉动下， 上拉电路 2的输出端 PD输出高电平信号， 该 高电平信号在第一时钟信号 CLKA的控制下， 使输出电路 4输 出第 n行像素单元的栅极驱动信号 Output[n]， 该信号为一个高 电平脉冲信号， 用于将第 n行像素单元打开； 同时， 第 n行像素 单元的栅极驱动信号还作为第 n+2 行像素单元的栅极驱动信号 的预充电电压信号， 以及作为第 n-2行像素单元的栅极驱动信号 的复位驱动信号， 即对第 n-2行像素单元的栅极驱动信号进行复 位。
S3： 通过复位电路 3输入第 n+2行像素单元的栅极驱动信 号作为复位驱动信号，使输出的第 n行像素单元的栅极驱动信号 由高电平信号复位为低电平信号。
歩骤 S3 即栅极驱动过程中的第三阶段： 在第一时钟信号 CLKA的下一周期的前 1/2周期中， 第 n行像素单元的栅极驱动 信号作为第 n+2行像素单元的栅极驱动信号的预充电电压信号， 对电容器 Cb进行预充电； 同时， 第 n+2行像素单元的栅极驱动 信号对第 n行像素单元的栅极驱动信号进行复位。具体地， 在该 第一时钟信号 CLKA的下一周期的前 1/2周期中，第一时钟信号 CLKA跳变为低电平信号，第三时钟信号 CLKC跳变为高电平信 号， 复位电路 3 输入第 n+2 行像素单元的栅极驱动信号 Output[n+2] , 该第 n+2 行像素单元的栅极驱动信号为高电平脉 冲信号， 且该第 n+2 行像素单元的栅极驱动信号使第七晶体管 M7和第八晶体管 M8导通， 在低电位端 Vss的拉动下， 电容器 Cb中的两个极板和上拉电路 2的输出端 PD输出的高电平信号 被拉低， 第六晶体管 M6被关断， 且该第 n+2行像素单元的栅极 驱动信号还使第九晶体管 M9导通，使得第 n行像素单元的栅极 驱动信号 Output[n]被低电位端 Vss拉低并保持低电位， 即第 n 行像素单元的栅极驱动信号被复位为低电平信号。
至此，栅极驱动单元就完成了第 n行像素单元的栅极驱动信 号的输出与复位。
同样地， 第 n+6行像素单元的栅极驱动信号 Output[n+6]的 输出与复位在第 n+4行像素单元的栅极驱动信号 Output[n+4] (上 拉驱动信号） 、 第 n+8行像素单元的栅极驱动信号 Output[n+8] (复位驱动信号）、第一时钟信号 CLKA和第三时钟信号 CLKC 的配合作用下按照上述驱动方法进行。
本实施例中的栅极驱动单元通过在输入电路 1和复位电路 3 的输入端分别接入两行像素单元的栅极驱动信号，并且在输出电 路 4的输出端输出两行像素单元的栅极驱动信号，从而提高了该 栅极驱动单元的使用效率，在待驱动像素单元的栅极行数相同的 情况下， 利用该栅极驱动单元组成的栅极驱动电路， 栅极驱动单 元的数量可减少一半， 相应地减少了栅极驱动电路的占用面积。 实施例 2 :
本实施例提供一种栅极驱动电路， 如图 5所示，包括上述栅 极驱动单元 GOA , 该栅极驱动电路由多个所述栅极驱动单元 GOA依次级联而成。多个所述栅极驱动单元 GOA依次循环交替 地采用第一时钟信号 CLKA和第三时钟信号 CLKC、以及第二时 钟信号 CLKB和第四时钟信号 CLKD, 也就是说， 相邻的两个栅 极驱动单元中的一个栅极驱动单元采用第一时钟信号 CLKA和 第三时钟信号 CLKC , 另一个栅极驱动单元采用第二时钟信号 CLKB和第四时钟信号 CLKD。
本实施例中， 相邻的两个栅极驱动单元 GOA所采用的四个 时钟信号依次间隔 1/4周期， gp， 第一时钟信号 CLKA与第二时 钟信号 CLKB之间间隔 1/4周期，第二时钟信号 CLKB与第三时 钟信号 CLKC之间间隔 1/4周期，第三时钟信号 CLKC与第四时 钟信号 CLKD之间间隔 1/4周期。 如此设置， 能够提前对下一个 栅极驱动单元进行预充电，从而缩短上一个栅极驱动单元到下一 个栅极驱动单元的预充电时间，进而提高整个栅极驱动电路的充 电效率。
本实施例中，栅极驱动电路包括两个 1/2帧起始信号和两个 1/2帧复位信号，其中， "帧"为显示屏显示时的一个时间参数， "1 帧"为从第一行像素单元扫描到最后一行像素单元所用的时间， 即整屏驱动一次所用的时间； 同理， "1/2帧"是半屏驱动所用的 时间； "1/2帧起始信号"指间隔 1/2帧的时间发出一个信号。 这 两个 1/2帧起始信号分别作为第 1行和第 2行像素单元的栅极驱 动信号的上拉驱动信号， 且两个 1/2帧起始信号之间的间隔为时 钟信号的 1/4周期。 即栅极驱动电路中， 按驱动顺序的第一奇数 栅极驱动单元和第一偶数栅极驱动单元（通常对应着第一栅极驱 动单元和第二栅极驱动单元）分别需要一个初始触发信号， 这两 个初始触发信号均为 1/2帧起始信号。 依照驱动顺序， 奇数序数 的栅极驱动单元分别驱动奇数行像素单元的栅极，偶数序数的栅 极驱动单元分别驱动偶数行像素单元的栅极。 "1/2帧复位信号" 指间隔 1/2帧的时间发出一个复位信号， 这两个 1/2帧复位信号 分别作为最后两行像素单元的栅极驱动信号的复位驱动信号，且 两个 1 /2帧复位信号之间的间隔为时钟信号的 1 / 4周期。
参考图 6所示的栅极驱动电路的驱动时序图，以依次级联的 四个栅极驱动单元的工作过程为例，该四个栅极驱动单元分别为 第一栅极驱动单元、第二栅极驱动单元、第三栅极驱动单元和第 四栅极驱动单元， 并在第一时钟信号 CLKA、 第二时钟信号 CLKB、第三时钟信号 CLKC和第四时钟信号 CLKD的配合下依 次输出第 n-2行、 第 n-1行、 第 n行和第 n+1行像素单元的栅极 驱动信号。
具体的， 上述栅极驱动电路的驱动过程为：
第一阶段：
当第一时钟信号 CLKA的第一个 1/4周期为低电平信号时， 通过第一栅极驱动单元的输入电路为第 n-2 行像素单元的栅极 驱动信号提供第一上拉驱动信号， 该第一上拉驱动信号对第 n-2 行像素单元的栅极驱动信号进行预充电； 在该第一个 1/4周期结 束的同时， 第一时钟信号 CLKA变为高电平信号， 第一栅极驱 动单元的输出电路输出第 n-2 行像素单元的栅极驱动信号 Output[n-2] 0 该第 n-2 行像素单元的栅极驱动信号 Output[n-2] 为高电平信号。
第二阶段：
在第一栅极驱动单元的输出电路输出第 n-2 行像素单元的 栅极驱动信号 Output[n-2]的同时，也即在紧接着的第二个 1/4周 期的起始时刻， 第二时钟信号 CLKB 为低电平信号， 通过第二 栅极驱动单元的输入电路为第 n-1 行像素单元的栅极驱动信号 提供第二上拉驱动信号，该第二上拉驱动信号对第 n-1行像素单 元的栅极驱动信号进行预充电； 在第二个 1/4周期结束的同时， 第二时钟信号 CLKB 变为高电平信号， 第二栅极驱动单元的输 出电路输出第 n-1行像素单元的栅极驱动信号 Output[n-l ]。该第 n-1行像素单元的栅极驱动信号 Output[n-l ]为高电平信号。
第三阶段：
在第二栅极驱动单元的输出电路输出第 n-1 行像素单元的 栅极驱动信号 Output[n-l]的同时，也即在紧接着的第三个 1/4周 期的起始时刻， 第三时钟信号 CLKC为低电平信号， 第 n-2行像 素单元的栅极驱动信号 Output[n-2]为第 n行像素单元的栅极驱 动信号提供第三上拉驱动信号，该第三上拉驱动信号对第 n行像 素单元的栅极驱动信号进行预充电； 充电结束时， 第 n-2行像素 单元的栅极驱动信号被复位为低电平信号； 在第三个 1/4周期结 束的同时， 第三时钟信号 CLKC 变为高电平信号， 第三栅极驱 动单元的输出电路输出第 n 行像素单元的栅极驱动信号 Output[n] 0 该第 n行像素单元的栅极驱动信号 Output[n]为高电 平信号。
第四阶段：
在第三栅极驱动单元的输出电路输出第 n 行像素单元的栅 极驱动信号 Output [n]的同时，也即在紧接着的第四个 1 /4周期的 起始时刻， 第四时钟信号 CLKD为低电平信号， 第 n-1行像素单 元的栅极驱动信号 Output[n-l ]为第 n+1 行像素单元的栅极驱动 信号提供第四上拉驱动信号，该第四上拉驱动信号对第 n+1行像 素单元的栅极驱动信号进行预充电； 充电结束时， 第 n-1行的栅 极驱动信号被复位为低电平信号；在第四个 1/4周期结束的同时， 第四时钟信号 CLKD 变为高电平信号， 第四栅极驱动单元的输 出电路输出第 n+1行像素单元的栅极驱动信号 Output[n+l]。 该 第 n+1行像素单元的栅极驱动信号 Output[n+l]为高电平信号。
其中， 第一上拉驱动信号、 第二上拉驱动信号、 第三上拉驱 动信号和第四上拉驱动信号依次间隔第一时钟信号 CLKA的 1/4 周期。
整个栅极驱动电路按照上述从第一阶段到第四阶段的驱动 过程循环往复进行驱动， 从而实现整个栅极驱动电路的驱动。
如图 6所示，第一至第四栅极驱动单元的输出电路分别输出 的第 n-2行到第 n+1行像素单元的栅极驱动信号为依次间隔第一 时钟信号 CLKA的 1/4周期的四个脉冲信号，该四个脉冲信号的 阴影部分分别对应第一时钟信号 CLKA、 第二时钟信号 CLKB、 第三时钟信号 CLKC和第四时钟信号 CLKD的 1/4周期， 且该 四个脉冲信号的阴影部分分别对应四个时钟信号的高电平信号 阶段， 即只有在阴影部分对应的栅极驱动信号的脉冲时间内， 第 一至第四栅极驱动单元才会分别输出第 n-2行到第 n+1行的像素 单元的栅极驱动信号，也即第 n-2行到第 n+1行的像素单元的栅 极对应的栅线才会刷新一次。另外， 所述四个脉冲信号的空白部 分也分别对应第一时钟信号 CLKA、 第二时钟信号 CLKB、 第三 时钟信号 CLKC和第四时钟信号 CLKD的 1/4周期， 该四个脉 冲信号的空白部分分别对应四个时钟信号的低电平信号阶段，该 空白部分表示相邻的下一行像素单元的栅极驱动信号相对上一 行像素单元的栅极驱动信号的预充电时间， 也即， 该四个脉冲信 号的空白部分对应的脉冲时间内，第一至第四栅极驱动单元不会 分别输出第 n-2行到第 n+1行像素单元的栅极驱动信号。由此可 见，整个栅极驱动电路任意相邻两行像素单元的栅极驱动信号不 会发生串扰， 同时， 由于相邻两行像素单元的栅极驱动信号的预 充电时间（对应栅极驱动信号的空白部分）和栅极驱动信号的输 出时间 （对应栅极驱动信号的阴影部分） 分别相隔 1/4周期， 相 对于传统的相邻两行像素单元的栅极驱动信号的输出时间相隔
1/2周期的栅极驱动电路， 不仅缩短了充电时间， 提高了充电效 率， 而且提高了整个栅极驱动电路的驱动效率。
需要说明的是， 如果第 n-2行像素单元是第 1行像素单元， 第 n-1行像素单元是第 2行像素单元， 此时， 第一上拉驱动信号 和第二上拉驱动信号均为初始触发信号，该初始触发信号由外部 触发电路提供。第 1行像素单元的初始触发信号用于启动奇数序 数栅极驱动单元的驱动，第 2行像素单元的初始触发信号用于启 动偶数序数栅极驱动单元的驱动， 针对一帧画面的刷新， 两个初 始触发信号彼此间隔 1/2帧起始信号。 由于两个初始触发信号之 间的间隔是第一时钟信号的 1/4周期， 所以提高了一帧画面的刷 新速度， 从而提高了栅极驱动电路的驱动效率。 另外， 如果第 n+6行像素单元是最后一行像素单元，则第 n+5行像素单元是倒 数第二行像素单元，这两行像素单元的栅极驱动信号的复位驱动 信号也需要由外部触发电路提供。第 n+5行像素单元的栅极驱动 信号的复位驱动信号用于启动最后一个偶数栅极驱动单元的复 位，第 n+6行像素单元的栅极驱动信号的复位驱动信号用于启动 最后一个奇数栅极驱动单元的复位。最后两行像素单元的栅极驱 动信号的复位驱动信号之间的间隔是 1/2帧起始信号， 且最后两 行像素单元的栅极驱动信号的复位驱动信号之间的间隔是第一 时钟信号的 1/4周期。 实施例 3 :
本实施例提供一种显示装置，包括实施例 2中的栅极驱动电 路。
由于采用了上述栅极驱动电路，一方面减少了栅极驱动电路 所占用的显示装置中显示基板的面积，另一方面提高了显示装置 显示时的刷新效率。 应当理解的是，以上实施方式仅仅是为了说明本发明的原理 而采用的示例性实施方式， 然而本发明并不局限于此。对于本领 域内的普通技术人员而言，在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也属于本发明的 保护范围。

Claims

1. 一种栅极驱动单元， 包括： 输入电路、 上拉电路、 复位 电路和输出电路，所述输入电路分别与所述上拉电路和所述复位 电路连接，所述上拉电路和所述复位电路分别与所述输出电路连 接；
所述输入电路用于接收上拉驱动信号，以及向所述上拉电路 输入所述上拉驱动信号；
所述上拉电路用于接收所述上拉驱动信号，以及向所述输出 电路的输入端输出高电平信号；
所述复位电路用于接收复位驱动信号，以及将所述输出电路 的输入端的高电平信号复位为低电平信号；
所述输出电路用于接收所述上拉电路的输出信号和复位电 路的输出信号， 以及在时钟信号的控制下输出栅极驱动信号； 其特征在于，所述输入电路中接收的所述上拉驱动信号包括 第 n-2行像素单元和第 n+4行像素单元的所述栅极驱动信号；所 述复位电路中接收的所述复位驱动信号包括第 n+2 行像素单元 和第 n+8行像素单元的所述栅极驱动信号；所述输出电路输出的 栅极驱动信号包括第 n行像素单元和第 n+6行像素单元的所述栅 极驱动信号， n为正整数， 且 n e [3,oo ) 。
2. 根据权利要求 1所述的栅极驱动单元， 其特征在于， 所 述输入电路包括第一晶体管、第二晶体管和第五晶体管， 所述第 一晶体管和所述第二晶体管的栅极分别与各自的源极连接、漏极 同时与所述第五晶体管的栅极和漏极连接，所述第五晶体管的源 极同时与所述上拉电路和所述复位电路连接，所述第 n-2行像素 单元的栅极驱动信号输入到所述第一晶体管的栅极，所述第 n+4 行像素单元的栅极驱动信号输入到所述第二晶体管的栅极；
所述上拉电路包括第六晶体管和连接于所述第六晶体管的 栅极与源极之间的电容器，所述第六晶体管的栅极还连接至所述 输入电路中的第五晶体管的源极、漏极连接至高电位端、源极还 连接至所述输出电路的输入端；
所述复位电路包括第三晶体管、第四晶体管、第七晶体管和 第八晶体管，所述第三晶体管和所述第四晶体管的栅极分别与各 自的源极连接、漏极同时与所述第七晶体管和所述第八晶体管的 栅极连接， 所述第七晶体管的栅极和所述第八晶体管的栅极连 接，所述第七晶体管的源极与所述输入电路中的所述第五晶体管 的源极连接，所述第八晶体管的源极与所述上拉电路中的所述第 六晶体管的源极连接，所述第七晶体管和所述第八晶体管的漏极 同时连接至低电位端，所述第 n+2行像素单元的栅极驱动信号输 入到所述第三晶体管的栅极，所述第 n+8行像素单元的栅极驱动 信号输入到所述第四晶体管的栅极；
所述输出电路包括第九晶体管、第十晶体管、第十一晶体管 和第十二晶体管，所述第十一晶体管的栅极连接第一时钟信号或 第二时钟信号，所述第十二晶体管的栅极连接第三时钟信号或第 四时钟信号，所述第十一晶体管和所述第十二晶体管的源极同时 与所述上拉电路中的第六晶体管的源极连接，所述第九晶体管和 所述第十晶体管的栅极同时与所述复位电路中的第七晶体管的 栅极连接，所述第十一晶体管的漏极与所述第九晶体管的源极连 接， 并输出所述第 n行像素单元的所述栅极驱动信号， 所述第十 二晶体管的漏极与所述第十晶体管的源极连接， 并输出所述第 n+6行像素单元的所述栅极驱动信号，所述第九晶体管和所述第 十晶体管的漏极同时连接至所述低电位端。
3. 根据权利要求 2所述的栅极驱动单元， 其特征在于， 所 述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述 第四时钟信号的脉宽均相等、 且占空比为 1/2， 所述第一时钟信 号比所述第三时钟信号超前 1/2周期， 所述第二时钟信号比所述 第四时钟信号超前 1/2周期。
4. 根据权利要求 3所述的栅极驱动单元， 其特征在于， 所 述输入电路接收的第 1 行或第 2行像素单元的栅极驱动信号为 1/2帧起始信号。
5. 根据权利要求 4所述的栅极驱动单元， 其特征在于， 相 邻的两奇数行或相邻的两偶数行像素单元的所述栅极驱动信号 之间间隔 1/2周期。
6. 根据权利要求 5所述的栅极驱动单元， 其特征在于， 所 述栅极驱动单元通过所述输入电路输入所述第 n-2 行像素单元 和所述第 n+4行像素单元的所述栅极驱动信号，使所述上拉电路 预充电；
所述上拉电路预充电完成后能输出高电平信号，且所述高电 平信号在所述第一至第四时钟信号的控制下，使所述输出电路输 出所述第 n行像素单元和所述第 n+6行像素单元的栅极驱动信 号；
所述栅极驱动单元通过所述复位电路输入所述第 n+2 行像 素单元和所述第 n+8行像素单元的所述栅极驱动信号，使输出的 所述第 n行像素单元和所述第 n+6行像素单元的所述栅极驱动信 号由高电平信号复位为低电平信号。
7. 一种栅极驱动电路， 其特征在于， 包括权利要求 1-6 中 任意一项所述的多个栅极驱动单元，所述多个栅极驱动单元依次 级联。
8. 根据权利要求 7所述的栅极驱动电路， 其特征在于， 所 述多个栅极驱动单元中相邻的两个所采用的各个时钟信号依次 间隔 1/4周期。
9. 根据权利要求 8所述的栅极驱动电路， 其特征在于， 所 述栅极驱动电路包括两个 1/2 帧起始信号和两个 1/2 帧复位信 号， 所述两个 1/2帧起始信号分别作为第 1行和第 2行像素单元 的栅极驱动信号的上拉驱动信号， 所述两个 1/2帧复位信号分别 作为最后两行像素单元的栅极驱动信号的复位驱动信号，且所述 两个 1/2帧起始信号之间的间隔是所述时钟信号的 1/4周期， 所 述两个 1/2帧复位信号之间的间隔是所述时钟信号的 1/4周期。
10. 一种显示装置， 其特征在于， 包括权利要求 7-9中任意 一项所述的栅极驱动电路。
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