WO2021016942A1 - 显示面板、显示装置以及驱动方法 - Google Patents

显示面板、显示装置以及驱动方法 Download PDF

Info

Publication number
WO2021016942A1
WO2021016942A1 PCT/CN2019/098700 CN2019098700W WO2021016942A1 WO 2021016942 A1 WO2021016942 A1 WO 2021016942A1 CN 2019098700 W CN2019098700 W CN 2019098700W WO 2021016942 A1 WO2021016942 A1 WO 2021016942A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
shift register
register unit
clock signal
units
Prior art date
Application number
PCT/CN2019/098700
Other languages
English (en)
French (fr)
Inventor
孟昭晖
孙伟
韩文超
杨虹
丛林
肖文俊
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980001200.XA priority Critical patent/CN112673417B/zh
Priority to US16/957,575 priority patent/US11715401B2/en
Priority to CN202211093675.6A priority patent/CN115938322A/zh
Priority to PCT/CN2019/098700 priority patent/WO2021016942A1/zh
Priority to EP19933196.8A priority patent/EP4006892A4/en
Publication of WO2021016942A1 publication Critical patent/WO2021016942A1/zh
Priority to US18/137,010 priority patent/US11948489B2/en
Priority to US18/590,339 priority patent/US20240212550A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the embodiments of the present disclosure relate to a display panel, a display device, and a driving method.
  • the driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the display panel.
  • GOA Gate Driver On Array
  • At least one embodiment of the present disclosure provides a display panel including a display area and a peripheral area.
  • the display area includes a sub-pixel unit array with multiple rows and multiple columns of sub-pixel units, a gate drive circuit is provided in the peripheral area, and the display area further includes multiple gate lines and multiple data lines for Drive the array of sub-pixel units, each sub-pixel unit is driven to display by a scan signal provided by a gate line and a data signal provided by a data line, and the same data line connects at least two sub-pixels of the same color that are not adjacent to each other Unit;
  • the gate driving circuit includes a plurality of shift register units arranged in sequence, and the plurality of gate lines are arranged in sequence and electrically connected with the plurality of shift register units arranged in sequence in a one-to-one correspondence;
  • the The gate driving circuit is configured to receive a clock signal and generate the scan signal so that the at least two non-adjacent sub-pixel units of the same color connected to the same data line are continuously displayed in time sequence.
  • the plurality of sub-pixel units sequentially connected to the same data line include at least a first color and a second color, and the plurality of sub-pixel units sequentially connected to the same data line Among the sub-pixel units, the minimum arrangement period of the sub-pixel units of the first color is G1, and the minimum arrangement period of the sub-pixel units of the second color is G2, and G is the least common multiple of G1 and G2.
  • the plurality of shift register units are divided into at least one shift register unit scan group, and each of the shift register unit scan groups includes a plurality of adjacent scan groups.
  • the shift register unit group formed by cascaded shift register units, and two adjacent shift register unit groups are not cascaded.
  • each scan group of shift register units includes 16 shift register units, and in each scan group of shift register units, the k+1th The shift register unit and the kth shift register unit are cascaded to form a shift register unit group, and the k+1th shift register unit and the k+2th shift register unit are not cascaded, k It is 1, 3, 5, 7, 9, 11, 13, 15.
  • the gate driving circuit includes a plurality of scan groups of shift register units. Among two adjacent scan groups of shift register units, one shift register unit scans The k-th shift register unit in the group is connected to the k+1-th shift register unit in the scanning group of another shift register unit, and k is 1, 3, 5, 7, 9, 11, 13, and 15.
  • the clock signals received by the 16 shift register units in each of the shift register unit scanning groups are the first clock signal to the sixteenth clock signal, respectively , And the period and duty cycle of the sixteen clock signals are equal.
  • the period is 16 time units
  • the first clock signal, the fifth clock signal, the ninth clock signal, the thirteenth clock signal, and the third clock signal Signal, the seventh clock signal, the eleventh clock signal, and the fifteenth clock signal are adjacent to each other in time sequence
  • the fourth clock signal, the fourth clock signal, the eighth clock signal, the twelfth clock signal, and the sixteenth clock signal are adjacent to each other in time sequence
  • the two clock signals differ by 8 time units in timing.
  • the duty ratio is 9/20.
  • the sub-pixel unit array is divided into at least one sub-pixel unit scanning group, the at least one sub-pixel unit scanning group and the at least one shift register unit scanning The groups correspond one to one.
  • each scan group of shift register units includes 16 shift register units, and each scan group of sub-pixel units includes 8 rows of adjacent sub-pixel units.
  • Two shift register units are electrically connected, and q is an integer greater than or equal to 1 and less than or equal to 8.
  • one gate line is provided on both sides of each row of sub-pixel units, and the row of sub-pixel units is connected to two gate lines provided on both sides.
  • the display panel further includes a data driving circuit disposed in the peripheral area, wherein the data driving circuit is connected to the plurality of data lines, and The data driving circuit is configured to provide the data signal to the sub-pixel unit array in a 2-point polarity switching manner.
  • the polarity of the data signal provided by any one of the plurality of data lines is the same, and the wiring shape of the data line is sawtooth.
  • the L-th shift register unit in each scan group of shift register units, is arranged on the first side of the display area, and the R-th shift register unit is Set on the second side of the display area, the second side is opposite to the first side, L is 1, 2, 3, 4, 9, 10, 11, 12; R is 5, 6, 7, 8, 13, 14, 15, 16.
  • all shift register units in each shift register unit scanning group are arranged on the same side of the display area.
  • At least one embodiment of the present disclosure further provides a display device, including any display panel provided in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for driving a display panel as provided by an embodiment of the present disclosure, including: providing the clock signal to the gate driving circuit so that the gate driving circuit generates the scan signal , So that the at least two non-adjacent sub-pixel units of the same color connected to the same data line are continuously displayed in time sequence.
  • the plurality of sub-pixel units sequentially connected to the same data line include at least a first color and a second color, and the plurality of sub-pixel units sequentially connected to the same data line
  • the minimum arrangement period of the sub-pixel units of the first color is G1
  • the minimum arrangement period of the sub-pixel units of the second color is G2.
  • the driving method further includes: combining G1 and G2. The least common multiple of is regarded as G.
  • the driving method further includes driving the plurality of sub-pixel units sequentially connected to the same data line according to the following sequence numbers: 1, 5, 9, 13, 3, 7, 11, 15, 2, 6, 10, 14, 4, 8, 12, 16.
  • At least one embodiment of the present disclosure further provides a method for driving a display panel as provided in an embodiment of the present disclosure.
  • the sub-pixel unit array is divided into at least one sub-pixel unit scanning group, and the at least one sub-pixel unit scanning group There is a one-to-one correspondence with the at least one shift register unit scanning group, and each of the sub-pixel unit scanning groups includes 8 rows of sub-pixel units adjacent to each other; for each shift register unit scanning group and the corresponding sub-pixel unit
  • the driving method includes: causing the shift register unit scanning group to provide the scanning signal to the sub-pixel unit scanning group corresponding to the shift register unit scanning group, so that the sub-pixel unit
  • the scan group scans and displays in the following order: Line 1, Line 3, Line 5, Line 7, Line 2, Line 4, Line 6, Line 8, Line 1, Line 3, Row 5, Row 7, Row 2, Row 4, Row 6, Row 8.
  • Figure 1 is a schematic diagram of a display panel
  • FIG. 2A is a schematic diagram of the relationship between a clock signal used in the display panel shown in FIG. 1 and a shift register unit;
  • 2B is an exemplary circuit diagram of a shift register unit
  • FIG. 3 is a signal timing diagram of a clock signal used in the display panel shown in FIG. 1;
  • FIG. 5 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a scan group of shift register units provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the connection relationship between scan groups of multiple shift register units provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the relationship between a clock signal used in the display panel shown in FIG. 5 and the shift register unit;
  • FIG. 10 is a signal timing diagram of a clock signal used in the display panel shown in FIG. 5;
  • FIG. 11 is a schematic diagram of another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a connection relationship between a scan group of shift register units and a scan group of sub-pixel units provided by at least one embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of still another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of still another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • Figure 1 shows a display panel that includes a plurality of sub-pixel units PU arranged in an array, for example, includes three-color sub-pixel units PU (red sub-pixel unit R, green sub-pixel unit G, blue Color sub-pixel unit B) to achieve color display. It should be noted that only 5 rows and 12 columns of sub-pixel units PU are shown in FIG. 1. The embodiments of the present disclosure include but are not limited to this. The number of sub-pixel units PU can be set according to actual conditions. In addition, the color type of the sub-pixel unit PU is not limited.
  • the display panel provided by the embodiments of the present disclosure is described by taking as an example the three sub-pixel units PU including RGB.
  • the display panel is a liquid crystal display (LCD) panel.
  • LCD liquid crystal display
  • the display panel is a dual gate drive display panel, that is, a row of sub-pixel units is connected to two gate lines correspondingly, and for example, two adjacent sub-pixel units in the row are connected to Different grid lines.
  • the sub-pixel unit PU in the first row is connected to the gate line GL ⁇ 1> and gate line GL ⁇ 2>
  • the sub-pixel unit PU in the second row is connected to the gate line GL ⁇ 3> and the gate line GL ⁇ 4>
  • the third The row sub-pixel unit PU is connected to the gate line GL ⁇ 5> and the gate line GL ⁇ 6>
  • the fourth row sub-pixel unit PU is connected to the gate line GL ⁇ 7> and the gate line GL ⁇ 8>
  • the fifth row sub-pixel unit PU It is connected to the gate line GL ⁇ 9> and the gate line GL ⁇ 10>.
  • the display panel also includes a plurality of data lines DL (for example, DL ⁇ n-1>, DL ⁇ n>, DL ⁇ n+1>, etc.) for transmitting data signals.
  • DL data lines
  • two sub-pixel units adjacent to each other and connected to different gate lines in the row are respectively connected to the same data line.
  • the wiring shapes of the multiple data lines DL are all zigzags, and the data signals received by multiple sub-pixel units PU connected to any one data line DL have the same polarity.
  • the display panel may use a data driving circuit to provide data signals to the sub-pixel unit PU through the data line DL.
  • the dual-gate line drive display panel adopts a 2-point polarity switching data drive mode, that is, in the same row of sub-pixel units PU, every two adjacent sub-pixel units PU receive The polarities of the data signals are the same. In the same column of sub-pixel units PU, the polarities of the data signals received by every two adjacent sub-pixel units PU are different.
  • the display panel in FIG. 1 may be driven by a gate driving circuit
  • FIG. 2A shows part of the shift register units (the first shift register unit SR1 to the sixteenth shift register unit SR1) included in the gate driving circuit.
  • Bit register unit SR16) and clock signals (first clock signal CLK1 to sixteenth clock signal CLK16) used for the gate drive circuit, these clock signals are passed through, for example, a timing controller (Timing Controller, not shown)
  • the corresponding clock signal line is provided.
  • the first shift register unit SR1 receives the first clock signal CLK1
  • the second shift register unit SR2 receives the second clock signal CLK2
  • the sixteenth shift register unit SR16 receives the first clock signal CLK2.
  • the cascade of the shift register unit A and the shift register unit B means that the output signal of the shift register unit A is provided as an input signal to the shift register B to trigger the shift register B, or, the output signal of the shift register unit B is provided as an input signal to the shift register A to trigger the shift register A.
  • the shift register unit 600 is the nth stage of the gate drive circuit.
  • the shift register unit 600 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a storage capacitor C1.
  • the first transistor T1 in the shift register unit 600 is the output transistor of the signal output terminal of the shift register unit 600.
  • the first electrode of the first transistor T1 is connected to the clock signal CLK
  • the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 to obtain the output terminal of the shift register unit 600 and can output the scan signal Gn , And the input signal for the next stage shift register unit 600.
  • the gate of the first transistor T1 is connected to the pull-up node PU, thereby connecting the first electrode of the third transistor T3 and the second electrode of the fourth transistor T4.
  • the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the low-level signal VGL.
  • the gate of the second transistor T2 is connected to the gate of the third transistor T3 and the output terminal of the shift register unit 600 in the next row, that is the n+1th row, to receive the scan signal G(n+1) as the output pull-down control signal .
  • the first pole of the second transistor T2 is connected to the second pole of the first transistor T1, so it can be turned on under the control of the output pull-down control signal, and the output signal at the output terminal is pulled down to the low-level signal VGL when there is no need to output the scan signal Gn .
  • the first pole of the third transistor T3 is also connected to the pull-up node PU, thereby being electrically connected to the second pole of the fourth transistor T4 and the gate of the first transistor T1.
  • the second electrode of the third transistor T3 is connected to the low-level signal VGL.
  • the gate of the third transistor T3 is also connected to the output terminal of the shift register unit 600 in the next row, the n+1th row, to receive the scan signal G(n+1) as a reset control signal (it also outputs a pull-down control signal ), which can be turned on under the control of the reset control signal to reset the pull-up node PU to the low level signal VGL, thereby turning off the first transistor T1.
  • the first electrode of the fourth transistor T4 is connected to its own gate, and is connected to the output terminal of the shift register unit 600 in the n-1th row of the previous row to receive the scanning signal G(n-1) as the input signal (and the input Control signal), the second electrode of the fourth transistor T4 is connected to the pull-up node PU, so that the pull-up node PU can be charged when the fourth transistor T4 is turned on, so that the voltage of the pull-up node PU can transfer the first transistor T1 Turn on, so that the clock signal CLK is output through the output terminal.
  • One end of the storage capacitor C1 is connected to the gate of the first transistor T1, that is, the pull-up node PU, and the other end is connected to the second electrode of the first transistor T1, so that the level of the pull-up node PU can be stored, and the first transistor T1 can be conductive.
  • the level of the pull-up node PU will continue to be pulled up through its own bootstrap effect to improve the output performance.
  • the fourth transistor T4 When the gate drive circuit composed of the shift register unit 600 shown in FIG. 2B cascaded in operation, when the scan signal G(n-1) is at a high level, the fourth transistor T4 is turned on and charges the pull-up node PU.
  • the raised level of the pull-up node PU causes the first transistor T1 to be turned on, so the clock signal CLK can be output at the output terminal through the first transistor T1, that is, the scan signal Gn is equal to the clock signal CLK.
  • the scan signal Gn When the clock signal CLK is at a high level, the scan signal Gn also outputs a high level.
  • the shift register unit 600 of the gate driving circuit inputs the high-level signal Gn to the gate line GL of the corresponding row, so that all the sub-pixel units corresponding to the gate line GL of the row
  • the signal is applied to the gate of the thin film transistors to make these thin film transistors turn on, and the data signal is input to the liquid crystal capacitor of the corresponding sub pixel unit through the thin film transistor in each sub pixel unit, so as to contact the liquid crystal in the corresponding sub pixel unit.
  • the capacitor is charged, so that the signal voltage of the sub-pixel unit is written and maintained.
  • the second transistor T2 and the third transistor T3 are turned on to achieve the effect of resetting the pull-up node PU and pulling down the output terminal. Therefore, through the gate driving circuit, for example, a progressive scan driving function can be realized.
  • the structure of the shift register unit of the gate drive circuit is not limited to the above-described structure, and the shift register unit of the gate drive circuit can have any applicable structure or Including more or less transistors and/or capacitors, for example, adding sub-circuits for implementing functions such as pull-up node control, pull-down node control, noise reduction, etc., which are not limited in the embodiments of the present disclosure.
  • FIG. 3 shows the timing relationship of the clock signals (the first clock signal CLK1 to the sixteenth clock signal CLK16) in FIG. 2A.
  • the duty ratio that is, the ratio of the duration of the high level to the period
  • the period of the first clock signal CLK1 to the sixteenth clock signal CLK16 are respectively equal.
  • the time when the sixteen clock signals are at a high level covers the entire time range, so the sixteen sub-clock signals can form a cycle group.
  • the time when any two adjacent clock signals are staggered in timing can be defined as a time unit TU, and the period of the clock signal is 16*TU.
  • the time sequence of two clock signals is adjacent, which means that the two clock signals are staggered by one time unit TU in time sequence.
  • the descriptions of the time unit TU and the adjacent time sequence in the following embodiments are the same, and will not be repeated.
  • the display panel needs to be tested after the manufacturing process is completed. For example, let the entire display panel display the same color, for example, red, green, or blue.
  • the order of the sub-pixel units PU connected to the data line DL ⁇ n-1> is R->B->R->G->R->B->R->G->R ->B->R->G->R->B->R->G.
  • the order of the polarity of the data signal to be provided by the data line DL ⁇ n-1> is +-+-+-+-+-+-+-+- (red
  • the sub-pixel unit R needs to be lit corresponding to polarity +, and other colors correspond to polarity -)
  • the polarity of the provided data signal is reversed (the polarity change from + to-or from-to + is called polarity inversion)
  • the number of times is 16; for another example, the order of the sub-pixel units PU connected to the data line DL ⁇ n> is R->G->B->G->R->G->B->G->R-> G->B->G->R->G->B->G.
  • the order of the polarity of the data signal to be provided by the data line DL ⁇ n> is +---+---+---+--- (red sub-pixel Unit R needs to be lit corresponding to polarity +, and other colors correspond to polarity -), then the polarity of the provided data signal is 8 times; for example, the sub-pixel unit PU connected to the data line DL ⁇ n+1>
  • the order is B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B.
  • the order of the polarity of the data signal to be provided by the data line DL ⁇ n+1> is --+---+---+---+- (red
  • the sub-pixel unit R needs to be lit corresponding to polarity +, and other colors correspond to polarity -), and the number of polarity inversions of the provided data signal is 8 times.
  • the inventors thought that the sub-pixel units of the same color connected to the same data line DL could be continuously displayed in time sequence, so as to reduce the polarity inversion. Times, thereby reducing the power consumption of the display panel.
  • the sub-pixel units PU connected to the same data line DL are arranged in four cycles.
  • the lighting sequence of each sub-pixel unit PU can be R->R->R->R->R->R->R ->R->B->B->B->G->G->G->G->G, in this case, the number of polarity inversions when the data driving circuit provides the data signal is 2 times.
  • the lighting order of each sub-pixel unit PU can be B->B->B->B->R->R->R- >R->G->G->G->G->B->B->B->B, in this case, the number of polarity inversions when the data driving circuit provides the data signal is 3;
  • the lighting order of each sub-pixel unit PU connected to the data line DL ⁇ n+1> can be R->R->R->R->B->B->B- >B->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G, in this case, the number of polarity inversions when the data driving circuit provides the data signal is 2 times. Therefore, the number of polarity inversions can be greatly reduced, thereby reducing the power consumption of the display panel.
  • At least one embodiment of the present disclosure provides a display panel including a display area and a peripheral area.
  • the display area includes a sub-pixel unit array with multiple rows and multiple columns of sub-pixel units, a gate drive circuit is arranged in the peripheral area, and the display area also includes multiple gate lines and multiple data lines for driving the sub-pixel unit array, Each sub-pixel unit is driven and displayed by a scan signal provided by a gate line and a data signal provided by a data line, and the same data line is connected to at least two sub-pixel units of the same color that are not adjacent to each other;
  • the gate driving circuit includes multiple A number of shift register units arranged in sequence, a plurality of gate lines are arranged in sequence and electrically connected with a plurality of shift register units arranged in sequence in a one-to-one correspondence;
  • the gate driving circuit is configured to receive a clock signal and generate a scanning signal to At least two sub-pixel units of the same color that are not adjacent to each other connected to the same data line are continuously displayed in time sequence.
  • At least one embodiment of the present disclosure also provides a display device and a driving method corresponding to the above-mentioned display panel.
  • the display panel, display device, and driving method provided by some embodiments of the present disclosure can avoid the problems of poor process and low product yield caused by the use of interleaved wiring in the gate driving circuit and gate lines, and can also reduce power consumption. .
  • At least one embodiment of the present disclosure provides a display panel 10. As shown in FIG. 5, the display panel 10 includes a display area DR and a peripheral area PR.
  • the display area DR includes a sub-pixel unit array 100 having multiple rows and multiple columns of sub-pixel units PU. It should be noted that FIG. 5 only schematically shows 5 rows and 12 columns of sub-pixel units PU. The embodiments of the present disclosure include but are not limited to this. The number of sub-pixel units PU included in the display panel 10 can be determined as required. Set up. For example, the arrangement of the sub-pixel unit array 100 shown in FIG. 5 may adopt the arrangement shown in FIG. 1.
  • a gate driving circuit 200 is provided in the peripheral area PR, and the display area DR also includes a plurality of gate lines GL (for example, GL ⁇ 1>, GL ⁇ 2>, etc.) and a plurality of data lines DL (for example, DL ⁇ 1> , DL ⁇ 2>, DL ⁇ 3>, etc.) for driving the sub-pixel unit array 100.
  • Each sub-pixel unit PU is driven and displayed by a scan signal provided by a gate line GL and a data signal provided by a data line DL, and the same One data line DL connects at least two sub-pixel units PU of the same color that are not adjacent to each other.
  • the order of the sub-pixel units PU connected to the data line DL ⁇ 1> is R->B->R->G->R-> B->R->G->R->B->R->G->R->B->R->G
  • the order of the sub-pixel unit PU connected to the data line DL ⁇ 2> is R-> G->B->G->R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G
  • the order of the connected sub-pixel units PU is B->G->R->B->B->G->R->B->B->G->R->B->G- >R->B.
  • any sub-pixel unit PU of the same color is not adjacent.
  • the sub-pixel units PU of only one color may not be adjacent and the sub-pixel units PU of the other two colors may be adjacent; for another example, the sub-pixel units of only two colors may also be PUs are not adjacent but sub-pixel units PU of another color are adjacent.
  • the gate driving circuit 200 includes a plurality of shift register units S1 to S10 arranged in sequence, and a plurality of gate lines GL are arranged in sequence and electrically connected to a plurality of shift register units (S1 to S10, etc.) arranged in sequence in a one-to-one correspondence. .
  • FIG. 5 when the multiple shift register units in the gate drive circuit 200 in the display panel 10 are connected to the multiple gate lines GL, there is no interleaved wiring, so that the gate drive circuit 200 and the gate lines GL can be avoided.
  • FIG. 5 only schematically shows 10 shift register units in the gate driving circuit 200.
  • the embodiments of the present disclosure include, but are not limited to, the shift register included in the gate driving circuit 200
  • the number of units can be set as required. For example, in a display panel using dual gate lines, the number of shift register units can be set to twice the number of rows of sub-pixel units PU.
  • the gate driving circuit 200 is configured to receive a clock signal and generate a scan signal, so that at least two non-adjacent sub-pixel units PU of the same color connected to the same data line DL are continuously displayed in time sequence.
  • the display order of the sub-pixel units PU connected to the data line DL ⁇ 1> may be R->R->R->R->R- >R->R->B->B->B->G->G->G->G->G->G
  • the display order of the sub-pixel unit PU connected to the data line DL ⁇ 2> can be B-> B->B->B->R->R->R->R->G->G->G->G->G->G->B->B->B->B
  • the display order of the connected sub-pixel units PU can be R->R->R->R->B->B->B->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->G->B->B->B->B
  • the sub-pixel unit array 100 in the display area DR is driven by the gate driving circuit 200, so that at least two connected to the same data line DL are not adjacent to each other.
  • the sub-pixel units PU of the same color are continuously displayed in time sequence, for example, so that all sub-pixel units PU of the same color that are not adjacent to each other connected to the same data line DL are continuously displayed in time sequence.
  • a data driving circuit may be used to provide data signals to the sub-pixel unit array 100.
  • the sequence number of the sub-pixel unit PU, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.
  • the multiple sub-pixel units PU sequentially connected to the same data line DL include at least a first color and a second color.
  • the sub-pixel unit of the first color The minimum arrangement period of the PU is G1
  • the minimum arrangement period of the sub-pixel unit PU of the second color is G2, so G is the least common multiple of G1 and G2.
  • the sub-pixel unit PU connected to the data line DL ⁇ 1> is taken as an example for description.
  • the arrangement period of the blue sub-pixel unit PU is also 4, the two colors are used as an example for description, but when the arrangement periods of the three colors are all different, the G The value is the least common multiple of the respective arrangement periods of the sub-pixel units PU of the three colors.
  • the sequence numbers of the sub-pixel units PU that are driven in sequence are 3,
  • the embodiment of the present disclosure does not limit the order of the above-mentioned driving groups.
  • the gate driving circuit 200 is configured such that the order in which the driving groups are driven is: Drive group, 3rd drive group, 2nd drive group, 4th drive group.
  • the order in which they are driven is: 1, 5, 9, 13, 3, 7, 11, 15, 2, 6, 10, 14, 4, 8, 12, 16.
  • the gate driving circuit 200 shown in FIG. 5 will be further described below.
  • each shift register unit scanning group 210 includes a plurality of adjacent and cascaded shift registers.
  • the shift register unit group 220 formed by the unit PU, and two adjacent shift register unit groups 220 are not cascaded.
  • each shift register unit group 220 includes m adjacent and cascaded shift register units PU, and m is an integer greater than or equal to 2.
  • FIG. 6 only schematically shows one shift register unit scanning group 210 included in the gate driving circuit 200.
  • the embodiments of the present disclosure include, but are not limited to, the implementation of the present disclosure.
  • the number of shift register unit scanning groups 210 included in the gate driving circuit 200 in the example can be set as required.
  • each shift register unit scanning group 210 includes 16 shift register units (S ⁇ 1> to S ⁇ 16>).
  • the k+1th shift register unit and the kth shift register unit are cascaded to form a shift register unit group 220, and the k+1th shift register unit and the k+th shift register unit
  • the two shift register units are not cascaded, and k is 1, 3, 5, 7, 9, 11, 13, 15.
  • the second shift register unit S ⁇ 2> and the first shift register unit S ⁇ 1> are cascaded to form a shift register unit group 220, and the second shift register unit S ⁇ 2> and the third shift register unit S ⁇ 3> are not cascaded;
  • the fourth shift register unit S ⁇ 4> and the third shift register unit S ⁇ 3> are cascaded to form a shift register Unit group 220, and the 4th shift register unit S ⁇ 4> and the 5th shift register unit S ⁇ 5> are not cascaded;
  • the 6th shift register unit S ⁇ 6> and the 5th shift register Unit S ⁇ 5> is cascaded to form a shift register unit group 220, and the 6th shift register unit S ⁇ 6> and the 7th shift register unit S ⁇ 7> are not cascaded;
  • the 8th shift register Unit S ⁇ 8> and the 7th shift register unit S ⁇ 7> are cascaded to form a shift register unit group 220, and the 8th shift register unit S ⁇ 8> and the 9th shift register unit S ⁇ 9>No cascade
  • the gate driving circuit 200 includes a plurality of scan groups 210 of shift register units, it will be described below with reference to FIG. 8 that the plurality of scan groups 210 of shift register units are cascaded.
  • the gate driving circuit 200 includes a plurality of shift register unit scanning groups 210.
  • FIG. 8 only shows the gate
  • the two scan groups 210 of shift register units included in the pole drive circuit 200 are represented as 210 ⁇ 1> and 210 ⁇ 2> respectively.
  • one shift register The k-th shift register unit in the unit scanning group 210 ⁇ 2> is connected to the k+1-th shift register unit in the other shift register unit scanning group 210 ⁇ 1>, and k is 1, 3, 5, 7, 9, 11, 13, 15.
  • the relative positional relationship between the scan groups 210 of the two shift register units shown in FIG. 8 does not represent the real positional relationship. This is only for the convenience of description, so the shift register unit scan groups 210 ⁇ 2> is drawn on the right side of the shift register unit scan group 210 ⁇ 1>.
  • the shift register unit scans the first shift register unit S ⁇ 1> in the group 210 ⁇ 2> and the shift register unit scans the second shift register in the group 210 ⁇ 1> Unit S ⁇ 2> is connected; the shift register unit scans the 3rd shift register unit S ⁇ 3> in the group 210 ⁇ 2> and the shift register unit scans the 4th shift register unit in the group 210 ⁇ 1> S ⁇ 4> connection; the fifth shift register unit S ⁇ 5> in the shift register unit scan group 210 ⁇ 2> and the sixth shift register unit S in the shift register unit scan group 210 ⁇ 1> ⁇ 6> Connection; the 7th shift register unit S ⁇ 7> in the shift register unit scan group 210 ⁇ 2> and the 8th shift register unit S ⁇ 1> in the shift register unit scan group 210 ⁇ 1> 8> Connection; the 9th shift register unit S ⁇ 9> in the shift register unit scan group 210 ⁇ 2> and the 10th shift register unit S ⁇ 10 in the shift register unit scan group 210 ⁇ 1> >Connect; the shift register unit S ⁇ 9> in the
  • each shift register unit scans the clock signals received by the 16 shift register units (S ⁇ 1> to S ⁇ 16>) in the group 210 respectively It is the first clock signal CK1 to the sixteenth clock signal CK16, and the periods and duty ratios of the sixteen clock signals are equal.
  • FIG. 10 shows a signal timing diagram of a clock signal for the display panel 10 provided by an embodiment of the present disclosure.
  • the first clock signal CK1 to the sixteenth clock signal CK16 are provided by the timing controller, and their periods and duty ratios are equal.
  • the period of each clock signal is 16 time units TU, that is, 16TU
  • the ratio of the high level time to the period in each clock signal is 7.2/16
  • the duty cycle of each clock signal is 9. /20.
  • the duty cycle shown in FIG. 10 is only illustrative, and the clock signal in the embodiment of the present disclosure may also adopt other duty cycles.
  • the time at the low level in the clock signal can be made slightly longer than the time at the high level.
  • the first clock signal CK1, the fifth clock signal CK5, the ninth clock signal CK9, the thirteenth clock signal CK13, the third clock signal CK3, the seventh clock signal CK7, and the eleventh clock signal CK11 and the fifteenth clock signal CK15 are adjacent to each other in timing.
  • the second clock signal CK2, the sixth clock signal CK6, the tenth clock signal CK10, the fourteenth clock signal CK14, the fourth clock signal CK4, the eighth clock signal CK8, the twelfth clock signal CK12, and the sixteenth clock signal CK16 Adjacent to each other in timing.
  • the first clock signal CK1 and the second clock signal CK2 differ in timing by 8 time units TU.
  • the first clock signal CK1 to the sixteenth clock signal CK16 are provided to the gate driving circuit 200 in the following order: CK1->CK5->CK9->CK13->CK3->CK7->CK11-> CK15->CK2->CK6->CK10->CK14->CK4->CK8->CK12->CK16.
  • the sequence of providing the clock signal can be stored in the timing controller (Timing Controller) or other devices of the display panel 10 in the form of program code (algorithm), and the program code can be directly executed when needed to generate the required clock. signal.
  • the sub-pixel unit array 100 is divided into at least one sub-pixel unit scanning group 110, at least one sub-pixel unit scanning group 110, and at least one shift register
  • the unit scanning group 210 has a one-to-one correspondence.
  • two sub-pixel unit scan groups 110 and two corresponding shift register unit scan groups 210 are shown in FIG. 11, but the embodiments of the present disclosure include but are not limited to this.
  • the sub-pixels in the embodiment of the present disclosure The number of unit scan groups 110 can be set as required.
  • each shift register unit scanning group 110 includes 16 shift register units (S ⁇ 1> to S ⁇ 16>), and each sub-pixel The unit scanning group 110 includes 8 rows of sub-pixel units adjacent to each other, for example, the first row of sub-pixel units PUL ⁇ 1> to the eighth row of sub-pixel units PUL ⁇ 8>.
  • each sub-pixel unit scanning group 110 the q-th row of sub-pixel units and the shift register unit corresponding to the sub-pixel unit scanning group 110 are the 2q-1th shift register unit and the 2qth shift register unit in the scanning group 210.
  • the shift register unit is electrically connected, and q is an integer greater than or equal to 1 and less than or equal to 8.
  • the first row of sub-pixel units PUL ⁇ 1> is electrically connected to the first shift register unit S ⁇ 1> and the second shift register unit S ⁇ 2>; the second row of sub-pixels The unit PUL ⁇ 2> is electrically connected to the third shift register unit S ⁇ 3> and the fourth shift register unit S ⁇ 4>; the third row sub-pixel unit PUL ⁇ 3> and the fifth shift register unit S ⁇ 5> and the sixth shift register unit S ⁇ 6> are electrically connected; the fourth row sub-pixel unit PUL ⁇ 4> and the seventh shift register unit S ⁇ 7> and the eighth shift register unit S ⁇ 8> Electrical connection; the fifth row sub-pixel unit PUL ⁇ 5> and the ninth shift register unit S ⁇ 9> and the tenth shift register unit S ⁇ 10> are electrically connected; the sixth row sub-pixel unit PUL ⁇ 6> is electrically connected to the eleventh shift register unit S ⁇ 11> and the twelfth shift register unit S ⁇ 12>; the seventh row sub-pixel unit PUL ⁇ 7> and the thirteen
  • the shift register unit may be electrically connected to the corresponding sub-pixel unit row through the gate line.
  • the gate line For example, as shown in FIG. 12, one gate line GL is provided on both sides of each row of sub-pixel units, and the row of sub-pixel units is connected to two gate lines GL provided on both sides.
  • FIG. 13 shows a connection manner between the gate line GL, the shift register unit and the corresponding sub-pixel unit.
  • the display panel 10 includes a gate driving circuit 200 provided in the peripheral area PR, and further includes a data driving circuit 300 provided in the peripheral area PR.
  • the gate driving circuit 200 is connected to a plurality of gate lines, and is also connected to the timing controller 400 through a clock signal line to receive a clock signal;
  • the data driving circuit 300 is connected to a plurality of data lines DL, and the data driving circuit 300 is configured as
  • the data signal is provided to the sub-pixel unit array 100 in a 2-point polarity switching manner.
  • 2-point polarity switching reference can be made to the corresponding description in FIG. 1, which will not be repeated here.
  • the polarity of the data signal provided by any one of the multiple data lines DL is the same, and the trace shape of the data line DL is Zigzag.
  • the working principle of the display panel 10 shown in FIG. 13 will be described below in conjunction with the signal timing diagram shown in FIG. 10.
  • the following takes the sub-pixel unit PU connected to the data line DL ⁇ 1> as an example for description.
  • the first shift register unit S ⁇ 1> provides a scan signal through the gate line GL ⁇ 1>, while the data driving circuit 300 provides data through the data line DL ⁇ 1> Therefore, a red sub-pixel unit R connected to the data line DL ⁇ 1> performs display under the driving of the scan signal and the data signal.
  • the fifth shift register unit S ⁇ 5> provides the scan signal through the gate line GL ⁇ 5>, and the data driving circuit 300 passes the data
  • the line DL ⁇ 1> provides a data signal, so another red sub-pixel unit R connected to the data line DL ⁇ 1> performs display under the driving of the scan signal and the data signal.
  • the ninth shift register unit S ⁇ 9> provides a scan signal through the gate line GL ⁇ 9>, and the data driving circuit 300 passes the data
  • the line DL ⁇ 1> provides a data signal, so another red sub-pixel unit R connected to the data line DL ⁇ 1> performs display under the driving of the scan signal and the data signal.
  • the thirteenth shift register unit S ⁇ 13> provides a scan signal through the gate line GL ⁇ 13> (not shown in FIG. 13). S ⁇ 13> and gate line GL ⁇ 13>), and the data driving circuit 300 provides data signals through the data line DL ⁇ 1>, so the other red sub-pixel unit R connected to the data line DL ⁇ 1> is in the scanning signal And display under the driving of the data signal.
  • the gate driving circuit 200 provides scan signals to the sub-pixel unit array 100 according to the timing of the received clock signal
  • the data driving circuit 300 provides data signals to the turned-on sub-pixel units PU through the data line DL ⁇ 1>. Therefore, the sub-pixel unit PU connected to the data line DL ⁇ 1> is displayed in the following order: R->R->R->R->R->R->R->R->B->B ->B->G->G->G->G->G->G->G, so that among the multiple sub-pixel units PU connected to the data line DL ⁇ 1>, the sub-pixel units PU of the same color are continuously displayed in time sequence Therefore, the number of polarity inversions of the data signal provided to the sub-pixel unit array 100 can be reduced, and the power consumption of the display panel 10 can be reduced.
  • the L-th shift register unit is arranged on the first side of the display area DR, and the R-th shift register unit
  • the bit register unit is arranged on the second side of the display area DR, the second side is opposite to the first side, L is 1, 2, 3, 4, 9, 10, 11, 12; R is 5, 6, 7, 8, 13, 14, 15, 16.
  • the first side is the left side of the display area DR, and the second side is the right side of the display area DR; or, the first side is the right side of the display area DR, and the second side is the left side of the display area DR.
  • the shift register unit in the gate driving circuit 200 in the display panel 10 provided by the embodiment of the present disclosure may be provided on both sides of the display area DR, respectively.
  • the shift register units in the gate driving circuit 200 in the display panel 10 may also be all arranged on one side of the display area DR.
  • arranging the shift register units in the gate driving circuit 200 on both sides of the display area DR can better reduce A smaller frame size of the display panel makes it easier to achieve a narrow frame.
  • At least one embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes any display panel 10 provided by the embodiments of the present disclosure.
  • the display device 1 in this embodiment can be: liquid crystal panel, liquid crystal TV, display, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Functional products or components.
  • At least one embodiment of the present disclosure further provides a driving method of a display panel.
  • the driving method may be used for any display panel 10 provided by the embodiments of the present disclosure.
  • the driving method includes: providing the gate driving circuit 200
  • the clock signal causes the gate driving circuit 200 to generate a scan signal, so that at least two sub-pixel units PU of the same color that are not adjacent to each other connected to the same data line DL are continuously displayed in time sequence.
  • the multiple sub-pixel units PU sequentially connected to the same data line DL include at least a first color and a second color
  • the multiple sub-pixel units PU sequentially connected to the same data line DL Among the sub-pixel units PU, the minimum arrangement period of the sub-pixel unit PU of the first color is G1, and the minimum arrangement period of the sub-pixel unit PU of the second color is G2.
  • the driving method further includes: the least common multiple of G1 and G2 As G.
  • the driving method further includes driving 16 sub-pixel units connected to the same data line according to the following sequence numbers: 1, 5 , 9, 13, 3, 7, 11, 15, 2, 6, 10, 14, 4, 8, 12, 16.
  • At least one embodiment of the present disclosure also provides a method for driving a display panel.
  • the sub-pixel unit array 100 of the display panel 10 is divided into at least one sub-pixel unit scanning group 110, at least one sub-pixel unit scanning group 110 and At least one shift register unit scanning group 210 has a one-to-one correspondence, and each sub-pixel unit scanning group 110 includes 8 rows of sub-pixel units PU adjacent to each other.
  • the driving method includes the following operation steps.
  • the shift register unit scanning group 210 is made to provide scanning signals to the sub-pixel unit scanning group 110 correspondingly connected to the shift register unit scanning group 210, so that the sub-pixel unit scanning group 110 scans and displays in the following order:
  • Row 1 Row 3, Row 5, Row 7, Row 2, Row 4, Row 6, Row 8, Row 1, Row 3, Row 5, Row 7, Row 2 Row, row 4, row 6, row 8.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板、显示装置以及驱动方法。该显示面板，包括显示区域和周边区域。显示区域包括具有多行、多列子像素单元的子像素单元阵列，在周边区域中设置有栅极驱动电路，显示区域还包括多条栅线和多条数据线，用于驱动子像素单元阵列，每个子像素单元由一条栅线提供的扫描信号和一条数据线提供的数据信号驱动显示，且同一条数据线连接至少两个彼此不相邻的相同颜色的子像素单元；栅极驱动电路包括多个依次布置的移位寄存器单元，多条栅线依次排列且与多个依次布置的移位寄存器单元依序一一对应电连接；栅极驱动电路被配置为接收时钟信号并产生扫描信号，以使得和同一条数据线连接的至少两个彼此不相邻的相同颜色的子像素单元在时序上连续显示。

Description

显示面板、显示装置以及驱动方法 技术领域
本公开的实施例涉及一种显示面板、显示装置以及驱动方法。
背景技术
在显示技术领域，为了改善显示画面的质量，提高用户体验，高PPI(Pixels Per Inch，每英寸像素数量)和窄边框的实现逐渐成为研究的方向。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，可以将驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对显示面板进行驱动。GOA技术有助于实现显示面板的窄边框设计，并且可以降低显示面板的生产成本。
发明内容
本公开至少一实施例提供一种显示面板，包括显示区域和周边区域。所述显示区域包括具有多行、多列子像素单元的子像素单元阵列，在所述周边区域中设置有栅极驱动电路，所述显示区域还包括多条栅线和多条数据线，用于驱动所述子像素单元阵列，每个子像素单元由一条栅线提供的扫描信号和一条数据线提供的数据信号驱动显示，且同一条数据线连接至少两个彼此不相邻的相同颜色的子像素单元；所述栅极驱动电路包括多个依次布置的移位寄存器单元，所述多条栅线依次排列且与所述多个依次布置的移位寄存器单元依序一一对应电连接；所述栅极驱动电路被配置为接收时钟信号并产生所述扫描信号，以使得和同一条数据线连接的所述至少两个彼此不相邻的相同颜色的子像素单元在时序上连续显示。
例如，在本公开一实施例提供的显示面板中，和同一条数据线依次连接的多个子像素单元被驱动时被划分为G个驱动组，所述时钟信号的个数为H，每个所述驱动组包括F个子像素单元，F＝[H/G]，[H/G]表示对H/G取整；所述栅极驱动电路还被配置为使得第B个驱动组中的F个子像素单元被驱动的顺序为：A d＝B+(d-1)*G，其中，A d表示第d次被驱动的子像素单元的顺序序号，B为小于等于G的正整数，d为小于等于F的正整数。
例如，在本公开一实施例提供的显示面板中，所述和同一条数据线依次连接的多个子像素单元至少包括第一颜色和第二颜色，在所述和同一条数据线依次连接的多个子像素单元中，所述第一颜色的子像素单元的最小排布周期为G1，所述第二颜色的子像素单元的最小排布周期为G2，则G为G1和G2的最小公倍数。
例如，在本公开一实施例提供的显示面板中，所述多个移位寄存器单元被划分为至少一个移位寄存器单元扫描组，每个所述移位寄存器单元扫描组包括多个由相邻且级联的移位寄存器单元构成的移位寄存器单元组，且相邻的两个移位寄存器单元组之间不级联。
例如，在本公开一实施例提供的显示面板中，每个所述移位寄存器单元扫描组包括16个移位寄存器单元，在每个所述移位寄存器单元扫描组中，第k+1个移位寄存器单元和第k个移位寄存器单元级联以构成一个所述移位寄存器单元组，且第k+1个移位寄存器单元和第k+2个移位寄存器单元不级联，k为1、3、5、7、9、11、13、15。
例如，在本公开一实施例提供的显示面板中，所述栅极驱动电路包括多个移位寄存器单元扫描组，在相邻的两个移位寄存器单元扫描组中，一个移位寄存器单元扫描组中的第k个移位寄存器单元和另一个移位寄存器单元扫描组中的第k+1个移位寄存器单元连接，k为1、3、5、7、9、11、13、15。
例如，在本公开一实施例提供的显示面板中，每个所述移位寄存器单元扫描组中的16个移位寄存器单元接收的所述时钟信号分别为第一时钟信号至第十六时钟信号，且该十六个时钟信号的周期以及占空比均相等。
例如，在本公开一实施例提供的显示面板中，所述周期为16个时间单元，且所述第一时钟信号、第五时钟信号、第九时钟信号、第十三时钟信号、第三时钟信号、第七时钟信号、第十一时钟信号以及第十五时钟信号在时序上彼此相邻；所述第二时钟信号、所述第六时钟信号、所述第十时钟信号、所述第十四时钟信号、所述第四时钟信号、所述第八时钟信号、所述第十二时钟信号以及所述第十六时钟信号在时序上彼此相邻；所述第一时钟信号和所述第二时钟信号在时序上相差8个时间单元。
例如，在本公开一实施例提供的显示面板中，所述占空比为9/20。
例如，在本公开一实施例提供的显示面板中，所述子像素单元阵列被划分为至少一个子像素单元扫描组，所述至少一个子像素单元扫描组和所述至 少一个移位寄存器单元扫描组一一对应。
例如，在本公开一实施例提供的显示面板中，每个所述移位寄存器单元扫描组包括16个移位寄存器单元，每个所述子像素单元扫描组中包括彼此相邻的8行子像素单元；在每个所述子像素单元扫描组中，第q行子像素单元和该子像素单元扫描组对应的移位寄存器单元扫描组中的第2q-1个移位寄存器单元以及第2q个移位寄存器单元电连接，q为大于等于1且小于等于8的整数。
例如，在本公开一实施例提供的显示面板中，在每一行子像素单元两侧分别设置一条栅线，且该行子像素单元和设置在两侧的两条栅线连接。
例如，在本公开一实施例提供的显示面板中，所述显示面板还包括设置在所述周边区域中的数据驱动电路，其中，所述数据驱动电路和所述多条数据线连接，且所述数据驱动电路被配置为采用2点极性切换的方式向所述子像素单元阵列提供所述数据信号。
例如，在本公开一实施例提供的显示面板中，所述多条数据线中的任一一条数据线提供的数据信号的极性相同，且该条数据线的走线形状为锯齿形。
例如，在本公开一实施例提供的显示面板中，在每一个移位寄存器单元扫描组中，第L个移位寄存器单元设置在所述显示区域的第一侧，第R个移位寄存器单元设置在所述显示区域的第二侧，所述第二侧与所述第一侧相对，L为1、2、3、4、9、10、11、12；R为5、6、7、8、13、14、15、16。
例如，在本公开一实施例提供的显示面板中，每一个移位寄存器单元扫描组中的所有移位寄存器单元均设置在所述显示区域的同一侧。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的任一显示面板。
本公开至少一实施例还提供一种如本公开的实施例提供的显示面板的驱动方法，包括：向所述栅极驱动电路提供所述时钟信号使得所述栅极驱动电路产生所述扫描信号，以使得和同一条数据线连接的所述至少两个彼此不相邻的相同颜色的子像素单元在时序上连续显示。
例如，在本公开一实施例提供的驱动方法中，和同一条数据线依次连接的多个子像素单元被驱动时被划分为G个驱动组，所述时钟信号的个数为H，每个所述驱动组包括F个子像素单元，F＝[H/G]，[H/G]表示对H/G取整，所述驱动方法还包括按照如下顺序对第B个驱动组中的F个子像素单元进行 驱动：A d＝B+(d-1)*G，其中，A d表示第d次被驱动的子像素单元的顺序序号，B为小于等于G的正整数，d为小于等于F的正整数。
例如，在本公开一实施例提供的驱动方法中，所述和同一条数据线依次连接的多个子像素单元至少包括第一颜色和第二颜色，在所述和同一条数据线依次连接的多个子像素单元中，所述第一颜色的子像素单元的最小排布周期为G1，所述第二颜色的子像素单元的最小排布周期为G2，所述驱动方法还包括：将G1和G2的最小公倍数作为G。
例如，在本公开一实施例提供的驱动方法中，G＝4，H＝16，所述驱动方法还包括按照如下顺序序号对所述和同一条数据线依次连接的多个子像素单元进行驱动：1、5、9、13、3、7、11、15、2、6、10、14、4、8、12、16。
本公开至少一实施例还提供一种如本公开的实施例提供的显示面板的驱动方法，所述子像素单元阵列被划分为至少一个子像素单元扫描组，所述至少一个子像素单元扫描组和所述至少一个移位寄存器单元扫描组一一对应，且每个所述子像素单元扫描组中包括彼此相邻的8行子像素单元；对于每一个移位寄存器单元扫描组以及对应的子像素单元扫描组来说，所述驱动方法包括：使得所述移位寄存器单元扫描组向该移位寄存器单元扫描组对应连接的子像素单元扫描组提供所述扫描信号，以使得该子像素单元扫描组按照如下的顺序进行扫描显示：第1行、第3行、第5行、第7行、第2行、第4行、第6行、第8行、第1行、第3行、第5行、第7行、第2行、第4行、第6行、第8行。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的示意图；
图2A为用于图1所示的显示面板的一种时钟信号和移位寄存器单元之间关系的示意图；
图2B为一种移位寄存器单元的示例性电路图；
图3为用于图1所示的显示面板的一种时钟信号的信号时序图；
图4为用于解释本公开实施例的原理示意图；
图5为本公开至少一实施例提供的一种显示面板的示意图；
图6为本公开至少一实施例提供的一种栅极驱动电路的示意图；
图7为本公开至少一实施例提供的一种移位寄存器单元扫描组的示意图；
图8为本公开至少一实施例提供的多个移位寄存器单元扫描组之间的连接关系示意图；
图9为用于图5所示的显示面板的一种时钟信号和移位寄存器单元之间关系的示意图；
图10为用于图5所示的显示面板的一种时钟信号的信号时序图；
图11为本公开至少一实施例提供的另一种显示面板的示意图；
图12为本公开至少一实施例提供的一种移位寄存器单元扫描组和子像素单元扫描组之间的连接关系示意图；
图13为本公开至少一实施例提供的再一种显示面板的示意图；
图14为本公开至少一实施例提供的又一种显示面板的示意图；以及
图15为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
图1示出了一种显示面板，该显示面板包括呈阵列排布的多个子像素单元PU，例如，包括三种颜色的子像素单元PU(红色子像素单元R、绿色子 像素单元G、蓝色子像素单元B)，以实现彩色显示。需要说明的是，图1中仅示出了5行12列子像素单元PU，本公开的实施例包括但不限于此，子像素单元PU的个数可以根据实际情况进行设置。另外，对于子像素单元PU的颜色种类也不作限定。本公开的实施例提供的显示面板是以包括RGB三种子像素单元PU为例进行说明的，例如该显示面板为液晶显示(LCD)面板。
如图1所示，该显示面板为一种双栅线(Dual Gate)驱动显示面板，即一行子像素单元对应连接两条栅线，并且例如该一行中相邻的两个子像素单元分别连接到不同的栅线。例如，第一行子像素单元PU和栅线GL<1>以及栅线GL<2>连接，第二行子像素单元PU和栅线GL<3>以及栅线GL<4>连接，第三行子像素单元PU和栅线GL<5>以及栅线GL<6>连接，第四行子像素单元PU和栅线GL<7>以及栅线GL<8>连接，第五行子像素单元PU和栅线GL<9>以及栅线GL<10>连接。
如图1所示，该显示面板还包括用于传输数据信号的多条数据线DL(例如DL<n-1>、DL<n>、DL<n+1>等)。例如，在双栅线驱动显示面板中，该一行中彼此相邻且连接到不同栅线的两个子像素单元分别连接到同一条数据线。该多条数据线DL的走线形状均为锯齿形(Zigzag)，任意一条数据线DL连接的多个子像素单元PU接收的数据信号的极性相同。例如，该显示面板可以采用数据驱动电路通过数据线DL为子像素单元PU提供数据信号。
另外，如图1所示，该双栅线驱动显示面板采用2点极性切换的数据驱动方式，也就是说，在同一行子像素单元PU中，每相邻的两个子像素单元PU接收的数据信号的极性相同，在同一列子像素单元PU中，每相邻的两个子像素单元PU接收的数据信号的极性不同。
例如，图1中的显示面板可以采用栅极驱动电路进行驱动，图2A中示出了用于该栅极驱动电路包括的部分移位寄存器单元(第一移位寄存器单元SR1至第十六移位寄存器单元SR16)以及用于该栅极驱动电路的时钟信号(第一时钟信号CLK1至第十六时钟信号CLK16)，这些时钟信号例如由时序控制器(Timing Controller，图中未示出)通过相应时钟信号线提供。例如，如图2A所示，第一移位寄存器单元SR1接收第一时钟信号CLK1，第二移位寄存器单元SR2接收第二时钟信号CLK2，以此类推，第十六移位寄存器单元SR16接收第十六时钟信号CLK16。另外，第九移位寄存器单元SR9和第一移位寄存器单元SR1级联，第十移位寄存器单元SR10和第二移位寄存 器单元SR2级联，以此类推，第十六移位寄存器单元SR16和第八移位寄存器单元SR8级联。
需要说明的是，在本公开的实施例中，移位寄存器单元A和移位寄存器单元B级联表示：移位寄存器单元A的输出信号作为输入信号提供至移位寄存器B以触发移位寄存器B，或者，移位寄存器单元B的输出信号作为输入信号提供至移位寄存器A以触发移位寄存器A。以下各实施例与此相同，不再赘述。
图2B为一种示例性移位寄存器单元600的电路图，例如该移位寄存器单元600是栅极驱动电路的第n级。如图2B所示，该移位寄存器单元600包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和存储电容C1。
该移位寄存器单元600中的第一晶体管T1为该移位寄存器单元600的信号输出端的输出晶体管。例如，第一晶体管T1的第一极连接时钟信号CLK，第一晶体管T1的第二极连接第二晶体管T2的第一极以得到该移位寄存器单元600的输出端，并可输出扫描信号Gn，以及用于下一级移位寄存器单元600的输入信号。第一晶体管T1的栅极连接上拉节点PU，由此连接第三晶体管T3的第一极以及第四晶体管T4的第二极。
第二晶体管T2的第二极连接第三晶体管T3的第二极以及低电平信号VGL。第二晶体管T2的栅极连接第三晶体管T3的栅极以及下一行即第n+1行的移位寄存器单元600的输出端，以接收扫描信号G(n+1)以作为输出下拉控制信号。第二晶体管T2的第一极连接第一晶体管T1的第二极，因此可以在输出下拉控制信号的控制下导通，在无需输出扫描信号Gn时将输出端的输出信号下拉至低电平信号VGL。
第三晶体管T3的第一极也连接至上拉节点PU，由此与第四晶体管T4的第二极以及第一晶体管T1的栅极电连接。第三晶体管T3的第二极连接至低电平信号VGL。第三晶体管T3的栅极同样连接下一行即第n+1行的移位寄存器单元600的输出端，以接收扫描信号G(n+1)以作为复位控制信号(其同时也是输出下拉控制信号)，从而可以在该复位控制信号的控制下导通，将上拉节点PU复位至低电平信号VGL，从而关闭第一晶体管T1。
第四晶体管T4的第一极和自身栅极相连，并连接上一行即第n-1行的移位寄存器单元600的输出端以接收扫描信号G(n-1)以作为输入信号(以 及输入控制信号)，第四晶体管T4的第二极与上拉节点PU连接，从而在第四晶体管T4导通时可以对上拉节点PU充电，以使上拉节点PU的电压可以将第一晶体管T1导通，从而使时钟信号CLK通过输出端输出。存储电容C1的一端连接第一晶体管T1的栅极即上拉节点PU，另一端连接第一晶体管T1的第二极，从而可以存储上拉节点PU的电平，并且可以在第一晶体管T1导通以输出时通过自身的自举效应将上拉节点PU的电平继续上拉以提升输出性能。
由图2B所示的移位寄存器单元600级联构成的栅极驱动电路工作时，当扫描信号G(n-1)为高电平时，第四晶体管T4导通并对上拉节点PU充电，上拉节点PU升高的电平使得第一晶体管T1导通，因此时钟信号CLK可以通过第一晶体管T1在输出端输出，也即扫描信号Gn等于时钟信号CLK。当时钟信号CLK为高电平时，扫描信号Gn也输出高电平。当扫描信号Gn为高电平时，栅极驱动电路的移位寄存器单元600将该高电平信号Gn输入到对应行的栅线GL，以使该行栅线GL对应的所有的子像素单元中的薄膜晶体管的栅极被施加该信号，以使得这些薄膜晶体管均打开，数据信号通过每个子像素单元中的薄膜晶体管输入到对应的子像素单元的液晶电容，以对相应子像素单元内的液晶电容实施充电，从而实现对该子像素单元的信号电压写入并保持。当扫描信号G(n+1)为高电平时，第二晶体管T2和第三晶体管T3导通，达到复位上拉节点PU以及将输出端下拉的效果。因此，通过栅极驱动电路，例如可以实现逐行扫描驱动功能。
需要说明的是，在本公开的各实施例中，栅极驱动电路的移位寄存器单元的结构不局限于上面描述的结构，栅极驱动电路的移位寄存器单元可以为任意适用结构，也可以包括更多或更少的晶体管和/或电容，例如加入用于实现上拉节点控制、下拉节点控制、降噪等功能的子电路等，本公开的实施例对此不作限制。
图3示出了图2A中的时钟信号(第一时钟信号CLK1至第十六时钟信号CLK16)的时序关系。如图3所示，该第一时钟信号CLK1至第十六时钟信号CLK16的占空比(即高电平持续的时间与周期的比值)和周期均分别相等。该十六个时钟信号处于高电平的时间覆盖了全部的时间范围，所以该十六个子时钟信号正好可以组成一个循环组。
另外，如图3所示，可以将任意相邻的两个时钟信号在时序上错开的时 间定义为一个时间单元TU，则该时钟信号的周期为16*TU。基于时间单元TU的定义，则两个时钟信号时序相邻即表示该两个时钟信号在时序上错开一个时间单元TU。以下各实施例关于时间单元TU以及时序相邻的描述均与此相同，不再赘述。
例如，显示面板在完成制作工艺后需要进行检测。例如，让整个显示面板显示同一种颜色，例如，红色、绿色或蓝色等。
例如，如图1所示，数据线DL<n-1>连接的子像素单元PU的顺序为R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G。假设需要使得红色子像素单元R全部点亮，则数据线DL<n-1>需要提供的数据信号的极性的顺序为+-+-+-+-+-+-+-+-(红色子像素单元R需要点亮对应极性+，其它颜色对应极性-)，则提供的数据信号的极性翻转(极性从+变为-或者从-变为+均称为极性翻转)次数为16次；又例如，数据线DL<n>连接的子像素单元PU的顺序为R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G。假设需要使得红色子像素单元R全部点亮，则数据线DL<n>需要提供的数据信号的极性的顺序为+---+---+---+---(红色子像素单元R需要点亮对应极性+，其它颜色对应极性-)，则提供的数据信号的极性翻转次数为8次；又例如，数据线DL<n+1>连接的子像素单元PU的顺序为B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B。假设需要使得红色子像素单元R全部点亮，则数据线DL<n+1>需要提供的数据信号的极性的顺序为--+---+---+---+-(红色子像素单元R需要点亮对应极性+，其它颜色对应极性-)，则提供的数据信号的极性翻转次数为8次。
由上述可知，当图1所示的显示面板在显示红色时，数据驱动电路提供数据信号时需要切换的次数较多，这样会增大该显示面板的功耗。
为了减少上述数据驱动电路提供数据信号时的极性翻转次数，发明人想到可以使得和同一条数据线DL连接的同一种颜色的子像素单元在时序上连续显示，这样就可以降低上述极性翻转次数，从而降低显示面板的功耗。
由上述可知，和同一条数据线DL连接的子像素单元PU在排列上是四个一个周期。例如，对于和数据线DL<n-1>连接的子像素单元PU，可以使得各个子像素单元PU的点亮顺序为R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G，在该情形中，数据驱动电路提供数据信号时的极性翻转次数为2次。又例如，对于和数据线 DL<n>连接的子像素单元PU，可以使得各个子像素单元PU的点亮顺序为B->B->B->B->R->R->R->R->G->G->G->G->B->B->B->B，在该情形中，数据驱动电路提供数据信号时的极性翻转次数为3次；又例如，对于和数据线DL<n+1>连接的子像素单元PU，可以使得各个子像素单元PU的点亮顺序为R->R->R->R->B->B->B->B->G->G->G->G->G->G->G->G，在该情形中，数据驱动电路提供数据信号时的极性翻转次数为2次。因此，可以大幅度减少极性翻转次数，从而降低该显示面板的功耗。
为了使得图1所示的显示面板按照上述顺序点亮子像素单元PU，如图4所示，移位寄存器单元(SR)和栅线(GL)之间的连接关系是交错的，这样会增加设计难度，从而可能会造成工艺不良，产品良率低等问题。
本公开至少一实施例提供一种显示面板，包括显示区域和周边区域。显示区域包括具有多行、多列子像素单元的子像素单元阵列，在周边区域中设置有栅极驱动电路，显示区域还包括多条栅线和多条数据线，用于驱动子像素单元阵列，每个子像素单元由一条栅线提供的扫描信号和一条数据线提供的数据信号驱动显示，且同一条数据线连接至少两个彼此不相邻的相同颜色的子像素单元；栅极驱动电路包括多个依次布置的移位寄存器单元，多条栅线依次排列且与多个依次布置的移位寄存器单元依序一一对应电连接；栅极驱动电路被配置为接收时钟信号并产生扫描信号，以使得和同一条数据线连接的至少两个彼此不相邻的相同颜色的子像素单元在时序上连续显示。
本公开至少一实施例还提供对应于上述显示面板的显示装置以及驱动方法。
本公开的一些实施例提供的显示面板、显示装置以及驱动方法，可以避免栅极驱动电路和栅线之前由于采用交错布线而带来的工艺不良以及产品良率低问题，同时还可以降低功耗。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开的至少一实施例提供一种显示面板10，如图5所示，该显示面板10包括显示区域DR和周边区域PR。
显示区域DR包括具有多行、多列子像素单元PU的子像素单元阵列100。需要说明的是，图5中仅示意性地示出了5行12列子像素单元PU，本公开的实施例包括但不限于此，显示面板10包括的子像素单元PU的个数可以根据需要进行设置。例如，图5中所示的子像素单元阵列100的排布方式可以 采用图1中所示的排布方式。
在周边区域PR中设置有栅极驱动电路200，显示区域DR还包括多条栅线GL(例如，GL<1>、GL<2>等)和多条数据线DL(例如，DL<1>、DL<2>、DL<3>等)，用于驱动子像素单元阵列100，每个子像素单元PU由一条栅线GL提供的扫描信号和一条数据线DL提供的数据信号驱动显示，且同一条数据线DL连接至少两个彼此不相邻的相同颜色的子像素单元PU。例如，数据线DL<1>连接的子像素单元PU的顺序(在图中为从上至下、从右至左，以下相同)为R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G，数据线DL<2>连接的子像素单元PU的顺序为R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G，数据线DL<3>连接的子像素单元PU的顺序为B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B。
需要说明的是，在图5所示的实施例中，在每一条数据线DL连接的多个子像素单元PU中，任意一种相同颜色的子像素单元PU都不相邻，本公开的实施例包括但不限于此，例如，还可以仅使得一种颜色的子像素单元PU不相邻而其它两种颜色的子像素单元PU相邻；又例如，还可以仅使得两种颜色的子像素单元PU不相邻而其它一种颜色的子像素单元PU相邻。
栅极驱动电路200包括多个依次布置的移位寄存器单元S1至S10，多条栅线GL依次排列且与多个依次布置的移位寄存器单元(S1至S10等)依序一一对应电连接。如图5所示，该显示面板10中的栅极驱动电路200中的多个移位寄存器单元和多条栅线GL连接时不存在交错布线，从而可以避免栅极驱动电路200和栅线GL之前由于采用交错布线而带来的工艺不良以及产品良率低问题。需要说明的是，图5中仅示意性地示出了栅极驱动电路200中的10个移位寄存器单元，本公开的实施例包括但不限于此，栅极驱动电路200包括的移位寄存器单元的个数可以根据需要进行设置，例如，在采用双栅线驱动显示面板中，可以将移位寄存器单元的个数设置为子像素单元PU的行数的两倍。
例如，栅极驱动电路200被配置为接收时钟信号并产生扫描信号，以使得和同一条数据线DL连接的至少两个彼此不相邻的相同颜色的子像素单元PU在时序上连续显示。例如，在栅极驱动电路200提供的扫描信号的驱动下，数据线DL<1>连接的子像素单元PU的显示顺序可以为 R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G，数据线DL<2>连接的子像素单元PU的显示顺序可以为B->B->B->B->R->R->R->R->G->G->G->G->B->B->B->B，数据线DL<3>连接的子像素单元PU的显示顺序可以为R->R->R->R->B->B->B->B->G->G->G->G->G->G->G->G。也就是说，在栅极驱动电路200提供的扫描信号的驱动下，在和任意一条数据线DL连接的多个子像素单元PU中，相同颜色的子像素单元PU在时序上连续显示。
在本公开的实施例提供的显示面板10中，通过栅极驱动电路200对显示区域DR中的子像素单元阵列100进行驱动，以使得和同一条数据线DL连接的至少两个彼此不相邻的相同颜色的子像素单元PU在时序上连续显示，例如，使得和同一条数据线DL连接的所有彼此不相邻的相同颜色的子像素单元PU在时序上连续显示。采用这种方式，可以降低提供给子像素单元阵列100的数据信号的极性翻转次数，从而可以降低该显示面板10的功耗。例如，可以采用数据驱动电路向子像素单元阵列100提供数据信号。
例如，在本公开的一些实施例中，和同一条数据线DL依次连接的多个子像素单元PU被驱动时被划分为G个驱动组，时钟信号的个数为H，每个驱动组包括F个子像素单元，F＝[H/G]，[H/G]表示对H/G取整。则栅极驱动电路200还被配置为使得第B个驱动组中的F个子像素单元PU被驱动的顺序为：A d＝B+(d-1)*G，A d表示第d次被驱动的子像素单元PU的顺序序号，B为小于等于G的正整数，d为小于等于F的正整数。
例如，和同一条数据线DL依次连接的多个子像素单元PU至少包括第一颜色和第二颜色，在和同一条数据线DL依次连接的多个子像素单元PU中，第一颜色的子像素单元PU的最小排布周期为G1，第二颜色的子像素单元PU的最小排布周期为G2，则G为G1和G2的最小公倍数。
例如，如图5所示，下面以和数据线DL<1>连接的子像素单元PU为例进行说明。和数据线DL<1>连接的子像素单元PU的顺序为R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G；例如，第一颜色为红色，第二颜色为绿色，则第一颜色的子像素单元PU的最小排布周期为2，即G1为2，第二颜色的子像素单元PU的最小排布周期为4，即G2为4，则取G1和G2的最小公倍数为4，即G＝4。需要说明的是，因为蓝色的子像素单元PU的排布周期也为4，所以这里是以两个颜色为例进行说明，但当 三个颜色的排布周期均各不相同时，G的取值为三个颜色的子像素单元PU各自的排布周期的最小公倍数。
例如，在一些实施例中，栅极驱动电路接收的时钟信号的个数为16，即H＝16，所以每个驱动组包括的子像素单元的个数F＝[H/G]＝4。则在第1个驱动组中(B＝1)，第1次(d＝1)被驱动的子像素单元PU的顺序序号A 1＝1+(1-1)*4＝1，第2次(d＝2)被驱动的子像素单元PU的顺序序号A 2＝1+(2-1)*4＝5，第3次(d＝3)被驱动的子像素单元PU的顺序序号A 3＝1+(3-1)*4＝9，第4次(d＝4)被驱动的子像素单元PU的顺序序号A 4＝1+(4-1)*4＝13；类似地，在第2个驱动组中，依次被驱动的子像素单元PU的顺序序号为2、6、10、14；在第3个驱动组中，依次被驱动的子像素单元PU的顺序序号为3、7、11、15；在第4个驱动组中，依次被驱动的子像素单元PU的顺序序号为4、8、12、16。
需要说明的是，本公开的实施例对上述各个驱动组之间的顺序不作限定，例如，在一些实施例中，栅极驱动电路200被配置为使得各个驱动组被驱动的顺序为：第1驱动组、第3驱动组、第2驱动组、第4驱动组。也就是说，对于和同一条数据线连接的16个子像素单元PU来说，它们被驱动的顺序依次为：1、5、9、13、3、7、11、15、2、6、10、14、4、8、12、16。下面对图5中所示的栅极驱动电路200作进一步说明。
例如，如图6所示，多个移位寄存器单元PU被划分为至少一个移位寄存器单元扫描组210，每个移位寄存器单元扫描组210包括多个由相邻且级联的移位寄存器单元PU构成的移位寄存器单元组220，且相邻的两个移位寄存器单元组220之间不级联。例如，如图6所示，每一个移位寄存器单元组220中包括m个相邻且级联的移位寄存器单元PU，m为大于等于2的整数。
需要说明的是，为了示意清楚，图6中仅示意性地示出了栅极驱动电路200包括的一个移位寄存器单元扫描组210，本公开的实施例包括但不限于此，本公开的实施例中的栅极驱动电路200包括的移位寄存器单元扫描组210的个数可以根据需要进行设置。
在本公开的一些实施例中，例如，如图7所示，每个移位寄存器单元扫描组210包括16个移位寄存器单元(S<1>至S<16>)，在每个移位寄存器单元扫描组210中，第k+1个移位寄存器单元和第k个移位寄存器单元级联以 构成一个移位寄存器单元组220，且第k+1个移位寄存器单元和第k+2个移位寄存器单元不级联，k为1、3、5、7、9、11、13、15。
例如，如图7所示，第2个移位寄存器单元S<2>和第1个移位寄存器单元S<1>级联构成一个移位寄存器单元组220，且第2个移位寄存器单元S<2>和第3个移位寄存器单元S<3>不级联；第4个移位寄存器单元S<4>和第3个移位寄存器单元S<3>级联构成一个移位寄存器单元组220，且第4个移位寄存器单元S<4>和第5个移位寄存器单元S<5>不级联；第6个移位寄存器单元S<6>和第5个移位寄存器单元S<5>级联构成一个移位寄存器单元组220，且第6个移位寄存器单元S<6>和第7个移位寄存器单元S<7>不级联；第8个移位寄存器单元S<8>和第7个移位寄存器单元S<7>级联构成一个移位寄存器单元组220，且第8个移位寄存器单元S<8>和第9个移位寄存器单元S<9>不级联；第10个移位寄存器单元S<10>和第9个移位寄存器单元S<9>级联构成一个移位寄存器单元组220，且第10个移位寄存器单元S<10>和第11个移位寄存器单元S<11>不级联；第12个移位寄存器单元S<12>和第11个移位寄存器单元S<11>级联构成一个移位寄存器单元组220，且第12个移位寄存器单元S<12>和第13个移位寄存器单元S<13>不级联；第14个移位寄存器单元S<14>和第13个移位寄存器单元S<13>级联构成一个移位寄存器单元组220，且第14个移位寄存器单元S<14>和第15个移位寄存器单元S<15>不级联；第16个移位寄存器单元S<16>和第15个移位寄存器单元S<15>级联构成一个移位寄存器单元组220。
下面结合图8描述当栅极驱动电路200包括多个移位寄存器单元扫描组210时，该多个移位寄存器单元扫描组210之间实现级联。
在本公开的一些实施例中，例如，如图8所示，栅极驱动电路200包括多个移位寄存器单元扫描组210，需要说明的是，为了清楚地示意，图8仅示出了栅极驱动电路200包括的两个移位寄存器单元扫描组210，例如分别表示为210<1>和210<2>，在该相邻的两个移位寄存器单元扫描组210中，一个移位寄存器单元扫描组210<2>中的第k个移位寄存器单元和另一个移位寄存器单元扫描组210<1>中的第k+1个移位寄存器单元连接，k为1、3、5、7、9、11、13、15。另外，需要说明的是，图8所示的两个移位寄存器单元扫描组210之间的相对位置关系不代表真实的位置关系，这里仅是为了便于描述，所以将移位寄存器单元扫描组210<2>绘制在了移位寄存器单元扫描 组210<1>的右侧。
例如，如图8所示，移位寄存器单元扫描组210<2>中的第1个移位寄存器单元S<1>和移位寄存器单元扫描组210<1>中的第2个移位寄存器单元S<2>连接；移位寄存器单元扫描组210<2>中的第3个移位寄存器单元S<3>和移位寄存器单元扫描组210<1>中的第4个移位寄存器单元S<4>连接；移位寄存器单元扫描组210<2>中的第5个移位寄存器单元S<5>和移位寄存器单元扫描组210<1>中的第6个移位寄存器单元S<6>连接；移位寄存器单元扫描组210<2>中的第7个移位寄存器单元S<7>和移位寄存器单元扫描组210<1>中的第8个移位寄存器单元S<8>连接；移位寄存器单元扫描组210<2>中的第9个移位寄存器单元S<9>和移位寄存器单元扫描组210<1>中的第10个移位寄存器单元S<10>连接；移位寄存器单元扫描组210<2>中的第11个移位寄存器单元S<11>和移位寄存器单元扫描组210<1>中的第12个移位寄存器单元S<12>连接；移位寄存器单元扫描组210<2>中的第13个移位寄存器单元S<13>和移位寄存器单元扫描组210<14>中的第2个移位寄存器单元S<14>连接；移位寄存器单元扫描组210<2>中的第15个移位寄存器单元S<15>和移位寄存器单元扫描组210<1>中的第16个移位寄存器单元S<16>连接。
在一些实施例提供的显示面板10中，如图9所示，每个移位寄存器单元扫描组210中的16个移位寄存器单元(S<1>至S<16>)接收的时钟信号分别为第一时钟信号CK1至第十六时钟信号CK16，且该十六个时钟信号的周期以及占空比均相等。
例如，图10示出了一种用于本公开的实施例提供的显示面板10的时钟信号的信号时序图。如图10所示，第一时钟信号CK1至第十六时钟信号CK16由时序控制器提供，它们的周期以及占空比均相等。例如，每一个时钟信号的周期为16个时间单元TU，即16TU，而每一个时钟信号中处于高电平的时间与周期的比值为7.2/16，即每一个时钟信号的占空比为9/20。需要说明的是，图10所示的占空比仅是示意性的，本公开的实施例中的时钟信号还可以采用其它占空比。例如，可以使得时钟信号中处于低电平的时间略长于处于高电平的时间。
例如，如图10所示，第一时钟信号CK1、第五时钟信号CK5、第九时钟信号CK9、第十三时钟信号CK13、第三时钟信号CK3、第七时钟信号CK7、第十一时钟信号CK11以及第十五时钟信号CK15在时序上彼此相邻。
第二时钟信号CK2、第六时钟信号CK6、第十时钟信号CK10、第十四时钟信号CK14、第四时钟信号CK4、第八时钟信号CK8、第十二时钟信号CK12以及第十六时钟信号CK16在时序上彼此相邻。第一时钟信号CK1和第二时钟信号CK2在时序上相差8个时间单元TU。
也就是说，第一时钟信号CK1至第十六时钟信号CK16是按照以下的顺序提供至栅极驱动电路200：CK1->CK5->CK9->CK13->CK3->CK7->CK11->CK15->CK2->CK6->CK10->CK14->CK4->CK8->CK12->CK16。例如，可以将上述提供时钟信号的顺序以程序代码(算法)的形式存储在时序控制器(Timing Controller)或显示面板10的其它器件中，在需要时直接执行该程序代码即可产生需要的时钟信号。
在一些实施例提供的显示面板10中，例如，如图11所示，子像素单元阵列100被划分为至少一个子像素单元扫描组110，至少一个子像素单元扫描组110和至少一个移位寄存器单元扫描组210一一对应。例如，图11中分别示出了两个子像素单元扫描组110和对应的两个移位寄存器单元扫描组210，但本公开的实施例包括但不限于此，本公开的实施例中的子像素单元扫描组110的个数可以根据需要进行设定。
例如，在一些实施例提供的显示面板10中，如图12所示，每个移位寄存器单元扫描组110包括16个移位寄存器单元(S<1>至S<16>)，每个子像素单元扫描组110包括彼此相邻的8行子像素单元，例如第一行子像素单元PUL<1>至第八行子像素单元PUL<8>。
例如，在每个子像素单元扫描组110中，第q行子像素单元和该子像素单元扫描组110对应的移位寄存器单元扫描组210中的第2q-1个移位寄存器单元以及第2q个移位寄存器单元电连接，q为大于等于1且小于等于8的整数。例如，如图12所示，第一行子像素单元PUL<1>和第一个移位寄存器单元S<1>以及第二个移位寄存器单元S<2>电连接；第二行子像素单元PUL<2>和第三个移位寄存器单元S<3>以及第四个移位寄存器单元S<4>电连接；第三行子像素单元PUL<3>和第五个移位寄存器单元S<5>以及第六个移位寄存器单元S<6>电连接；第四行子像素单元PUL<4>和第七个移位寄存器单元S<7>以及第八个移位寄存器单元S<8>电连接；第五行子像素单元PUL<5>和第九个移位寄存器单元S<9>以及第十个移位寄存器单元S<10>电连接；第六行子像素单元PUL<6>和第十一个移位寄存器单元S<11>以及第 十二个移位寄存器单元S<12>电连接；第七行子像素单元PUL<7>和第十三个移位寄存器单元S<13>以及第十四个移位寄存器单元S<14>电连接；第八行子像素单元PUL<8>和第十五个移位寄存器单元S<15>以及第十六个移位寄存器单元S<16>电连接。
例如，移位寄存器单元可以通过栅线和对应的子像素单元行实现电连接。例如，如图12所示，在每一行子像素单元两侧分别设置一条栅线GL，且该行子像素单元和设置在两侧的两条栅线GL连接。例如，图13中示出了一种栅线GL、移位寄存器单元以及对应的子像素单元之间的连接方式。
在一些实施例提供的显示面板10中，如图13所示，所述显示面板10包括设置在周边区域PR中的栅极驱动电路200，并且还包括设置在周边区域PR中的数据驱动电路300。栅极驱动电路200和多条栅线连接，且还通过时钟信号线与时序控制器400连接以接收时钟信号；该数据驱动电路300和多条数据线DL连接，且数据驱动电路300被配置为采用2点极性切换的方式向子像素单元阵列100提供数据信号。关于2点极性切换可以参考图1中相应的描述，这里不再赘述。
例如，如图13所示，多条数据线DL中的任一一条数据线DL提供的数据信号的极性相同，且该条数据线DL的走线形状为锯齿形(Zigzag)。
下面结合图10所示的信号时序图对图13所示的显示面板10的工作原理进行描述。下面以和数据线DL<1>连接的子像素单元PU为例进行说明。
由于第一时钟信号CK1在时序上最靠前，所以第一个移位寄存器单元S<1>通过栅线GL<1>提供扫描信号，同时数据驱动电路300通过数据线DL<1>提供数据信号，所以和数据线DL<1>连接的一个红色子像素单元R在扫描信号以及数据信号的驱动下进行显示。
然后，由于第五时钟信号CK5在时序上和第一时钟信号CK1相邻，所以第五个移位寄存器单元S<5>通过栅线GL<5>提供扫描信号，同时数据驱动电路300通过数据线DL<1>提供数据信号，所以和数据线DL<1>连接的另一个红色子像素单元R在扫描信号以及数据信号的驱动下进行显示。
然后，由于第九时钟信号CK9在时序上和第五时钟信号CK5相邻，所以第九个移位寄存器单元S<9>通过栅线GL<9>提供扫描信号，同时数据驱动电路300通过数据线DL<1>提供数据信号，所以和数据线DL<1>连接的另一个红色子像素单元R在扫描信号以及数据信号的驱动下进行显示。
然后，由于第十三时钟信号CK13在时序上和第九时钟信号CK9相邻，所以第十三个移位寄存器单元S<13>通过栅线GL<13>提供扫描信号(图13中未示出S<13>和栅线GL<13>)，同时数据驱动电路300通过数据线DL<1>提供数据信号，所以和数据线DL<1>连接的另一个红色子像素单元R在扫描信号以及数据信号的驱动下进行显示。
以此类推，栅极驱动电路200按照接收到的时钟信号的时序向子像素单元阵列100提供扫描信号，数据驱动电路300通过数据线DL<1>向被开启的子像素单元PU提供数据信号，从而使得和数据线DL<1>连接的子像素单元PU按照以下的顺序进行显示：R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G，从而使得在和数据线DL<1>连接的多个子像素单元PU中，相同颜色的子像素单元PU在时序上连续显示，从而可以降低提供给子像素单元阵列100的数据信号的极性翻转次数，从而可以降低该显示面板10的功耗。
在一些实施例提供的显示面板10中，如图14所示，在每一个移位寄存器单元扫描组210中，第L个移位寄存器单元设置在显示区域DR的第一侧，第R个移位寄存器单元设置在显示区域DR的第二侧，第二侧与第一侧相对，L为1、2、3、4、9、10、11、12；R为5、6、7、8、13、14、15、16。例如，第一侧为显示区域DR的左侧，第二侧为显示区域DR的右侧；或者，第一侧为显示区域DR的右侧，第二侧为显示区域DR的左侧。也就是说，本公开的实施例提供的显示面板10中的栅极驱动电路200中的移位寄存器单元可以分别设置显示区域DR的两侧。
又例如，在另一些实施例提供的显示面板10中，显示面板10中的栅极驱动电路200中的移位寄存器单元也可以全部设置在显示区域DR的一侧。
相对于将栅极驱动电路200中的移位寄存器单元都设置在显示区域DR的一侧，将栅极驱动电路200中的移位寄存器单元分别设置在显示区域DR的两侧可以更好地减小该显示面板的边框尺寸，更易于实现窄边框。
本公开的至少一实施例还提供一种显示装置1，如图15所示，该显示装置1包括本公开的实施例提供的任一显示面板10。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于显示面板10中的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种显示面板的驱动方法，例如，该驱动方法可以用于本公开的实施例提供的任一显示面板10，该驱动方法包括：向栅极驱动电路200提供时钟信号使得栅极驱动电路200产生扫描信号，以使得和同一条数据线DL连接的至少两个彼此不相邻的相同颜色的子像素单元PU在时序上连续显示。
在本公开的一些实施例提供的驱动方法中，例如，和同一条数据线DL依次连接的多个子像素单元PU被驱动时被划分为G个驱动组，时钟信号的个数为H，每个驱动组包括F个子像素单元，F＝[H/G]，[H/G]表示对H/G取整，驱动方法还包括按照如下顺序对第B个驱动组中的F个子像素单元PU进行驱动：A d＝B+(d-1)*G，A d表示第d次被驱动的子像素单元的顺序序号，B为小于等于G的正整数，d为小于等于F的正整数。
在本公开的一些实施例提供的驱动方法中，例如，和同一条数据线DL依次连接的多个子像素单元PU至少包括第一颜色和第二颜色，在和同一条数据线DL依次连接的多个子像素单元PU中，第一颜色的子像素单元PU的最小排布周期为G1，第二颜色的子像素单元PU的最小排布周期为G2，驱动方法还包括：将G1和G2的最小公倍数作为G。
在本公开的一些实施例提供的驱动方法中，例如，G＝4，H＝16，驱动方法还包括按照如下顺序序号对和同一条数据线依次连接的16个子像素单元进行驱动：1、5、9、13、3、7、11、15、2、6、10、14、4、8、12、16。
本公开的至少一实施例还提供一种显示面板的驱动方法，例如，该显示面板10的子像素单元阵列100被划分为至少一个子像素单元扫描组110，至少一个子像素单元扫描组110和至少一个移位寄存器单元扫描组210一一对应，且每个子像素单元扫描组110中包括彼此相邻的8行子像素单元PU。
对于每一个移位寄存器单元扫描组210以及对应的子像素单元扫描组110来说，该驱动方法包括以下操作步骤。
使得移位寄存器单元扫描组210向该移位寄存器单元扫描组210对应连接的子像素单元扫描组110提供扫描信号，以使得该子像素单元扫描组110按照如下的顺序进行扫描显示：
第1行、第3行、第5行、第7行、第2行、第4行、第6行、第8行、 第1行、第3行、第5行、第7行、第2行、第4行、第6行、第8行。
需要说明的是，关于上述驱动方法的详细描述以及技术效果可以参考上述关于显示面板10的相应描述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括显示区域和周边区域，其中，
    所述显示区域包括具有多行、多列子像素单元的子像素单元阵列，在所述周边区域中设置有栅极驱动电路，
    所述显示区域还包括多条栅线和多条数据线，用于驱动所述子像素单元阵列，每个子像素单元由一条栅线提供的扫描信号和一条数据线提供的数据信号驱动显示，且同一条数据线连接至少两个彼此不相邻的相同颜色的子像素单元；
    所述栅极驱动电路包括多个依次布置的移位寄存器单元，所述多条栅线依次排列且与所述多个依次布置的移位寄存器单元依序一一对应电连接；
    所述栅极驱动电路被配置为接收时钟信号并产生所述扫描信号，以使得和同一条数据线连接的所述至少两个彼此不相邻的相同颜色的子像素单元在时序上连续显示。
  2. 根据权利要求1所述的显示面板，其中，
    和同一条数据线依次连接的多个子像素单元被驱动时被划分为G个驱动组，所述时钟信号的个数为H，每个所述驱动组包括F个子像素单元，F＝[H/G]，[H/G]表示对H/G取整；
    所述栅极驱动电路还被配置为使得第B个驱动组中的F个子像素单元被驱动的顺序为：
    A d＝B+(d-1)*G，其中，A d表示第d次被驱动的子像素单元的顺序序号，B为小于等于G的正整数，d为小于等于F的正整数。
  3. 根据权利要求2所述的显示面板，其中，
    所述和同一条数据线依次连接的多个子像素单元至少包括第一颜色和第二颜色，
    在所述和同一条数据线依次连接的多个子像素单元中，所述第一颜色的子像素单元的最小排布周期为G1，所述第二颜色的子像素单元的最小排布周期为G2，则G为G1和G2的最小公倍数。
  4. 根据权利要求1-3任一项所述的显示面板，其中，
    所述多个移位寄存器单元被划分为至少一个移位寄存器单元扫描组，每个所述移位寄存器单元扫描组包括多个由相邻且级联的移位寄存器单元构 成的移位寄存器单元组，且相邻的两个移位寄存器单元组之间不级联。
  5. 根据权利要求4所述的显示面板，其中，每个所述移位寄存器单元扫描组包括16个移位寄存器单元，在每个所述移位寄存器单元扫描组中，第k+1个移位寄存器单元和第k个移位寄存器单元级联以构成一个所述移位寄存器单元组，且第k+1个移位寄存器单元和第k+2个移位寄存器单元不级联，k为1、3、5、7、9、11、13、15。
  6. 根据权利要求5所述的显示面板，其中，所述栅极驱动电路包括多个移位寄存器单元扫描组，其中，
    在相邻的两个移位寄存器单元扫描组中，一个移位寄存器单元扫描组中的第k个移位寄存器单元和另一个移位寄存器单元扫描组中的第k+1个移位寄存器单元连接，k为1、3、5、7、9、11、13、15。
  7. 根据权利要求5所述的显示面板，其中，每个所述移位寄存器单元扫描组中的16个移位寄存器单元接收的所述时钟信号分别为第一时钟信号至第十六时钟信号，且该十六个时钟信号的周期以及占空比均相等。
  8. 根据权利要求7所述的显示面板，其中，所述周期为16个时间单元，且所述第一时钟信号、第五时钟信号、第九时钟信号、第十三时钟信号、第三时钟信号、第七时钟信号、第十一时钟信号以及第十五时钟信号在时序上彼此相邻；
    所述第二时钟信号、所述第六时钟信号、所述第十时钟信号、所述第十四时钟信号、所述第四时钟信号、所述第八时钟信号、所述第十二时钟信号以及所述第十六时钟信号在时序上彼此相邻；
    所述第一时钟信号和所述第二时钟信号在时序上相差8个时间单元。
  9. 根据权利要求7或8所述的显示面板，其中，所述占空比为9/20。
  10. 根据权利要求2所述的显示面板，其中，
    所述子像素单元阵列被划分为至少一个子像素单元扫描组，所述至少一个子像素单元扫描组和所述至少一个移位寄存器单元扫描组一一对应。
  11. 根据权利要求10所述的显示面板，其中，每个所述移位寄存器单元扫描组包括16个移位寄存器单元，
    每个所述子像素单元扫描组包括彼此相邻的8行子像素单元；
    其中，在每个所述子像素单元扫描组中，第q行子像素单元和该子像素单元扫描组对应的移位寄存器单元扫描组中的第2q-1个移位寄存器单元以 及第2q个移位寄存器单元电连接，q为大于等于1且小于等于8的整数。
  12. 根据权利要求11所述的显示面板，其中，在每一行子像素单元两侧分别设置一条栅线，且该行子像素单元和设置在两侧的两条栅线连接。
  13. 根据权利要求1-12任一项所述的显示面板，其中，
    所述显示面板还包括设置在所述周边区域中的数据驱动电路，其中，所述数据驱动电路和所述多条数据线连接，且所述数据驱动电路被配置为采用2点极性切换的方式向所述子像素单元阵列提供所述数据信号。
  14. 根据权利要求13所述的显示面板，其中，所述多条数据线中的任意一条数据线提供的数据信号的极性相同，且该条数据线的走线形状为锯齿形。
  15. 根据权利要求4-14任一项所述的显示面板，其中，在每一个移位寄存器单元扫描组中，第L个移位寄存器单元设置在所述显示区域的第一侧，第R个移位寄存器单元设置在所述显示区域的第二侧，所述第二侧与所述第一侧相对，
    其中，L为1、2、3、4、9、10、11、12；R为5、6、7、8、13、14、15、16。
  16. 一种显示装置，包括如权利要求1-15任一项所述的显示面板。
  17. 一种如权利要求1-15任一项所述的显示面板的驱动方法，包括：
    向所述栅极驱动电路提供所述时钟信号使得所述栅极驱动电路产生所述扫描信号，
    以使得和同一条数据线连接的所述至少两个彼此不相邻的相同颜色的子像素单元在时序上连续显示。
  18. 根据权利要求17所述的驱动方法，其中，和同一条数据线依次连接的多个子像素单元被驱动时被划分为G个驱动组，所述时钟信号的个数为H，每个所述驱动组包括F个子像素单元，F＝[H/G]，[H/G]表示对H/G取整，
    所述驱动方法还包括按照如下顺序对第B个驱动组中的F个子像素单元进行驱动：
    A d＝B+(d-1)*G，其中，A d表示第d次被驱动的子像素单元的顺序序号，B为小于等于G的正整数，d为小于等于F的正整数。
  19. 根据权利要求18所述的驱动方法，其中，所述和同一条数据线依次连接的多个子像素单元至少包括第一颜色和第二颜色，
    在所述和同一条数据线依次连接的多个子像素单元中，所述第一颜色的 子像素单元的最小排布周期为G1，所述第二颜色的子像素单元的最小排布周期为G2，
    所述驱动方法还包括：将G1和G2的最小公倍数作为G。
  20. 根据权利要求18或19所述的驱动方法，其中，G＝4，H＝16，所述驱动方法还包括按照如下顺序序号对所述和同一条数据线依次连接的多个子像素单元进行驱动：
    1、5、9、13、3、7、11、15、2、6、10、14、4、8、12、16。
PCT/CN2019/098700 2019-07-31 2019-07-31 显示面板、显示装置以及驱动方法 WO2021016942A1 (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN201980001200.XA CN112673417B (zh) 2019-07-31 2019-07-31 显示面板、显示装置以及驱动方法
US16/957,575 US11715401B2 (en) 2019-07-31 2019-07-31 Display panel, display device and driving method
CN202211093675.6A CN115938322A (zh) 2019-07-31 2019-07-31 显示面板、显示装置以及驱动方法
PCT/CN2019/098700 WO2021016942A1 (zh) 2019-07-31 2019-07-31 显示面板、显示装置以及驱动方法
EP19933196.8A EP4006892A4 (en) 2019-07-31 2019-07-31 DISPLAY BOARD, DISPLAY DEVICE AND DRIVE METHOD
US18/137,010 US11948489B2 (en) 2019-07-31 2023-04-20 Display panel, display device and driving method
US18/590,339 US20240212550A1 (en) 2019-07-31 2024-02-28 Display panel, display device and driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/098700 WO2021016942A1 (zh) 2019-07-31 2019-07-31 显示面板、显示装置以及驱动方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/957,575 A-371-Of-International US11715401B2 (en) 2019-07-31 2019-07-31 Display panel, display device and driving method
US18/137,010 Continuation US11948489B2 (en) 2019-07-31 2023-04-20 Display panel, display device and driving method

Publications (1)

Publication Number Publication Date
WO2021016942A1 true WO2021016942A1 (zh) 2021-02-04

Family

ID=74228516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/098700 WO2021016942A1 (zh) 2019-07-31 2019-07-31 显示面板、显示装置以及驱动方法

Country Status (4)

Country Link
US (3) US11715401B2 (zh)
EP (1) EP4006892A4 (zh)
CN (2) CN112673417B (zh)
WO (1) WO2021016942A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021102909A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 显示装置及其驱动方法
CN115206244B (zh) * 2021-04-09 2023-11-17 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN113257130B (zh) * 2021-05-17 2022-07-12 武汉华星光电技术有限公司 一种显示区集成栅极驱动电路的显示面板
CN113470559B (zh) * 2021-06-29 2024-03-19 厦门天马微电子有限公司 驱动电路、驱动方法、显示面板及装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004264476A (ja) * 2003-02-28 2004-09-24 Sharp Corp 表示装置およびその駆動方法
US20150109347A1 (en) * 2013-10-18 2015-04-23 Au Optronics Corporation Charge-sharing controlling method and display panel
CN105845066A (zh) * 2016-05-30 2016-08-10 深圳市华星光电技术有限公司 显示面板的驱动方法
WO2016188257A1 (zh) * 2015-05-22 2016-12-01 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN109817150A (zh) * 2019-03-28 2019-05-28 京东方科技集团股份有限公司 一种像素驱动方法、像素驱动装置及显示装置
CN110379390A (zh) * 2019-07-01 2019-10-25 武汉天马微电子有限公司 一种显示面板、其驱动方法及显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5774911B2 (ja) * 2011-06-01 2015-09-09 株式会社ジャパンディスプレイ 表示装置
CN103514846A (zh) * 2012-06-29 2014-01-15 北京京东方光电科技有限公司 一种液晶显示器及其驱动方法
CN103474044B (zh) * 2013-09-29 2016-01-27 北京京东方光电科技有限公司 一种栅极驱动电路、阵列基板、显示装置以及驱动方法
KR102114155B1 (ko) * 2013-10-01 2020-05-25 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR102202128B1 (ko) * 2014-01-08 2021-01-14 삼성디스플레이 주식회사 액정표시장치와 그 구동방법
TWI537928B (zh) * 2014-01-27 2016-06-11 友達光電股份有限公司 顯示面板及其驅動方法
CN104200786A (zh) * 2014-07-31 2014-12-10 京东方科技集团股份有限公司 一种阵列基板及其驱动方法、显示面板、显示装置
KR102279353B1 (ko) * 2014-12-01 2021-07-20 엘지디스플레이 주식회사 표시패널
CN105182638A (zh) * 2015-08-28 2015-12-23 重庆京东方光电科技有限公司 阵列基板、显示装置及其驱动方法
CN105629606A (zh) * 2016-01-13 2016-06-01 深圳市华星光电技术有限公司 液晶显示面板及其驱动方法
JP2018072821A (ja) * 2016-10-26 2018-05-10 株式会社半導体エネルギー研究所 表示装置およびその動作方法
KR102643465B1 (ko) * 2017-01-17 2024-03-05 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN106875890B (zh) * 2017-04-27 2021-01-12 京东方科技集团股份有限公司 阵列基板、显示面板、显示设备及驱动方法
CN108375855B (zh) * 2018-02-28 2021-03-12 厦门天马微电子有限公司 显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004264476A (ja) * 2003-02-28 2004-09-24 Sharp Corp 表示装置およびその駆動方法
US20150109347A1 (en) * 2013-10-18 2015-04-23 Au Optronics Corporation Charge-sharing controlling method and display panel
WO2016188257A1 (zh) * 2015-05-22 2016-12-01 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN105845066A (zh) * 2016-05-30 2016-08-10 深圳市华星光电技术有限公司 显示面板的驱动方法
CN109817150A (zh) * 2019-03-28 2019-05-28 京东方科技集团股份有限公司 一种像素驱动方法、像素驱动装置及显示装置
CN110379390A (zh) * 2019-07-01 2019-10-25 武汉天马微电子有限公司 一种显示面板、其驱动方法及显示装置

Also Published As

Publication number Publication date
CN115938322A (zh) 2023-04-07
US20220383787A1 (en) 2022-12-01
EP4006892A1 (en) 2022-06-01
US20230260442A1 (en) 2023-08-17
EP4006892A4 (en) 2022-12-21
US20240212550A1 (en) 2024-06-27
US11948489B2 (en) 2024-04-02
US11715401B2 (en) 2023-08-01
CN112673417A (zh) 2021-04-16
CN112673417B (zh) 2022-11-18

Similar Documents

Publication Publication Date Title
US9626922B2 (en) GOA circuit, array substrate, display device and driving method
WO2021016942A1 (zh) 显示面板、显示装置以及驱动方法
WO2020024641A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11402714B2 (en) Pixel array substrate, a driving method, and a display apparatus
EP3571691B1 (en) Shift register unit, gate drive circuit and method of driving the same
CN110060645B (zh) 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2020015641A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
WO2020015642A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
WO2021238787A1 (zh) 显示基板、显示面板、显示装置和显示驱动方法
CN110415664B (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2020048305A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
WO2021022554A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN108538237A (zh) 一种栅极驱动电路、方法及显示装置
CN110942742B (zh) 栅极驱动单元及驱动方法、栅极驱动电路和显示装置
WO2020140195A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2021022437A1 (zh) 移位寄存器单元、栅极驱动电路、显示面板、显示装置以及驱动方法
CN110689839B (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN112309335B (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN117037737A (zh) 显示控制电路、显示控制装置及显示装置
US20240212643A1 (en) Display panel, driving method for the display panel and display device
US11144159B2 (en) Driving method of display panel, display panel and display device
US11804196B2 (en) Display substrate including shift circuits configured to provide gate driving signals in a skipping mode, method for driving same and display device
WO2024065658A1 (zh) 栅极驱动电路及其驱动方法、显示面板及显示装置
CN118414032A (zh) 显示基板和显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19933196

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019933196

Country of ref document: EP

Effective date: 20220228