WO2019010756A1 - 扫描驱动电路及显示装置 - Google Patents

扫描驱动电路及显示装置 Download PDF

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Publication number
WO2019010756A1
WO2019010756A1 PCT/CN2017/098438 CN2017098438W WO2019010756A1 WO 2019010756 A1 WO2019010756 A1 WO 2019010756A1 CN 2017098438 W CN2017098438 W CN 2017098438W WO 2019010756 A1 WO2019010756 A1 WO 2019010756A1
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Prior art keywords
signal
controllable switch
signal output
scan
controllable
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PCT/CN2017/098438
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English (en)
French (fr)
Inventor
石龙强
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/557,448 priority Critical patent/US10311796B2/en
Publication of WO2019010756A1 publication Critical patent/WO2019010756A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a display device.
  • Indium gallium zinc oxide (IGZO) thin film transistor has high mobility and good device stability, which can reduce the complexity of the scan driving circuit. Due to the high mobility of the IGZO thin film transistor, the size of the thin film transistor in the scan driving circuit is relatively large. Small, is conducive to the production of a narrow bezel display device.
  • a scan drive circuit is used, that is, the scan drive circuit is fabricated on the array substrate by using the existing thin film transistor display device array process to realize the drive for progressive scan.
  • each driving unit drives only one scanning line, and a plurality of scanning lines are generally disposed in the display device, which requires designing a plurality of driving units, which makes the circuit complicated and takes up space, which is disadvantageous for the narrow frame design of the display device.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a display device to simplify the circuit and save space, thereby facilitating the narrow bezel design of the display device.
  • a technical solution adopted by the present invention is to provide a scan driving circuit, including:
  • the driving circuit comprises a plurality of driving units connected in sequence, each driving unit is correspondingly connected with a multiplexing circuit, and each driving unit comprises a first signal input end, a second signal input end, a first signal output end and a a second signal output end, the first signal input end is configured to receive a trigger signal or a superior scan signal, and the second signal input end is configured to receive a lower level scan signal, the first signal output end and the second signal output end Connecting the multiplexing circuit; and
  • the multiplexing circuit includes a plurality of multiplexing units, each multiplexing unit includes first to fifth signal receiving ends and a scanning signal output end, and the first signal receiving end is connected to the first of the driving units a signal output end, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is configured to receive an upper level scanning signal, and the fourth signal receiving end is configured to receive a lower level scanning signal
  • the fifth signal receiving end is configured to receive a clock signal
  • the scan signal output end is configured to output a scan signal to the scan line to drive the pixel unit;
  • Each of the driving units includes first to fifth controllable switches and a first capacitor, and a control end of the first controllable switch is connected to the first signal input end, and the first end of the first controllable switch Connecting a voltage end, the second end of the first controllable switch is connected to the control end of the third controllable switch, the first end of the fourth controllable switch, and the first end of the fifth controllable switch And the first signal output end, the control end of the second controllable switch is connected to the first end of the second controllable switch and the voltage end, and the second end of the second controllable switch is connected a second signal output end, a first end of the third controllable switch, and a control end of the fourth controllable switch, wherein the second ends of the third to fifth controllable switches are grounded, the a control terminal of the five controllable switch is connected to the second signal input end, one end of the first capacitor is connected to the first end of the fifth controllable switch, and the other end of the first capacitor is grounded;
  • the potential of the output signal of the first signal output of the drive unit is opposite to the potential of the output signal of the second signal output.
  • a technical solution adopted by the present invention is to provide a scan driving circuit, including:
  • the driving circuit comprises a plurality of driving units connected in sequence, each driving unit is correspondingly connected with a multiplexing circuit, and each driving unit comprises a first signal input end, a second signal input end, a first signal output end and a a second signal output end, the first signal input end is configured to receive a trigger signal or a superior scan signal, and the second signal input end is configured to receive a lower level scan signal, the first signal output end and the second signal output end Connecting the multiplexing circuit; and
  • the multiplexing circuit includes a plurality of multiplexing units, each multiplexing unit includes first to fifth signal receiving ends and a scanning signal output end, and the first signal receiving end is connected to the first of the driving units a signal output end, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is configured to receive an upper level scanning signal, and the fourth signal receiving end is configured to receive a lower level scanning signal
  • the fifth signal receiving end is configured to receive a clock signal
  • the scan signal output end is configured to output a scan signal to the scan line to drive the pixel unit.
  • a technical solution adopted by the present invention is to provide a display device, the display device including a scan driving circuit, and the scan driving circuit includes:
  • the driving circuit comprises a plurality of driving units connected in sequence, each driving unit is correspondingly connected with a multiplexing circuit, and each driving unit comprises a first signal input end, a second signal input end, a first signal output end and a a second signal output end, the first signal input end is configured to receive a trigger signal or a superior scan signal, and the second signal input end is configured to receive a lower level scan signal, the first signal output end and the second signal output end Connecting the multiplexing circuit; and
  • the multiplexing circuit includes a plurality of multiplexing units, each multiplexing unit includes first to fifth signal receiving ends and a scanning signal output end, and the first signal receiving end is connected to the first of the driving units a signal output end, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is configured to receive an upper level scanning signal, and the fourth signal receiving end is configured to receive a lower level scanning signal
  • the fifth signal receiving end is configured to receive a clock signal
  • the scan signal output end is configured to output a scan signal to the scan line to drive the pixel unit.
  • the scan driving circuit and the display device of the present invention are connected to a multiplexing circuit through a driving unit in the driving circuit, and pass through the multiplexing circuit.
  • a plurality of multiplexing units can realize one driving unit to simultaneously drive a plurality of scanning signal output ends to output scanning signals, thereby simplifying the circuit and saving space, thereby facilitating the narrow frame design of the display device.
  • FIG. 1 is a schematic structural view of a scan driving circuit of the present invention.
  • FIG. 2 is a circuit diagram of each driving unit of the driving circuit of FIG. 1;
  • FIG. 3 is a circuit diagram of the multiplexing circuit of FIG. 1;
  • FIG. 4 is a schematic waveform diagram of a scan driving circuit of the present invention.
  • FIG. 5 is a schematic diagram showing simulation waveforms of a scan driving circuit of the present invention.
  • FIG. 6 is a schematic waveform diagram of a first four-stage driving unit of the scan driving circuit of the present invention.
  • Fig. 7 is a schematic structural view of a display device of the present invention.
  • FIG. 1 is a schematic structural diagram of a scan driving circuit of the present invention.
  • the scan driving circuit includes a driving circuit 10, and the driving circuit 10 includes a plurality of driving units 11 connected in sequence.
  • Each driving unit 11 is connected to a multiplexing circuit 20, and each driving unit 11 includes a first signal input end. a signal input terminal, a first signal output terminal GM (K) and a second signal output terminal QGM (K), wherein the first signal input terminal is configured to receive a trigger signal STV or a superior scan signal G(N-1),
  • the second signal input terminal is configured to receive the lower level scan signal G(N+6), the first signal output terminal GM(K) and the second signal output terminal QGM(K) are connected to the multiplexing circuit 20;
  • the multiplexing circuit 20 includes a plurality of multiplexing units 21, each multiplexing unit 21 includes first to fifth signal receiving ends and a scanning signal output terminal G(N), the first signal receiving end Connecting a first signal output terminal GM(K) of the driving unit 11, the second signal receiving end is connected to a second signal output terminal QGM(K) of the driving unit 11, and the third signal receiving end is used for Receiving a superior scan signal G(N-2), the fourth signal receiving end is configured to receive a lower level scan signal G(N+3), and the fifth signal receiving end is configured to receive a clock signal CK, the scan signal The output terminal G(N) is used to output a scan signal to the scan line to drive the pixel unit.
  • each of the driving units 11 includes first to fifth controllable switches T1-T5 and a first capacitor C1, and a control end of the first controllable switch T1 is connected to the first signal input end.
  • the first end of the first controllable switch T1 is connected to the voltage terminal VDD, and the second end of the first controllable switch T1 is connected to the control end of the third controllable switch T3, and the fourth controllable switch T4 a first end, a first end of the fifth controllable switch T5, and the first signal output end GM(K), and a control end of the second controllable switch T2 is connected to the second controllable switch T2
  • the first end of the second controllable switch T2 is connected to the second signal output terminal QGM(K), the first end of the third controllable switch T3, and the a control end of the fourth controllable switch T4, the second ends of the third to fifth controllable switches T3-T5 are grounded, and the control end of the fifth controllable switch T5 is connected to
  • each of the multiplexing units 21 includes sixth to tenth controllable switches T6-T10 and a second capacitor C2, and a control end of the sixth controllable switch T6 is connected to the first signal receiving end.
  • the first end of the sixth controllable switch T6 is connected to the voltage terminal VDD, and the second end of the sixth controllable switch T6 is connected to the first end of the seventh controllable switch T7, the seventh
  • the control end of the controllable switch T7 is connected to the third signal receiving end
  • the second end of the seventh controllable switch T7 is connected to the first end of the eighth controllable switch T8 and the ninth controllable switch T9
  • a control end of the eighth controllable switch T8 is connected to the fourth signal receiving end, a second end of the eighth controllable switch T8 is grounded, and a first end of the ninth controllable switch T9 Connecting the fifth signal receiving end, the second end of the ninth controllable switch T9 is connected to the first end of the tenth controllable
  • the first to tenth controllable switches T1-T10 are N-type thin film transistors, and the control ends, the first end and the second end of the first to tenth controllable switches T1-T10 Corresponding to the gate, source and drain of the N-type thin film transistor, respectively.
  • the first through tenth controllable switches can also be other types of switches as long as the objectives of the present invention are achieved.
  • the potential of the output signal of the first signal output terminal GM(K) of the drive unit 11 is opposite to the potential of the output signal of the second signal output terminal QGM(K).
  • the trigger signal STV is alternating current, the pulse width is 2H time (H is the time corresponding to data), the high potential is VGH, the low potential is VGL, and the trigger signal STV is used to provide the first to the driving circuit 10.
  • the first signal input end of the stage driving unit 11 receives the upper level scanning signal G(N-1) from the first signal input end of the remaining stage driving unit 11.
  • the voltage terminal VDD is a high voltage direct current and the potential is VGH.
  • the pulse width of the clock signal CK is 2H, the period is 7H, the interval between the two clock signals is 1H, the interval between the clock signal CK and the trigger signal STV is 1H, and the high potential of the clock signal CK is VGH, low potential. For VGL.
  • the scan signal output terminal G(n) is used to describe the operating state of the scan driving circuit, and the scan signal output terminal G is assumed.
  • (n) is controlled by a clock signal CK5, wherein CK5, CK6, CK7, and CK1 are clock signals of the same phase, and the scan driving circuit requires seven clock signals CK, that is, sequentially circulated from CK1-CK7, each The clock signal CK controls a scan signal output.
  • the operating state of the K-th scan driving circuit is as follows: when the upper-level scan signal G(N-1) received by the first signal input terminal is high, the first controllable switch T1 is turned on, The first signal output terminal GM(K) outputs a high potential, and the third controllable switch T3 is turned on. Due to the relationship between the second controllable switch T2 and the third controllable switch T3, the voltage divider is At this time, the potential of the second signal output terminal QGM(K) is a low potential of the ground terminal VSS, and the lower-level scan signal G(N+6) received by the second signal input terminal is high.
  • the fifth controllable switch T5 is turned on, and the high potential of the first signal output terminal GM(K) is pulled low to the low potential by the ground terminal VSS, then the third controllable switch T3 is turned off, and the control terminal of the second controllable switch T2 always receives the high potential of the voltage terminal VDD, and the potential of the second voltage output terminal QGM(K) is the voltage terminal VDD. High potential.
  • the working states of the other driving units are the same as those described above, and are not described herein again.
  • the working state of the multiplexing circuit 20 is as follows: when the signal of the first signal output terminal GM(K) received by the first signal receiving end is high, the sixth controllable switch T6 is turned on. The high potential of the voltage terminal VDD is supplied to the seventh controllable switch T7 through the sixth controllable switch T6, and the upper scan signal G(N-2) received by the third signal receiving end is high.
  • the seventh controllable switch T7 is turned on, and the high potential of the voltage terminal VDD is supplied to the pull-up control signal point Q(N) through the seventh controllable switch T7, and the pull-up control signal point
  • the potential of Q(N) becomes a high potential VGH
  • the ninth controllable switch T9 is turned on, and when the clock signal CK5 received by the fifth signal receiving end is at a high potential, the scan signal output terminal G ( The potential of N) is the high potential of the clock signal CK5, and at the same time, because the upper-level scan signal G(N-2) received by the third signal receiving end and the fourth signal receiving end are received
  • the lower-level scan signal G(N+3) is low at this time, so the seventh controllable switch T7 and the eighth controllable switch T8 are both
  • the potential of the pull-up control signal point Q(N) rises to a higher potential due to the bootstrap action of the second capacitor C2, thereby causing the ninth controllable switch T9 to be fully turned on.
  • the high potential of the clock signal CK5 received by the fifth signal receiving end is transmitted to the scanning signal output terminal G(N) faster, thereby obtaining a better waveform output, when the second signal receiving end is from the
  • the tenth controllable switch T10 is turned on, and the potential of the scan signal output terminal G(N) is pulled down to the ground terminal.
  • FIG. 7 is a schematic structural view of a display device of the present invention.
  • the display device includes the scan driving circuit, the scan driving circuit is disposed on the left and right sides of the display device, the display device is an LCD or an OLED, and other devices and functions of the display device are compatible with the existing display device.
  • the devices and functions are the same and will not be described here.
  • the scan driving circuit and the display device are connected to one multiplexing circuit through one driving unit in the driving circuit, and one driving unit can simultaneously drive a plurality of scanning signal outputs through a plurality of multiplexing units in the multiplexing circuit.
  • the terminal outputs a scan signal to simplify the circuit and save space, thereby facilitating the narrow bezel design of the display device.

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Abstract

公开了一种扫描驱动电路及显示装置。每一驱动单元11包括第一信号输入端接收触发信号STV或上级扫描信号G(N-1)，第二信号输入端接收下级扫描信号G(N+6)，第一及第二信号输出端连接复用电路20；每一复用单元21包括第一及第二信号接收端分别连接第一及第二信号输出端，第三信号接收端接收上级扫描信号G(N-2)，第四信号接收端接收下级扫描信号G(N+3)，第五信号接收端接收时钟信号，扫描信号输出端输出扫描信号G(N)，以简化电路，节省空间，利于显示装置的窄边框设计。

Description

扫描驱动电路及显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及显示装置。
【背景技术】
GOA(Gate Driver on Array)技术有利于显示屏窄边框设计和成本的降低，得到广泛地应用和研究。铟镓锌氧化物（IGZO）薄膜晶体管具有高的迁移率和良好的器件稳定性，可减少扫描驱动电路的复杂程度，由于IGZO薄膜晶体管的高迁移率使得扫描驱动电路中薄膜晶体管的尺寸相对较小，有利于窄边框显示装置的制作，然而目前的显示装置中采用扫描驱动电路，也就是利用现有薄膜晶体管显示装置阵列制程将扫描驱动电路制作在阵列基板上，实现对逐行扫描的驱动方式，这使得每一驱动单元仅驱动一条扫描线，而一般显示装置中设置诸多条扫描线，这将需要设计诸多驱动单元，使得电路复杂，且占用空间，不利于显示装置的窄边框设计。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及显示装置，以简化电路，节省空间，进而利于显示装置的窄边框设计。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，包括：
驱动电路，所述驱动电路包括若干依次连接的驱动单元，每一驱动单元对应连接一个复用电路，每一驱动单元包括第一信号输入端、第二信号输入端、第一信号输出端及第二信号输出端，所述第一信号输入端用于接收触发信号或者上级扫描信号，所述第二信号输入端用于接收下级扫描信号，所述第一信号输出端及所述第二信号输出端连接所述复用电路；及
复用电路，所述复用电路包括若干复用单元，每一复用单元包括第一至第五信号接收端及扫描信号输出端，所述第一信号接收端连接所述驱动单元的第一信号输出端，所述第二信号接收端连接所述驱动单元的第二信号输出端，所述第三信号接收端用于接收上级扫描信号，所述第四信号接收端用于接收下级扫描信号，所述第五信号接收端用于接收一时钟信号，所述扫描信号输出端用于输出扫描信号给扫描线以驱动像素单元；
所述每一驱动单元包括第一至第五可控开关及第一电容，所述第一可控开关的控制端连接所述第一信号输入端，所述第一可控开关的第一端连接电压端，所述第一可控开关的第二端连接所述第三可控开关的控制端、所述第四可控开关的第一端、所述第五可控开关的第一端及所述第一信号输出端，所述第二可控开关的控制端连接所述第二可控开关的第一端及所述电压端，所述第二可控开关的第二端连接所述第二信号输出端、所述第三可控开关的第一端及所述第四可控开关的控制端，所述第三至第五可控开关的第二端均接地，所述第五可控开关的控制端连接所述第二信号输入端，所述第一电容的一端连接所述第五可控开关的第一端，所述第一电容的另一端接地；
所述驱动单元的第一信号输出端的输出信号的电位与所述第二信号输出端的输出信号的电位相反。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，包括：
驱动电路，所述驱动电路包括若干依次连接的驱动单元，每一驱动单元对应连接一个复用电路，每一驱动单元包括第一信号输入端、第二信号输入端、第一信号输出端及第二信号输出端，所述第一信号输入端用于接收触发信号或者上级扫描信号，所述第二信号输入端用于接收下级扫描信号，所述第一信号输出端及所述第二信号输出端连接所述复用电路；及
复用电路，所述复用电路包括若干复用单元，每一复用单元包括第一至第五信号接收端及扫描信号输出端，所述第一信号接收端连接所述驱动单元的第一信号输出端，所述第二信号接收端连接所述驱动单元的第二信号输出端，所述第三信号接收端用于接收上级扫描信号，所述第四信号接收端用于接收下级扫描信号，所述第五信号接收端用于接收一时钟信号，所述扫描信号输出端用于输出扫描信号给扫描线以驱动像素单元。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示装置，所述显示装置包括扫描驱动电路，所述扫描驱动电路包括：
驱动电路，所述驱动电路包括若干依次连接的驱动单元，每一驱动单元对应连接一个复用电路，每一驱动单元包括第一信号输入端、第二信号输入端、第一信号输出端及第二信号输出端，所述第一信号输入端用于接收触发信号或者上级扫描信号，所述第二信号输入端用于接收下级扫描信号，所述第一信号输出端及所述第二信号输出端连接所述复用电路；及
复用电路，所述复用电路包括若干复用单元，每一复用单元包括第一至第五信号接收端及扫描信号输出端，所述第一信号接收端连接所述驱动单元的第一信号输出端，所述第二信号接收端连接所述驱动单元的第二信号输出端，所述第三信号接收端用于接收上级扫描信号，所述第四信号接收端用于接收下级扫描信号，所述第五信号接收端用于接收一时钟信号，所述扫描信号输出端用于输出扫描信号给扫描线以驱动像素单元。
本发明的有益效果是：区别于现有技术的情况，本发明的所述扫描驱动电路及显示装置通过驱动电路中的一个驱动单元与一个复用电路连接，并通过所述复用电路中的多个复用单元即可实现一个驱动单元同时驱动多个扫描信号输出端来输出扫描信号，以简化电路，节省空间，进而利于显示装置的窄边框设计。
【附图说明】
图1是本发明的扫描驱动电路的结构示意图。
图2是图1中的驱动电路的每一驱动单元的电路示意图；
图3是图1中的复用电路的电路示意图；
图4是本发明的扫描驱动电路的波形示意图；
图5是本发明的扫描驱动电路的仿真波形示意图；
图6是本发明的扫描驱动电路的前四级驱动单元的波形示意图；
图7是本发明的显示装置的结构示意图。
【具体实施方式】
请参阅图1，是本发明的扫描驱动电路的结构示意图。所述扫描驱动电路包括驱动电路10，所述驱动电路10包括若干依次连接的驱动单元11，每一驱动单元11对应连接一个复用电路20，每一驱动单元11包括第一信号输入端、第二信号输入端、第一信号输出端GM(K)及第二信号输出端QGM(K)，所述第一信号输入端用于接收触发信号STV或者上级扫描信号G(N-1)，所述第二信号输入端用于接收下级扫描信号G(N+6)，所述第一信号输出端GM(K)及所述第二信号输出端QGM(K)连接所述复用电路20；
复用电路20，所述复用电路20包括若干复用单元21，每一复用单元21包括第一至第五信号接收端及扫描信号输出端G（N），所述第一信号接收端连接所述驱动单元11的第一信号输出端GM(K)，所述第二信号接收端连接所述驱动单元11的第二信号输出端QGM(K)，所述第三信号接收端用于接收上级扫描信号G(N-2)，所述第四信号接收端用于接收下级扫描信号G(N+3)，所述第五信号接收端用于接收一时钟信号CK，所述扫描信号输出端G(N)用于输出扫描信号给扫描线以驱动像素单元。
请参阅图2，所述每一驱动单元11包括第一至第五可控开关T1-T5及第一电容C1，所述第一可控开关T1的控制端连接所述第一信号输入端，所述第一可控开关T1的第一端连接电压端VDD，所述第一可控开关T1的第二端连接所述第三可控开关T3的控制端、所述第四可控开关T4的第一端、所述第五可控开关T5的第一端及所述第一信号输出端GM(K)，所述第二可控开关T2的控制端连接所述第二可控开关T2的第一端及所述电压端VDD，所述第二可控开关T2的第二端连接所述第二信号输出端QGM(K)、所述第三可控开关T3的第一端及所述第四可控开关T4的控制端，所述第三至第五可控开关T3-T5的第二端均接地，所述第五可控开关T5的控制端连接所述第二信号输入端，所述第一电容C1的一端连接所述第五可控开关T5的第一端，所述第一电容C1的另一端接地。
请参阅图3，所述每一复用单元21包括第六至第十可控开关T6-T10及第二电容C2，所述第六可控开关T6的控制端连接所述第一信号接收端，所述第六可控开关T6的第一端连接所述电压端VDD，所述第六可控开关T6的第二端连接所述第七可控开关T7的第一端，所述第七可控开关T7的控制端连接所述第三信号接收端，所述第七可控开关T7的第二端连接所述第八可控开关T8的第一端及所述第九可控开关T9的控制端，所述第八可控开关T8的控制端连接所述第四信号接收端，所述第八可控开关T8的第二端接地，所述第九可控开关T9的第一端连接所述第五信号接收端，所述第九可控开关T9的第二端连接所述第十可控开关T10的第一端及所述扫描信号输出端G(N)，所述第十可控开关T10的控制端连接所述第二信号接收端，所述第十可控开关T10的第二端接地，所述第二电容C2的一端连接所述第九可控开关T9的控制端，所述第二电容C2的另一端连接所述第九可控开关T9的第二端。
在本实施例中，所述第一至第十可控开关T1-T10均为N型薄膜晶体管，所述第一至第十可控开关T1-T10的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。在其他实施中，所述第一至第十可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
在本实施例中，所述驱动单元11的第一信号输出端GM(K)的输出信号的电位与所述第二信号输出端QGM(K)的输出信号的电位相反。所述触发信号STV为交流电，脉宽为2H时间（H为data对应的时间），其高电位为VGH，低电位为VGL，所述触发信号STV用于提供给所述驱动电路10的第一级驱动单元11的第一信号输入端，其余级的驱动单元11的第一信号输入端接收所述上级扫描信号G(N-1)。所述电压端VDD为高压直流电，电位为VGH。时钟信号CK的脉宽为2H，周期为7H，两个时钟信号之间的间隔为1H，时钟信号CK和所述触发信号STV之前的间隔为1H，时钟信号CK的高电位为VGH，低电位为VGL。
请参阅图1至图6，所述扫描驱动电路的工作原理描述如下，在此以所述扫描信号输出端G(n)说明所述扫描驱动电路的工作状态，假设所述扫描信号输出端G(n)是由时钟信号CK5控制的，其中时钟信号CK5、CK6、CK7和CK1是相位相同的时钟信号，所述扫描驱动电路需要7个时钟信号CK，即从CK1-CK7依次循环，每个时钟信号CK控制一个扫描信号输出端。
首先第K级扫描驱动电路的工作状态如下：当所述第一信号输入端接收到的所述上级扫描信号G(N-1)为高电位时，所述第一可控开关T1导通，所述第一信号输出端GM(K)输出高电位，所述第三可控开关T3导通，由于所述第二可控开关T2及所述第三可控开关T3电阻分压的关系，此时，所述第二信号输出端QGM(K)的电位为所述接地端VSS的低电位，当所述第二信号输入端接收到的所述下级扫描信号G(N+6)为高电位时，所述第五可控开关T5导通，所述第一信号输出端GM(K)的高电位被所述接地端VSS拉低至低电位，则此时所述第三可控开关T3截止，而所述第二可控开关T2的控制端始终接收所述电压端VDD的高电位一直导通，此时所述第二电压输出端QGM(K)的电位为所述电压端VDD的高电位。其他驱动单元的工作状态与上述相同，在此不再赘述。
其次所述复用电路20的工作状态如下：当所述第一信号接收端接收到的第一信号输出端GM(K)的信号为高电位时，所述第六可控开关T6导通，所述电压端VDD的高电位通过所述第六可控开关T6提供给所述第七可控开关T7，当所述第三信号接收端接收到的上级扫描信号G(N-2)为高电位时，所述第七可控开关T7导通，所述电压端VDD的高电位通过所述第七可控开关T7提供给上拉控制信号点Q(N)，所述上拉控制信号点Q(N)的电位变为高电位VGH，所述第九可控开关T9导通，当所述第五信号接收端接收到的时钟信号CK5为高电位时，所述扫描信号输出端G(N)的电位为所述时钟信号CK5的高电位，与此同时，因为所述第三信号接收端接收到的所述上级扫描信号G(N-2)及所述第四信号接收端接收到的所述下级扫描信号G(N+3)此时均为低电位，因此所述第七可控开关T7及所述第八可控开关T8均截止，所述上拉控制信号点Q(N)的电位由于所述第二电容C2的自举作用上升到更高的电位，从而使得所述第九可控开关T9完全导通，所述第五信号接收端接收到的所述时钟信号CK5的高电位更快的传入到所述扫描信号输出端G(N)，从而得到更好的波形输出，当所述第二信号接收端从所述第一信号输出端QGM(K)接收到的信号为高电位时，所述第十可控开关T10导通，所述扫描信号输出端G(N)的电位被拉低到所述接地端VSS的低电位，当所述第四信号接收端接收到的下级扫描信号G(N+3)为高电位时，所述第八可控开关T8导通，所述上拉控制信号点Q(N)的电位被拉低到所述接地端VSS的低电位，防止因所述上拉控制信号点Q(N)的电位高导致的所述扫描信号输出端输出多个波形。其他复用单元的工作状态与上述相同，在此不再赘述。
请参阅图7，是本发明的显示装置的结构示意图。所述显示装置包括上述扫描驱动电路，所述扫描驱动电路设置在所述显示装置的左右两侧，所述显示装置为LCD或OLED，所述显示装置的其他器件及功能与现有显示装置的器件及功能相同，在此不再赘述。
所述扫描驱动电路及显示装置通过驱动电路中的一个驱动单元与一个复用电路连接，并通过所述复用电路中的多个复用单元即可实现一个驱动单元同时驱动多个扫描信号输出端来输出扫描信号，以简化电路，节省空间，进而利于显示装置的窄边框设计。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括：
    驱动电路，所述驱动电路包括若干依次连接的驱动单元，每一驱动单元对应连接一个复用电路，每一驱动单元包括第一信号输入端、第二信号输入端、第一信号输出端及第二信号输出端，所述第一信号输入端用于接收触发信号或者上级扫描信号，所述第二信号输入端用于接收下级扫描信号，所述第一信号输出端及所述第二信号输出端连接所述复用电路；及
    复用电路，所述复用电路包括若干复用单元，每一复用单元包括第一至第五信号接收端及扫描信号输出端，所述第一信号接收端连接所述驱动单元的第一信号输出端，所述第二信号接收端连接所述驱动单元的第二信号输出端，所述第三信号接收端用于接收上级扫描信号，所述第四信号接收端用于接收下级扫描信号，所述第五信号接收端用于接收一时钟信号，所述扫描信号输出端用于输出扫描信号给扫描线以驱动像素单元；
    所述每一驱动单元包括第一至第五可控开关及第一电容，所述第一可控开关的控制端连接所述第一信号输入端，所述第一可控开关的第一端连接电压端，所述第一可控开关的第二端连接所述第三可控开关的控制端、所述第四可控开关的第一端、所述第五可控开关的第一端及所述第一信号输出端，所述第二可控开关的控制端连接所述第二可控开关的第一端及所述电压端，所述第二可控开关的第二端连接所述第二信号输出端、所述第三可控开关的第一端及所述第四可控开关的控制端，所述第三至第五可控开关的第二端均接地，所述第五可控开关的控制端连接所述第二信号输入端，所述第一电容的一端连接所述第五可控开关的第一端，所述第一电容的另一端接地；
    所述驱动单元的第一信号输出端的输出信号的电位与所述第二信号输出端的输出信号的电位相反。
  2. 一种扫描驱动电路，其中，所述扫描驱动电路包括：
    驱动电路，所述驱动电路包括若干依次连接的驱动单元，每一驱动单元对应连接一个复用电路，每一驱动单元包括第一信号输入端、第二信号输入端、第一信号输出端及第二信号输出端，所述第一信号输入端用于接收触发信号或者上级扫描信号，所述第二信号输入端用于接收下级扫描信号，所述第一信号输出端及所述第二信号输出端连接所述复用电路；及
    复用电路，所述复用电路包括若干复用单元，每一复用单元包括第一至第五信号接收端及扫描信号输出端，所述第一信号接收端连接所述驱动单元的第一信号输出端，所述第二信号接收端连接所述驱动单元的第二信号输出端，所述第三信号接收端用于接收上级扫描信号，所述第四信号接收端用于接收下级扫描信号，所述第五信号接收端用于接收一时钟信号，所述扫描信号输出端用于输出扫描信号给扫描线以驱动像素单元。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述每一驱动单元包括第一至第五可控开关及第一电容，所述第一可控开关的控制端连接所述第一信号输入端，所述第一可控开关的第一端连接电压端，所述第一可控开关的第二端连接所述第三可控开关的控制端、所述第四可控开关的第一端、所述第五可控开关的第一端及所述第一信号输出端，所述第二可控开关的控制端连接所述第二可控开关的第一端及所述电压端，所述第二可控开关的第二端连接所述第二信号输出端、所述第三可控开关的第一端及所述第四可控开关的控制端，所述第三至第五可控开关的第二端均接地，所述第五可控开关的控制端连接所述第二信号输入端，所述第一电容的一端连接所述第五可控开关的第一端，所述第一电容的另一端接地。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述每一复用单元包括第六至第十可控开关及第二电容，所述第六可控开关的控制端连接所述第一信号接收端，所述第六可控开关的第一端连接所述电压端，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端连接所述第三信号接收端，所述第七可控开关的第二端连接所述第八可控开关的第一端及所述第九可控开关的控制端，所述第八可控开关的控制端连接所述第四信号接收端，所述第八可控开关的第二端接地，所述第九可控开关的第一端连接所述第五信号接收端，所述第九可控开关的第二端连接所述第十可控开关的第一端及所述扫描信号输出端，所述第十可控开关的控制端连接所述第二信号接收端，所述第十可控开关的第二端接地，所述第二电容的一端连接所述第九可控开关的控制端，所述第二电容的另一端连接所述第九可控开关的第二端。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述第一至第十可控开关均为N型薄膜晶体管，所述第一至第十可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。
  6. 根据权利要求2所述的扫描驱动电路，其中，所述驱动单元的第一信号输出端的输出信号的电位与所述第二信号输出端的输出信号的电位相反。
  7. 一种显示装置，其中，所述显示装置包括扫描驱动电路，所述扫描驱动电路包括：
    驱动电路，所述驱动电路包括若干依次连接的驱动单元，每一驱动单元对应连接一个复用电路，每一驱动单元包括第一信号输入端、第二信号输入端、第一信号输出端及第二信号输出端，所述第一信号输入端用于接收触发信号或者上级扫描信号，所述第二信号输入端用于接收下级扫描信号，所述第一信号输出端及所述第二信号输出端连接所述复用电路；及
    复用电路，所述复用电路包括若干复用单元，每一复用单元包括第一至第五信号接收端及扫描信号输出端，所述第一信号接收端连接所述驱动单元的第一信号输出端，所述第二信号接收端连接所述驱动单元的第二信号输出端，所述第三信号接收端用于接收上级扫描信号，所述第四信号接收端用于接收下级扫描信号，所述第五信号接收端用于接收一时钟信号，所述扫描信号输出端用于输出扫描信号给扫描线以驱动像素单元。
  8. 根据权利要求7所述的显示装置，其中，所述每一驱动单元包括第一至第五可控开关及第一电容，所述第一可控开关的控制端连接所述第一信号输入端，所述第一可控开关的第一端连接电压端，所述第一可控开关的第二端连接所述第三可控开关的控制端、所述第四可控开关的第一端、所述第五可控开关的第一端及所述第一信号输出端，所述第二可控开关的控制端连接所述第二可控开关的第一端及所述电压端，所述第二可控开关的第二端连接所述第二信号输出端、所述第三可控开关的第一端及所述第四可控开关的控制端，所述第三至第五可控开关的第二端均接地，所述第五可控开关的控制端连接所述第二信号输入端，所述第一电容的一端连接所述第五可控开关的第一端，所述第一电容的另一端接地。
  9. 根据权利要求8所述的显示装置，其中，所述每一复用单元包括第六至第十可控开关及第二电容，所述第六可控开关的控制端连接所述第一信号接收端，所述第六可控开关的第一端连接所述电压端，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端连接所述第三信号接收端，所述第七可控开关的第二端连接所述第八可控开关的第一端及所述第九可控开关的控制端，所述第八可控开关的控制端连接所述第四信号接收端，所述第八可控开关的第二端接地，所述第九可控开关的第一端连接所述第五信号接收端，所述第九可控开关的第二端连接所述第十可控开关的第一端及所述扫描信号输出端，所述第十可控开关的控制端连接所述第二信号接收端，所述第十可控开关的第二端接地，所述第二电容的一端连接所述第九可控开关的控制端，所述第二电容的另一端连接所述第九可控开关的第二端。
  10. 根据权利要求9所述的显示装置，其中，所述第一至第十可控开关均为N型薄膜晶体管，所述第一至第十可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。
  11. 根据权利要求7所述的显示装置，其中，所述驱动单元的第一信号输出端的输出信号的电位与所述第二信号输出端的输出信号的电位相反。
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