WO2020248993A1 - 显示面板的驱动电路、显示面板及显示装置 - Google Patents

显示面板的驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2020248993A1
WO2020248993A1 PCT/CN2020/095266 CN2020095266W WO2020248993A1 WO 2020248993 A1 WO2020248993 A1 WO 2020248993A1 CN 2020095266 W CN2020095266 W CN 2020095266W WO 2020248993 A1 WO2020248993 A1 WO 2020248993A1
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Prior art keywords
gate driving
circuit
display panel
gate
output
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PCT/CN2020/095266
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English (en)
French (fr)
Inventor
曹军红
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重庆惠科金渝光电科技有限公司
北海惠科光电技术有限公司
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Publication of WO2020248993A1 publication Critical patent/WO2020248993A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • This application relates to the field of display technology, and in particular to a drive circuit of a display panel, a display panel and a display device.
  • GOA is the abbreviation of Gate Driver on Array, which means the integration of gate driver on the array substrate, which can realize the progressive scan driving function on the display panel.
  • GOA technology is to fabricate the driving circuit of the horizontal scan line on the substrate around the display area of the display panel, so that it can replace the external integrated circuit board to complete the driving of the horizontal scan line.
  • one GOA circuit drives one horizontal scan line, and the number of GOA circuits is too large, which is not conducive to the design of narrow border display devices or even borderless display devices.
  • the present application provides a driving circuit for a display panel, a display panel and a display device, aiming to reduce the number of gate driving circuits.
  • the present application provides a driving circuit for a display panel, the driving circuit for the display panel includes:
  • the control circuit is configured to output drive signals and control signals
  • a plurality of gate driving circuits each of the gate driving circuits is provided with a plurality of output terminals, and the input terminals of the plurality of gate driving circuits are all connected to the signal output terminal of the control circuit;
  • the gate driving circuit is configured to receive the driving signal and sequentially output a pulse signal; wherein, in each clock signal period, one of the gate driving circuits of the plurality of gate driving circuits outputs a pulse signal;
  • a plurality of switching tubes, the plurality of output terminals of each of the gate driving circuits are connected to the input terminals of the plurality of switching tubes in a one-to-one correspondence, and the controlled terminals of the plurality of switching tubes are all connected to the control circuit
  • the control terminals are connected, and the output terminals of the plurality of switching tubes are connected to the plurality of scan lines in a one-to-one correspondence; the plurality of switching tubes are configured to turn on sequentially according to the control signal output by the control circuit, so that the gate The pulse signal output by the pole driving circuit sequentially drives the plurality of scanning lines.
  • the present application also provides a display panel, the display panel including: a driving circuit;
  • the driving circuit includes: a control circuit configured to output a driving signal and a control signal;
  • a plurality of gate driving circuits each of the gate driving circuits is provided with a plurality of output terminals, and the input terminals of the plurality of gate driving circuits are all connected to the signal output terminal of the control circuit;
  • the gate driving circuit is configured to receive the driving signal and sequentially output a pulse signal; wherein, in each clock signal period, one of the gate driving circuits of the plurality of gate driving circuits outputs a pulse signal;
  • a plurality of switching tubes, the plurality of output terminals of each of the gate driving circuits are connected to the input terminals of the plurality of switching tubes in a one-to-one correspondence, and the controlled terminals of the plurality of switching tubes are all connected to the control circuit
  • the control terminals are connected, and the output terminals of the plurality of switching tubes are connected to the plurality of scan lines in a one-to-one correspondence; the plurality of switching tubes are configured to turn on sequentially according to the control signal output by the control circuit, so that the gate The pulse signal output by the pole driving circuit sequentially drives the plurality of scanning lines.
  • the present application also provides a display device, the display device includes: a display panel, and the display panel includes: a drive circuit;
  • the driving circuit includes: a control circuit configured to output a driving signal and a control signal;
  • a plurality of gate driving circuits each of the gate driving circuits is provided with a plurality of output terminals, and the input terminals of the plurality of gate driving circuits are all connected to the signal output terminal of the control circuit;
  • the gate driving circuit is configured to receive the driving signal and sequentially output a pulse signal; wherein, in each clock signal period, one of the gate driving circuits of the plurality of gate driving circuits outputs a pulse signal;
  • a plurality of switching tubes, the plurality of output terminals of each of the gate driving circuits are connected to the input terminals of the plurality of switching tubes in a one-to-one correspondence, and the controlled terminals of the plurality of switching tubes are all connected to the control circuit
  • the control terminals are connected, and the output terminals of the plurality of switching tubes are connected to the plurality of scan lines in a one-to-one correspondence; the plurality of switching tubes are configured to turn on sequentially according to the control signal output by the control circuit, so that the gate The pulse signal output by the pole driving circuit sequentially drives the plurality of scanning lines.
  • each gate driving circuit is connected to n continuously arranged scan lines through n switching tubes; in each clock signal period, the control circuit controls the n switching tubes to be turned on sequentially; further, when A gate drive circuit generates a pulse signal.
  • the gate drive circuit first outputs the 1/n pulse signal through the switch tube that is turned on to drive the scan line connected to the switch tube that is turned on; the next switch tube is turned on At this time, another 1/n pulse signal is used to drive another scan line, and so on, until a gate driving circuit sequentially drives n consecutive scan lines within one clock signal cycle.
  • Such an arrangement can reduce the number of gate driving circuits on the display panel and reduce the width of the gate side, which is beneficial for manufacturing a display device with a narrow frame or even a display device without a frame.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of a driving circuit of a display panel of the present application
  • FIG. 2 is a schematic diagram of a circuit structure of an exemplary embodiment of a driving circuit of a display panel of the present application
  • FIG. 3 is a schematic diagram of the effect of the driving circuit of the display panel described in FIG. 2.
  • the directional indication is only used to explain that it is in a specific posture ( As shown in the figure), the relative positional relationship and movement conditions of the components under the following, if the specific posture changes, the directional indication will also change accordingly.
  • This application proposes a driving circuit for a display panel.
  • the driving circuit of the display panel includes a control circuit 10, a plurality of gate driving circuits 20, and a plurality of switch tubes 30, wherein each gate driving circuit 20 is provided with a plurality of output terminals;
  • the input terminals of each of the gate drive circuits 20 are connected to the signal output terminal of the control circuit 10, and the multiple output terminals of each of the gate drive circuits 20 are connected to the input terminals of the multiple switch tubes 30 in a one-to-one correspondence,
  • the controlled terminals of the plurality of switch tubes 30 are all connected to the control terminal of the control circuit 10, and the output terminals of the plurality of switch tubes 30 are connected to a plurality of scan lines in a one-to-one correspondence.
  • the plurality of gate driving circuits 20 may be selected as a plurality of GOA circuits.
  • the GOA circuit is manufactured using the same process as the active switch based on the control circuit 10 (such as the timing controller) providing only a few drive signals.
  • the active switch may be a thin film transistor.
  • the GOA circuit is used to drive the row and scan lines.
  • the GOA circuit generates a shift pulse signal under the action of the driving signal of the control circuit 10 to drive the pixels of the current row so that the active switch is turned on, and the driving signal includes at least signals of opposite phase to CKV and CKVB, and the gate is closed.
  • Signal VSS such as VSS of -8V.
  • each gate driving circuit 20 is provided with n output terminals, and each output terminal of the gate driving circuit 20 is connected to a scan line through a switch tube 30.
  • n is an integer greater than or equal to 2, for example, the n can be 2, 3, 4, 5, etc. Of course n can also be set according to the size of the circuit board.
  • a plurality of gate driving circuits 20 receive driving signals output by the control circuit 10, and sequentially output pulse signals according to the received driving signals.
  • one of the gate driving circuits 20 of the plurality of gate driving circuits 20 outputs a pulse signal, while the remaining gate driving circuits 20 have no output.
  • each of the n switching tubes connected to the gate drive circuit 20 is represented by the first switching tube to the nth switching tube, and the first switching tube to the first switching tube
  • the n switch tubes are respectively connected with n continuously arranged scan lines.
  • control circuit 10 outputs driving signals to the plurality of gate driving circuits 20, and the plurality of gate driving circuits 20 sequentially output pulse signals according to the received driving signals, and in each clock signal period, the plurality of gate driving circuits 20 One of the gate drive circuits 20 outputs a pulse signal.
  • the control circuit 10 outputs the n channels of control signals Enable 1 to Enable n to the controlled ends of the first switching tube to the nth switching tube to control the first switching tube to the nth switching tube.
  • the tubes are turned on sequentially. And when any one of the n switching tubes 30 connected to each gate driving circuit 20 is turned on, the remaining n ⁇ 1 switching tubes 30 are turned off. For example, when Enable 1 is at a high level and Enable 2 to Enable n are at a low level, the first switch tube is turned on, and the second switch tube to the nth switch tube are turned off.
  • each switch tube 30 can also be set to be turned on when the received control signal is at a low level, which is not limited here.
  • one of the gate driving circuits 20 sequentially outputs the 1/n pulse signal through the n switching tubes to sequentially drive the n continuously arranged scan lines. It can be understood that when one of the gate driving circuits 20 generates a pulse signal, the gate driving circuit 20 divides the pulse signal into n segments. When the n switching tubes connected to the gate driving circuit 20 are turned on sequentially, the gate driving circuit 20 sequentially outputs n segments of pulse signals through the n switching tubes to sequentially drive the n switching tubes connected to the n switching tubes. Scan lines set continuously.
  • the gate driving circuit 20 first transmits the 1/n pulse signal Output through the first switching tube to drive the scan line connected to the first switching tube; then, when the second switching tube is turned on, the gate driving circuit 20 transmits another 1/n pulse signal through the second switching tube Output to drive the scan line connected to the second switching tube; and so on, when the nth switching tube is turned on, the last 1/n pulse signal is output through the nth switching tube to drive the nth switching tube Scan line.
  • a gate driving circuit 20 can sequentially drive n continuously arranged scanning lines, thereby reducing the number of gate driving circuits 20 on the display panel and reducing the number of gate driving circuits 20.
  • the width is beneficial to the manufacture of display devices with narrow bezels, and even display devices without bezels.
  • each gate driving circuit has two output terminals, and each output terminal is connected to a scan line through a switch tube.
  • CK1 and CK2 are set as two clock signal periods, and Enable1 and Enable2 are two control signals output by the control circuit 10.
  • Gate1 ⁇ Gate4 are four scan lines set continuously.
  • Gate1 and Gate2 are connected to a gate drive circuit 20 via two switch tubes 30.
  • Gate3 and Gate4 are connected to another gate drive circuit 20 via two switch tubes.
  • the control signal Enable1 output by the control circuit 10 is high and Enable2 is low.
  • the two switch tubes 30 connected to Gate1 and Gate3 are turned on and connected to Gate2 and Gate4. The two switch tubes 30 are closed.
  • the control signal Enable1 output by the control circuit 10 is low level, Enable2 is high level, the two switch tubes 30 connected to Gate1 and Gate3 are closed, and they are connected to Gate2 and Gate4. The two switch tubes 30 are turned on.
  • the gate drive circuit 20 connected to Gate1 and Gate2 generates pulse signals.
  • the gate driving circuit 20 outputs the first half pulse signal through the switch tube 30 connected to the scan line Gate1 to drive the scan line Gate1.
  • the gate driving circuit 20 In the second half of the clock signal period of the CK1 clock signal period, the gate driving circuit 20 outputs the second half of the pulse signal through the switch tube 30 connected to the scan line Gate2 to drive the scan line Gate2.
  • the other gate driving circuit 20 outputs a pulse signal.
  • the gate driving circuit 20 In the first half of the clock signal period of the CK2 clock signal period, the gate driving circuit 20 outputs the first half of the pulse signal to the scan line Gate3 to drive the scan line Gate3.
  • the gate driving circuit 20 In the second half of the clock signal period of the CK2 clock signal period, the gate driving circuit 20 outputs the second half pulse signal to the scan line Gate4 to drive the scan line Gate4.
  • each gate driving circuit 20 is connected to n consecutive scan lines through n switch tubes.
  • the control circuit 10 controls the n switch tubes to be turned on sequentially.
  • the gate driving circuit 20 first outputs the 1/n pulse signal through the turned-on switch tube to drive the scan line connected to the turned-on switch tube.
  • the gate driving circuit 20 then outputs another 1/n pulse signal through the turned-on switching tube to drive another scan line.
  • one gate driving circuit 20 sequentially drives n continuously arranged scan lines.
  • the switch tube 30 may be an N-type insulating field effect transistor, and the drain of the N-type insulating field effect transistor is connected to the output terminal of the gate driving circuit, The gate of the N-type insulating field effect transistor is connected to the control terminal of the control circuit, and the source of the N-type insulating field effect transistor is connected to the scan line.
  • the N-type insulating field effect transistor is a high-level conducting switch tube, and n output terminals of each gate driving circuit 20 are respectively connected to n N-type insulating field effect transistors.
  • the n N-type insulating field effect transistors are turned on sequentially according to the control signal output by the control circuit 10.
  • the gate driving circuit 20 can drive the scan line connected to the turned-on switching tube 30 through the turned-on switching tube 30. Therefore, since the n switching tubes are turned on sequentially, when one of the gate driving circuits 20 generates a pulse signal, the gate driving circuit 20 can sequentially drive a plurality of continuously arranged scan lines to achieve the effect of progressive scanning.
  • the switch tube 30 may also be a triode, a P-type insulating field effect tube, etc., which is not limited here.
  • the switch tube is a P-type insulating field effect tube
  • the source of the P-type insulating field effect tube is connected to the output terminal of the gate drive circuit
  • the gate of the P-type insulating field effect tube The pole is connected with the control terminal of the control circuit
  • the drain of the P-type insulating field effect transistor is connected with the scan line.
  • the present application also provides a display panel, which includes a drive circuit and an active switch of the display panel.
  • the driving circuit of the display panel includes a control circuit 10, a plurality of gate driving circuits 20, and a plurality of switch tubes 30, wherein each gate driving circuit 20 is provided with a plurality of output terminals; the plurality of gate driving
  • the input terminals of the circuit 20 are all connected to the signal output terminals of the control circuit 10, and the multiple output terminals of each gate drive circuit 20 are connected to the input terminals of the multiple switch tubes 30 in a one-to-one correspondence.
  • the controlled terminals of the switch tubes 30 are all connected to the control terminal of the control circuit 10, and the output terminals of the plurality of switch tubes 30 are connected to a plurality of scan lines in a one-to-one correspondence.
  • the plurality of gate driving circuits 20 may be selected as a plurality of GOA circuits.
  • the GOA circuit is manufactured using the same process as the active switch based on the control circuit 10 (such as the timing controller) providing only a few drive signals.
  • the active switch may be a thin film transistor.
  • the GOA circuit is used to drive the row and scan lines.
  • the GOA circuit generates a shift pulse signal under the action of the driving signal of the control circuit 10 to drive the pixels of the current row so that the active switch is turned on, and the driving signal includes at least signals of opposite phase to CKV and CKVB, and the gate is closed.
  • Signal VSS such as VSS of -8V.
  • each gate driving circuit 20 is provided with n output terminals, and each output terminal of the gate driving circuit 20 is connected to a scan line through a switch tube 30.
  • n is an integer greater than or equal to 2, for example, the n can be 2, 3, 4, 5, etc. Of course n can also be set according to the size of the circuit board.
  • a plurality of gate driving circuits 20 receive driving signals output by the control circuit 10, and sequentially output pulse signals according to the received driving signals.
  • one of the gate driving circuits 20 of the plurality of gate driving circuits 20 outputs a pulse signal, while the remaining gate driving circuits 20 have no output.
  • each of the n switching tubes connected to the gate drive circuit 20 is represented by the first switching tube to the nth switching tube, and the first switching tube to the first switching tube
  • the n switch tubes are respectively connected with n continuously arranged scan lines.
  • control circuit 10 outputs driving signals to a plurality of gate driving circuits 20, and the plurality of gate driving circuits 20 sequentially output pulse signals according to the received driving signals, and in each clock signal period, the plurality of gate driving circuits One of the gate driving circuits 20 in 20 outputs a pulse signal.
  • the control circuit 10 outputs the n channels of control signals Enable 1 to Enable n to the controlled ends of the first switching tube to the nth switching tube to control the first switching tube to the nth switching tube.
  • the tubes are turned on sequentially. And when any one of the n switching tubes 30 connected to each gate driving circuit 20 is turned on, the remaining n-1 switching tubes 30 are turned off. For example, when Enable 1 is at a high level and Enable 2 to Enable n are at a low level, the first switch tube is turned on, and the second switch tube to the nth switch tube are turned off.
  • Enable 2 When Enable 2 is high, Enable 1, Enable 3 to Enable n are low, the second switching tube is turned on, and the remaining n-1 switching tubes are turned off.
  • Enable n When Enable n is high, Enable 1 to Enable n-1 are low, the n-th switch tube is turned on, and the remaining n-1 switches are turned off.
  • one of the gate driving circuits 20 sequentially outputs the 1/n pulse signal through the n switching tubes to sequentially drive the n continuously arranged scan lines. It can be understood that when one of the gate driving circuits 20 generates a pulse signal, the gate driving circuit 20 divides the pulse signal into n segments. When the n switching tubes connected to the gate driving circuit 20 are turned on sequentially, the gate driving circuit 20 sequentially outputs n segments of pulse signals through the n switching tubes to sequentially drive the n switching tubes connected to the n switching tubes. Scan lines set continuously.
  • the gate driving circuit 20 first transmits the 1/n pulse signal Output through the first switching tube to drive the scan line connected to the first switching tube; then, when the second switching tube is turned on, the gate driving circuit 20 transmits another 1/n pulse signal through the second switching tube Output to drive the scan line connected to the second switching tube; and so on, when the nth switching tube is turned on, the last 1/n pulse signal is output through the nth switching tube to drive the nth switching tube Scan line.
  • a gate driving circuit 20 can sequentially drive n continuously arranged scanning lines, thereby reducing the number of gate driving circuits 20 on the display panel and reducing the number of gate driving circuits 20.
  • the width is beneficial to the manufacture of display devices with narrow bezels, and even display devices without bezels.
  • the display panel may be any of the following: liquid crystal display panel, OLED display panel, QLED display panel, twisted nematic (TN) or super twisted nematic (STN) type, plane switching (In -Plane Switching, IPS) type, Vertical Alignment (VA) type, curved panel, or other display panels.
  • TN twisted nematic
  • STN super twisted nematic
  • IPS plane switching
  • VA Vertical Alignment
  • the present application also provides a display device, which includes the display panel described above.
  • a display device which includes the display panel described above.
  • the display panel described above.
  • the embodiment of the display device of the present application includes the above-mentioned display All the technical solutions of all the embodiments of the panel, and the achieved technical effects are also completely the same, and will not be repeated here.
  • the display device may be a display device with a display panel such as a television, a tablet computer, a mobile phone, and the like.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板的驱动电路、显示面板及显示装置，显示面板的驱动电路包括控制电路(10)、多个栅极驱动电路(20)、多个开关管(30)，其中，每个栅极驱动电路(20)均设有多个输出端；多个栅极驱动电路(20)的输入端均与控制电路(10)的信号输出端连接，每个栅极驱动电路(20)的多个输出端与多个开关管(30)的输入端一一对应连接，多个开关管(30)的受控端均与控制电路(10)的控制端连接，多个开关管(30)的输出端与多条扫描线一一对应连接。

Description

显示面板的驱动电路、显示面板及显示装置
相关申请的交叉引用
本申请要求于2019年6月11日提交中国专利局、申请号为201910503771.5、申请名称为“显示面板的驱动电路、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板的驱动电路、显示面板及显示装置。
背景技术
GOA是Gate Driver on Array的简称，是阵列基板上栅驱动集成的意思，能实现显示面板上逐行扫描驱动功能。GOA技术，就是将水平扫描线的驱动电路制作在显示面板的显示区周围的基板上，使之能替代外接集成电路板完成水平扫描线的驱动。
然而，在传统的GOA电路中，一个GOA电路驱动一条水平扫描线，GOA电路数量过多，将不利于窄边框显示装置甚至无边框显示装置的设计。
发明概述
技术问题
问题的解决方案
技术解决方案
本申请提供一种显示面板的驱动电路、显示面板及显示装置，旨在减少栅极驱动电路的数量。
为实现上述目的，本申请提供一种显示面板的驱动电路，所述显示面板的驱动电路包括：
控制电路，被配置为输出驱动信号及控制信号；
多个栅极驱动电路，每个所述栅极驱动电路均设有多个输出端，所述多个栅极驱动电路的输入端均与所述控制电路的信号输出端连接；所述多个栅极驱动电 路，被配置为接收所述驱动信号，依次输出脉冲信号；其中，在每个时钟信号周期，所述多个栅极驱动电路的其中一个栅极驱动电路输出脉冲信号；
多个开关管，每个所述栅极驱动电路的多个输出端与所述多个开关管的输入端一一对应连接，所述多个开关管的受控端均与所述控制电路的控制端连接，所述多个开关管的输出端与多条扫描线一一对应连接；所述多个开关管，被配置为根据所述控制电路输出的控制信号依次导通，使所述栅极驱动电路输出的脉冲信号依次驱动所述多条扫描线。
为实现上述目的，本申请还提供一种显示面板，所述显示面板包括：驱动电路；
所述驱动电路包括：控制电路，被配置为输出驱动信号及控制信号；
多个栅极驱动电路，每个所述栅极驱动电路均设有多个输出端，所述多个栅极驱动电路的输入端均与所述控制电路的信号输出端连接；所述多个栅极驱动电路，被配置为接收所述驱动信号，依次输出脉冲信号；其中，在每个时钟信号周期，所述多个栅极驱动电路的其中一个栅极驱动电路输出脉冲信号；
多个开关管，每个所述栅极驱动电路的多个输出端与所述多个开关管的输入端一一对应连接，所述多个开关管的受控端均与所述控制电路的控制端连接，所述多个开关管的输出端与多条扫描线一一对应连接；所述多个开关管，被配置为根据所述控制电路输出的控制信号依次导通，使所述栅极驱动电路输出的脉冲信号依次驱动所述多条扫描线。
为实现上述目的，本申请还提供一种显示装置，所述显示装置包括：显示面板，所述显示面板包括：驱动电路；
所述驱动电路包括：控制电路，被配置为输出驱动信号及控制信号；
多个栅极驱动电路，每个所述栅极驱动电路均设有多个输出端，所述多个栅极驱动电路的输入端均与所述控制电路的信号输出端连接；所述多个栅极驱动电路，被配置为接收所述驱动信号，依次输出脉冲信号；其中，在每个时钟信号周期，所述多个栅极驱动电路的其中一个栅极驱动电路输出脉冲信号；
多个开关管，每个所述栅极驱动电路的多个输出端与所述多个开关管的输入端一一对应连接，所述多个开关管的受控端均与所述控制电路的控制端连接，所 述多个开关管的输出端与多条扫描线一一对应连接；所述多个开关管，被配置为根据所述控制电路输出的控制信号依次导通，使所述栅极驱动电路输出的脉冲信号依次驱动所述多条扫描线。
本申请的技术方案，设置每个栅极驱动电路通过n个开关管连接n条连续设置的扫描线；在每个时钟信号周期，控制电路控制n个开关管依次导通；进一步的，当其中一个栅极驱动电路产生脉冲信号，该栅极驱动电路先将1/n脉冲信号经导通的开关管输出，以驱动与导通的所述开关管连接的扫描线；在下一个开关管导通时，再以另一个1/n脉冲信号驱动另一条扫描线，以此类推，直至在一个时钟信号周期内，一个栅极驱动电路依次驱动n条连续设置的扫描线。如此设置，能够减少显示面板上的栅极驱动电路的数量，缩减栅极侧的宽度，有利于制作窄边框的显示装置甚至无边框的显示装置。
发明的有益效果
对附图的简要说明
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板的驱动电路一实施例的电路结构示意图；
图2为本申请显示面板的驱动电路一示例性实施例的电路结构示意图；
图3为图2所述的显示面板的驱动电路的效果示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
本申请的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示(诸如上、下、左、右、前、 后......)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种显示面板的驱动电路。
参照图1，所述显示面板的驱动电路包括控制电路10、多个栅极驱动电路20、多个开关管30，其中，每个栅极驱动电路20均设有多个输出端；所述多个栅极驱动电路20的输入端均与所述控制电路10的信号输出端连接，每个所述栅极驱动电路20的多个输出端与多个开关管30的输入端一一对应连接，所述多个开关管30的受控端均与所述控制电路10的控制端连接，所述多个开关管30的输出端与多条扫描线一一对应连接。
所述多个栅极驱动电路20，可选为多个GOA电路。所述GOA电路就是在控制电路10(例如时序控制器)仅提供几路驱动信号的基础上，采用与制作出主动开关同样的工艺制作出的，所述主动开关可选为薄膜晶体管。所述GOA电路用于驱动行扫描线的电路。所述GOA电路在控制电路10的驱动信号的作用下产生移位脉冲信号，从而驱动当前行的像素，以使得主动开关打开，所述驱动信号至少包括相位相反的信号对CKV和CKVB、栅关闭信号VSS，例如-8V的VSS。
本实施例中，每个栅极驱动电路20均设有n个输出端，栅极驱动电路20的每个输出端均通过一个开关管30与一条扫描线连接。其中，n为大于或者等于2的整数，例如，所述n可选为2、3、4、5等。当然n还可根据电路板的空间大小设置。
本实施例中，多个栅极驱动电路20接收控制电路10输出的驱动信号，并根据接 收到的驱动信号依次输出脉冲信号。并且，在每个时钟信号周期，多个栅极驱动电路20中的其中一个栅极驱动电路20输出脉冲信号，而其余的栅极驱动电路20无输出。
为了更好的说明本申请的发明构思，将每个栅极驱动电路20连接的n个开关管，该n个开关管分别以第一开关管至第n开关管表示，第一开关管至第n开关管分别与n条连续设置的扫描线连接。
具体的，控制电路10输出驱动信号至多个栅极驱动电路20，多个栅极驱动电路20根据接收到的驱动信号依次输出脉冲信号，且在每个时钟信号周期，多个栅极驱动电路20中的其中一个栅极驱动电路20输出脉冲信号。
同时，在每个时钟信号周期，控制电路10将n路控制信号Enable 1至Enable n，分别输出至第一开关管至第n开关管的受控端，以控制第一开关管至第n开关管依次导通。且在每个栅极驱动电路20所连接的n个开关管30中的任一开关管30导通时，剩余的n-1个开关管30关闭。例如，在Enable 1为高电平时，Enable 2至Enable n为低电平，则第一开关管导通，第二开关管至第n开关管关闭。在Enable 2为高电平时，Enable 1、Enable 3至Enable n为低电平，第二开关管导通，剩余的n-1个开关管关闭。依次类推，在Enable n为高电平时，Enable 1至Enable n-1为低电平，第n开关管导通，剩余的n-1个开关管关闭。在其他实施例中，也可以设置各个开关管30在接收到的控制信号为低电平时导通，此处不限。
并且，在n个开关管依次导通时，其中一个栅极驱动电路20依次将1/n脉冲信号经n个开关管输出，以依次驱动n条连续设置的扫描线。可以理解为，当其中一个栅极驱动电路20产生脉冲信号，该栅极驱动电路20将该脉冲信号分为n段。当与该栅极驱动电路20连接的n个开关管依次导通时，该栅极驱动电路20依次将n段脉冲信号经n个开关管输出，以依次驱动与该n个开关管连接的n条连续设置的扫描线。例如，若第一开关管至第n开关管依次导通，当在第一开关管导通时且其中一个栅极驱动电路20产生脉冲信号，该栅极驱动电路20先将1/n脉冲信号经第一开关管输出，以驱动与第一开关管连接的扫描线；接着，在第二开关管导通时，该栅极驱动电路20再将另一个1/n脉冲信号经第二开关管输出，以驱动与 第二开关管连接的扫描线；以此类推，在第n开关管导通时，将最后1/n脉冲信号经第n开关管输出，以驱动与第n开关管连接的扫描线。通过这样的设置方式使得在每个时钟信号周期，一个栅极驱动电路20能够依次驱动n条连续设置的扫描线，从而能够减少显示面板上栅极驱动电路20的数量，缩减栅极驱动电路20的宽度，有利于制作窄边框的显示装置，甚至无边框的显示装置。
为了更好了阐述本申请的发明构思，下面以每个栅极驱动电路均具有2个输出端，每个输出端均通过一个开关管连接一条扫描线为例阐述本申请的发明构思。
参照图2以及图3，设定CK1和CK2为两个时钟信号周期，Enable1和Enable2为控制电路10输出两路控制信号。Gate1～Gate4为连续设置的四条扫描线。Gate1与Gate2经两个开关管30与一个栅极驱动电路20连接。Gate3与Gate4经两个开关管与另外一个栅极驱动电路20连接。在CK1时钟信号周期的前半个时钟信号周期，控制电路10输出的控制信号Enable1为高电平，Enable2为低电平，与Gate1以及Gate3连接的两个开关管30导通，与Gate2以及Gate4连接的两个开关管30关闭。在CK1时钟信号周期的后半个时钟信号周期，控制电路10输出的控制信号Enable1为低电平，Enable2为高电平，与Gate1以及Gate3连接的两个开关管30关闭，与Gate2以及Gate4连接的两个开关管30导通。与此同时，在CK1时钟信号周期，与Gate1以及Gate2连接的栅极驱动电路20产生脉冲信号。在CK1时钟信号周期的前半个时钟信号周期，栅极驱动电路20将前半段脉冲信号经与扫描线Gate1连接的开关管30输出，以驱动扫描线Gate1。在CK1时钟信号周期的后半个时钟信号周期，栅极驱动电路20将后半段脉冲信号经与扫描线Gate2连接的开关管30输出，以驱动扫描线Gate2。通过这样的设置方式实现了在一个时钟信号周期内，通过一个栅极驱动电路20驱动两条扫描线的目的。以此类推，在下一个时钟信号周期，例如CK2时钟信号周期，另一个栅极驱动电路20输出脉冲信号。在CK2时钟信号周期的前半个时钟信号周期，该栅极驱动电路20将脉冲信号的前半段脉冲信号输出至扫描线Gate3，以驱动扫描线Gate3。在CK2时钟信号周期的后半个时钟信号周期，该栅极驱动电路20将后半段脉冲信号输出至扫描线Gate4，以驱动扫描线Gate4。
本申请的技术方案是每个栅极驱动电路20通过n个开关管连接n条连续设置的扫描线。在每个时钟信号周期，控制电路10控制n个开关管依次导通。当其中一个栅极驱动电路20产生脉冲信号，该栅极驱动电路20先将1/n脉冲信号经导通的开关管输出，以驱动与所导通的开关管连接的扫描线。在下一个开关管导通时，该栅极驱动电路20再将另一个1/n脉冲信号经该导通的开关管输出，以驱动另一条扫描线。以此类推，直至在一个时钟信号周期内，一个栅极驱动电路20依次驱动n条连续设置的扫描线。通过这样的设置方式能够减少显示面板上的栅极驱动电路20的数量，缩减栅极侧的宽度，有利于制作窄边框的显示装置甚至无边框的显示装置。
在一实施例中，参照图1，所述开关管30可选为N型绝缘性场效应管，所述N型绝缘性场效应管的漏极与所述栅极驱动电路的输出端连接，所述N型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述N型绝缘性场效应管的源极与所述扫描线连接。
所述N型绝缘性场效应管为高电平导通的开关管，每个栅极驱动电路20的n个输出端分别连接n个N型绝缘性场效应管。
在每个时钟信号周期，n个N型绝缘性场效应管根据控制电路10输出的控制信号依次导通。并且，每个栅极驱动电路20所连接的n个N型绝缘性场效应管中的任意一个N型绝缘性场效应管导通时，剩余的n-1个N型绝缘性场效应管关闭，使栅极驱动电路20能够通过导通的开关管30驱动与该导通的开关管30连接的扫描线。因此，由于n个开关管依次导通，则当其中一个栅极驱动电路20产生脉冲信号时，该栅极驱动电路20能够依次驱动多条连续设置的扫描线，实现逐行扫描的作用。
在其他实施例中，所述开关管30还可以为三极管、P型绝缘性场效应管等，此处不限。在所述开关管为P型绝缘性场效应管时，所述P型绝缘性场效应管的源极与所述栅极驱动电路的输出端连接，所述P型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述P型绝缘性场效应管的漏极与所述扫描线连接。
本申请还提供一种显示面板，所述显示面板包括显示面板的驱动电路及主动开关。所述显示面板的驱动电路包括控制电路10、多个栅极驱动电路20、多个开 关管30，其中，每个栅极驱动电路20均设有多个输出端；所述多个栅极驱动电路20的输入端均与所述控制电路10的信号输出端连接，每个所述栅极驱动电路20的多个输出端与多个开关管30的输入端一一对应连接，所述多个开关管30的受控端均与所述控制电路10的控制端连接，所述多个开关管30的输出端与多条扫描线一一对应连接。
所述多个栅极驱动电路20，可选为多个GOA电路。所述GOA电路就是在控制电路10(例如时序控制器)仅提供几路驱动信号的基础上，采用与制作出主动开关同样的工艺制作出的，所述主动开关可选为薄膜晶体管。所述GOA电路用于驱动行扫描线的电路。所述GOA电路在控制电路10的驱动信号的作用下产生移位脉冲信号，从而驱动当前行的像素，以使得主动开关打开，所述驱动信号至少包括相位相反的信号对CKV和CKVB、栅关闭信号VSS，例如-8V的VSS。
本实施例中，每个栅极驱动电路20均设有n个输出端，栅极驱动电路20的每个输出端均通过一个开关管30与一条扫描线连接。其中，n为大于或者等于2的整数，例如，所述n可选为2、3、4、5等。当然n还可根据电路板的空间大小设置。
本实施例中，多个栅极驱动电路20接收控制电路10输出的驱动信号，并根据接收到的驱动信号依次输出脉冲信号。并且，在每个时钟信号周期，多个栅极驱动电路20中的其中一个栅极驱动电路20输出脉冲信号，而其余的栅极驱动电路20无输出。
为了更好的说明本申请的发明构思，将每个栅极驱动电路20连接的n个开关管，该n个开关管分别以第一开关管至第n开关管表示，第一开关管至第n开关管分别与n条连续设置的扫描线连接。
具体的，控制电路10输出驱动信号至多个栅极驱动电路20，多个栅极驱动电路20根据接收到的驱动信号，依次输出脉冲信号，且在每个时钟信号周期，多个栅极驱动电路20中的其中一个栅极驱动电路20输出脉冲信号。
同时，在每个时钟信号周期，控制电路10将n路控制信号Enable 1至Enable n，分别输出至第一开关管至第n开关管的受控端，以控制第一开关管至第n开关管依次导通。且在每个栅极驱动电路20所连接的n个开关管30中的任一开关管30导 通时，剩余的n-1个开关管30关闭。例如，在Enable 1为高电平时，Enable 2至Enable n为低电平，则第一开关管导通，第二开关管至第n开关管关闭。在Enable 2为高电平时，Enable 1、Enable 3至Enable n为低电平，第二开关管导通，剩余的n-1个开关管关闭。依次类推，在Enable n为高电平时，Enable 1至Enable n-1为低电平，第n开关管导通，剩余的n-1个开关管关闭。在其他实施例中，也可以设置其他的开关管30接收到的控制信号为低电平时导通，此处不限。
并且，在n个开关管依次导通时，其中一个栅极驱动电路20依次将1/n脉冲信号经n个开关管输出，以依次驱动n条连续设置的扫描线。可以理解为，当其中一个栅极驱动电路20产生脉冲信号，该栅极驱动电路20将该脉冲信号分为n段。当与该栅极驱动电路20连接的n个开关管依次导通时，该栅极驱动电路20依次将n段脉冲信号经n个开关管输出，以依次驱动与该n个开关管连接的n条连续设置的扫描线。例如，若第一开关管至第n开关管依次导通，当在第一开关管导通时且其中一个栅极驱动电路20产生脉冲信号，该栅极驱动电路20先将1/n脉冲信号经第一开关管输出，以驱动与第一开关管连接的扫描线；接着，在第二开关管导通时，该栅极驱动电路20再将另一个1/n脉冲信号经第二开关管输出，以驱动与第二开关管连接的扫描线；以此类推，在第n开关管导通时，将最后1/n脉冲信号经第n开关管输出，以驱动与第n开关管连接的扫描线。通过这样的设置方式使得在每个时钟信号周期，一个栅极驱动电路20能够依次驱动n条连续设置的扫描线，从而能够减少显示面板上栅极驱动电路20的数量，缩减栅极驱动电路20的宽度，有利于制作窄边框的显示装置，甚至无边框的显示装置。
所述显示面板可以为以下任一种：液晶显示面板、OLED显示面板、QLED显示面板、扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型，平面转换(In-Plane Switching，IPS)型、垂直配向(Vertical Alignment，VA)型、曲面型面板、或其他显示面板。
本申请还提供一种显示装置，所述显示装置包括如上所述的显示面板。该显示面板的详细结构可参照上述实施例，此处不再赘述；可以理解的是，由于在本申请的显示装置中使用了上述显示面板，因此，本申请的显示装置的实施例包 括上述显示面板全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
本实施例中，显示装置可以是电视机、平板电脑、手机等具有显示面板的显示装置。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (17)

  1. 一种显示面板的驱动电路，其中，所述显示面板的驱动电路包括：
    控制电路，被配置为输出驱动信号及控制信号；
    多个栅极驱动电路，每个所述栅极驱动电路均设有多个输出端，所述多个栅极驱动电路的输入端均与所述控制电路的信号输出端连接；所述多个栅极驱动电路，被配置为接收所述驱动信号，依次输出脉冲信号；其中，在每个时钟信号周期，所述多个栅极驱动电路的其中一个栅极驱动电路输出脉冲信号；
    多个开关管，每个所述栅极驱动电路的多个输出端与所述多个开关管的输入端一一对应连接，所述多个开关管的受控端均与所述控制电路的控制端连接，所述多个开关管的输出端与多条扫描线一一对应连接；所述多个开关管，被配置为根据所述控制电路输出的控制信号依次导通，使所述栅极驱动电路输出的脉冲信号依次驱动所述多条扫描线。
  2. 如权利要求1所述的显示面板的驱动电路，其中，每个所述栅极驱动电路均设有n个输出端，所述栅极驱动电路的n个输出端分别与n个开关管的输入端对应连接，所述n个开关管的输出端分别与n条连续设置的扫描线对应连接，所述n个开关管的受控端均与所述控制电路的控制端连接；其中，所述n为大于等于2的整数。
  3. 如权利要求2所述的显示面板的驱动电路，其中，在每个时钟信号周期，所述控制电路控制所述n个开关管依次导通。
  4. 如权利要求3所述的显示面板的驱动电路，其中，在所述n个开关管中的任一开关管导通时，剩余的n-1个开关管关闭。
  5. 如权利要求4所述的显示面板的驱动电路，其中，在任一所述开关管导通时，所述栅极驱动电路将1/n脉冲信号输出至与所述开关管连接的扫描线，以驱动所述扫描线。
  6. 如权利要求1所述的显示面板的驱动电路，其中，所述开关管为N 型绝缘性场效应管，所述N型绝缘性场效应管的漏极与所述栅极驱动电路的输出端连接，所述N型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述N型绝缘性场效应管的源极与所述扫描线连接。
  7. 如权利要求2所述的显示面板的驱动电路，其中，所述开关管为N型绝缘性场效应管，所述N型绝缘性场效应管的漏极与所述栅极驱动电路的输出端连接，所述N型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述N型绝缘性场效应管的源极与所述扫描线连接。
  8. 如权利要求1所述的显示面板的驱动电路，其中，所述开关管为P型绝缘性场效应管，所述P型绝缘性场效应管的源极与所述栅极驱动电路的输出端连接，所述P型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述P型绝缘性场效应管的漏极与所述扫描线连接。
  9. 如权利要求2所述的显示面板的驱动电路，其中，在每个时钟信号周期内，所述n个开关管中接收到的控制信号为高电平的所述开关管导通，接收到的控制信号为低电平的所述开关管关闭。
  10. 一种显示面板，其中，所述显示面板包括：驱动电路，所述驱动电路包括：控制电路，被配置为输出驱动信号及控制信号；
    多个栅极驱动电路，每个所述栅极驱动电路均设有多个输出端，所述多个栅极驱动电路的输入端均与所述控制电路的信号输出端连接；所述多个栅极驱动电路，被配置为接收所述驱动信号，依次输出脉冲信号；其中，在每个时钟信号周期，所述多个栅极驱动电路的其中一个栅极驱动电路输出脉冲信号；
    多个开关管，每个所述栅极驱动电路的多个输出端与所述多个开关管的输入端一一对应连接，所述多个开关管的受控端均与所述控制电路的控制端连接，所述多个开关管的输出端与多条扫描线一一对应连接；所述多个开关管，被配置为根据所述控制电路输 出的控制信号依次导通，使所述栅极驱动电路输出的脉冲信号依次驱动所述多条扫描线。
  11. 如权利要求10所述的显示面板，其中，所述显示面板上设有主动开关，所述主动开关经扫描线与所述驱动电路连接。
  12. 如权利要求10所述的显示面板，其中，每个所述栅极驱动电路均设有n个输出端，所述栅极驱动电路的n个输出端分别与n个开关管的输入端对应连接，所述n个开关管的输出端分别与n条连续设置的扫描线对应连接，所述n个开关管的受控端均与所述控制电路的控制端连接；其中，所述n为大于等于2的整数。
  13. 如权利要求12所述的显示面板，其中，在每个时钟信号周期，所述控制电路控制所述n个开关管依次导通。
  14. 一种显示装置，其中，所述显示装置包括：显示面板，所述显示面板包括：驱动电路；所述驱动电路包括：控制电路，被配置为输出驱动信号及控制信号；
    多个栅极驱动电路，每个所述栅极驱动电路均设有多个输出端，所述多个栅极驱动电路的输入端均与所述控制电路的信号输出端连接；所述多个栅极驱动电路，被配置为接收所述驱动信号，依次输出脉冲信号；其中，在每个时钟信号周期，所述多个栅极驱动电路的其中一个栅极驱动电路输出脉冲信号；
    多个开关管，每个所述栅极驱动电路的多个输出端与所述多个开关管的输入端一一对应连接，所述多个开关管的受控端均与所述控制电路的控制端连接，所述多个开关管的输出端与多条扫描线一一对应连接；所述多个开关管，被配置为根据所述控制电路输出的控制信号依次导通，使所述栅极驱动电路输出的脉冲信号依次驱动所述多条扫描线；
    所述显示面板上设有主动开关，所述主动开关经扫描线与所述驱动电路连接；
    每个所述栅极驱动电路均设有n个输出端，所述栅极驱动电路的n 个输出端分别与n个开关管的输入端对应连接，所述n个开关管的输出端分别与n条连续设置的扫描线对应连接，所述n个开关管的受控端均与所述控制电路的控制端连接；其中，所述n为大于等于2的整数；
    在每个时钟信号周期，所述控制电路控制所述n个开关管依次导通；
    在任一所述开关管导通时，所述栅极驱动电路将1/n脉冲信号输出至与所述开关管连接的扫描线，以驱动所述扫描线。
  15. 如权利要求14所述的显示面板的驱动电路，其中，所述开关管为N型绝缘性场效应管，所述N型绝缘性场效应管的漏极与所述栅极驱动电路的输出端连接，所述N型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述N型绝缘性场效应管的源极与所述扫描线连接。
  16. 如权利要求14所述的显示面板的驱动电路，其中，所述开关管为P型绝缘性场效应管，所述P型绝缘性场效应管的源极与所述栅极驱动电路的输出端连接，所述P型绝缘性场效应管的栅极与所述控制电路的控制端连接，所述P型绝缘性场效应管的漏极与所述扫描线连接。
  17. 如权利要求14所述的显示面板的驱动电路，其中，在每个时钟信号周期内，所述n个开关管中接收到的控制信号为高电平的所述开关管导通，接收到的控制信号为低电平的所述开关管关闭。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110910775A (zh) * 2019-11-26 2020-03-24 深圳市华星光电半导体显示技术有限公司 一种显示装置
CN111063316A (zh) * 2020-01-17 2020-04-24 Tcl华星光电技术有限公司 驱动电路及其应用的显示面板
US11043175B1 (en) 2020-01-17 2021-06-22 Tcl China Star Optoelectronics Technology Co., Ltd. Driving circuit and display panel used therefor
CN113066417B (zh) * 2021-03-25 2023-01-17 重庆惠科金渝光电科技有限公司 栅极驱动电路、驱动装置和显示装置
CN114639361B (zh) * 2022-04-26 2023-04-28 长沙惠科光电有限公司 栅极驱动电路和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110254831A1 (en) * 2010-04-16 2011-10-20 Chunghwa Picture Tubes, Ltd. Scan drive control system and method for liquid crystal panel and computer program product thereof
CN202075968U (zh) * 2011-06-02 2011-12-14 北京京东方光电科技有限公司 液晶显示模块
CN202084275U (zh) * 2011-06-15 2011-12-21 北京京东方光电科技有限公司 一种显示装置、显示面板及显示面板驱动装置
CN202210402U (zh) * 2011-09-22 2012-05-02 京东方科技集团股份有限公司 一种驱动单元、显示面板和液晶显示器
CN102446498A (zh) * 2010-10-12 2012-05-09 北京京东方光电科技有限公司 液晶显示器的驱动装置和驱动方法
CN202473182U (zh) * 2012-03-23 2012-10-03 北京京东方光电科技有限公司 一种平板显示装置
CN109410885A (zh) * 2018-12-27 2019-03-01 信利半导体有限公司 扫描驱动电路、像素阵列基板及显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060076480A (ko) * 2004-12-29 2006-07-04 엘지.필립스 엘시디 주식회사 액정 표시장치의 구동장치
CN102621758B (zh) * 2012-04-16 2015-07-01 深圳市华星光电技术有限公司 液晶显示装置及其驱动电路
CN102866551B (zh) * 2012-10-11 2015-04-15 深圳市华星光电技术有限公司 液晶显示装置及其驱动电路
CN107833557B (zh) * 2017-11-20 2019-05-31 深圳市华星光电半导体显示技术有限公司 Amoled显示器及其驱动方法
CN109119043A (zh) * 2018-09-30 2019-01-01 惠科股份有限公司 显示面板及其驱动方法、显示装置
CN109559676A (zh) * 2018-12-18 2019-04-02 深圳市奥拓电子股份有限公司 Led显示驱动电路及led显示屏

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110254831A1 (en) * 2010-04-16 2011-10-20 Chunghwa Picture Tubes, Ltd. Scan drive control system and method for liquid crystal panel and computer program product thereof
CN102446498A (zh) * 2010-10-12 2012-05-09 北京京东方光电科技有限公司 液晶显示器的驱动装置和驱动方法
CN202075968U (zh) * 2011-06-02 2011-12-14 北京京东方光电科技有限公司 液晶显示模块
CN202084275U (zh) * 2011-06-15 2011-12-21 北京京东方光电科技有限公司 一种显示装置、显示面板及显示面板驱动装置
CN202210402U (zh) * 2011-09-22 2012-05-02 京东方科技集团股份有限公司 一种驱动单元、显示面板和液晶显示器
CN202473182U (zh) * 2012-03-23 2012-10-03 北京京东方光电科技有限公司 一种平板显示装置
CN109410885A (zh) * 2018-12-27 2019-03-01 信利半导体有限公司 扫描驱动电路、像素阵列基板及显示面板

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