WO2017084110A1 - 薄膜晶体管阵列面板及其制作方法 - Google Patents

薄膜晶体管阵列面板及其制作方法 Download PDF

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Publication number
WO2017084110A1
WO2017084110A1 PCT/CN2015/095418 CN2015095418W WO2017084110A1 WO 2017084110 A1 WO2017084110 A1 WO 2017084110A1 CN 2015095418 W CN2015095418 W CN 2015095418W WO 2017084110 A1 WO2017084110 A1 WO 2017084110A1
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Prior art keywords
layer
buffer layer
thin film
film transistor
transistor array
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PCT/CN2015/095418
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English (en)
French (fr)
Inventor
胡国仁
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/904,954 priority Critical patent/US10141341B2/en
Publication of WO2017084110A1 publication Critical patent/WO2017084110A1/zh
Priority to US15/937,866 priority patent/US10204923B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/07—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 buffer layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array panel and a method of fabricating the same.
  • Traditional flexible display generally includes a flexible substrate, which is generally thin and cannot be directly processed on the flexible substrate. Therefore, conventional flexible displays generally need to be fixed on a glass substrate to perform a corresponding process.
  • the thermal expansion coefficient of the glass substrate and the flexible substrate are different. Therefore, the phenomenon of warpage/bending of the glass substrate may occur during the fabrication of the flexible substrate, which is disadvantageous for the process of the flexible substrate.
  • An object of the present invention is to provide a thin film transistor array panel and a manufacturing method thereof, which can effectively reduce (slow) the stress of the flexible substrate and prevent excessive stress of the flexible substrate.
  • a thin film transistor array panel comprising: a flexible substrate; a buffer layer, wherein the buffer layer is disposed on the flexible substrate, wherein the buffer layer is provided with a stress relieving portion, and the stress relieving portion is used And mitigating the stress of the flexible substrate; the display device layer, the display device layer is disposed on the buffer layer; the stress relieving portion includes at least one recessed portion and/or at least one raised portion, at least one of the recesses And/or at least one of the raised portions are arranged in a one-dimensional array or a two-dimensional array; or the stress relieving portion comprises at least one groove and/or at least one rib, at least one of the grooves and/or Or at least one of the ribs is arranged in a one-dimensional array or a two-dimensional array.
  • the stress relieving portion is formed by a mask process and/or an etching process, and the stress relieving portion is disposed on a side of the buffer layer facing the display device layer;
  • the stress relieving portion is formed by coating a photoresist material on the flexible substrate and patterning the photoresist material to obtain a photoresist block corresponding to the size, shape, and area of the stress relieving portion to be formed, and then Forming a material layer corresponding to the buffer layer on the photoresist block and the flexible substrate, and finally removing the photoresist block, wherein the stress relieving portion is disposed on the buffer layer facing away from the buffer layer On one side of the display device layer.
  • a thin film transistor array panel comprising: a flexible substrate; a buffer layer, wherein the buffer layer is disposed on the flexible substrate, wherein the buffer layer is provided with a stress relieving portion, and the stress relieving portion is used And mitigating stress of the flexible substrate; displaying a device layer, the display device layer being disposed on the buffer layer.
  • the thin film transistor array panel further includes: a first protective layer, the first protective layer is disposed on the flexible substrate, and the buffer layer is disposed on the first protective layer.
  • the display device layer includes a second protective layer and a display unit component layer, the second protective layer is disposed on the buffer layer, and the second protective layer covers the buffer layer, The display unit component layer is disposed on the second protective layer.
  • the stress relieving portion includes at least one recessed portion and/or at least one raised portion; at least one of the depressed portion and/or at least one of the raised portions is in a one-dimensional array or two-dimensional Arranged in the form of an array.
  • the second protective layer fills at least one of the depressed portion and a gap between the two raised portions.
  • the stress relieving portion includes at least one groove and/or at least one ridge; at least one of the grooves and/or at least one of the ribs in a one-dimensional array or a two-dimensional array Formal arrangement.
  • the second protective layer fills at least one of the groove and a gap between the two ridges.
  • the stress relieving portion is formed by a mask process and/or an etching process; the stress relieving portion is disposed on a side of the buffer layer facing the display device layer.
  • the stress relieving portion is formed by coating a photoresist material on the flexible substrate and patterning the photoresist material to obtain a size and a shape of a stress relieving portion to be formed. a photoresist block corresponding to an area, and then forming a material layer corresponding to the buffer layer on the photoresist block and the flexible substrate, and finally removing the photoresist block; the stress relieving portion And disposed on a side of the buffer layer facing away from the display device layer.
  • a method for fabricating a thin film transistor array panel comprising the steps of: A, disposing the buffer layer on the flexible substrate; B, disposing the stress relieving portion on the buffer layer, wherein The stress relieving portion is for slowing the stress of the flexible substrate; C. disposing the display device layer on the buffer layer.
  • a first protective layer is disposed between the flexible substrate and the buffer layer.
  • the display device layer includes a second protective layer and a display unit component layer, the second protective layer is disposed on the buffer layer, and the second protective layer covers the a buffer layer, the display unit component layer being disposed on the second protective layer.
  • the stress relieving portion includes at least one recessed portion and/or at least one raised portion; at least one of the depressed portion and/or at least one of the raised portions is in a one-dimensional array Or in the form of a two-dimensional array.
  • the second protective layer fills at least one of the depressed portion and a gap between the two raised portions.
  • the stress relieving portion includes at least one groove and/or at least one ridge; at least one of the grooves and/or at least one of the ribs in a one-dimensional array or two The arrangement of the dimension arrays.
  • the second protective layer fills at least one of the groove and a gap between the two ridges.
  • the step B includes: b1, performing a mask process and/or an etching process on the buffer layer to form the stress relieving portion on the buffer layer;
  • the stress relieving portion is disposed on a side of the buffer layer facing the display device layer.
  • the step B includes: b2, coating a photoresist material on the flexible substrate; b3, patterning the photoresist material to obtain a stress mitigation portion to be formed a photoresist block corresponding in size, shape, and area; b4, forming a material layer corresponding to the buffer layer on the photoresist block and the flexible substrate; b5, removing the photoresist block; The mitigation portion is disposed on a side of the buffer layer facing away from the display device layer.
  • the present invention can effectively reduce (slow) the stress of the flexible substrate, avoid excessive stress of the flexible substrate, and thereby facilitate avoiding the flexible substrate or the glass substrate used for fabricating the flexible substrate. Warping/bending, which in turn helps to improve the accuracy of the yellow alignment process.
  • FIG. 1 is a schematic view of a first embodiment of a thin film transistor array panel of the present invention
  • FIG. 2 is a schematic view showing a second embodiment of a thin film transistor array panel of the present invention.
  • FIG. 3 is a schematic view showing a third embodiment of a thin film transistor array panel of the present invention.
  • FIGS. 1 to 3 are top views of different forms of buffer layers in the thin film transistor array panel of FIGS. 1 to 3;
  • FIG. 8 is a flow chart of a method of fabricating a thin film transistor array panel of the present invention.
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel), AMOLED (Active Matrix Organic Light Emitting) Diode, organic light-emitting two-body display panel), organic light-emitting lighting panels, etc.
  • TFT-LCD Thin Film Transistor Liquid
  • AMOLED Active Matrix Organic Light Emitting
  • Diode organic light-emitting two-body display panel
  • organic light-emitting lighting panels etc.
  • FIG. 1 is a schematic view of a first embodiment of a thin film transistor array panel of the present invention
  • FIG. 2 is a schematic view of a second embodiment of the thin film transistor array panel of the present invention
  • FIGS. 4 through 7 are top views of different forms of buffer layer 102 in the thin film transistor array panel of FIGS. 1 through 3.
  • the thin film transistor array panel of the present embodiment includes a flexible substrate 101, a first protective layer 104, a buffer layer 102, and a display device layer 103.
  • the first protective layer 104 is disposed on the flexible substrate 101, and the buffer layer 102 is disposed on the flexible substrate 101. Specifically, the buffer layer 102 is disposed on the first protective layer 104.
  • the buffer layer 102 is provided with a stress relieving portion for mitigating stress of the flexible substrate 101.
  • the display device layer 103 is disposed on the buffer layer 102.
  • the display device layer 103 includes a second protective layer 1031 and a display unit component layer 1032.
  • the second protective layer 1031 is disposed on the buffer layer 102, and the display unit component layer 1032 is disposed on the second protective layer. On 1031.
  • the stress relieving portion includes at least one recess 402 and/or at least one boss 401. At least one of the recesses 402 and/or at least one of the raised portions 401 are arranged in a one-dimensional array or a two-dimensional array, as shown in FIG.
  • the stress relieving portion includes at least one groove 1022 and/or at least one rib 1021. At least one of the grooves 1022 and/or at least one of the ribs 1021 are arranged in a one-dimensional array or a two-dimensional array, as shown in FIGS.
  • the stress relieving portion is formed by a mask process and/or an etching process, and the stress relieving portion is disposed on a side of the buffer layer 102 facing the display device layer 103. .
  • the stress relieving portion is formed by depositing an underlying protective layer (ie, the first protective layer 104) and a buffer layer 102 (eg, silicon nitride, silicon oxide, etc.) on the flexible substrate 101, and then coating a photoresist material, and patterning the photoresist material to obtain a photoresist block corresponding to the size, shape, and area of the stress relieving portion to be formed, and then performing an etching process to obtain a material corresponding to the buffer layer 102 a layer (eg, silicon nitride, silicon oxide, etc.), and finally removing the photoresist block (ie, stripping the photoresist block) to form, or using Sputter Lift Off (sputtering and stripping) mode, that is, without etching, the
  • the stress relieving portion is disposed on a side of the buffer layer 102 facing away from the display device layer 103. .
  • the second protective layer 1031 covers the buffer layer 102, and the second protective layer 1031 fills the recess 402, the groove 1022, the gap between the two protrusions 401, and the two At least one of the gaps between the ribs 1021.
  • the stress of the flexible substrate 101 can be effectively reduced (slowed), and the stress of the flexible substrate 101 is prevented from being excessively large, thereby facilitating the avoidance of the flexible substrate 101 or the use of the flexible substrate 101.
  • the warpage/bending of the glass substrate is beneficial to improve the accuracy of the yellow light alignment process.
  • FIG. 8 is a flowchart of a method of fabricating a thin film transistor array panel of the present invention.
  • the manufacturing method of the thin film transistor array panel of the present invention comprises the following steps:
  • the buffer layer 102 is provided on the flexible substrate 101.
  • the stress relieving portion is disposed on the buffer layer 102, wherein the stress relieving portion is for slowing stress of the flexible substrate 101.
  • the display device layer 103 is provided on the buffer layer 102.
  • the stress relieving portion includes at least one recess 402 and/or at least one protrusion 401, and at least one of the recesses 402 and/or at least one of the protrusions 401 is in a one-dimensional array or a two-dimensional array. Formal arrangement.
  • the stress relieving portion includes at least one groove 1022 and/or at least one rib 1021, and at least one of the grooves 1022 and/or at least one of the ribs 1021 are arranged in a one-dimensional array or a two-dimensional array. .
  • the step B (ie, the step 802) includes:
  • the stress relieving portion is disposed on a side of the buffer layer 102 facing the display device layer 103.
  • the step B (ie, the step 802) includes:
  • this second buffer layer may be an organic material, an inorganic metal material, or the like).
  • the stress relieving portion is disposed on a side of the buffer layer 102 facing away from the display device layer 103.
  • the stress of the flexible substrate 101 can be effectively reduced (slowed), and the stress of the flexible substrate 101 is prevented from being excessively large, thereby facilitating the avoidance of the flexible substrate 101 or the use of the flexible substrate 101.
  • the warpage/bending of the glass substrate is beneficial to improve the accuracy of the yellow light alignment process.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种薄膜晶体管阵列面板及其制作方法。薄膜晶体管阵列面板包括：柔性基板（101）、缓冲层（102）、显示器件层（103）。缓冲层（102）设置在柔性基板（101）上，缓冲层（102）上设置有应力减缓部，应力减缓部用于减缓柔性基板（101）的应力；显示器件层（103）设置在缓冲层（102）上，可以有效降低柔性基板（101）的应力，避免柔性基板（101）的应力过大。

Description

薄膜晶体管阵列面板及其制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列面板及其制作方法。
 背景技术
传统的柔性显示器（Flexible Display）一般都包括柔性基板，所述柔性基板一般较薄，无法直接在所述柔性基板上进行相应的制程，因此，传统的柔性显示器一般都需要固定在玻璃基板上来进行相应的制程。
在实践中，发明人发现现有技术至少存在以下问题：
玻璃基板与柔性基板的热膨胀系数不同，因此在所述柔性基板的制作过程中会出现所述玻璃基板翘曲/弯曲的现象，这不利于所述柔性基板的制程的进行。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列面板及其制作方法，其能有效降低（减缓）所述柔性基板的应力，避免所述柔性基板的应力过大。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种薄膜晶体管阵列面板，所述薄膜晶体管阵列面板包括：柔性基板；缓冲层，所述缓冲层设置在所述柔性基板上，所述缓冲层上设置有应力减缓部，所述应力减缓部用于减缓所述柔性基板的应力；显示器件层，所述显示器件层设置在所述缓冲层上；所述应力减缓部包括至少一凹陷部和/或至少一凸起部，至少一所述凹陷部和/或至少一所述凸起部以一维阵列或二维阵列的形式排列；或者所述应力减缓部包括至少一凹槽和/或至少一凸条，至少一所述凹槽和/或至少一所述凸条以一维阵列或二维阵列的形式排列。
在上述薄膜晶体管阵列面板中，所述应力减缓部是通过光罩制程和/或蚀刻制程来形成的，所述应力减缓部设置于所述缓冲层面向所述显示器件层的一面上；或者所述应力减缓部是通过在所述柔性基板上涂布光阻材料，并对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块，然后再在所述光阻块和所述柔性基板上形成所述缓冲层所对应的材料层，最后再清除所述光阻块来形成的，所述应力减缓部设置于所述缓冲层背向所述显示器件层的一面上。
一种薄膜晶体管阵列面板，所述薄膜晶体管阵列面板包括：柔性基板；缓冲层，所述缓冲层设置在所述柔性基板上，所述缓冲层上设置有应力减缓部，所述应力减缓部用于减缓所述柔性基板的应力；显示器件层，所述显示器件层设置在所述缓冲层上。
在上述薄膜晶体管阵列面板中，所述薄膜晶体管阵列面板还包括：第一保护层，所述第一保护层设置在所述柔性基板上，所述缓冲层设置在所述第一保护层上。
在上述薄膜晶体管阵列面板中，所述显示器件层包括第二保护层和显示单元部件层，所述第二保护层设置于所述缓冲层上，所述第二保护层覆盖所述缓冲层，所述显示单元部件层设置于所述第二保护层上。
在上述薄膜晶体管阵列面板中，所述应力减缓部包括至少一凹陷部和/或至少一凸起部；至少一所述凹陷部和/或至少一所述凸起部以一维阵列或二维阵列的形式排列。
在上述薄膜晶体管阵列面板中，所述第二保护层填充所述凹陷部、两所述凸起部之间的间隙中的至少一者。
在上述薄膜晶体管阵列面板中，所述应力减缓部包括至少一凹槽和/或至少一凸条；至少一所述凹槽和/或至少一所述凸条以一维阵列或二维阵列的形式排列。
在上述薄膜晶体管阵列面板中，所述第二保护层填充所述凹槽、两所述凸条之间的间隙中的至少一者。
在上述薄膜晶体管阵列面板中，所述应力减缓部是通过光罩制程和/或蚀刻制程来形成的；所述应力减缓部设置于所述缓冲层面向所述显示器件层的一面上。
在上述薄膜晶体管阵列面板中，所述应力减缓部是通过在所述柔性基板上涂布光阻材料，并对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块，然后再在所述光阻块和所述柔性基板上形成所述缓冲层所对应的材料层，最后再清除所述光阻块来形成的；所述应力减缓部设置于所述缓冲层背向所述显示器件层的一面上。
一种上述薄膜晶体管阵列面板的制作方法，所述方法包括以下步骤：A、在所述柔性基板上设置所述缓冲层；B、在所述缓冲层上设置所述应力减缓部，其中，所述应力减缓部用于减缓所述柔性基板的应力；C、在所述缓冲层上设置所述显示器件层。
在上述薄膜晶体管阵列面板的制作方法中，所述柔性基板和所述缓冲层之间设有第一保护层。
在上述薄膜晶体管阵列面板的制作方法中，所述显示器件层包括第二保护层和显示单元部件层，所述第二保护层设置于所述缓冲层上，所述第二保护层覆盖所述缓冲层，所述显示单元部件层设置于所述第二保护层上。
在上述薄膜晶体管阵列面板的制作方法中，所述应力减缓部包括至少一凹陷部和/或至少一凸起部；至少一所述凹陷部和/或至少一所述凸起部以一维阵列或二维阵列的形式排列。
在上述薄膜晶体管阵列面板的制作方法中，所述第二保护层填充所述凹陷部、两所述凸起部之间的间隙中的至少一者。
在上述薄膜晶体管阵列面板的制作方法中，所述应力减缓部包括至少一凹槽和/或至少一凸条；至少一所述凹槽和/或至少一所述凸条以一维阵列或二维阵列的形式排列。
在上述薄膜晶体管阵列面板的制作方法中，所述第二保护层填充所述凹槽、两所述凸条之间的间隙中的至少一者。
在上述薄膜晶体管阵列面板的制作方法中，所述步骤B包括：b1、对所述缓冲层实施光罩制程和/或蚀刻制程，以在所述缓冲层上形成所述应力减缓部；所述应力减缓部设置于所述缓冲层面向所述显示器件层的一面上。
在上述薄膜晶体管阵列面板的制作方法中，所述步骤B包括：b2、在所述柔性基板上涂布光阻材料；b3、对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块；b4、在所述光阻块和所述柔性基板上形成所述缓冲层所对应的材料层；b5、清除所述光阻块；所述应力减缓部设置于所述缓冲层背向所述显示器件层的一面上。
 有益效果
相对现有技术，本发明可以有效降低（减缓）所述柔性基板的应力，避免所述柔性基板的应力过大，从而有利于避免所述柔性基板或者为制作所述柔性基板所使用的玻璃基板翘曲/弯曲，进而有利于提高黄光对位制程的精准度。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
 附图说明
图1为本发明的薄膜晶体管阵列面板的第一实施例的示意图；
图2为本发明的薄膜晶体管阵列面板的第二实施例的示意图；
图3为本发明的薄膜晶体管阵列面板的第三实施例的示意图；
图4至7为图1至3中的薄膜晶体管阵列面板中不同形式的缓冲层的上视图；
图8为本发明的薄膜晶体管阵列面板的制作方法的流程图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板），AMOLED（Active Matrix Organic Light Emitting Diode，有机发光二机体显示面板），有机发光照明面板等。
参考图1至图7，图1为本发明的薄膜晶体管阵列面板的第一实施例的示意图，图2为本发明的薄膜晶体管阵列面板的第二实施例的示意图，图3为本发明的薄膜晶体管阵列面板的第三实施例的示意图，图4至7为图1至3中的薄膜晶体管阵列面板中不同形式的缓冲层102的上视图。
本实施例的薄膜晶体管阵列面板包括柔性基板101、第一保护层104、缓冲层102和显示器件层103。
所述第一保护层104设置在所述柔性基板101上，所述缓冲层102设置在所述柔性基板101上，具体地，所述缓冲层102设置在所述第一保护层104上，所述缓冲层102上设置有应力减缓部，所述应力减缓部用于减缓所述柔性基板101的应力。
所述显示器件层103设置在所述缓冲层102上。所述显示器件层103包括第二保护层1031和显示单元部件层1032，所述第二保护层1031设置于所述缓冲层102上，所述显示单元部件层1032设置于所述第二保护层1031上。
所述应力减缓部包括至少一凹陷部402和/或至少一凸起部401。至少一所述凹陷部402和/或至少一所述凸起部401以一维阵列或二维阵列的形式排列，如图4所示。
或者，所述应力减缓部包括至少一凹槽1022和/或至少一凸条1021。至少一所述凹槽1022和/或至少一所述凸条1021以一维阵列或二维阵列的形式排列，如图5至7所示。
在上述实施例中，所述应力减缓部是通过光罩制程和/或蚀刻制程来形成的，此时，所述应力减缓部设置于所述缓冲层102面向所述显示器件层103的一面上。或者，所述应力减缓部是通过在所述柔性基板101上沉积底层保护层（即，所述第一保护层104）和缓冲层102（例如，氮化硅、氧化硅等），然后涂布光阻材料，并对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块，然后进行蚀刻制程，得到所述缓冲层102所对应的材料层（例如，氮化硅、氧化硅等），最后再清除所述光阻块（即，对所述光阻块进行剥离（Strip））来形成，或使用Sputter Lift Off（溅镀剥离）方式，即不用经过蚀刻，只是将PI（Polyimide，聚酰亚胺）上先沉积第一层整面保护层（即，所述第一保护层104）所对应的材料层（例如，氮化硅、氧化硅等），再在所述整面保护层（即，所述第一保护层104）上涂布光阻材料，并对光阻材料进行图形化，之后利用物理气相沉积方式形成第二层缓冲层102，再将光阻块去除，而完成应力缓冲部，此时，所述应力减缓部设置于所述缓冲层102背向所述显示器件层103的一面上。
所述第二保护层1031覆盖所述缓冲层102，并且所述第二保护层1031填充所述凹陷部402、所述凹槽1022、两所述凸起部401之间的间隙、两所述凸条1021之间的间隙中的至少一者。
通过上述技术方案，可以有效降低（减缓）所述柔性基板101的应力，避免所述柔性基板101的应力过大，从而有利于避免所述柔性基板101或者为制作所述柔性基板101所使用的玻璃基板翘曲/弯曲，进而有利于提高黄光对位制程的精准度。
参考图8，图8为本发明的薄膜晶体管阵列面板的制作方法的流程图。
本发明的薄膜晶体管阵列面板的制作方法包括以下步骤：
A（步骤801）、在所述柔性基板101上设置所述缓冲层102。
B（步骤802）、在所述缓冲层102上设置所述应力减缓部，其中，所述应力减缓部用于减缓所述柔性基板101的应力。
C（步骤803）、在所述缓冲层102上设置所述显示器件层103。
其中，所述应力减缓部包括至少一凹陷部402和/或至少一凸起部401，至少一所述凹陷部402和/或至少一所述凸起部401以一维阵列或二维阵列的形式排列。或者，所述应力减缓部包括至少一凹槽1022和/或至少一凸条1021，至少一所述凹槽1022和/或至少一所述凸条1021以一维阵列或二维阵列的形式排列。
在本实施例中，所述步骤B（即，所述步骤802）包括：
b1、对所述缓冲层102实施光罩制程和/或蚀刻制程，以在所述缓冲层102上形成所述应力减缓部。此时，所述应力减缓部设置于所述缓冲层102面向所述显示器件层103的一面上。
或者，所述步骤B（即，所述步骤802）包括：
b2、在所述柔性基板101上涂布光阻材料；
b3、对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块；
b4、在所述光阻块和所述柔性基板101上形成所述缓冲层102所对应的材料层；
b5、清除所述光阻块，即，对所述光阻块进行剥离（Strip）；
或不用蚀刻的方式，即Sputter Lift Off（溅镀剥离）方式，只是将PI上先沉积第一层整面保护层（即，所述第一保护层104）所对应的材料层（例如，氮化硅、氧化硅等），再在所述第一层整面保护层（即，所述第一保护层104）上涂布光阻材料，并对光阻材料进行图形化，之后利用物理气相沉积方式形成第二层缓冲层，再将光阻块去除，而完成应力缓冲部102（此第二层缓冲层可以是有机材无机材金属材等）。
此时，所述应力减缓部设置于所述缓冲层102背向所述显示器件层103的一面上。
通过上述技术方案，可以有效降低（减缓）所述柔性基板101的应力，避免所述柔性基板101的应力过大，从而有利于避免所述柔性基板101或者为制作所述柔性基板101所使用的玻璃基板翘曲/弯曲，进而有利于提高黄光对位制程的精准度。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：
    柔性基板；
    缓冲层，所述缓冲层设置在所述柔性基板上，所述缓冲层上设置有应力减缓部，所述应力减缓部用于减缓所述柔性基板的应力；
    显示器件层，所述显示器件层设置在所述缓冲层上；
    所述应力减缓部包括至少一凹陷部和/或至少一凸起部，至少一所述凹陷部和/或至少一所述凸起部以一维阵列或二维阵列的形式排列；或者所述应力减缓部包括至少一凹槽和/或至少一凸条，至少一所述凹槽和/或至少一所述凸条以一维阵列或二维阵列的形式排列。
  2. 根据权利要求1所述的薄膜晶体管阵列面板，其中，所述应力减缓部是通过光罩制程和/或蚀刻制程来形成的，所述应力减缓部设置于所述缓冲层面向所述显示器件层的一面上；或者
    所述应力减缓部是通过在所述柔性基板上涂布光阻材料，并对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块，然后再在所述光阻块和所述柔性基板上形成所述缓冲层所对应的材料层，最后再清除所述光阻块来形成的，所述应力减缓部设置于所述缓冲层背向所述显示器件层的一面上。
  3. 一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：
    柔性基板；
    缓冲层，所述缓冲层设置在所述柔性基板上，所述缓冲层上设置有应力减缓部，所述应力减缓部用于减缓所述柔性基板的应力；
    显示器件层，所述显示器件层设置在所述缓冲层上。
  4. 根据权利要求3所述的薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板还包括：
    第一保护层，所述第一保护层设置在所述柔性基板上，所述缓冲层设置在所述第一保护层上。
  5. 根据权利要求3所述的薄膜晶体管阵列面板，其中，所述显示器件层包括第二保护层和显示单元部件层，所述第二保护层设置于所述缓冲层上，所述第二保护层覆盖所述缓冲层，所述显示单元部件层设置于所述第二保护层上。
  6. 根据权利要求5所述的薄膜晶体管阵列面板，其中，所述应力减缓部包括至少一凹陷部和/或至少一凸起部；
    至少一所述凹陷部和/或至少一所述凸起部以一维阵列或二维阵列的形式排列。
  7. 根据权利要求6所述的薄膜晶体管阵列面板，其中，所述第二保护层填充所述凹陷部、两所述凸起部之间的间隙中的至少一者。
  8. 根据权利要求5所述的薄膜晶体管阵列面板，其中，所述应力减缓部包括至少一凹槽和/或至少一凸条；
    至少一所述凹槽和/或至少一所述凸条以一维阵列或二维阵列的形式排列。
  9. 根据权利要求8所述的薄膜晶体管阵列面板，其中，所述第二保护层填充所述凹槽、两所述凸条之间的间隙中的至少一者。
  10. 根据权利要求3所述的薄膜晶体管阵列面板，其中，所述应力减缓部是通过光罩制程和/或蚀刻制程来形成的；
    所述应力减缓部设置于所述缓冲层面向所述显示器件层的一面上。
  11. 根据权利要求3所述的薄膜晶体管阵列面板，其中，所述应力减缓部是通过在所述柔性基板上涂布光阻材料，并对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块，然后再在所述光阻块和所述柔性基板上形成所述缓冲层所对应的材料层，最后再清除所述光阻块来形成的；
    所述应力减缓部设置于所述缓冲层背向所述显示器件层的一面上。
  12. 一种如权利要求3所述的薄膜晶体管阵列面板的制作方法，其中，所述方法包括以下步骤：
    A、在所述柔性基板上设置所述缓冲层；
    B、在所述缓冲层上设置所述应力减缓部，其中，所述应力减缓部用于减缓所述柔性基板的应力；
    C、在所述缓冲层上设置所述显示器件层。
  13. 根据权利要求12所述的薄膜晶体管阵列面板的制作方法，其中，所述柔性基板和所述缓冲层之间设有第一保护层。
  14. 根据权利要求12所述的薄膜晶体管阵列面板的制作方法，其中，所述显示器件层包括第二保护层和显示单元部件层，所述第二保护层设置于所述缓冲层上，所述第二保护层覆盖所述缓冲层，所述显示单元部件层设置于所述第二保护层上。
  15. 根据权利要求14所述的薄膜晶体管阵列面板的制作方法，其中，所述应力减缓部包括至少一凹陷部和/或至少一凸起部；
    至少一所述凹陷部和/或至少一所述凸起部以一维阵列或二维阵列的形式排列。
  16. 根据权利要求15所述的薄膜晶体管阵列面板的制作方法，其中，所述第二保护层填充所述凹陷部、两所述凸起部之间的间隙中的至少一者。
  17. 根据权利要求14所述的薄膜晶体管阵列面板的制作方法，其中，所述应力减缓部包括至少一凹槽和/或至少一凸条；
    至少一所述凹槽和/或至少一所述凸条以一维阵列或二维阵列的形式排列。
  18. 根据权利要求17所述的薄膜晶体管阵列面板的制作方法，其中，所述第二保护层填充所述凹槽、两所述凸条之间的间隙中的至少一者。
  19. 根据权利要求12所述的薄膜晶体管阵列面板的制作方法，其中，所述步骤B包括：
    b1、对所述缓冲层实施光罩制程和/或蚀刻制程，以在所述缓冲层上形成所述应力减缓部；
    所述应力减缓部设置于所述缓冲层面向所述显示器件层的一面上。
  20. 根据权利要求12所述的薄膜晶体管阵列面板的制作方法，其中，所述步骤B包括：
    b2、在所述柔性基板上涂布光阻材料；
    b3、对光阻材料进行图形化，以得到与待形成的应力减缓部的尺寸、形状、面积相对应的光阻块；
    b4、在所述光阻块和所述柔性基板上形成所述缓冲层所对应的材料层；
    b5、清除所述光阻块；
    所述应力减缓部设置于所述缓冲层背向所述显示器件层的一面上。
PCT/CN2015/095418 2015-11-20 2015-11-24 薄膜晶体管阵列面板及其制作方法 Ceased WO2017084110A1 (zh)

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