WO2016206164A1 - 液晶显示面板及液晶显示面板的制造方法 - Google Patents

液晶显示面板及液晶显示面板的制造方法 Download PDF

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Publication number
WO2016206164A1
WO2016206164A1 PCT/CN2015/085403 CN2015085403W WO2016206164A1 WO 2016206164 A1 WO2016206164 A1 WO 2016206164A1 CN 2015085403 W CN2015085403 W CN 2015085403W WO 2016206164 A1 WO2016206164 A1 WO 2016206164A1
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Prior art keywords
liquid crystal
thickness
layer
display panel
crystal display
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PCT/CN2015/085403
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English (en)
French (fr)
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陈彩琴
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武汉华星光电技术有限公司
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Publication of WO2016206164A1 publication Critical patent/WO2016206164A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a liquid crystal display panel and a method of manufacturing the liquid crystal display panel.
  • a conventional liquid crystal display panel includes a color filter (CF, Color) Filter) substrate, array substrate, and liquid crystal.
  • the color filter substrate comprises a first glass substrate, a black matrix (BM, Black Matrix) layer, a colored pattern layer and a protective layer (OC, Over) a first glass substrate, a black matrix layer, a colored pattern layer, and a protective layer are integrally laminated in a stack;
  • the array substrate includes a second glass substrate, a gate line layer, an insulating layer, a semiconductor layer, a metal layer, and a passivation layer; The layer, the second glass substrate, the gate line layer, the insulating layer, the semiconductor layer, the metal layer, and the passivation layer are sequentially stacked and integrated.
  • the color film substrate and the array substrate of the conventional liquid crystal display panel are supported by a spacer.
  • the color filter substrate and the array substrate are superimposedly combined, and there is a gap of a fixed distance due to the spacers interposed therebetween, and the liquid crystal is placed in the gap.
  • the spacer is a photosensitive spacer (Photo) Spacer, PS) to achieve.
  • the photosensitive spacer is formed on the color filter substrate.
  • the fabrication of the photosensitive spacer formed on the color filter substrate requires a high-cost lithography process compared to the process of fabricating the conventional color filter substrate, which is disadvantageous for cost reduction.
  • Another object of the present invention is to provide a method for fabricating a liquid crystal display panel, which can be fabricated into a flat layer and a columnar bump as a spacer by one exposure through a halftone photolithography process, thereby saving on the color filter substrate. Photosensitive spacer process.
  • a preferred embodiment of the present invention provides a liquid crystal display panel including an array substrate and a color filter substrate, the array substrate including a data line, a scan line, and a thin film transistor, the data line and the The scan line defines the open area.
  • the array substrate further includes a patterned planarization layer formed on the data line, the scan line, and the thin film transistor, and exposing the open area, wherein the patterning on the scan line
  • the flat layer forms a columnar protrusion supported between the array substrate and the color filter substrate.
  • the patterned planarization layer forming the columnar protrusion has a first thickness
  • the patterned planarization layer on the data line has a second thickness
  • the A thickness is greater than the second thickness.
  • the first thickness is between 2.8 and 3.2 microns
  • the second thickness is between 2.1 and 2.6 microns.
  • the array substrate and the color filter substrate have a liquid crystal cell thickness, and the first thickness is equal to the thickness of the liquid crystal cell.
  • the thin film transistor is a low temperature polysilicon thin film transistor
  • the liquid crystal display panel is a fringe field switch mode display panel.
  • the array substrate includes a base substrate, and a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, and an interlayer dielectric layer sequentially formed on the base substrate at the position of the scan line. The patterned planarization layer, the common electrode layer, the passivation layer, and the pixel electrode layer.
  • another preferred embodiment of the present invention provides a method of fabricating a liquid crystal display panel, including: providing an array substrate including a data line, a scan line, and a thin film transistor, the data line and the The scan line defines an open area; coating a flat layer on the array substrate; patterning the flat layer by a halftone photolithography process to form on the data line, the scan line, and the thin film transistor And exposing the patterned planar layer of the open area, wherein the patterned planar layer on the scan line forms a columnar protrusion; and the array substrate and the color filter substrate are combined such that the columnar protrusion Supported between the array substrate and the color filter substrate.
  • the patterned planarization layer forming the columnar protrusion has a first thickness
  • the patterned planarization layer on the data line has a second thickness
  • the A thickness is greater than the second thickness.
  • the first thickness is between 2.8 and 3.2 microns
  • the second thickness is between 2.1 and 2.6 microns.
  • the array substrate and the color filter substrate after the array substrate and the color filter substrate are combined, the array substrate and the color filter substrate have a liquid crystal cell thickness, and the first thickness is equal to the thickness of the liquid crystal cell. .
  • the present invention forms a columnar bump as a spacer between the array substrate and the color filter substrate through a halftone photolithography process in the flat layer in the array substrate, and removes the flat layer originally in the open region to A sufficient liquid crystal cell thickness between the array substrate and the color filter substrate is achieved without additional spacers, thereby saving the photosensitive spacer process on the color filter substrate.
  • FIG. 1 is a schematic plan view of an array substrate of a liquid crystal display panel of the present invention.
  • FIG. 2 is a cross-sectional view of the liquid crystal display panel of FIG. 1 taken along line AA';
  • FIG. 3 is a cross-sectional view of the liquid crystal display panel of FIG. 1 taken along line BB';
  • FIG. 4 is a flow chart showing a method of fabricating a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 5A is a schematic diagram of step S10
  • FIG. 5B is a schematic diagram of step S20
  • FIG. 5C is a schematic diagram of step S30.
  • FIG. 5D is a schematic diagram of step S40.
  • FIG. 1 is a top plan view of an array substrate of a liquid crystal display panel of the present invention
  • FIG. 2 is a cross-sectional view of the liquid crystal display panel of FIG. 1 taken along line AA'
  • FIG. 3 is a liquid crystal display panel of FIG. Schematic diagram of the BB' line segment.
  • the liquid crystal display panel 10 of the present embodiment includes an array substrate 20 and a color filter substrate 30, and a liquid crystal layer (not shown) therebetween.
  • FIG. 1 illustrates a pixel structure on an array substrate 20 .
  • the array substrate 20 includes a data line 210 , a scan line 220 , and a thin film transistor 230 .
  • the data line 210 and the scan line 220 define an opening.
  • the area 240, wherein the open area 240 is a light transmissive area.
  • the thin film transistor 230 is a low temperature polysilicon (LTPS, Low Temperature). Poly-silicon) thin film transistor.
  • the array substrate 20 includes a base substrate 201, and a buffer layer (Buffer layer) 202 and a semiconductor layer 203 sequentially formed on the base substrate 201 at the position of the scan line 220.
  • a pixel electrode layer 210 The color filter substrate 30 includes a glass substrate 301, a black matrix (BM) 302, a color resist layer 303, and a protective layer (OC) 304 thereon.
  • BM black matrix
  • OC protective layer
  • the common electrode is not disposed on the color filter substrate 30, and the common electrode layer 208, the passivation layer 209, and the pixel electrode layer 210 of the array substrate 20 are all on the same substrate, so the liquid crystal display of the embodiment
  • the panel 10 is a fringe field switch (FFS, which generates a horizontal electric field, Fringe Filed Switching) mode display panel.
  • FFS fringe field switch
  • AD-SDS Advanced-Super Dimensional
  • IPS In Plane Switch
  • the patterned planarization layer 207 is formed on the data line 210, the scan line 220, and the thin film transistor 230, and exposes the open area 240. That is to say, the patterned planarization layer 207 of the present embodiment does not entirely cover the interlayer dielectric layer 206, but has holes in the opening region 240 to expose the interlayer dielectric layer 206 of the opening region 240.
  • the patterned flat layer 207 on the scan line 220 forms a columnar protrusion 2071 supported between the array substrate 20 and the color filter substrate 30. A spacer between the two substrates.
  • FIG. 3 is a schematic cross-sectional view of the liquid crystal display panel 10 of the data line 210.
  • the array substrate 20 includes a substrate substrate 201 and is sequentially formed at the position of the scan line 220.
  • a gate insulating layer (GI layer) 204 an interlayer dielectric layer (ILD layer) 206, a source metal layer 211, a patterned planarization layer (PLN layer) 207, a common electrode layer 208, and a blunt on the base substrate 201 Layer 209 and pixel electrode layer 210.
  • GI layer gate insulating layer
  • ILD layer interlayer dielectric layer
  • PPN layer patterned planarization layer
  • the patterned planarization layer 207 forming the columnar protrusions 2071 has a first thickness T1, and the patterned planarization layer on the data line has a second thickness T2. And the first thickness T1 is greater than the second thickness T2. Specifically, in this embodiment, the first thickness T1 is between 2.8 and 3.2 micrometers ( ⁇ m) and the second thickness T2 is between 2.1 and 2.6 micrometers. As shown in FIG. 2, the array substrate 20 and the color filter substrate 30 have a liquid crystal cell thickness (Cell Gap) Cg, the first thickness T1 is equal to the liquid crystal cell thickness Cg. That is, the columnar protrusions 2071 of the present embodiment serve as spacers between the two substrates, that is, the height of the columnar protrusions 2071 is equal to the thickness Cg of the liquid crystal cell.
  • Cell Gap liquid crystal cell thickness
  • FIG. 4 is a flowchart of a method for manufacturing a liquid crystal display panel according to a preferred embodiment of the present invention
  • FIGS. 5A to 5D are steps. Schematic diagram of S10 to S40. The manufacturing method of the liquid crystal display panel of this embodiment starts in step S10.
  • step S10 an array substrate 20 including a data line 210, a scan line 220, and a thin film transistor 230 is provided.
  • the data line 210 and the scan line 220 define an open area 240, and then step S20 is performed. That is, the buffer layer 202, the semiconductor layer 203, the gate insulating layer 204, the gate metal layer 205, and the interlayer dielectric layer which are provided on the base substrate 201 in this position on the substrate 240 are provided. Electrical layer 206. This step is well known to those skilled in the art and will not be described in detail herein.
  • step S20 a flat layer 207 is coated on the array substrate 20, and then step S30 is performed.
  • the flat layer 207 is a transparent organic material.
  • step S30 the planarization layer 207 is patterned by a halftone photolithography process to form on the data line 210, the scan line 220, and the thin film transistor 230 and expose the The planarization layer 207 of the open region 240 is patterned, and then step S40 is performed in which the patterned planarization layer 207 on the scan line 220 forms a columnar bump 2071.
  • the above-mentioned halftone lithography process includes a process of coating a photoresist layer, prebaking, halftone mask exposure, development, post-baking, etching, stripping photoresist, and the like.
  • step S40 the common electrode layer 208, the passivation layer 209, and the pixel electrode layer 210 are formed, and then step S50 is performed.
  • This step is well known to those skilled in the art and will not be described in detail herein.
  • step S50 the array substrate 20 and the color filter substrate 30 are combined such that the columnar protrusions 2071 are supported between the array substrate 20 and the color filter substrate 30, and A spacer between the substrates.
  • the patterned planarization layer 207 forming the columnar protrusions 2071 has a first thickness T1
  • the patterned planarization layer 207 on the data line 220 has a second thickness T2, and the first thickness T1 Greater than the second thickness T2.
  • the first thickness T1 is easily set to be between 2.8 and 3.2 microns by a halftone lithography process
  • the second thickness T2 is set to be between 2.1 and 2.6 microns.
  • the array substrate 20 and the color filter substrate 30 have a liquid crystal cell thickness Cg
  • the first thickness T1 is equal to the liquid crystal cell thickness Cg.
  • the present invention forms a columnar protrusion 207 as a spacer between the array substrate 20 and the color filter substrate 30 through the halftone lithography process in the planar layer 207 of the array substrate 20, and removes the original opening region 240.
  • the flat layer 207 is used to achieve a sufficient liquid crystal cell thickness Cg between the array substrate 20 and the color filter substrate 30 without additional spacers, thereby saving the photosensitive spacer process on the color filter substrate.

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Abstract

一种液晶显示面板及其制造方法，所述液晶显示面板包括阵列基板（20）及彩膜基板（30），所述阵列基板（20）包括数据线（210）、扫描线（220）、薄膜晶体管（230）及开口区（240）。所述阵列基板（20）还包括图案化平坦层（207），其形成于所述数据线（210）、所述扫描线（220）及所述薄膜晶体管（230）上，并暴露出所述开口区（240），其中位于所述扫描线（220）上的所述图案化平坦层（207）形成一柱状凸起（2071），所述柱状凸起（2071）支撑于所述阵列基板（20）及所述彩膜基板（30）之间，而不需额外制作间隔子，从而节省在彩膜基板（30）上的感光型间隔子制程。

Description

液晶显示面板及液晶显示面板的制造方法 技术领域
本发明涉及液晶显示领域，特别涉及一种液晶显示面板及液晶显示面板的制造方法。
 背景技术
传统的液晶显示面板包括彩色滤光片(CF, Color filter)基板、阵列基板以及液晶。该彩膜基板包括第一玻璃基板、黑矩阵(BM，Black Matrix)层、着色图案层和保护层(OC，Over Coat)层，该第一玻璃基板、黑矩阵层、着色图案层和保护层依次层叠设置为一体；阵列基板包括第二玻璃基板、栅极线层、绝缘层、半导体层、金属层和钝化层，该第二玻璃基板、栅极线层、绝缘层、半导体层、金属层和钝化层依次层叠设置为一体。
传统的液晶显示面板的彩膜基板和阵列基板之间是用间隔子(Spacer)来支撑的。彩膜基板和阵列基板叠加组合在一起，并且由于间隔子置于之间而存在固定距离的间隙，液晶置于该间隙内。一般在低温多晶硅(LTPS, Low Temperature Poly-silicon)薄膜晶体管液晶显示器(即LTPS-TFT LCD)中，间隔子是采用感光型间隔子(Photo Spacer, PS)来达成。对于中小尺寸的产品中，感光型间隔子是形成在彩膜基板上，具体彩色滤光片制程为黑矩阵层、着色图案层和保护层完成后，通过使用光掩膜(Photomask)的光刻工艺将感光型间隔子形成在保护层上的特定区域。
然而，制作感光型间隔子形成于彩膜基板相较于制作传统彩膜基板的制程需要多一次高成本的光刻工艺，不利于成本的降低。
 技术问题
本发明的一个目的在于提供一种液晶显示面板，其对阵列基板中的平坦层形成一柱状凸起作为间隔子，从而节省在彩膜基板上的感光型间隔子制程。
本发明的另一个目的在于提供一种液晶显示面板的制造方法，其可透过半色调光刻工艺经一次曝光即可制作成平坦层及作为间隔子的柱状凸起，从而节省在彩膜基板上的感光型间隔子制程。
 技术解决方案
为解决上述问题，本发明的优选实施例提供了一种液晶显示面板，其包括包括阵列基板及彩膜基板，所述阵列基板包括数据线、扫描线及薄膜晶体管，所述数据线及所述扫描线定义出开口区。所述阵列基板还包括图案化平坦层，其形成于所述数据线、所述扫描线及所述薄膜晶体管上，并暴露出所述开口区，其中位于所述扫描线上的所述图案化平坦层形成一柱状凸起，所述柱状凸起支撑于所述阵列基板及所述彩膜基板之间。
在本发明优选实施例中，形成所述柱状凸起的所述图案化平坦层具有一第一厚度，位于所述数据线上的所述图案化平坦层具有一第二厚度，且所述第一厚度大于所述第二厚度。优选地，所述第一厚度介于2.8至3.2微米之间，所述第二厚度介于2.1至2.6微米之间。另外，所述阵列基板及所述彩膜基板之间具有一液晶盒厚度，所述第一厚度等于所述液晶盒厚度。
在本发明优选实施例中，所述薄膜晶体管为低温多晶硅薄膜晶体管，且所述液晶显示面板为边缘场开关模式显示面板。优选地，所述阵列基板包括衬底基板、并在所述扫描线位置上依次形成在所述衬底基板上的缓冲层、半导体层、栅极绝缘层、栅金属层、层间介电层、所述图案化平坦层、公共电极层、钝化层及像素电极层。
同样地，为解决上述问题，本发明的另一优选实施例提供了一种液晶显示面板的制造方法，其包括：提供包括数据线、扫描线及薄膜晶体管的阵列基板，所述数据线及所述扫描线定义出开口区；涂布平坦层于所述阵列基板上；采用半色调光刻工艺图案化所述平坦层，以形成位于所述数据线、所述扫描线及所述薄膜晶体管上并暴露出所述开口区的图案化平坦层，其中位于所述扫描线上的所述图案化平坦层形成一柱状凸起；以及结合所述阵列基板及彩膜基板，使得所述柱状凸起支撑于所述阵列基板及所述彩膜基板之间。
在本发明优选实施例中，形成所述柱状凸起的所述图案化平坦层具有一第一厚度，位于所述数据线上的所述图案化平坦层具有一第二厚度，且所述第一厚度大于所述第二厚度。优选地，所述第一厚度介于2.8至3.2微米之间，所述第二厚度介于2.1至2.6微米之间。
在本发明优选实施例中，结合所述阵列基板及所述彩膜基板后，所述阵列基板及所述彩膜基板之间具有一液晶盒厚度，所述第一厚度等于所述液晶盒厚度。
 有益效果
相对于现有技术，本发明对阵列基板中的平坦层透过半色调光刻工艺形成柱状凸起作为阵列基板及彩膜基板之间的间隔子，且去除掉原本在开口区的平坦层，以达到阵列基板与彩膜基板之间的足够的液晶盒厚度，而不需额外制作间隔子，从而节省在彩膜基板上的感光型间隔子制程。
 附图说明
图1为本发明的液晶显示面板的阵列基板的俯视示意图；
图2为图1的液晶显示面板在AA’线段的剖面示意图；
图3为图1的液晶显示面板在BB’线段的剖面示意图；
图4为本发明优选实施例的液晶显示面板的制造方法的流程图；
图5A为步骤S10的示意图；
图5B为步骤S20的示意图；
图5C为步骤S30的示意图；
图5D为步骤S40的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
参考图1至图3，图1为本发明的液晶显示面板的阵列基板的俯视示意图，图2为图1的液晶显示面板在AA’线段的剖面示意图，图3为图1的液晶显示面板在BB’线段的剖面示意图。如图所示，本实施例的液晶显示面板10包括阵列基板20及彩膜基板30以及两者之间的液晶层(图未示)。
如图1所示，图1绘示阵列基板20上的一个像素结构，阵列基板20上包括数据线210、扫描线220及薄膜晶体管230，所述数据线210及所述扫描线220定义出开口区240，其中开口区240即可透光区。
在此实施例中，薄膜晶体管230为低温多晶硅(LTPS, Low Temperature Poly-silicon)薄膜晶体管。具体而言，如图2所示，阵列基板20包括衬底基板201、并在所述扫描线220位置上依次形成在所述衬底基板201上的缓冲层(Buffer层)202、半导体层203、栅极绝缘层(GI层)204、栅金属层(GE层)205、层间介电层(ILD层)206、图案化平坦层(PLN层)207、公共电极层208、钝化层209及像素电极层210。彩膜基板30包括玻璃基板301、黑矩阵(BM)302、色阻层303、及其上的保护层(OC)304。
在此实施例中，彩膜基板30上并无设置公共电极，而阵列基板20的公共电极层208、钝化层209及像素电极层210都在同一个基板上，因此本实施例的液晶显示面板10为一种产生水平电场的边缘场开关(FFS, Fringe Filed Switching)模式显示面板。然而本发明并不限于此，AD-SDS (Advanced-Super Dimensional Switching，简称为ADS，高级超维场开关)型、IPS (In Plane Switch，横向电场效应)型、TN (Twist Nematic，扭曲向列)型等的液晶显示面板都在本发明范围中。
需注意的是，所述图案化平坦层207形成于所述数据线210、扫描线220及薄膜晶体管230上，并暴露出所述开口区240。也就是说，本实施例的图案化平坦层207并非全部覆盖在层间介电层206上，而是在开口区240有挖孔，而露出开口区240的层间介电层206。
参考图1及图2，位于所述扫描线220上的所述图案化平坦层207形成一柱状凸起2071，所述柱状凸起2071支撑于阵列基板20及彩膜基板30之间，而作为两基板之间的间隔子。
参考图1及图3，图3绘示位于所述数据线210的液晶显示面板10的剖面示意图，此处的阵列基板20包括衬底基板201、并在所述扫描线220位置上依次形成在所述衬底基板201上的栅极绝缘层(GI层)204、层间介电层(ILD层)206、源金属层211、图案化平坦层(PLN层)207、公共电极层208、钝化层209及像素电极层210。
如图2及图3所示，形成所述柱状凸起2071的所述图案化平坦层207具有一第一厚度T1，位于所述数据线上的所述图案化平坦层具有一第二厚度T2，且所述第一厚度T1大于第二厚度T2。具体而言，在此实施例中，所述第一厚度T1介于2.8至3.2微米(μm)之间，所述第二厚度T2介于2.1至2.6微米之间。如图2如示，阵列基板20及所述彩膜基板30之间具有一液晶盒厚度(Cell gap)Cg，所述第一厚度T1等于所述液晶盒厚度Cg。也就是说，本实施例的柱状凸起2071作为两基板之间的间隔子，即柱状凸起2071的高度等于液晶盒厚度Cg。
以下将详细说明本实施例的液晶显示面板的制造方法，请一并参阅图4至图5D，图4为本发明优选实施例的液晶显示面板的制造方法的流程图，图5A至5D为步骤S10至S40的示意图。本实施例的液晶显示面板的制造方法开始于步骤S10。
请参照图5A，在步骤S10中，提供包括数据线210、扫描线220及薄膜晶体管230的阵列基板20，所述数据线210及所述扫描线220定义出开口区240，然后执行步骤S20。也就是提供衬底基板201、并在所述扫描线220位置上依次形成在所述衬底基板201上的缓冲层202、半导体层203、栅极绝缘层204、栅金属层205、层间介电层206。此步骤为本领域技术人员所熟知的，在此不再详细说明。
请参照图5B，在步骤S20中，涂布平坦层207于所述阵列基板20上，然后执行步骤S30。具体来说，平坦层207为透明的有机材料。
请参照图5C，在步骤S30中，采用半色调光刻工艺图案化所述平坦层207，以形成位于所述数据线210、所述扫描线220及所述薄膜晶体管230上并暴露出所述开口区240的图案化平坦层207，然后执行步骤S40，其中位于所述扫描线220上的所述图案化平坦层207形成一柱状凸起2071。值得一提的是，上述半色调光刻工艺包括涂布光刻胶层、预焙、半色调掩模曝光、显影、后焙、蚀刻、剥离光刻胶等工序。
请参照图5D，在步骤S40中，形成公共电极层208、钝化层209及像素电极层210，然后执行步骤S50。此步骤为本领域技术人员所熟知的，在此不再详细说明。
请再参照图2，在步骤S50中，结合所述阵列基板20及彩膜基板30，使得所述柱状凸起2071支撑于所述阵列基板20及所述彩膜基板30之间，而作为两基板之间的间隔子。
同样的，形成所述柱状凸起2071的所述图案化平坦层207具有第一厚度T1，位于所述数据线220上的所述图案化平坦层207具有第二厚度T2，且第一厚度T1大于所述第二厚度T2。优选地，透过半色调光刻工艺可轻易将所述第一厚度T1设置为介于2.8至3.2微米之间，所述第二厚度T2设置为介于2.1至2.6微米之间。如图2所示，结合阵列基板20及彩膜基板30后，所述阵列基板20及所述彩膜基板30之间具有液晶盒厚度Cg，且第一厚度T1等于液晶盒厚度Cg。
综上所述，本发明对阵列基板20中的平坦层207透过半色调光刻工艺形成柱状凸起207作为阵列基板20及彩膜基板30之间的间隔子，且去除掉原本在开口区240的平坦层207，以达到阵列基板20与彩膜基板30之间的足够的液晶盒厚度Cg，而不需额外制作间隔子，从而节省在彩膜基板上的感光型间隔子制程。
虽然本发明已以优选实施例揭露如上，但上述优选实施例幷非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种液晶显示面板，包括阵列基板及彩膜基板，所述阵列基板包括数据线、扫描线及薄膜晶体管，所述数据线及所述扫描线定义出开口区，其中所述阵列基板还包括：
    图案化平坦层，形成于所述数据线、所述扫描线及所述薄膜晶体管上，并暴露出所述开口区，其中位于所述扫描线上的所述图案化平坦层形成一柱状凸起，所述柱状凸起支撑于所述阵列基板及所述彩膜基板之间，形成所述柱状凸起的所述图案化平坦层具有一第一厚度，位于所述数据线上的所述图案化平坦层具有一第二厚度，且所述第一厚度大于所述第二厚度，其中所述阵列基板及所述彩膜基板之间具有一液晶盒厚度，所述第一厚度等于所述液晶盒厚度。
  2. 根据权利要求1所述的液晶显示面板，其中所述第一厚度介于2.8至3.2微米之间。
  3. 根据权利要求2所述的液晶显示面板，其中所述第二厚度介于2.1至2.6微米之间。
  4. 根据权利要求1所述的液晶显示面板，其中所述薄膜晶体管为低温多晶硅薄膜晶体管，且所述液晶显示面板为边缘场开关模式显示面板。
  5. 根据权利要求4所述的液晶显示面板，其中所述阵列基板包括衬底基板、并在所述扫描线位置上依次形成在所述衬底基板上的缓冲层、半导体层、栅极绝缘层、栅金属层、层间介电层、所述图案化平坦层、公共电极层、钝化层及像素电极层。
  6. 一种液晶显示面板，包括阵列基板及彩膜基板，所述阵列基板包括数据线、扫描线及薄膜晶体管，所述数据线及所述扫描线定义出开口区，其中所述阵列基板还包括：
    图案化平坦层，形成于所述数据线、所述扫描线及所述薄膜晶体管上，并暴露出所述开口区，其中位于所述扫描线上的所述图案化平坦层形成一柱状凸起，所述柱状凸起支撑于所述阵列基板及所述彩膜基板之间。
  7. 根据权利要求6所述的液晶显示面板，其中形成所述柱状凸起的所述图案化平坦层具有一第一厚度，位于所述数据线上的所述图案化平坦层具有一第二厚度，且所述第一厚度大于所述第二厚度。
  8. 根据权利要求7所述的液晶显示面板，其中所述第一厚度介于2.8至3.2微米之间，所述第二厚度介于2.1至2.6微米之间。
  9. 根据权利要求7所述的液晶显示面板，其中所述阵列基板及所述彩膜基板之间具有一液晶盒厚度，所述第一厚度等于所述液晶盒厚度。
  10. 根据权利要求6所述的液晶显示面板，其中所述薄膜晶体管为低温多晶硅薄膜晶体管，且所述液晶显示面板为边缘场开关模式显示面板。
  11. 根据权利要求10所述的液晶显示面板，其中所述阵列基板包括衬底基板、并在所述扫描线位置上依次形成在所述衬底基板上的缓冲层、半导体层、栅极绝缘层、栅金属层、层间介电层、所述图案化平坦层、公共电极层、钝化层及像素电极层。
  12. 一种液晶显示面板的制造方法，包括：
    提供包括数据线、扫描线及薄膜晶体管的阵列基板，所述数据线及所述扫描线定义出开口区；
    涂布平坦层于所述阵列基板上；
    采用半色调光刻工艺图案化所述平坦层，以形成位于所述数据线、所述扫描线及所述薄膜晶体管上并暴露出所述开口区的图案化平坦层，其中位于所述扫描线上的所述图案化平坦层形成一柱状凸起；以及
    结合所述阵列基板及彩膜基板，使得所述柱状凸起支撑于所述阵列基板及所述彩膜基板之间。
  13. 根据权利要求12所述的液晶显示面板的制造方法，其中形成所述柱状凸起的所述图案化平坦层具有一第一厚度，位于所述数据线上的所述图案化平坦层具有一第二厚度，且所述第一厚度大于所述第二厚度。
  14. 根据权利要求13所述的液晶显示面板的制造方法，其中所述第一厚度介于2.8至3.2微米之间，所述第二厚度介于2.1至2.6微米之间。
  15. 根据权利要求13所述的液晶显示面板的制造方法，其中结合所述阵列基板及所述彩膜基板后，所述阵列基板及所述彩膜基板之间具有一液晶盒厚度，所述第一厚度等于所述液晶盒厚度。
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