WO2017038372A1 - 能動素子、および能動素子の製造方法 - Google Patents
能動素子、および能動素子の製造方法 Download PDFInfo
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- WO2017038372A1 WO2017038372A1 PCT/JP2016/072945 JP2016072945W WO2017038372A1 WO 2017038372 A1 WO2017038372 A1 WO 2017038372A1 JP 2016072945 W JP2016072945 W JP 2016072945W WO 2017038372 A1 WO2017038372 A1 WO 2017038372A1
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- electrode
- organic semiconductor
- active element
- partition wall
- partition
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
- H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
Definitions
- the present invention relates to an active element using an organic semiconductor for a semiconductor layer.
- a bank (partition) surrounding the ink is formed of an insulating material having liquid repellency by containing, for example, a fluorine component.
- a bank is formed by, for example, a photolithography method or a printing method (see, for example, paragraphs 0028 and 0033 of Patent Document 1).
- An insulator material containing a fluorine component such as polytetrafluoroethylene (PTFE) is suitable as a material for the partition wall because it has low wettability with respect to the organic semiconductor ink.
- PTFE polytetrafluoroethylene
- the displacement of the partition relative to the electrode is likely to occur.
- the dimensions of the base material may change due to stretching or shrinkage of the base material as the thermal process such as film formation or heat treatment is repeatedly performed. Deviation is more likely to occur.
- an object of the present invention is to provide an active element capable of suppressing the spread of wetting of the organic semiconductor ink and the positional deviation of the partition wall with respect to the electrode, and a method for manufacturing the active element.
- the active element of the present invention that has achieved the above-described object includes a base material, a first electrode and a second electrode that are formed adjacent to each other on one main surface of the base material, and one main surface of the base material.
- An organic semiconductor layer formed so as to cover at least a region between the first electrode and the second electrode, on one main surface of the substrate, on the outer side in the plane direction than the organic semiconductor layer, and And a partition formed in a region different from the region where the first electrode and the second electrode are formed, and the summary is that the partition is a conductive material.
- the partition walls are made of a conductive material, the partition walls can be formed together in the step of forming the electrodes, and the step of separately providing the partition walls can be omitted.
- the positional displacement of the partition wall with respect to the first electrode and the second electrode is suppressed, it becomes easy to control the wetting spread of the organic semiconductor ink.
- a plurality of partition walls are formed, and an organic semiconductor layer is formed between one partition wall and another partition wall. Thereby, wetting of the organic semiconductor ink can be blocked while considering various electrode shapes.
- One side of the first electrode and one side of the second electrode are arranged to face each other, one partition and the other partition are arranged to face each other, and the second of one side of the first electrode is arranged. It is preferable that the facing direction of one side of the electrode is orthogonal to the facing direction of one partition and the other partition. With the first electrode, the second electrode, one partition, and the other partition, wetting of the organic semiconductor ink can be blocked from four directions.
- the conductive material of the partition wall is Cu. Since the wettability of Cu is lower than that of other conductive materials, if Cu is used as the material of the partition wall, the organic semiconductor ink can be prevented from spreading outward in the plane direction.
- It preferably has an insulating layer formed on the organic semiconductor layer and a third electrode formed on the insulating layer, and the wettability of the partition wall is smaller than the wettability of the substrate.
- the wettability of the partition wall is smaller than the wettability of the insulating layer.
- a third electrode formed on the other main surface of the substrate, and the wettability of the partition wall is preferably smaller than the wettability of the substrate.
- the wettability of the partition wall is smaller than the wettability of the first electrode and the second electrode. Thereby, it is suppressed that an organic semiconductor ink spreads out on a surface direction outer side across a partition.
- the first electrode has a lower first electrode formed on one main surface of the substrate and an upper first electrode formed on the lower first electrode
- the second electrode is The lower second electrode formed on the one main surface of the base material and the upper second electrode formed on the lower second electrode have wettability of the upper first electrode. It is preferable that the wettability of the lower first electrode is smaller than that of the lower second electrode, and the wettability of the upper second electrode is smaller than that of the lower second electrode. If the wettability of the electrode disposed on the lower side is higher than that of the electrode disposed on the upper side, the organic semiconductor ink is more likely to come into contact with the lower electrode than the upper electrode. As the contact area between the electrode and the organic semiconductor layer increases, the carrier injection efficiency from the lower electrode to the organic semiconductor layer, or from the organic semiconductor layer to the lower electrode increases, and the operation speed of the device improves.
- the partition walls are preferably formed higher in the thickness direction of the substrate than at least a part of the first electrode and the second electrode. Thereby, it is further suppressed that the organic semiconductor ink spreads across the partition wall to the outside in the surface direction.
- the method for manufacturing an active element of the present invention includes: a step of forming a first conductive layer on one main surface of a substrate; and a formation of a second conductive layer on the first conductive layer.
- Forming a mask layer on the second conductive layer bringing the first conductive layer and the second conductive layer into contact with an etching solution and being covered with the mask layers of the first conductive layer and the second conductive layer
- the first electrode and the second electrode adjacent on the one main surface of the base material and the region where the first electrode and the second electrode on the one main surface of the base material are formed by removing the non-existing region Forming a partition wall in a different region, outside the region between the first electrode and the second electrode; on one main surface of the substrate, at least between the first electrode and the second electrode
- a step of forming an organic semiconductor layer so as to cover the region.
- the partition walls are made of a conductive material, the partition walls can be formed together in the step of forming the first electrode and the second electrode, and the step of separately providing the partition walls is omitted. Can do.
- the positional displacement of the partition wall with respect to the first electrode and the second electrode is suppressed, it becomes easy to control the wetting spread of the organic semiconductor ink.
- the active element manufacturing method of the present invention includes: before forming the organic semiconductor layer; removing the mask layer covering the first electrode and the second electrode and the partition; and a portion constituting at least the partition on the second conductive layer Forming another mask layer on the first conductive layer; contacting the first electrode and the second electrode with another etching solution to remove a region not covered with the other mask layer of the second conductive layer; And exposing at least a part of the first electrode and the second electrode. Since at least a part of the first electrode and the second electrode is exposed, the partition is formed higher in the thickness direction than at least a part of the first electrode and the second electrode. Spreading of the organic semiconductor ink is further suppressed.
- the material of the first conductive layer is ITO and the material of the second conductive layer is Cu.
- ITO has a low energy barrier between the organic semiconductor layer and the carrier injection efficiency into the organic semiconductor layer is high.
- Cu has a high conductivity, it contributes to an improvement in the operating speed of the active element. Further, since Cu is inexpensive, the productivity of active elements can be increased.
- the partition is made of a conductive material, it is possible to form the partition together in the step of forming the electrode, and the step of separately providing the partition can be omitted.
- the positional displacement of the partition wall with respect to the first electrode and the second electrode is suppressed, it becomes easy to control the wetting spread of the organic semiconductor ink.
- the present invention when a film is used as the base material, even when a thermal process such as film formation or heat treatment is repeatedly performed, the position of the partition wall with respect to the electrode hardly occurs.
- FIG. 1 represents a plan view of an active device of the present invention.
- FIG. 2 is a sectional view of the active element shown in FIG. 1 taken along the line II-II.
- the modification of the top view of the active element of this invention is represented.
- 4 represents a cross-sectional view of the active element shown in FIG. 3 taken along the line IV-IV.
- 5 shows a modification of the cross-sectional view of the active element shown in FIG. 5 shows a modification of the cross-sectional view of the active element shown in FIG. 5 shows a modification of the cross-sectional view of the active element shown in FIG.
- the modification of the top view of the active element shown in FIG. 1 is represented.
- Process sectional drawing which shows the manufacturing method of the active element of this invention is represented.
- the schematic diagram which shows the evaluation method of the wetting spread width of the organic-semiconductor ink with respect to a conductive material is represented.
- the photograph which shows the result of the wetting spread of the organic semiconductor ink with respect to Cu is represented.
- the photograph which shows the result of the wetting spread of the organic semiconductor ink with respect to Au is represented.
- the photograph which shows the result of the wetting spread of the organic semiconductor ink with respect to ITO is represented.
- the photograph which shows the result of the wetting spread of the organic semiconductor ink with respect to IGZO is represented.
- an active element is an element that performs signal amplification and rectification, and is, for example, an element such as a transistor, a thyristor, or a diode. Examples of these applications include displays, touch panels, solar cells, semiconductor lasers, pressure sensors, and biosensors.
- the active element has a thickness direction and a surface direction.
- the thickness direction of the active element is a direction in which the base material, the first electrode, the second electrode, and the organic semiconductor layer are laminated, and the surface direction of the active element is a direction orthogonal to the thickness direction.
- FIG. 1 shows a plan view of the active element of the present invention
- FIG. 2 shows a II-II cross-sectional view of the active element shown in FIG.
- the active element 1 of the present invention includes a base material 2, a first electrode 5, a second electrode 6, an organic semiconductor layer 9, and a partition wall 12.
- the base material 2 has one main surface and the other main surface, and is provided to support the first electrode 5, the second electrode 6, and the organic semiconductor layer 9.
- a flexible substrate made of a polymer film such as polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyimide (PI), or a rigid substrate such as a glass substrate is preferably used.
- PEN polyethylene naphthalate
- PET polyethylene terephthalate
- PI polyimide
- a rigid substrate such as a glass substrate
- the thickness of the base material 2 is preferably, for example, 5 ⁇ m or more, more preferably 10 ⁇ m or more, and further preferably 18 ⁇ m or more.
- the thickness of the substrate 2 is preferably 200 ⁇ m or less, more preferably 150 ⁇ m or less, and further preferably 125 ⁇ m or less.
- the thickness of the substrate 2 is preferably 10 ⁇ m or less, more preferably 7 ⁇ m or less, and further preferably 5 ⁇ m or less. Preferably, it is 0.1 ⁇ m or more, more preferably 0.5 ⁇ m or more, and further preferably 1 ⁇ m or more.
- the active element 1 of the present invention has a first electrode 5 and a second electrode 6 that are formed adjacent to each other on one main surface of a substrate 2.
- the first electrode 5, the second electrode 6, and a third electrode 11 (hereinafter also referred to collectively as “electrode”) to be described later are electrically connected to operate the active element 1.
- the active element 1 is a transistor
- the first electrode 5 corresponds to a source electrode
- the second electrode 6 corresponds to a drain electrode
- the third electrode 11 corresponds to a gate electrode.
- the electrode material for example, conductive materials such as Cu, Al, Ag, C, Ni, Au, ITO, ZnO, IGO, IGZO, carbon nanotubes, graphene, and graphite can be used.
- the electrode can be formed by, for example, a photolithography method or a printing method. From the viewpoint of improving the accuracy of the relative positions of the first electrode 5 and the second electrode 6, the first electrode 5 and the second electrode 6 are preferably formed by a photolithography method.
- the thickness of the electrode is, for example, preferably 5 nm or more, more preferably 10 nm or more, and further preferably 20 nm or more in order to ensure the necessary electrical conductivity.
- the upper limit of the thickness of the electrode is not particularly limited, but is preferably 1 ⁇ m or less, for example, from the viewpoint of suppressing an increase in the entire thickness of the active element 1 and shortening the etching time when using a photolithography method, It is more preferably 700 nm or less, and further preferably 500 nm or less.
- the first electrode and the second electrode need only be formed adjacent to each other, and one side of the first electrode and one side of the second electrode may be arranged to face each other.
- one side 5C of the first electrode 5 and the one side 6C of the second electrode are arranged to face each other.
- the first electrode 5 or the second electrode 6 may be laminated.
- the first electrode 5 includes a lower first electrode 5A formed on one main surface of the substrate 2 and an upper first electrode 5B formed on the lower first electrode 5A. You may have.
- the second electrode 6 includes a lower second electrode 6A formed on one main surface of the substrate 2 and an upper second electrode formed on the lower second electrode 6A. You may have the electrode 6B.
- the performance of the active element 1 can be enhanced by appropriately selecting the electrode material disposed on the lower side and the electrode material disposed on the upper side.
- the wettability of the upper first electrode 5B is smaller than the wettability of the lower first electrode 5A, and the wettability of the upper second electrode 6B is smaller than the wettability of the lower second electrode 6A. If the wettability of the electrode disposed on the lower side is higher than that of the electrode disposed on the upper side, the organic semiconductor ink is more likely to come into contact with the lower electrode than the upper electrode. Depending on the size of the energy barrier between the electrode and the organic semiconductor layer 9, the larger the contact area between the electrode and the organic semiconductor layer 9, the greater the injection from the lower electrode to the organic semiconductor layer, or the organic semiconductor layer 9 to the lower electrode. The ratio of the generated charge (carrier injection efficiency) is increased, and the operation speed of the device is improved. The “wetting property” will be described later.
- a material having high wettability to the organic semiconductor layer 9 and high carrier injection efficiency for example, ITO is preferably used.
- the electrode disposed on the upper side in order to increase the operation speed of the active element 1, it is preferable to use a material having high conductivity and mobility, for example, Cu.
- the area of the upper first electrode 5B may be larger than the area of the lower first electrode 5A (not shown).
- the operation speed of the active element 1 can be increased by adopting a material having high conductivity and mobility as the material of the upper first electrode 5B.
- the area of the upper second electrode 6B may be larger than the area of the lower second electrode 6A (not shown).
- FIG. 3 shows a modification of the plan view of the active element shown in FIG. 1
- FIG. 4 shows a IV-IV sectional view of the active element shown in FIG.
- the area of the upper first electrode 5B may be smaller than the area of the lower first electrode 5A.
- a material with high carrier injection efficiency is selected as the material of the lower first electrode 5A, carriers are efficiently injected from the electrode into the organic semiconductor layer 9, so that the performance of the active element 1 is improved. be able to.
- the contact area between the lower first electrode 5A and the organic semiconductor layer 9 can be increased, and therefore further. Carrier injection efficiency is improved.
- the area of the upper second electrode 6B may be smaller than the area of the lower second electrode 6A as shown in FIG.
- the lower limit of the difference in electrode width between the lower first electrode 5A and the upper first electrode 5B is not particularly limited, and is preferably, for example, 1 ⁇ m or more, more preferably 3 ⁇ m or more, and further preferably 5 ⁇ m or more.
- the upper limit of the difference between the electrode widths of the lower first electrode 5A and the upper first electrode 5B is not particularly limited, and is preferably 20 ⁇ m or less, more preferably 18 ⁇ m or less, and even more preferably 15 ⁇ m or less.
- the difference in electrode width between the lower second electrode 6A and the upper second electrode 6B is also preferably set in the above range.
- the distance between the first electrode 5 and the second electrode 6 is not particularly limited.
- the first electrode 5 and the second electrode 6 is a drain electrode
- the channel length, which is a length between 6, is preferably 20 ⁇ m or less, more preferably 15 ⁇ m or less, and even more preferably 10 ⁇ m or less. The shorter the channel length, the higher the transistor processing speed and integration.
- the active element 1 of the present invention includes an insulating layer 10 formed on the organic semiconductor layer 9 and a third electrode 11 formed on the insulating layer 10. It is preferable.
- the first electrode 5 is a source electrode
- the second electrode 6 is a drain electrode
- the third electrode 11 is a gate electrode
- a top-gate transistor in which the gate electrode is disposed above the source electrode and the drain electrode. Can be configured.
- the active element 1 of the present invention includes a third electrode 11 formed on one main surface of the base 2 and an insulating layer 10 formed on the third electrode 11. You may have.
- the first electrode 5 is a source electrode
- the second electrode 6 is a drain electrode
- the third electrode 11 is a gate electrode
- the gate electrode is below the source electrode and the drain electrode (side closer to the base material 2).
- a bottom-gate transistor disposed in the gate can be configured.
- the insulating layer 10 functions as a gate insulating film.
- the insulating layer 10 is preferably formed from an insulating material such as SiO 2 or SiON.
- the thickness of the insulating layer 10 is preferably 200 nm or more, more preferably 250 nm or more, and further preferably 300 nm or more.
- the thickness of the insulating layer 10 is preferably 600 nm or less, more preferably 550 nm or less, and further preferably 500 nm or less.
- the active element 1 of the present invention may have a third electrode 11 formed on the other main surface of the substrate 2.
- the first electrode 5 is a source electrode
- the second electrode 6 is a drain electrode
- the third electrode 11 is a gate electrode
- a transistor in which the substrate 2 also serves as a gate insulating film can be configured.
- the organic semiconductor layer 9 is formed on one main surface of the substrate 2 so as to cover at least a region between the first electrode and the second electrode.
- the organic semiconductor layer 9 functions as a channel region.
- a material of the organic semiconductor layer 9 for example, pentacene, anthracene, tetracene, rubrene, polyacetylene, polythiophene, fullerene, carbon nanotube, or the like can be used.
- the upper limit of the thickness of the organic semiconductor layer 9 is not particularly limited, but in order to obtain a thin active element 1, the thickness of the organic semiconductor layer 9 is preferably 200 nm or less, and more preferably 150 nm or less, for example. Preferably, it is 100 nm or less.
- the organic semiconductor layer 9 is preferably formed by a printing method. More specifically, it is formed by applying a liquid mixture (hereinafter referred to as “organic semiconductor ink”) in which organic semiconductor molecules are dispersed in an organic solvent for application to the substrate 2 and then drying.
- organic semiconductor ink a liquid mixture
- organic semiconductor ink in which organic semiconductor molecules are dispersed in an organic solvent for application to the substrate 2 and then drying.
- the organic semiconductor layer 9 is formed by a printing method, for example, mesitylene, toluene, chloroform, p-diisopropylbenzene, benzyl alcohol, or a mixed solvent thereof can be used as the organic solvent.
- the partition wall 12 is provided to control the wetting and spreading of the organic semiconductor ink. As shown in FIG. 1, the partition wall 12 is on one main surface of the substrate 2, outside the organic semiconductor layer 9 in the surface direction, and in a region where the first electrode 5 and the second electrode 6 are formed. Are formed in different regions.
- the position at which the partition wall 12 is formed is not particularly limited, but from the viewpoint of insulating the partition wall 12 from the first electrode 5 and the second electrode 6 to ensure the operating speed of the active element 1, as shown in FIG. 12 is not in contact with the first electrode 5 and the second electrode 6. That is, the partition wall 12 is preferably arranged outside the first electrode 5 and the second electrode 6 in the surface direction of the substrate 2.
- the partition wall 12 is preferably arranged so as to surround the organic semiconductor layer 9 as much as possible except for the wiring. Thereby, wetting of the organic semiconductor ink can be reliably stopped.
- the partition wall 12 is disposed so as to surround the organic semiconductor layer 9 in a range not in contact with the first electrode 5 and the second electrode 6.
- FIG. 1 In the plan view of FIG. 1, two U-shaped partition walls 12 are shown. However, from the viewpoint of simplifying the shape of the partition wall 12, as shown in FIG. 8, the upper and lower sides of the channel region where the partition walls 12 ⁇ / b> A and 12 ⁇ / b> B are formed from the first electrode 5 and the second electrode 6 in plan view. It may be provided in a strip shape parallel to.
- partition walls 12 are provided, and a plurality of partition walls 12 may be provided.
- a plurality of partition walls 12 are formed as shown in FIGS. 1 and 3, and one partition wall 12A and another partition wall 12B It is preferable that the organic semiconductor layer 9 is formed between them. 1 and 3, the first electrode 5 and the second electrode 6 are formed so as to protrude outward in the plane direction (the left side of the first electrode 5 and the right side of the second electrode 6). (Not shown). Accordingly, the wetting and spreading of the organic semiconductor ink is blocked while avoiding portions protruding outward in the surface direction of the first electrode 5 and the second electrode 6.
- one partition wall 12A and another partition wall 12B are formed, the arrangement relationship between one partition wall 12A and another partition wall 12B is not limited.
- one partition wall 12A and another partition wall 12B can be disposed to face each other.
- one side 5C of the first electrode 5 and one side 6C of the second electrode 6 are arranged to face each other, and one partition 12A and the other partition 12B are arranged to face each other.
- the facing direction of one side 5C of the first electrode 5 and one side 6C of the second electrode 6 is preferably orthogonal to the facing direction of one partition 12A and the other partition 12B.
- the partition wall 12 may be formed on the inner side in the left-right direction with respect to the first electrode 5 and the second electrode 6 as shown in FIG.
- the partition wall 12 is a conductive material. Conventionally, when an insulating material is used as the material of the partition wall 12, a step of providing the partition wall 12 is necessary in addition to the step of forming electrodes. On the other hand, in the present invention, since the partition wall 12 is made of a conductive material, the partition wall 12 can be formed together in the step of forming the electrode, and the step of providing the partition wall 12 can be omitted. In addition, in the present invention, since the positional deviation of the partition wall 12 with respect to the first electrode 5 and the second electrode 6 is suppressed, it is easy to control the wetting spread of the organic semiconductor ink.
- the conductive material of the partition wall 12 is, for example, Cu, Al, Ag, C, Ni, Au, ITO, ZnO, IGO, IGZO, carbon nanotube, graphene, graphite or the like.
- the conductive material of the partition wall 12 is Cu. According to the verification described later, the wettability of Cu is very low compared to other conductive materials (Au, ITO, IGZO). Therefore, if Cu is used as the material of the partition wall 12, the organic semiconductor layer 9 is placed outward in the plane direction. Excessive spreading is suppressed.
- the wettability of the partition wall 12 means the wettability of the organic semiconductor ink that forms the organic semiconductor layer 9 with respect to the partition wall 12.
- the wettability of the base material 2 means the wettability of the organic semiconductor ink that forms the organic semiconductor layer 9 with respect to the base material 2
- the wettability of the electrode means the organic semiconductor ink that forms the organic semiconductor layer 9.
- the wettability can be evaluated by the following index.
- the contact angle is an angle formed by a liquid surface and a solid surface, and is measured based on a wettability test method for the surface of a JIS R 3257: 1999 substrate glass. Although it is desirable that the contact angle of the liquid organic semiconductor ink is directly measured, in order to more easily evaluate the wettability, it is assumed that the contact angle of the organic semiconductor ink is proportional to the contact angle of water. The contact angle may be measured.
- the contact angle between the partition wall 12 and the organic semiconductor ink is preferably 70 degrees or more, and more preferably 90 degrees or more. 110 degrees or more is more preferable.
- the surface free energy can be obtained from the following extended Fowkes equation (1) and Young equation (2) using the contact angle and the surface tension value of the measurement liquid.
- the contact angle measurement solution can be selected from pure water, liquid paraffin, glycerin, methylene iodide, n-hexadecane, ⁇ -bromonaphthalene, and the like.
- the surface free energy of the partition wall 12 is small, the adhesive force of the organic semiconductor ink to the partition wall 12 is small, so that the organic semiconductor ink is difficult to spread in the surface direction. Therefore, the surface free energy of the partition wall 12 is preferably small.
- the active element 1 has an insulating layer 10 formed on the organic semiconductor layer 9 and a third electrode 11 formed on the insulating layer 10.
- the organic semiconductor ink that forms the organic semiconductor layer 9 is desirably disposed on the inner side in the plane direction than the partition wall 12 while spreading moderately on the substrate 2. For this reason, it is preferable that the wettability of the partition wall 12 is smaller than the wettability of the substrate 2.
- the active element 1 has a third electrode 11 formed on one main surface of the substrate 2 and an insulating layer 10 formed on the third electrode 11.
- the organic semiconductor ink that forms the organic semiconductor layer 9 spreads moderately on the insulating layer 10.
- the organic semiconductor ink forming the organic semiconductor layer 9 is not formed on the substrate 2. Since it is desirable that the partition wall 12 is appropriately spread and disposed on the inner side in the plane direction than the partition wall 12, the wettability of the partition wall 12 is preferably smaller than the wettability of the substrate 2.
- the wettability of the partition wall 12 is smaller than the wettability of the first electrode 5 and the second electrode 6. Thereby, it is suppressed that the organic semiconductor ink spreads out beyond the partition wall 12 in the surface direction.
- the partition wall 12 may be configured by laminating a plurality of conductive materials. That is, the partition wall 12 may be a laminated body of a lower partition wall 13 formed on the main surface of the substrate 2 and an upper partition wall 14 formed on the lower partition wall 13.
- the partition 12 when the partition 12 is formed together when the electrode is stacked using a plurality of conductive materials, the partition 12 has the same stacked structure as the electrode.
- the wettability of the organic semiconductor ink with respect to the upper partition wall 14 is preferably lower than the wettability of the lower partition wall 13. Thereby, it is suppressed that organic-semiconductor ink spreads over the upper partition 14 to a surface direction outer side.
- the partition wall 12 is preferably formed higher in the thickness direction of the base material than at least a part of the first electrode 5 and the second electrode 6. Thereby, it is further suppressed that the organic semiconductor ink spreads outside the partition wall 12 in the surface direction.
- the lower limit of the height in the thickness direction of the partition wall 12 is not particularly limited, but the height of the partition wall 12 is preferably at least 1.2 times the height of the first electrode 5 and the second electrode 6, for example. It is more preferably 5 times or more, and still more preferably 1.8 times or more.
- FIGS. 9 to 19 are process sectional views showing the active device manufacturing method of the present invention.
- the manufacturing method of the active element of the present invention is as follows: (1) forming a first conductive layer on one main surface of the substrate; (2) forming a second conductive layer on the first conductive layer; (3) forming a mask layer on the second conductive layer; (4) By bringing the first conductive layer and the second conductive layer into contact with the etching solution, and removing the region not covered with the first conductive layer and the second conductive layer mask layer, on one main surface of the substrate The first electrode and the second electrode adjacent to each other and the region where the first electrode and the second electrode on one main surface of the substrate are formed are different regions between the first electrode and the second electrode.
- the manufacturing method of the active element 1 of the present invention includes the step (8) of forming the organic semiconductor layer. (5) peeling the mask layer covering the first electrode, the second electrode, and the partition; (6) forming another mask layer on at least a portion constituting the partition on the second conductive layer; (7) By contacting the first electrode and the second electrode with another etching solution and removing a region not covered with the other mask layer of the second conductive layer, at least one of the first electrode and the second electrode A step of exposing a portion; May be included. By performing the steps (6) and (7), the size of the upper first electrode 5B relative to the lower first electrode 5A and the size of the upper second electrode 6B relative to the lower second electrode 6A can be adjusted. it can. Details of each step will be described.
- Step of forming first conductive layer on one main surface of base material As shown in FIG. 9, the base material 2 is prepared. Although not shown, an adhesion layer, a planarization layer, an optical adjustment layer, and the like may be formed on the main surface of the substrate 2. Moreover, in order to form a terminal electrode and a via electrode in the base material 2, you may form the through-hole (not shown) which penetrates the base material 2 in the thickness direction. For the formation of the through hole, puncturing with a needle-like object, punching, laser processing or the like can be used.
- the first conductive layer 3 is formed on one main surface of the substrate 2.
- the first conductive layer 3 is for forming various electrodes such as a source electrode, a drain electrode, a gate electrode, a terminal electrode, and a via electrode.
- the method for forming the first conductive layer 3 is not particularly limited, and for example, a vacuum deposition method or a sputtering method can be used. Moreover, when the through-hole which penetrates in the thickness direction is not formed in the base material 2, the 1st conductive layer 3 can also be formed into a film by sticking the conductive material formed in foil shape.
- the second conductive layer 4 is formed on the first conductive layer 3. Similar to the first conductive layer 3, the second conductive layer 4 is for forming various electrodes such as a source electrode, a drain electrode, a gate electrode, a terminal electrode, and a via electrode.
- the method for forming the second conductive layer 4 is not particularly limited, and for example, a vacuum deposition method or a sputtering method can be used in the same manner as the formation of the first conductive layer 3. Moreover, when the through-hole which penetrates in the thickness direction is not formed in the base material 2, the 2nd conductive layer 4 can also be formed into a film by sticking the conductive material formed in foil shape.
- the material of the 1st conductive layer 3 is ITO. This is because ITO has a low energy barrier between the organic semiconductor layer 9 and high carrier injection efficiency into the organic semiconductor layer 9.
- the material of the second conductive layer 4 is preferably Cu. Since Cu has a high conductivity, it contributes to an improvement in the operating speed of the active element 1. Further, since Cu is inexpensive, the productivity of the active element 1 can be increased.
- mask layers 20a, 20b, and 20c are formed on the second conductive layer 4.
- the mask layers 20a, 20b, and 20c determine the formation positions of the first electrode 5, the second electrode 6, and the partition wall 12, respectively.
- a photosensitive resin composition such as a dry film resist or a liquid resist is applied on the second conductive layer 4.
- the photosensitive resin includes a negative type in which the exposed portion is insoluble in the developer and a positive type in which the exposed portion is soluble in the developer.
- a negative photosensitive resin is taken as an example. explain.
- a resist is applied on the second conductive layer 4, and an electron beam or light (ultraviolet rays) is irradiated on the resist to draw a predetermined circuit shape on the resist.
- the shape of the first electrode 5 and the second electrode 6 for example, a source electrode and a drain electrode in the case of a transistor
- the partition wall 12 is drawn on the resist.
- the circuit shape is transferred and baked on the resist.
- resist exposed portions remain on the second conductive layer 4 as mask layers 20a, 20b, and 20c.
- the mask layer can be formed of a dry film resist or a liquid resist, but is preferably formed of a dry film resist. Compared with the case where the mask layer is formed of a liquid resist, the solvent drying after applying the resist is unnecessary, so that productivity is improved.
- the first conductive layer and the second conductive layer are brought into contact with the etching solution, and the first main surface of the base material is removed by removing a region not covered with the mask layer of the first conductive layer and the second conductive layer.
- the first conductive layer 3 and the second conductive layer 4 are brought into contact with an etching solution. By this operation, as shown in FIG. 13, the regions of the first conductive layer 3 and the second conductive layer 4 that are not covered with the mask layer are removed.
- the partition wall 12 is made of a conductive material, the partition wall 12 can be formed together in the process of forming the first electrode 5 and the second electrode 6, and the step of providing a separate partition is omitted. can do.
- the positional shift of the partition wall 12 with respect to the first electrode 5 and the second electrode 6 is suppressed, it becomes easy to control the wetting spread of the organic semiconductor ink.
- Step of peeling the mask layer covering the first electrode, the second electrode, and the partition wall The mask layer formed on the first electrode 5, the second electrode 6 and the partition wall 12 is brought into contact with the stripping solution and dissolved. Then, the mask layer covering the first electrode 5 and the second electrode 6 and the partition wall 12 is peeled off. As a result, as shown in FIG. 14, the first electrode 5, the second electrode 6, and the partition wall 12 are formed on one main surface of the substrate 2. The first electrode 5 and the second electrode 6 are formed adjacent to each other.
- the partition wall 12 is a region different from the region where the first electrode 5 and the second electrode 6 are formed, and is formed outside the region between the first electrode 5 and the second electrode 6.
- the first electrode 5 was formed from the lower first electrode 5 ⁇ / b> A formed from the first conductive layer 3 and the second conductive layer 4. And an upper first electrode 5B.
- the second electrode 6 includes a lower second electrode 6 ⁇ / b> A formed from the second conductive layer 4 and an upper second electrode 6 ⁇ / b> B.
- Step of forming another mask layer on at least a portion constituting the partition on the second conductive layer As shown in FIG. 15, in order to prevent the partition 12 from being etched, at least on the second conductive layer 4 Another mask layer 20 d may be formed on the portion constituting the partition wall 12.
- the other mask layer forming method is the same as the mask layer 20a, 20b, 20c forming method described above.
- the first electrode 5 and the second electrode 6 are brought into contact with another etching solution to remove a region not covered with another mask layer of the second conductive layer 4.
- the upper first electrode 5B and the upper second electrode 6B are removed by bringing the first electrode 5 and the second electrode 6 into contact with another etching solution.
- an etching solution that removes the second conductive layer 4 without removing the first conductive layer 3 is selected.
- the other mask layer 20d is removed by bringing the other mask layer 20d into contact with the stripping solution and dissolving it.
- the partition wall 12 is formed higher in the thickness direction than at least a part of the first electrode 5 and the second electrode 6.
- An organic semiconductor layer 9 is formed so as to cover a region between the first electrode 5 and the second electrode 6.
- the next step (9) can be performed.
- Step of forming insulating layer 10 on organic semiconductor layer 9 and forming third electrode 11 on insulating layer 10 As shown in FIG. 19, insulating layer 10 is formed on organic semiconductor layer 9. Next, a third electrode 11 is formed on the insulating layer 10 as shown in FIG.
- FIG. 5 and FIG. 19 each show an example in which steps (6) to (7) are performed.
- a top gate type transistor in which the first electrode 5, the second electrode 6, and the third electrode 11 correspond to the source electrode, the drain electrode, and the gate electrode, respectively, is manufactured. Can do.
- step (10) can be performed before the step (1).
- Step of forming third electrode 11 on one main surface of base material 2 and forming insulating layer 10 on third electrode 11 Preparing base material 2, forming the first electrode on one main surface of base material 2 Three electrodes 11 are formed.
- the third electrode 11 can be formed by a printing method or a photolithography method. When the photolithography method is used, a mask layer having a desired shape is formed on the third conductive layer after forming a third conductive layer (not shown) in the same manner as the formation of the first electrode 5 and the second electrode 6. Then, the third electrode 11 is formed by bringing the third conductive layer into contact with the etching solution.
- the insulating layer 10 is formed on the third electrode 11.
- FIG. 6 shows an example in which steps (6) to (7) are performed.
- FIGS. 21, 22, 23, and 24 show how ink spreads when the conductive material is Cu, Au, ITO, or IGZO, respectively.
- Printing device Ink-Jet (Dimatix (registered trademark) DMP-2831) manufactured by Fuji Film Co., Ltd.
- Organic semiconductor ink Organic semiconductor; dif-TES-ADT 2wt% Solvent; mesitylene
- the wetting spread width of the organic semiconductor ink in the vertical and horizontal directions of Cu was extremely small as compared with other conductive materials (Au, ITO, IGZO). Specifically, the wetting spread width in the lateral direction is approximately proportional to the length of the drawn line in any conductive material, whereas the wetting spread width in the vertical direction of Cu is about 1 of other conductive materials. / 4 or less. From this result, it was found that Cu is the most preferable material for the partition wall 12 because the wettability of Cu with respect to the organic semiconductor ink is lower than that of other conductive materials.
- Active element 2 Base material 3: First conductive layer 4: Second conductive layer 5: First electrode 5A: Lower first electrode 5B: Upper first electrode 6: Second electrode 6A: Lower second electrode 6B: Upper second electrode 9: Organic semiconductor layer 10: Insulating layer 11: Third electrodes 12, 12A, 12B: Partition 13: Lower partition 14: Upper partitions 20a, 20b, 20c, 20d: Mask layer
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Abstract
Description
そこで本発明は、有機半導体インキのぬれ広がりと電極に対する隔壁の位置ズレを抑制できる能動素子と、能動素子の製造方法を提供することを目的とする。
本発明において能動素子は、信号増幅や整流を行う素子であり、例えばトランジスタ、サイリスタ、ダイオード等の素子である。これらの応用例としては、例えば、ディスプレイ、タッチパネル、太陽電池、半導体レーザ、圧力センサー、生体センサー等がある。
(1)接触角
接触角は、液体面と固体面のなす角度であり、JIS R 3257:1999 基板ガラス表面のぬれ性試験方法に基づき測定される。液体の有機半導体インキの接触角が直接的に測定されることが望ましいが、より簡便にぬれ性を評価するために、有機半導体インキの接触角が水の接触角に比例するとみなして、水の接触角を測定してもよい。
ぬれ性の指標として固体表面の分子間力を数値化した表面自由エネルギーγS(単位:N/m)を用いることもできる。表面自由エネルギーは接触角と測定液の表面張力の値を用いて、以下の拡張Fowkes式(1)式とYoung式(2)式から求めることができる。なお、接触角の測定液は純水、流動パラフィン、グリセリン、ヨウ化メチレン、n-ヘキサデカン、α-ブロモナフタレンなどから選択することができる。
γL(1+cosθ)/2=(γSd×γLd)1/2+(γSp×γLp)1/2+(γSh×γLh)1/2・・・(1)
γS=γSd+γSp+γSh・・・(2)
γL:測定液の表面張力
γLd:測定液の表面張力分散成分
γLp:測定液の表面張力極性成分
γLh:測定液の表面張力水素結合成分
γS:表面自由エネルギー
γSd:表面自由エネルギー分散成分
γSp:表面自由エネルギー極性成分
γSh:表面自由エネルギー水素結合成分
図9~図19は、本発明の能動素子の製造方法を示す工程断面図を表す。
本発明の能動素子の製造方法は、
(1)基材の一方主面上に第1導電層を形成する工程と、
(2)第1導電層上に第2導電層を形成する工程と、
(3)第2導電層上にマスク層を形成する工程と、
(4)第1導電層および第2導電層をエッチング液に接触させて、第1導電層および第2導電層マスク層で覆われていない領域を除去することにより、基材の一方主面上に隣り合う第1電極および第2電極と、基材の一方主面上の第1電極および第2電極が形成されている領域とは異なる領域であって、第1電極および第2電極の間の領域の外側に隔壁と、
を形成する工程と、
(8)基材の一方主面上であって、少なくとも第1電極と第2電極の間の領域を覆うように有機半導体層を形成する工程と、を含むものである。
(5)第1電極および第2電極および隔壁を覆うマスク層を剥離する工程と、
(6)第2導電層上の少なくとも隔壁を構成する部分に他のマスク層を形成する工程と、
(7)第1電極および第2電極を他のエッチング液に接触させて、第2導電層の他のマスク層で覆われていない領域を除去することにより、第1電極および第2電極の少なくとも一部を露出させる工程と、
を含んでいてもよい。工程(6)および(7)を実施することにより、下側第1電極5Aに対する上側第1電極5Bの大きさや、下側第2電極6Aに対する上側第2電極6Bの大きさを調整することができる。各工程の詳細について説明する。
図9に示すように、基材2を準備する。図示していないが、基材2の主面上には、密着層、平坦化層、光学調整層等が形成されてもよい。また、基材2には、端子電極やビア電極を形成するために、基材2を厚み方向に貫通する貫通孔(図示せず)を形成してもよい。貫通孔の形成には、針状物による穿刺、パンチング、レーザー加工等を用いることができる。
図11に示すように、第1導電層3上に第2導電層4を形成する。第1導電層3と同様に、第2導電層4もソース電極、ドレイン電極、ゲート電極、端子電極、ビア電極等の各種電極を形成するためのものである。
図12に示すように、第2導電層4上にマスク層20a、20b、20cを形成する。マスク層20aおよび20b、20cはそれぞれ第1電極5および第2電極6、隔壁12の形成位置を決める。
第1導電層3および第2導電層4をエッチング液に接触させる。この操作によって、図13に示すように、第1導電層3および第2導電層4のマスク層で覆われていない領域が除去される。
第1電極5、第2電極6、隔壁12上に形成されたマスク層を剥離液に接触させて溶解することにより、第1電極5および第2電極6および隔壁12を覆うマスク層を剥離する。その結果、図14に示すように、基材2の一方の主面上に第1電極5と、第2電極6と、隔壁12とが形成される。第1電極5および第2電極6は隣り合って形成されている。また、隔壁12は、第1電極5および第2電極6が形成されている領域とは異なる領域であって、第1電極5および第2電極6の間の領域の外側に形成されている。第1導電層3上に第2導電層4を形成していたため、第1電極5は、第1導電層3から形成された下側第1電極5Aと、第2導電層4から形成された上側第1電極5Bとを有している。また、第1電極5と同様に、第2電極6は、第2導電層4から形成された下側第2電極6Aと、上側第2電極6Bを有している。
図15に示すように、隔壁12がエッチングされるのを防ぐために、第2導電層4上の少なくとも隔壁12を構成する部分に他のマスク層20dを形成してもよい。他のマスク層の形成方法は、上述したマスク層20a、20b、20cの形成方法と同様である。
図16に示すように、第1電極5および第2電極6を他のエッチング液に接触させて、第2導電層4の他のマスク層で覆われていない領域を除去することにより、第1電極および第2電極の少なくとも一部を露出させてもよい。具体的には、第1電極5および第2電極6を他のエッチング液に接触することにより、上側第1電極5Bと、上側第2電極6Bを除去する。ここで用いる他のエッチング液としては、第1導電層3を除去せず、第2導電層4を除去するエッチング液を選択する。
基材2の一方主面上であって、少なくとも第1電極5と第2電極6の間の領域を覆うように有機半導体層9を形成する。これにより、第1導電層3および第2導電層4が除去された基材2の一方の主面上に有機半導体層9が形成された能動素子1を製造することができる。なお、工程(6)および(7)を実施しない場合には、図2に示すような能動素子1が得られ、工程(6)および(7)を実施した場合には、図18に示す能動素子1が得られる。
図19に示すように、有機半導体層9上に絶縁層10を形成する。次いで、図5に示すように絶縁層10上に第3電極11を形成する。ここで、図5、図19は、いずれも工程(6)~(7)を実施した場合の例を表している。
基材2を準備し、基材2の一方主面上に第3電極11を形成する。第3電極11の形成は、印刷法やフォトリソグラフィ法を用いることができる。フォトリソグラフィ法を用いる場合には、第1電極5、第2電極6の形成と同様に、第3導電層(図示せず)を形成した後、第3導電層上に所望の形状のマスク層を形成し、第3導電層をエッチング液に接触させることにより、第3電極11を形成する。
以下に示す印刷装置を用いて、縦方向と横方向を有するCu、Au、ITO、IGZOの導電材料に対して、図20に示すように、有機半導体インキを用いて長さ750μmの線を印刷し、有機半導体インキのぬれ広がりが収まった後に縦方向および横方向における有機半導体インキのぬれ広がり幅をそれぞれ3回ずつ測定した。縦方向および横方向におけるインキのぬれ広がり幅の測定値(単位:μm)と、3回の測定値の平均(単位:μm)を表1に示す。また、導電材料がCu、Au、ITO、IGZOの場合のインキのぬれ広がりの様子を、図21、図22、図23、図24にそれぞれ表す。
<描画条件>
印刷装置:富士フィルム株式会社製
Ink-Jet (Dimatix(登録商標) DMP-2831)
有機半導体インキ:有機半導体;dif-TES-ADT 2wt%
溶媒;メシチレン
2:基材
3:第1導電層
4:第2導電層
5:第1電極
5A:下側第1電極
5B:上側第1電極
6:第2電極
6A:下側第2電極
6B:上側第2電極
9:有機半導体層
10:絶縁層
11:第3電極
12、12A、12B:隔壁
13:下側隔壁
14:上側隔壁
20a、20b、20c、20d:マスク層
Claims (13)
- 基材と、
該基材の一方主面上に隣り合って形成されている第1電極および第2電極と、
前記基材の一方主面上であって、少なくとも前記第1電極と前記第2電極の間の領域を覆うように形成されている有機半導体層と、
前記基材の一方主面上であって、前記有機半導体層よりも面方向外側で、かつ前記第1電極および前記第2電極が形成されている領域とは異なる領域に形成されている隔壁と、を有し、
前記隔壁は、導電材料であることを特徴とする能動素子。 - 前記隔壁が複数形成されており、
一の前記隔壁と他の前記隔壁との間に、前記有機半導体層が形成されている請求項1に記載の能動素子。 - 前記第1電極の一つの辺と前記第2電極の一つの辺が対向して配置されており、
一の前記隔壁と他の前記隔壁が対向して配置されており、
前記第1電極の一つの辺の前記第2電極の一つの辺の対向方向と、一の前記隔壁と他の前記隔壁の対向方向が直交している請求項2に記載の能動素子。 - 前記隔壁の前記導電材料がCuである請求項1~3のいずれか一項に記載の能動素子。
- 前記有機半導体層上に形成されている絶縁層と、
該絶縁層上に形成されている第3電極と、を有し、
前記隔壁のぬれ性が、前記基材のぬれ性よりも小さい請求項1~4のいずれか一項に記載の能動素子。 - 前記基材の一方主面上に形成されている第3電極と、
該第3電極上に形成されている絶縁層と、を有し、
前記第1電極、前記第2電極、前記有機半導体層が、前記絶縁層上に形成され、前記隔壁のぬれ性が、前記絶縁層のぬれ性よりも小さい請求項1~4のいずれか一項に記載の能動素子。 - 前記基材の他方主面上に形成されている第3電極と、を有し、
前記隔壁のぬれ性が、前記基材のぬれ性よりも小さい請求項1~4のいずれか一項に記載の能動素子。 - 前記隔壁のぬれ性が、前記第1電極および前記第2電極のぬれ性よりも小さい請求項1~7のいずれか一項に記載の能動素子。
- 前記第1電極は、前記基材の一方主面上に形成されている下側第1電極と、該下側第1電極上に形成されている上側第1電極とを有しており、
前記第2電極は、前記基材の一方主面上に形成されている下側第2電極と、該下側第2電極上に形成されている上側第2電極とを有しており、
前記上側第1電極のぬれ性が、前記下側第1電極のぬれ性よりも小さく、
前記上側第2電極のぬれ性が、前記下側第2電極のぬれ性よりも小さい請求項1~8のいずれか一項に記載の能動素子。 - 前記隔壁は、前記第1電極と前記第2電極の少なくとも一部よりも前記基材の厚み方向に高く形成されている請求項1~9のいずれか一項に記載の能動素子。
- 基材の一方主面上に第1導電層を形成する工程と、
前記第1導電層上に第2導電層を形成する工程と、
前記第2導電層上にマスク層を形成する工程と、
前記第1導電層および前記第2導電層をエッチング液に接触させて、前記第1導電層および前記第2導電層の前記マスク層で覆われていない領域を除去することにより、前記基材の一方主面上に隣り合う第1電極および第2電極と、前記基材の一方主面上の前記第1電極および前記第2電極が形成されている領域とは異なる領域であって、前記第1電極および前記第2電極の間の領域の外側に隔壁と、を形成する工程と、
前記基材の一方主面上であって、少なくとも前記第1電極と前記第2電極の間の領域を覆うように有機半導体層を形成する工程と、を含むことを特徴とする能動素子の製造方法。 - 前記有機半導体層を形成する前に、
前記第1電極および前記第2電極および前記隔壁を覆う前記マスク層を剥離する工程と、
前記第2導電層上の少なくとも前記隔壁を構成する部分に他のマスク層を形成する工程と、
前記第1電極および前記第2電極を他のエッチング液に接触させて、前記第2導電層の前記他のマスク層で覆われていない領域を除去することにより、前記第1電極および前記第2電極の少なくとも一部を露出させる工程と、を含む請求項11に記載の能動素子の製造方法。 - 前記第1導電層の材料がITOであり、前記第2導電層の材料がCuである請求項11または12に記載の能動素子の製造方法。
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