WO2019100438A1 - Tft基板及其制造方法 - Google Patents

Tft基板及其制造方法 Download PDF

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WO2019100438A1
WO2019100438A1 PCT/CN2017/114252 CN2017114252W WO2019100438A1 WO 2019100438 A1 WO2019100438 A1 WO 2019100438A1 CN 2017114252 W CN2017114252 W CN 2017114252W WO 2019100438 A1 WO2019100438 A1 WO 2019100438A1
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layer
graphene
insulating layer
gate
metal substrate
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PCT/CN2017/114252
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English (en)
French (fr)
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夏慧
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2019100438A1 publication Critical patent/WO2019100438A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT substrate and a method of fabricating the same.
  • each pixel is driven by a Thin Film Transistor (TFT) integrated therein, thereby realizing a high-speed, high-brightness, high-contrast screen display effect.
  • TFT Thin Film Transistor
  • a common TFT is usually composed of a gate/source/drain three electrode, an insulating layer, and a semiconductor layer.
  • Graphene as the world's thinnest and hardest nanomaterial, has become one of the current research hotspots because of its good electrical conductivity, mechanical properties and thermal conductivity. As a new material with extremely low conductivity, graphene has great potential for application in electronic components/transistors. According to reports, graphene films have extremely low sheet resistance ( ⁇ 100 ⁇ / ⁇ ), but after doping, broadband two-dimensional insulating materials can be formed, so that graphene can form n-type or p after certain treatment.
  • the characteristics of semiconductors can be applied to TFT devices in the display industry. However, the method is difficult to adjust the process, and the performance is difficult to ensure. It is difficult to apply to the TFT device in the display industry.
  • the present invention provides a TFT substrate and a method of manufacturing the same.
  • a method of manufacturing a TFT substrate comprising the steps of:
  • Step S101 providing a metal substrate, and forming a gate insulating layer on the metal substrate to obtain a first primary structure
  • Step S102 depositing graphene on the first primary structure, the graphene including a first graphene layer and a second graphene layer are disposed, the second graphene layer and a portion of the first graphene layer form a double layer graphene for use as an active layer, and the double layer graphene is located at On the gate insulating layer;
  • Step S103 forming an organic insulating layer on the first graphene layer and the second graphene layer;
  • Step S104 forming a bottom gate on the organic insulating layer to obtain a second primary structure
  • Step S105 the second primary structure is turned upside down, so that the bottom gate is located at the lowermost layer, and the metal substrate is located at the uppermost layer;
  • Step S106 etching the metal substrate to form a source, a top gate, and a drain, wherein the source and the drain are connected to the first graphene layer, the top gate and the gate Insulation connection.
  • step S101 the following steps are included:
  • Peeling the first photoresist layer forms the first primary structure.
  • the method includes the steps of: forming a patterned second photoresist layer on a side of the metal substrate away from the gate insulating layer; etching the metal substrate to obtain the a source, the top gate, and the drain; stripping the second photoresist layer.
  • the material of the metal substrate is copper or nickel.
  • the material of the gate insulating layer is one of silicon dioxide, hafnium oxide, and hafnium oxide.
  • the material of the organic insulating layer is polymethyl methacrylate.
  • step S103 the graphene is deposited by plasma enhanced chemical vapor deposition.
  • a TFT substrate comprising a bottom gate, an organic insulating layer, a graphene, a gate insulating layer, a source, a top gate and a drain, the bottom gate, the organic insulating layer, the graphene and
  • the gate insulating layer is sequentially disposed in a stack, the graphene includes a first graphene layer and a second graphene layer which are connected to each other, and the first graphene layer is disposed on the organic insulating layer, the first a graphene layer is connected to the source and the drain, and the second graphene layer and a portion of the first graphene layer form a double layer graphene for use as an active layer, and the double layer graphene clip Provided between the organic insulating layer and the gate insulating layer, the top gate is connected to the gate insulating layer.
  • the organic insulating layer forms a receiving groove
  • the gate insulating layer is accommodated in the receiving groove
  • the double-layered graphene is disposed in the receiving groove adjacent to a bottom of the organic insulating layer.
  • the organic insulating layer includes a first surface, a second surface, a third surface, a fourth surface, and a fifth surface that are sequentially connected, and the second surface, the third surface, and the fourth surface enclose the a receiving groove, the first side being disposed adjacent to the third surface, the first graphene layer and the first surface, the second surface, the third surface, the fourth surface, and the a fifth surface connection, the second graphene layer is interposed between the third surface and the first graphene layer, the source is located on the first surface, and the drain is located at the On the fifth surface.
  • the bottom gate is a carbon nanotube layer.
  • a patterned carbon nanotube layer is obtained by inkjet printing on the organic insulating layer through the carbon nanotube ink.
  • the bottom gate is also a stacked combination of one or more of molybdenum, aluminum, and copper.
  • the first graphene layer and the second graphene layer are formed on the gate insulating layer to form a double-layer graphene as an active layer, and are controlled by two gates of a top gate and a bottom gate.
  • the vertical electric field acts as a switching function of the TFT.
  • the source and the drain are connected to the double layer graphene through a single layer of graphene, thereby reducing contact resistance between the source and the active layer and between the drain and the active layer
  • the performance of the TFT substrate is improved. Further, by reusing the metal substrate for depositing graphene into a raw material for fabricating the source, the top gate, and the drain, the manufacturing process is simplified and the cost is reduced.
  • FIG. 1 is a cross-sectional view of a TFT substrate according to an embodiment of the present invention.
  • FIG. 2 is a flow chart of a method of manufacturing a TFT substrate according to an embodiment of the present invention.
  • Figure 3 is a cross-sectional view of the first primary structure formed in step S101 shown in Figure 2 .
  • Fig. 4 is a cross-sectional view showing the structure formed in step S102 shown in Fig. 2 .
  • Fig. 5 is a cross-sectional view showing the structure formed in step S103 shown in Fig. 2 .
  • Figure 6 is a cross-sectional view of the second primary structure formed in step S104 shown in Figure 2 .
  • Figure 7 is a cross-sectional view of the second primary structure shown in Figure 6 upside down.
  • FIG. 8 is a flowchart of step S101 of the method of manufacturing the TFT substrate.
  • Fig. 9 is a cross-sectional view showing the structure formed in step S81 shown in Fig. 8.
  • Fig. 10 is a cross-sectional view showing the structure formed in step S82 shown in Fig. 8.
  • Fig. 11 is a cross-sectional view showing the structure formed in step S83 shown in Fig. 8.
  • FIG. 12 is a flowchart of step S106 of the method of manufacturing the TFT substrate.
  • Figure 13 is a cross-sectional view showing the structure formed in step S91 shown in Figure 12 .
  • Fig. 14 is a cross-sectional view showing the structure formed in step S92 shown in Fig. 12.
  • FIG. 1 is a TFT substrate 1 according to an embodiment of the present invention.
  • the TFT substrate 1 includes a bottom gate 10, an organic insulating layer 20, graphene 30, a gate insulating layer 40, a source 51, a top gate 53, and a drain 55.
  • the bottom gate 10 is a carbon nanotube layer. It can be understood that the bottom gate 10 can also be one of molybdenum (Mo), aluminum (Al), and copper (Cu). Or a variety of stack combinations.
  • Mo molybdenum
  • Al aluminum
  • Cu copper
  • the organic insulating layer 20 is disposed on the bottom gate 10 .
  • the organic insulating layer 20 has a thickness of 1 ⁇ m.
  • the dielectric constant of the organic insulating layer 20 needs to be three times the vacuum dielectric constant.
  • the material of the organic insulating layer 20 is polymethyl methacrylate.
  • the organic insulating layer 20 includes a first surface 21, a second surface 22, a third surface 23, a fourth surface 24, and a fifth surface 25 which are sequentially connected.
  • the second surface 22, the third surface 23, and the fourth surface 24 enclose a receiving groove 27.
  • the graphene 30 is disposed on the organic insulating layer 20 and away from the bottom gate 10, and is partially accommodated in the receiving groove 27.
  • the graphene 30 is a double layer graphene on the third surface 23,
  • the first surface 21, the second surface 22, the fourth surface 24, and the fifth surface 25 are single-layer graphene.
  • the graphene 30 includes a first graphene layer 35 and a second graphene layer 37 connected to the first graphene layer 35.
  • the first graphene layer 35 is disposed on the first surface 21, the second surface 22, the third surface 23, the fourth surface 24, and the fifth surface 25.
  • the second graphene layer 37 is connected to the first graphene layer 35.
  • the second graphene layer 37 is interposed between the first graphene layer 35 and the third surface 22 .
  • the double layer graphene serves as an active layer.
  • the gate insulating layer 40 is provided on the graphene 30 and housed in the accommodating groove 27.
  • the gate insulating layer 40 is a silicon dioxide insulating layer.
  • the gate insulating layer 20 is not limited to a silicon dioxide material, which may be replaced by other inorganic insulating materials such as yttrium oxide (Y 2 O 3 ), hafnium oxide (HfO 2 ).
  • the gate insulating layer 40 includes a first side surface 41 and a second side surface 43 opposite to each other, and the first side surface 41 is disposed adjacent to the third surface 23 and the second graphene layer 37. In other words, the second graphene layer 37 is disposed corresponding to the first side surface 41.
  • the double layer graphene is disposed adjacent to the bottom of the organic insulating layer 20 in the receiving groove 27.
  • the source 51 is provided on the first graphene layer 35 and connected to the first graphene layer 35.
  • the source 51 is located above the first surface 21 .
  • the source 51 is away from the organic insulating layer 20.
  • the top gate 53 is disposed on the gate insulating layer 40 and away from the organic insulating layer 20 .
  • the drain 55 is connected to the first graphene layer 35 and to the first graphene layer 35.
  • the drain 55 is located on the fifth surface 21.
  • the drain 55 is away from the organic insulating layer 20.
  • the source 51 and the drain 55 are connected to the double layer graphene as an active layer through a single layer of graphene to reduce the distance between the source 51 and the active layer, and the drain 55 Contact resistance with the active layer.
  • the source 51, the drain 55, and the top gate 53 are made of copper (Au).
  • a method for fabricating a TFT substrate according to an embodiment of the present invention includes the following steps:
  • Step S101 referring to FIG. 3, a metal substrate 50 is provided, and a gate insulating layer 40 is formed on the metal substrate 50 to obtain a first preliminary structure 100.
  • the material of the metal substrate 50 can be used as a base material for depositing and preparing a graphene film, and also has a conductive property for subsequent use as an electrode material, such as copper (Cu) or nickel (Ni).
  • an electrode material such as copper (Cu) or nickel (Ni).
  • Metal materials such as copper (Cu) or nickel (Ni).
  • copper (Cu) is selected as the metal substrate and has a thickness of about 1 ⁇ m (micrometer).
  • the gate insulating layer 40 is a silicon dioxide insulating layer.
  • the gate insulating layer 40 is not limited to a silicon dioxide material, which may be replaced by other inorganic insulating materials such as hafnium oxide (Y 2 O 3 ), hafnium oxide (HfO 2 ).
  • the gate insulating layer 40 includes a first side surface 41 and a second side surface 43 opposite to each other, and the first side surface 41 is disposed away from the metal substrate 50.
  • the first primary structure 100 includes a first region 102 and a second region 103 that are connected to each other, the first region 102 is a region where the first side surface 41 is located, and the second region 103 is adjacent to the first primary structure 100. The remaining portion of the side of the first side 43 is.
  • Step S102 referring to FIG. 4, depositing a graphene 30 on the first primary structure 100, the graphene 30 including a first graphene layer 35 and a second graphene layer 37 disposed in a connection, the second The graphene layer 37 forms a double layer of graphene as an active layer with a portion of the first graphene layer 35, and the double layer graphene is located on the gate insulating layer 40.
  • the graphene 30 is a double layer graphene in the first region 102 and a single layer graphene in the second region 103.
  • the first graphene layer 35 is formed in the first region 102 and the second region 103.
  • the second graphene layer 37 is formed in the first region 102.
  • the second graphene layer 37, the first graphene layer 35, and the gate insulating layer 40 are sequentially laminated. In other words, a double layer of graphene is formed on the first side face 41 of the gate insulating layer 40.
  • the graphene is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the preparation process by controlling the parameters, only two layers of graphene are deposited in the first region 101 due to the catalytic action of Cu, and a single layer of graphene is obtained in the second region 103.
  • Step S103 referring to FIG. 5, an organic insulating layer 20 is formed on the first graphene layer 35 and the second graphene layer 37.
  • the second graphene layer 37 is interposed between the first graphene layer 35 and the organic insulating layer 20 .
  • the organic insulating layer 20 is formed by solution coating and curing.
  • the organic insulating layer 20 has a thickness of about 1 ⁇ m.
  • the dielectric constant of the organic insulating layer 20 needs to be three times the vacuum dielectric constant.
  • the material of the organic insulating layer 20 is polymethyl methacrylate.
  • the organic insulating layer 20 includes a first surface 21 and a second table that are sequentially connected to each other. Face 22, third surface 23, fourth surface 24, and fifth surface 25.
  • the second surface 22, the third surface 23, and the fourth surface 24 enclose a receiving groove 27.
  • the graphene 30 is partially housed in the accommodating groove 27.
  • the graphene 30 is a bilayer graphene on the third surface 23, and the first surface 21, the second surface 22, the fourth surface 24, and the fifth surface 25 are single-layer graphite. Alkene.
  • the first graphene layer 35 is disposed adjacent to the first surface 21, the second surface 22, the third surface 23, the fourth surface 24, and the fifth surface 25.
  • the second graphene layer 37 is interposed between the first graphene layer 35 and the third surface 22 .
  • Step S104 referring to FIG. 6, a bottom gate 10 is formed on the organic insulating layer 20 to obtain a second preliminary structure 200.
  • the bottom gate 10 is a carbon nanotube layer
  • the patterned carbon nanotube layer is obtained by inkjet printing on the organic insulating layer 20 through the carbon nanotube ink.
  • the bottom gate 10 can also be a stack combination of one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • Step S105 referring to FIG. 7, the second primary structure 200 is turned upside down such that the bottom gate 10 is located at the lowermost layer, and the metal substrate 50 is located at the uppermost layer.
  • Step S106 referring again to FIG. 1, the metal substrate 50 is etched to form a source 51, a top gate 53, and a drain 55 to obtain a TFT substrate 1.
  • the source 51 and the drain 55 are the first
  • the graphene layer 35 is connected, and the top gate 53 is provided on the second side surface 43 of the gate insulating layer 40.
  • the source 51 is located on the first surface 21, and the drain 55 is located on the fifth surface 25.
  • step S101 that is, providing a metal substrate 50
  • step S102 in the step of forming the gate insulating layer 40 on the metal substrate 50, referring to FIG. 8, specifically includes the following steps:
  • Step S81 referring to FIG. 9, the metal substrate 50 is provided, and a non-pattern inorganic insulating layer 46 is deposited on the metal substrate 50.
  • Step S82 referring to FIG. 10, a patterned first photoresist layer 47 is formed on the inorganic insulating layer 46.
  • a patterned second photoresist layer 91 is obtained by a reticle-coating-developing method.
  • Step S83 referring to FIG. 11, a patterned gate insulating layer 40 is formed by a curing process.
  • Step S84 referring again to FIG. 3, the first photoresist layer 47 is peeled off to form the first preliminary structure 100.
  • the first photoresist layer 47 is peeled off by a photoresist removing liquid which has no corrosive action on the metal substrate 50.
  • step 106 that is, in the step of forming the source 51, the top gate 53 and the drain 55 on the metal substrate 50, please refer to FIG. 12, specifically including the following steps:
  • Step S91 referring to FIG. 13, a patterned second photoresist layer 91 is formed on a side of the metal substrate 50 away from the gate insulating layer 40.
  • a patterned second photoresist layer 91 is obtained by a second mask-coating-developing method.
  • Step S92 referring to FIG. 14, the metal substrate 50 is etched to obtain a source 51, a top gate 53, and a drain 55.
  • step S93 the second photoresist layer 91 is peeled off.
  • the first graphene layer 35 and the second graphene layer 37 are formed on the first side surface 41 of the gate insulating layer 40 to form a double layer graphene as an active layer.
  • the source 51 and the drain 55 are connected to the double layer graphene by a single layer of graphene, and the contact between the source 51 and the active layer and between the drain 55 and the active layer can be reduced.
  • the resistance improves the performance of the TFT substrate 1.
  • the two-layer graphene is used as an active layer, and the vertical electric field is controlled by the two gates of the top gate 53 and the bottom gate 10 to function as a switching function of the TFT.
  • the bottom gate 53 is obtained by an inkjet printing method by using carbon nanotube ink, so that the amount of use of the mask is reduced, and the cost is reduced.
  • the most common technique for obtaining graphene is chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the process of fabricating TFT devices by this method is mainly First, depositing graphene on a metal substrate such as copper/nickel by CVD, etching the metal substrate to obtain a graphene film, and transferring the graphene film to a deposited place by roll to roll or other means.
  • the substrate of the film is required to be assembled into a TFT device, and the method has the disadvantages of long cycle, complicated process, and high cost and high cost of the metal substrate.
  • the TFT substrate provided by the present application and the method of manufacturing the same directly use the metal for depositing graphene 30
  • the substrate 50 is reused as a raw material for fabricating the source 11, top gate 13, and drain 15, thereby simplifying the manufacturing process and reducing the cost.

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Abstract

一种TFT基板的制造方法。首先提供金属基底并在其上形成栅极绝缘层，得到第一初级结构。在第一初级结构上沉积形成石墨烯，石墨烯包括连接设置的第一石墨烯层及第二石墨烯层，第二石墨烯层与部分第一石墨烯层形成双层石墨烯用作有源层，双层石墨烯位于栅极绝缘层上。在石墨烯上形成有机绝缘层。再于有机绝缘层上形成底栅极，得到第二初级结构。将第二初级结构进行上下翻转，使底栅极位于最下层，金属基底位于最上层。蚀刻金属基底形成源极、顶栅极和漏极。源极及漏极与第一石墨烯层连接，降低源、漏极与双层石墨烯间的接触电阻。本发明还提供了一种TFT基板。

Description

TFT基板及其制造方法
本发明要求2017年11月22日递交的发明名称为“TFT基板及其制造方法”的申请号2017111783742的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，特别涉及一种TFT基板及其制造方法。
背景技术
在有源矩阵显示技术中，每一个像素点都由集成在其后的薄膜晶体管(Thin Film Transistor，TFT)进行驱动，从而可以实现高速度、高亮度、高对比度的屏幕显示效果。常见的TFT通常由栅极/源极/漏极(Gate/Source/Drain)三电极、绝缘层以及半导体层构成。
石墨烯，作为目前已知世界上最薄、最坚硬的纳米材料，因其具有良好的导电调控性，机械特性，导热特性，从而成为当前研究热点之一。石墨烯作为一种极薄导电率极高的新型材料，具有很大潜能被应用到电子元件/晶体管中。根据报道，石墨烯薄膜具有极低的方块电阻(＜100Ω/□)，然而经过掺杂之后，又可以形成宽带系的二维绝缘材料，因而石墨烯经过一定处理后，可形成n型或p型半导体的特性，可被应用到显示行业的TFT器件中。然而，该方法处理工艺调整困难，性能难以保证，应用到显示行业TFT器件较为困难。
发明内容
为了解决前述问题，本发明提供一种TFT基板及其制造方法。
一种TFT基板的制造方法，包括以下步骤：
步骤S101，提供金属基底，并在所述金属基底上形成栅极绝缘层，得到第一初级结构；
步骤S102，在所述第一初级结构上沉积形成石墨烯，所述石墨烯包括连 接设置的第一石墨烯层及第二石墨烯层，所述第二石墨烯层与部分所述第一石墨烯层形成双层石墨烯用作有源层，所述双层石墨烯位于所述栅极绝缘层上；
步骤S103，于所述第一石墨烯层及所述第二石墨烯层上形成有机绝缘层；
步骤S104，于所述有机绝缘层上形成底栅极，得到第二初级结构；
步骤S105，将所述第二初级结构进行上下翻转，使所述底栅极位于最下层，所述金属基底位于最上层；
步骤S106，蚀刻所述金属基底形成源极、顶栅极和漏极，其中，所述源极及所述漏极与所述第一石墨烯层连接，所述顶栅极与所述栅极绝缘层连接。
进一步地，在所述步骤S101中，包括以下步骤：
提供所述金属基底，并于所述金属基底上沉积形成无图形的无机绝缘层；
于所述无机绝缘层上形成图形化的第一光阻层；
通过固化工艺形成图形化的所述栅极绝缘层；
剥离所述第一光阻层形成所述第一初级结构。
进一步地，在所述步骤S107中，包括以下步骤：于所述金属基底远离所述栅极绝缘层的一面上形成图形化的第二光阻层；对所述金属基底进行蚀刻，得到所述源极、所述顶栅极和所述漏极；剥离所述第二光阻层。
进一步地，所述金属基底的材料为铜、或镍。
进一步地，所述栅极绝缘层的材料为二氧化硅、氧化钇、二氧化铪中的一种。
进一步地，所述有机绝缘层的材料为聚甲基丙烯酸甲酯。
进一步地，在步骤S103中，通过等离子增强化学气相沉积法沉积所述石墨烯。
一种TFT基板，其包括底栅极、有机绝缘层、石墨烯、栅极绝缘层、源极、顶栅极和漏极，所述底栅极、所述有机绝缘层、所述石墨烯及所述栅极绝缘层依次呈层叠设置，所述石墨烯包括连接设置的第一石墨烯层及第二石墨烯层，所述第一石墨烯层设于所述有机绝缘层上，所述第一石墨烯层与所述源极、所述漏极连接，所述第二石墨烯层与部分所述第一石墨烯层形成双层石墨烯用作有源层，所述双层石墨烯夹设于所述有机绝缘层与所述栅极绝缘层之间，所述顶栅极与所述栅极绝缘层连接。
进一步地，所述有机绝缘层形成容纳槽，所述栅极绝缘层容纳于所述容纳槽，所述双层石墨烯设于所述容纳槽邻近所述有机绝缘层的底部。
进一步地，所述有机绝缘层包括依次连接设置的第一表面、第二表面、第三表面、第四表面及第五表面，所述第二表面、第三表面、第四表面围成所述容纳槽，所述第一侧面邻近所述第三表面设置，所述第一石墨烯层与所述第一表面、所述第二表面、所述第三表面、所述第四表面及所述第五表面连接，所述第二石墨烯层夹设于所述第三表面与所述第一石墨烯层之间，所述源极位于所述第一表面上，所述漏极位于所述第五表面上。
进一步地，所述底栅极为碳纳米管层。
进一步地，于所述有机绝缘层通过碳纳米管墨水采用喷墨打印法得到图形化的碳纳米管层。
进一步地，所述底栅极还为钼、铝、铜中的一种或多种的堆栈组合。
上述TFT基板及其制造方法，于栅极绝缘层上设第一石墨烯层及第二石墨烯层形成双层石墨烯以作为有源层，通过顶栅极及底栅极两个栅极控制垂直电场，起到TFT的开关作用。所述源极及所述漏极通过单层石墨烯与双层石墨烯连接，进而能够降低所述源极与有源层之间及所述漏极与所述有源层之间的接触电阻，提高了所述TFT基板的性能。进一步地，通过将用于沉积石墨烯的金属基底再次利用成为制作所述源极、顶栅极和漏极的原材料，从而简化的制备工艺并降低了成本。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的TFT基板的剖视图。
图2是本发明实施例提供的TFT基板的制造方法流程图。
图3是图2所示的步骤S101中形成的第一初级结构的剖视图。
图4是图2所示的步骤S102中形成的结构的剖视图。
图5是图2所示的步骤S103中形成的结构的剖视图。
图6是图2所示的步骤S104中形成的第二初级结构的剖视图。
图7是图6所示的第二初级结构上下翻转后的剖视图。
图8是TFT基板的制造方法的步骤S101的流程图。
图9是图8所示的步骤S81中形成的结构的剖视图。
图10是图8所示的步骤S82中形成的结构的剖视图。
图11是图8所示的步骤S83中形成的结构的剖视图。
图12是TFT基板的制造方法的步骤S106的流程图。
图13是图12所示的步骤S91中形成的结构的剖视图。
图14是图12所示的步骤S92中形成的结构的剖视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，为本发明实施例提供的一种TFT基板1。所述TFT基板1包括底栅极10、有机绝缘层20、石墨烯30、栅极绝缘层40、源极51、顶栅极53和漏极55。
具体地，本实施例中，所述底栅极10为碳纳米管层，可以理解，所述底栅极10还可以为钼(Mo)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
所述有机绝缘层20设于所述底栅极10上。所述有机绝缘层20的厚度为1μm。所述有机绝缘层20的介电常数需达到3倍真空介电常数，例如所述有机绝缘层20的材料为聚甲基丙烯酸甲酯。
进一步地，所述有机绝缘层20包括依次连接设置的第一表面21、第二表面22、第三表面23、第四表面24及第五表面25。所述第二表面22、第三表面23、第四表面24围成容纳槽27。
所述石墨烯30设于所述有机绝缘层20并远离所述底栅极10，并部分容纳于所述容纳槽27。所述石墨烯30于所述第三表面23为双层石墨烯，于所 述第一表面21、所述第二表面22、所述第四表面24及所述第五表面25为单层石墨烯。具体的，所述石墨烯30包括第一石墨烯层35及与所述第一石墨烯层35连接的第二石墨烯层37。所述第一石墨烯层35设于所述第一表面21、所述第二表面22、所述第三表面23、所述第四表面24及所述第五表面25。所述第二石墨烯层37与所述第一石墨烯层35连接。所述第二石墨烯层37夹设于所述第一石墨烯层35及所述第三表面22之间。所述双层石墨烯作为有源层。
所述栅极绝缘层40设于所述石墨烯30并容纳于所述容纳槽27。本实施例中，所述栅极绝缘层40为二氧化硅绝缘层。所述栅极绝缘层20不限定为二氧化硅材料，其可以由其他无机绝缘材料替代，例如氧化钇(Y2O3)、二氧化铪(HfO2)。所述栅极绝缘层40包括相对设置的第一侧面41及第二侧面43，所述第一侧面41邻近所述第三表面23及第二石墨烯层37设置。换句话说，所述第二石墨烯层37对应所述第一侧面41设置。所述双层石墨烯设于所述容纳槽27邻近所述有机绝缘层20的底部。
所述源极51设于所述第一石墨烯层35并与所述第一石墨烯层35连接。所述源极51位于所述第一表面21上方。所述源极51远离所述有机绝缘层20。
所述顶栅极53设于所述栅极绝缘层40并远离所述有机绝缘层20。
所述漏极55于所述第一石墨烯层35并与所述第一石墨烯层35连接。所述漏极55位于所述第五表面21上。所述漏极55远离所述有机绝缘层20。
所述源极51及所述漏极55与作为有源层的双层石墨烯之间通过单层石墨烯连接，以降低所述源极51与有源层之间，及所述漏极55与有源层之间的接触电阻。本实施例中，所述源极51、所述漏极55及所述顶栅极53为铜(Au)制成。
请参阅图2，为本发明实施例提供的一种TFT基板制造方法，其包括以下步骤：
步骤S101，请参阅图3，提供金属基底50，并在所述金属基底50上形成栅极绝缘层40，得到第一初级结构100。
具体地，所述金属基底50的材料既可作为基底材料用于沉积制备石墨烯薄膜，同时也需具备导电性质，以供后续作电极材料用，例如铜(Cu)、或镍(Ni) 等金属材料。本实施例中，选用铜(Cu)作为金属基底，其厚度约为1μm(微米)。
所述栅极绝缘层40为二氧化硅绝缘层。所述栅极绝缘层40不限定为二氧化硅材料，其可以由其他无机绝缘材料替代，例如氧化钇(Y2O3)、二氧化铪(HfO2)。所述栅极绝缘层40包括相对设置的第一侧面41及第二侧面43，所述第一侧面41远离所述金属基底50设置。
所述第一初级结构100包括相互连接的第一区域102及第二区域103，所述第一区域102为第一侧面41所在区域，所述第二区域103为所述第一初级结构100邻近所述第一侧面43的侧面其余部分。
步骤S102，请参阅图4，于所述第一初级结构100上沉积形成石墨烯30，所述石墨烯30包括连接设置的第一石墨烯层35及第二石墨烯层37，所述第二石墨烯层37与部分所述第一石墨烯层35形成双层石墨烯作为有源层，所述双层石墨烯位于所述栅极绝缘层40上。
具体地，所述石墨烯30于所述第一区域102为双层石墨烯，于所述第二区域103为单层石墨烯。所述第一石墨烯层35形成于所述第一区域102及所述第二区域103。所述第二石墨烯层37形成于所述第一区域102。所述第二石墨烯层37、所述第一石墨烯层35、所述栅极绝缘层40依次层叠。换句话说，在所述栅极绝缘层40的第一侧面41上形成双层石墨烯。
通过等离子增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积所述石墨烯。本实施例中，在制备过程，通过控制参数，由于Cu的催化作用，仅在所述第一区域101沉积得到双层石墨烯，在所述第二区域103得到单层石墨烯。
步骤S103，请参阅图5，于所述第一石墨烯层35及所述第二石墨烯层37上形成有机绝缘层20。
所述第二石墨烯层37夹设于所述第一石墨烯层35与所述有机绝缘层20之间。
所述有机绝缘层20通过溶液涂布及固化形成。所述有机绝缘层20的厚度约为1μm。所述有机绝缘层20的介电常数需达到3倍真空介电常数，例如所述有机绝缘层20的材料为聚甲基丙烯酸甲酯。
进一步地，所述有机绝缘层20包括依次连接设置的第一表面21、第二表 面22、第三表面23、第四表面24及第五表面25。所述第二表面22、第三表面23、第四表面24围成容纳槽27。所述石墨烯30部分容纳于所述容纳槽27。所述石墨烯30于所述第三表面23为双层石墨烯，于所述第一表面21、所述第二表面22、所述第四表面24及所述第五表面25为单层石墨烯。
所述第一石墨烯层35邻近所述第一表面21、所述第二表面22、所述第三表面23、所述第四表面24及所述第五表面25设置。
所述第二石墨烯层37夹设于所述第一石墨烯层35及所述第三表面22之间。
步骤S104，请参阅图6，于所述有机绝缘层20上形成底栅极10，得到第二初级结构200。
本实施例中，所述底栅极10为碳纳米管层，在所述有机绝缘层20通过碳纳米管墨水采用喷墨打印法得到图形化的碳纳米管层。
可以理解，所述底栅极10还可以为钼(Mo)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
步骤S105，请参阅图7，将所述第二初级结构200进行上下翻转，使所述底栅极10位于最下层，所述金属基底50位于最上层。
步骤S106，请再次参阅图1，蚀刻金属基底50形成源极51、顶栅极53和漏极55，得到TFT基板1，其中，所述源极51及所述漏极55与所述第一石墨烯层35连接，所述顶栅极53设于所述栅极绝缘层40的第二侧面43。
所述源极51位于所述第一表面21上，所述漏极55位于所述第五表面25上。
进一步地，在步骤S101，即，提供金属基底50，在所述金属基底50上形成栅极绝缘层40的步骤中，请参阅图8，具体包括以下步骤：
步骤S81，请参阅图9，提供所述金属基底50，并于所述金属基底50上沉积形成无图形的无机绝缘层46。
步骤S82，请参阅图10，于所述无机绝缘层46上形成图形化的第一光阻层47。
具体地，通过一道光罩-涂布光胶-显影的方式，得到图形化的第二光阻层91。
步骤S83，请参阅图11，通过固化工艺形成图形化的栅极绝缘层40。
步骤S84，请再次参阅图3，剥离所述第一光阻层47形成所述第一初级结构100。
在步骤S84中，本实施例中，采用的是对所述金属基底50无腐蚀作用的去光阻液剥离所述第一光阻层47。
进一步地，在步骤106中，即，在所述金属基底50上形成源极51、顶栅极53和漏极55的步骤中，请参阅图12，具体包括以下步骤：
步骤S91，请参阅图13，于所述金属基底50远离所述栅极绝缘层40的一面上形成图形化的第二光阻层91。
具体地，通过第二道光罩-涂布光胶-显影的方式，得到图形化的第二光阻层91。
步骤S92，请参阅图14，对所述金属基底50进行蚀刻，得到源极51、顶栅极53和漏极55。
步骤S93，剥离所述第二光阻层91。
本申请提供的TFT基板及其制造方法，于栅极绝缘层40的第一侧面41上设第一石墨烯层35及第二石墨烯层37形成双层石墨烯以作为有源层，所述源极51及所述漏极55通过单层石墨烯与双层石墨烯连接，能够降低所述源极51与有源层之间及所述漏极55与所述有源层之间的接触电阻，提高了所述TFT基板1的性能。更甚者，以所述双层石墨烯作为有源层，通过顶栅机53及底栅极10两个栅极控制垂直电场，起到TFT的开关作用。进一步地，所述底栅极53通过碳纳米管墨水采用喷墨打印法得到，故减少光罩使用量，降低成本。
此外，传统的技术中，对于大面积制备石墨烯，较常用且得到的石墨烯性能较好的技术主要为化学气相沉积法(Chemical Vapor Deposition，CVD)，利用该方法制作TFT器件的过程主要为，首先在金属基底如铜/镍上通过CVD法沉积石墨烯，再蚀刻掉金属基底得到石墨烯薄膜，再将该石墨烯薄膜通过卷对卷(Roll to Roll)或其他方式转移至已沉积所需薄膜的基底上，从而组装成TFT器件，该方法具有周期长，工艺复杂，且金属基底耗费大成本高的等缺点。
本申请提供的TFT基板及其制造方法，直接将用于沉积石墨烯30的金属 基底50再次利用成为制作所述源极11、顶栅极13和漏极15的原材料，从而简化制造工艺及降低了成本。
可以理解，以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (15)

  1. 一种TFT基板的制造方法，其特征在于，包括以下步骤：
    步骤S101，提供金属基底，并在所述金属基底上形成栅极绝缘层，得到第一初级结构；
    步骤S102，在所述第一初级结构上沉积形成石墨烯，所述石墨烯包括连接设置的第一石墨烯层及第二石墨烯层，所述第二石墨烯层与部分所述第一石墨烯层形成双层石墨烯用作有源层，所述双层石墨烯位于所述栅极绝缘层上；
    步骤S103，于所述第一石墨烯层及所述第二石墨烯层上形成有机绝缘层；
    步骤S104，于所述有机绝缘层上形成底栅极，得到第二初级结构；
    步骤S105，将所述第二初级结构进行上下翻转，使所述底栅极位于最下层，所述金属基底位于最上层；
    步骤S106，蚀刻所述金属基底形成源极、顶栅极和漏极，其中，所述源极及所述漏极与所述第一石墨烯层连接，所述顶栅极与所述栅极绝缘层连接。
  2. 如权利要求1所述的制造方法，其中，在所述步骤S101中，包括以下步骤：
    提供所述金属基底，并于所述金属基底上沉积形成无图形的无机绝缘层；
    于所述无机绝缘层上形成图形化的第一光阻层；
    通过固化工艺形成图形化的所述栅极绝缘层；
    剥离所述第一光阻层形成所述第一初级结构。
  3. 如权利要求1所述的制造方法，其中，在所述步骤S107中，包括以下步骤：
    于所述金属基底远离所述栅极绝缘层的一面上形成图形化的第二光阻层；
    对所述金属基底进行蚀刻，得到所述源极、所述顶栅极和所述漏极；
    剥离所述第二光阻层。
  4. 如权利要求1所述的制造方法，其中，所述金属基底的材料为铜、或镍。
  5. 如权利要求1所述的制造方法，其中，所述栅极绝缘层的材料为二氧化硅、氧化钇、二氧化铪中的一种。
  6. 如权利要求1所述的制造方法，其中，所述有机绝缘层的材料为聚甲基丙 烯酸甲酯。
  7. 如权利要求1所述的制造方法，其中，在步骤S103中，通过等离子增强化学气相沉积法沉积所述石墨烯。
  8. 如权利要求1所述的制造方法，其中，在步骤S104中，所述底栅极为碳纳米管层。
  9. 如权利要求8所述的制造方法，其中，于所述有机绝缘层通过碳纳米管墨水采用喷墨打印法得到图形化的碳纳米管层。
  10. 一种TFT基板，其包括底栅极、有机绝缘层、石墨烯、栅极绝缘层、源极、顶栅极和漏极，所述底栅极、所述有机绝缘层、所述石墨烯及所述栅极绝缘层依次呈层叠设置，其中，所述石墨烯包括连接设置的第一石墨烯层及第二石墨烯层，所述第一石墨烯层设于所述有机绝缘层上，所述第一石墨烯层与所述源极、所述漏极连接，所述第二石墨烯层与部分所述第一石墨烯层形成双层石墨烯用作有源层，所述双层石墨烯夹设于所述有机绝缘层与所述栅极绝缘层之间，所述顶栅极与所述栅极绝缘层连接。
  11. 如权利要求10所述的TFT基板，其中，所述有机绝缘层形成容纳槽，所述栅极绝缘层容纳于所述容纳槽，所述双层石墨烯设于所述容纳槽邻近所述有机绝缘层的底部。
  12. 如权利要求11所述的TFT基板，其中，所述有机绝缘层包括依次连接设置的第一表面、第二表面、第三表面、第四表面及第五表面，所述第二表面、第三表面、第四表面围成所述容纳槽，所述第一侧面邻近所述第三表面设置，所述第一石墨烯层与所述第一表面、所述第二表面、所述第三表面、所述第四表面及所述第五表面连接，所述第二石墨烯层夹设于所述第三表面与所述第一石墨烯层之间，所述源极位于所述第一表面上，所述漏极位于所述第五表面上。
  13. 如权利要求10所述的TFT基板，其中，所述底栅极为碳纳米管层。
  14. 如权利要求13所述的TFT基板，其中，于所述有机绝缘层通过碳纳米管墨水采用喷墨打印法得到图形化的碳纳米管层。
  15. 如权利要求10所述的TFT基板，其中，所述底栅极还为钼、铝、铜中的一种或多种的堆栈组合。
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