WO2017024548A1 - 一种液晶面板、tft基板及其检测方法 - Google Patents

一种液晶面板、tft基板及其检测方法 Download PDF

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Publication number
WO2017024548A1
WO2017024548A1 PCT/CN2015/086739 CN2015086739W WO2017024548A1 WO 2017024548 A1 WO2017024548 A1 WO 2017024548A1 CN 2015086739 W CN2015086739 W CN 2015086739W WO 2017024548 A1 WO2017024548 A1 WO 2017024548A1
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Prior art keywords
pixel unit
pixel
row
auxiliary
scan line
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PCT/CN2015/086739
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English (en)
French (fr)
Inventor
刘桓
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深圳市华星光电技术有限公司
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Priority to US14/783,771 priority Critical patent/US10043426B2/en
Publication of WO2017024548A1 publication Critical patent/WO2017024548A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
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    • G09G2300/04—Structural and physical details of display devices
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    • G09G2300/0426—Layout of electrodes and connections
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal panel, a TFT substrate, and a detecting method thereof.
  • a pixel unit In a liquid crystal display with a large viewing angle, a pixel unit is generally divided into a main pixel region (Main region) and a sub-pixel region (Sub region), and the voltage of the Sub region is lower than the voltage of the Main region.
  • charge-sharing is a commonly used method.
  • FIG. 1 is a pixel of the prior art adopting "charge sharing" mode. The structural diagram of the unit.
  • the pixel unit 100 shown in FIG. 1 is divided into a main area 101 and a Sub area 102.
  • the scan line G11 provides a scan driving signal
  • the switch tubes 103 and 104 are simultaneously turned on
  • the signal line S11 (Data) simultaneously goes to the Main area 101 and Sub.
  • the pixel electrode of the region 102 that is, ITO (Indium Tin oxide
  • the scan line G11 stops supplying the scan driving signal
  • the shared scan line G12 starts to provide the scan driving signal
  • the switch tube 105 is turned on
  • the voltage dividing capacitor C11 is turned on with the pixel electrode of the Sub area 102
  • a part of the Sub area is shared.
  • the charge on the pixel electrode of 102 causes the voltage of the pixel electrode of the Sub region 102 to be lowered to an appropriate ratio to be displayed together with the pixel electrode of the main region 101 to form a large viewing angle effect.
  • the pixel unit 100 shown in FIG. 1 is fabricated in a 4Mask process, and the voltage dividing capacitor C11 usually adopts an MII (double-layer metal) capacitor structure, that is, the voltage dividing capacitor C11 has the structure: M1 (first layer) Metal), G-SiNx (gate silicon nitride), PA-SiNx (filled nitride layer), ITO conductive film.
  • M1 first layer
  • G-SiNx gate silicon nitride
  • PA-SiNx filled nitride layer
  • ITO conductive film ITO conductive film
  • the scan line G11 supplies the scan driving signal
  • the data line S11 simultaneously charges the pixel electrode of the Sub area 102 and the pixel electrode of the Main area 101 and the voltage dividing capacitor C11.
  • the scan line G11 stops supplying the scan driving signal and the shared scan line G12 provides the scan drive signal
  • the voltage dividing capacitor C11 cannot share the charge of the Sub region 102, so that the voltage is divided.
  • the voltage fails, so that the potential of the Sub region 102 cannot be pulled down, and the effect of a large viewing angle cannot be formed.
  • the defective pixel is also made brighter than the normal pixel, thereby generating a micro bright spot under the medium and low gray scale, which affects the quality of the liquid crystal panel.
  • the technical problem to be solved by the present invention is to provide a liquid crystal panel, a TFT substrate, and a detecting method thereof, which can detect whether a capacitance in a same pixel unit is short-circuited with a main pixel area or a sub-pixel area, so that repair and improvement can be performed in time. product quality.
  • a technical solution adopted by the present invention is to provide a TFT substrate, and the TFT substrate includes:
  • each of the pixel units includes a main pixel area, a sub-pixel area, and a capacitor
  • the pixel unit including a first pixel unit distributed in odd rows and a second pixel distributed in even rows a unit, a secondary pixel unit of the 2n+1th row is electrically connected to a capacitance of the second pixel unit of the 2n+2th row, and a second pixel unit of the 2n+2th row is auxiliary
  • the pixel region is electrically connected to the capacitance of the first pixel unit of the 2n+1th row, where n is a natural number;
  • the first pixel unit and the second pixel unit are respectively provided with unequal voltage signals to detect whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area.
  • the secondary pixel region of the first pixel unit of the 2n+1th row and the secondary pixel region of the second pixel unit of the 2n+2th row are close to each other, and the first pixel unit of the 2n+1th row
  • the main pixel area and the main pixel area of the second pixel unit of the 2n+2th row are distant from each other;
  • the capacitance of the first pixel unit of the 2n+1th row is set between the auxiliary pixel region and the second pixel unit of the 2n+2th row, and the capacitance of the second pixel unit of the 2n+2th row It is disposed between its auxiliary pixel area and the first pixel unit of the 2n+1th row.
  • the voltage signals received by the main pixel area and the sub-pixel area in the pixel unit of the same row are equal.
  • the TFT substrate further includes a first scan line, a second scan line, a shared scan line, a first switch tube, and a second switch tube, wherein:
  • the first scan line is electrically connected to the first pixel unit
  • the second scan line is electrically connected to the second pixel unit
  • the first switch tube is electrically connected to the shared scan line, the auxiliary pixel region of the first pixel unit of the 2n+1th row, and the capacitance of the second pixel unit of the 2n+2th row;
  • the second switch tube electrically connects the shared scan line, the auxiliary pixel area of the second pixel unit of the 2n+2th row, and the capacitance of the first pixel unit of the 2n+1th row, respectively;
  • the sharing line is further electrically connected to the first scan line, so that when the scan driving signal is supplied to the first scan line, the first switch tube and the second switch tube on the shared scan line are both guided through.
  • the scan driving signal is provided for the first scan line and the second scan line.
  • the difference between the voltage signals provided by the first pixel unit and the second pixel unit is greater than or equal to 6V.
  • a liquid crystal panel including a TFT substrate, the TFT substrate including:
  • each of the pixel units includes a main pixel area, a sub-pixel area, and a capacitor
  • the pixel unit including a first pixel unit distributed in odd rows and a second pixel distributed in even rows a unit, a secondary pixel unit of the 2n+1th row is electrically connected to a capacitance of the second pixel unit of the 2n+2th row, and a second pixel unit of the 2n+2th row is auxiliary
  • the pixel region is electrically connected to the capacitance of the first pixel unit of the 2n+1th row, where n is a natural number;
  • the first pixel unit and the second pixel unit are respectively provided with unequal voltage signals to detect whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area.
  • the secondary pixel region of the first pixel unit of the 2n+1th row and the secondary pixel region of the second pixel unit of the 2n+2th row are close to each other, and the first pixel unit of the 2n+1th row
  • the main pixel area and the main pixel area of the second pixel unit of the 2n+2th row are distant from each other;
  • the capacitance of the first pixel unit of the 2n+1th row is set between the auxiliary pixel region and the second pixel unit of the 2n+2th row, and the capacitance of the second pixel unit of the 2n+2th row It is disposed between its auxiliary pixel area and the first pixel unit of the 2n+1th row.
  • the voltage signals received by the main pixel area and the sub-pixel area in the pixel unit of the same row are equal.
  • the TFT substrate further includes a first scan line, a second scan line, a shared scan line, a first switch tube, and a second switch tube, wherein:
  • the first scan line is electrically connected to the first pixel unit
  • the second scan line is electrically connected to the second pixel unit
  • the first switch tube is electrically connected to the shared scan line, the auxiliary pixel region of the first pixel unit of the 2n+1th row, and the capacitance of the second pixel unit of the 2n+2th row;
  • the second switch tube electrically connects the shared scan line, the auxiliary pixel area of the second pixel unit of the 2n+2th row, and the capacitance of the first pixel unit of the 2n+1th row, respectively;
  • the sharing line is further electrically connected to the first scan line, so that when the scan driving signal is supplied to the first scan line, the first switch tube and the second switch tube on the shared scan line are both guided through.
  • the scan driving signal is provided for the first scan line and the second scan line.
  • the difference between the voltage signals provided by the first pixel unit and the second pixel unit is greater than or equal to 6V.
  • another technical solution adopted by the present invention is to provide a method for detecting a TFT substrate, wherein the TFT substrate is the first four TFT substrates described above, and the detecting method includes the following steps:
  • auxiliary pixel region of the pixel unit is electrically connected to the capacitance of the second pixel unit of the 2n+2th row through the first switching transistor, and the auxiliary pixel region of the second pixel unit of the 2nd+2th row is electrically connected to the second through the second switching transistor +1 row of capacitance of the first pixel unit;
  • Detecting whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area by detecting whether the voltage signal of the auxiliary pixel area of the second pixel unit changes, wherein if the second pixel unit is detected If the voltage signal in the pixel region changes, it is detected that the capacitance in the same pixel unit is short-circuited with the main pixel region or the auxiliary pixel region; if the voltage signal of the auxiliary pixel region of the second pixel unit is detected to be unchanged, the detection is performed.
  • the capacitor in the same pixel unit is not short-circuited with the main pixel area or the auxiliary pixel area.
  • the step of providing the scan driving signal to the first pixel unit further includes:
  • the supply of the scan driving signal to the second pixel unit is stopped.
  • the difference between the voltage signals provided by the first pixel unit and the second pixel unit is greater than or equal to 6V.
  • the TFT substrate of the present invention includes a plurality of pixel units arranged in a matrix, wherein each of the pixel units includes a main pixel area, a sub-pixel area, and a capacitor,
  • the pixel unit includes a first pixel unit distributed in odd rows and a second pixel unit distributed in even rows, a secondary pixel region of the first pixel unit of the 2n+1th row and the second pixel of the 2n+2th row
  • the capacitance of the pixel unit is electrically connected, and the auxiliary pixel region of the second pixel unit of the 2n+2th row is electrically connected to the capacitance of the first pixel unit of the 2n+1th row, and n is a natural number.
  • the first pixel unit and the second pixel unit are respectively provided with unequal voltage signals to detect whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area. Thereby, it is possible to detect whether or not the capacitance in the same pixel unit is short-circuited with the main pixel area or the sub-pixel area, so that repair can be performed in time to improve product quality.
  • FIG. 1 is a structural diagram of a pixel unit of the prior art
  • FIG. 2 is a schematic structural diagram of a liquid crystal panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of two adjacent rows of pixel units in the liquid crystal panel shown in FIG. 2;
  • FIG. 4 is a flowchart of a method for detecting a TFT substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a liquid crystal panel according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of two adjacent rows of pixel units in the liquid crystal panel shown in FIG.
  • the liquid crystal panel 200 of the present embodiment includes a TFT (Thin Film Transistor, thin film transistor substrate 20, which includes a plurality of pixel units 21 arranged in a matrix.
  • Each of the pixel units 21 includes a main pixel region 22, a sub-pixel region 23, and a capacitor 24.
  • the pixel unit 21 includes a first pixel unit 211 distributed in odd rows and a second pixel unit 212 distributed in even rows.
  • the odd number is represented by 2n+1
  • the even number is represented by 2n+2
  • n is a natural number, for example, 0, 1, 2, 3....
  • the secondary pixel region 231 of the first pixel unit 211 of the 2n+1th row is electrically connected to the capacitance 242 of the second pixel unit 212 of the 2n+2th row
  • the second pixel unit 212 of the 2n+2th row is electrically connected.
  • the auxiliary pixel region 232 is electrically connected to the capacitance 241 of the first pixel unit 211 of the 2n+1th row.
  • the secondary pixel region 231 of the first pixel unit 211 of the 2n+1th row and the secondary pixel region 232 of the second pixel unit 212 of the 2n+2th row are close to each other, and the first pixel unit 211 of the 2n+1th row is adjacent to each other.
  • the main pixel region 221 and the main pixel region 222 of the second pixel unit 212 of the 2n+2th row are distant from each other. That is to say, the arrangement of the first pixel unit 211 of the 2n+1th row is opposite to the arrangement of the second pixel unit 212 of the 2n+2th row. For example, as shown in FIG.
  • the auxiliary pixel area 231 of the first pixel unit 211 of the first row and the secondary pixel area 232 of the second pixel unit 212 of the second row are close to each other, and the main pixel of the first pixel unit 211 of the first row
  • the main pixel regions 222 of the second pixel unit 212 of the region 221 and the second row are distant from each other.
  • the arrangement of pixel units of other rows is also the same.
  • the capacitance 241 of the first pixel unit 211 of the 2n+1th row is disposed between the auxiliary pixel area 231 and the second pixel unit 212 of the 2n+2th row, and the 2n+2th row
  • the capacitance 242 of the second pixel unit 212 is disposed between its secondary pixel region 232 and the first pixel unit 211 of the 2n+1th row.
  • the auxiliary pixel region 231 is disposed adjacent to the capacitor 241
  • the auxiliary pixel region 232 is disposed adjacent to the capacitor 242
  • the two capacitors 241 and 242 are disposed between the two auxiliary pixel regions 231 and 232.
  • the arrangement of the first pixel unit 211 and the second pixel unit 212 may be the same, and the capacitors 241 and 242 and the main pixel area 221 and the second pixel unit 212 of the first pixel unit 211, respectively.
  • the pixel regions 222 are disposed adjacent to each other.
  • the voltage signals provided by the main pixel area and the auxiliary pixel area of the pixel unit of the same row are equal.
  • unequal voltage signals are respectively supplied to the first pixel unit 211 and the second pixel unit 212 to detect whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area.
  • the difference between the voltage signals supplied to the first pixel unit 211 and the second pixel unit 212 is greater than or equal to 6V.
  • the circuit structure specifically implemented is as follows:
  • the TFT substrate 20 further includes a plurality of first scan lines G21, second scan lines G22, shared scan lines G23, first data lines S20, second data lines S21, and switches 25, 26, 27, 28, 29 arranged in parallel. And 30.
  • the number of the first scanning lines G21 is equal to the number of rows of the first pixel unit 211, and the number of the data lines S20 is equal to the number of columns of the first pixel unit 211.
  • Each of the first scan lines G21 is electrically connected to a corresponding row of first pixel units 211, and each of the data lines S20 is electrically connected to a corresponding column of the first pixel units 211.
  • the first scan line G21 is electrically connected to the control ends of the switch tubes 27 and 28, and the data line S20 is electrically connected to the input ends of the switch tubes 27, 28, and the output ends of the switch tubes 27, 28 are electrically connected respectively.
  • the main pixel region 221 and the auxiliary pixel region 231 of the first pixel unit 211 should be understood that the output ends of the switching transistors 27, 28 are specifically ITO electrodes electrically connecting the main pixel region 221 and the auxiliary pixel region 231, respectively.
  • the switching transistors 27 and 28 are simultaneously turned on, and the input terminal and the output terminal of the switching transistors 27 and 28 are respectively turned on, and the voltage signal supplied from the data line S20 passes through the turned-on input terminal.
  • the output terminal are respectively supplied to the main pixel region 221 and the sub-pixel region 231 to charge the main pixel region 221 and the sub-pixel region 231.
  • all of the first scanning lines G21 are connected to the same shorting bar (shorting Bar) on L1.
  • the switching transistors 27 and 28 of all the first pixel units 211 are simultaneously turned on by simultaneously supplying the scan driving signals to the first scanning line G21, thereby simultaneously charging the main pixel region 221 and the auxiliary pixel region 231 of the first pixel unit 211.
  • all the data lines S20 may be connected to the same shorting bar to simultaneously supply the same voltage signal to the first pixel unit 211.
  • the number of the second scanning lines G22 is equal to the number of rows of the second pixel unit 212, and the number of the data lines S21 is equal to the number of columns of the second pixel unit 212.
  • Each second scan line G22 is electrically connected to a corresponding row of second pixel units 212, and each data line S21 is electrically connected to a corresponding column of second pixel units 212.
  • the second scan line G22 is electrically connected to the control ends of the switch tubes 29 and 30, the data line S21 is electrically connected to the input ends of the switch tubes 29, 30, and the output ends of the switch tubes 29 and 30 are respectively electrically connected.
  • the main pixel area 222 and the sub-pixel area 232 of the second pixel unit 212 are respectively electrically connected.
  • the output ends of the switching transistors 29 and 30 are specifically ITO electrodes electrically connecting the main pixel region 222 and the sub-pixel region 232, respectively.
  • the switching transistors 29 and 30 are simultaneously turned on, and the input terminal and the output terminal of the switching transistors 29 and 30 are respectively turned on, and the voltage signal supplied from the data line S21 passes through the turned-on input terminal.
  • the output and the output are respectively supplied to the main pixel area 222 and the sub-pixel area 232 to charge the main pixel area 222 and the sub-pixel area 232.
  • all of the second scanning lines G22 are connected to the same shorting bar (shorting Bar) on L2.
  • the switching transistors 29 and 30 of all the second pixel units 212 are simultaneously turned on by simultaneously supplying the scan driving signals to the second scanning line G22, thereby simultaneously charging the main pixel region 222 and the sub-pixel region 232 of the second pixel unit 212.
  • all the data lines S21 may be connected to the same shorting bar to simultaneously provide the same voltage signal to the second pixel unit 212.
  • the shared scan line G23 is disposed between the first pixel unit 211 and the second pixel unit 212. And the shared scan line G23 is further electrically connected to the first scan line G21, more specifically, the scan drive signal provided in the normal operation phase, that is, the non-detection phase, in the two first scan lines G21 adjacent thereto.
  • the later first scanning line G21 is connected.
  • the switch tube 25 electrically connects the shared scan line G23, the auxiliary pixel region 213 of the first pixel unit 211 of the 2n+1th row, and the capacitor 242 of the second pixel unit 212 of the 2n+2th row, respectively.
  • the number of the switching tubes 25 is equal to the number of the capacitances 241 of the first pixel unit 211.
  • the control terminal of each of the switch tubes 25 is electrically connected to a shared scan line G23.
  • the input terminal and the output terminal are electrically connected to the auxiliary pixel region 213 and the second pixel unit 212 of the first pixel unit 211 on both sides of the shared scan line G23, respectively.
  • the second switching tube 26 electrically connects the shared pixel line 232 of the second pixel unit 212 of the second scan unit G23, the second n+2 row, and the capacitor 241 of the first pixel unit 211 of the second n+1 row. Specifically, the number of the switching tubes 26 and the number of the capacitors 242 of the second pixel unit 212 are equal.
  • the control terminal of each of the switch tubes 26 is electrically connected to a shared scan line G23.
  • the input terminal and the output terminal are electrically connected to the auxiliary pixel region 232 and the first pixel unit 211 of the second pixel unit 212 on both sides of the shared scan line G23, respectively.
  • the adjacent two capacitors 241 and 242 respectively correspond to the switch tubes 25 and 26 sharing the same shared scan line G23. Thereby, the number of shared scanning lines is reduced, the aperture ratio of the pixel unit is increased, and the transmittance of the liquid crystal panel 200 can be provided.
  • the switch tubes 25 and 26 may be electrically connected to a shared scan line G23, respectively, regardless of the transmittance.
  • control end of the above-mentioned switch tube is the gate of the switch tube, the input end is one of the source or the drain of the switch tube, and the output end is the other of the source or the drain.
  • the detection principle of the TFT substrate 20 of the present embodiment will be described below:
  • the scan driving signal is provided for the first scan line G21 and the second scan line G22 in a time division manner.
  • This embodiment exemplifies the detection principle of the structure in which the arrangement of the first pixel unit 211 and the second pixel unit 212 shown in FIG. 2 is reversed: first, the high-level signal is given to the short-circuit bar L2, and the low-level signal of the short-circuit bar L1 is used.
  • the second scan line G22 of the second pixel unit 212 of the even-numbered row receives the scan driving signal, so that the corresponding switch transistors 29 and 30 are turned on, and the data line S21 supplies the voltage signal to the corresponding main pixel region 222 and the auxiliary pixel region. 232.
  • the main pixel region 222 and the auxiliary pixel region 232 of the second pixel unit 212 of all the even rows are written with a 1 V pixel voltage.
  • a short-level signal is then supplied to the shorting bar L2 to turn off the switching transistors 29 and 30, and the charging of the main pixel region 222 and the auxiliary pixel region 232 is ended.
  • the short-circuit bar L1 is supplied with a high-level signal, and then the first scan line G21 of the first pixel unit 211 of all odd rows receives the scan drive signal, so that the corresponding switch tubes 27 and 28 are turned on, and the data line S20 turns the voltage signal.
  • the voltage signal provided at this time is 16V, and the main pixel region 221 and the auxiliary pixel region 231 of the first pixel unit 211 of all odd rows are written with the 16V pixel voltage. .
  • the capacitor 241 divides the auxiliary pixel area 232 of the second pixel unit 212, that is, the auxiliary pixel area 232.
  • the voltage of 1V is divided.
  • the capacitor 242 obtains a voltage signal from the data line S20 through the auxiliary pixel region 231, and obtains a voltage signal of 16 V like the auxiliary pixel region 231 of the first pixel unit 211.
  • the data line S20 is charged to the secondary pixel region 232 of the second pixel unit 212 by the shorted capacitance.
  • the voltage of the auxiliary pixel region 232 is increased from 1V to 16V.
  • the secondary pixel region 232 of the second pixel unit 212 is short-circuited with the capacitor 242
  • the secondary pixel region 232 is electrically connected to the secondary pixel region 231 of the first pixel unit 211 through the capacitor 242, thereby causing the data line S20 to pass.
  • the shorted capacitor 242 writes a 16V voltage signal to the secondary pixel region 232.
  • the auxiliary pixel region 231 of the first pixel unit 211 is short-circuited with the capacitor 241
  • the auxiliary pixel region 231 is electrically connected to the auxiliary pixel region 232 of the second pixel unit 212 through the capacitor 241, so that the data line S20 is also A 16V voltage signal is written to this secondary pixel region 232. It can be seen that whether the secondary pixel region 231 of the first pixel unit 211 of the odd-numbered row is short-circuited with the capacitor 241 or the secondary pixel region 232 of the second pixel unit 212 of the even-numbered row is short-circuited with the capacitor 242, an even-numbered row is caused.
  • the voltage of the auxiliary pixel region 232 of the second pixel unit 212 is changed from 1V to 16V. This voltage difference can make Array Test is checked out. Therefore, the circuit structure of the present invention can be in Array In the test, the defect in which the auxiliary pixel area of the pixel unit is short-circuited is detected, so that the defective pixel unit is repaired in time.
  • the embodiment of the present invention provides that the high- and low-voltage signals are respectively supplied to the first pixel unit 211 and the second pixel unit 212 to detect whether the secondary pixel area and the main pixel area of the pixel unit are short-circuited.
  • the foregoing is to detect whether the capacitance in the same pixel unit is short-circuited with the auxiliary pixel region by detecting whether the voltage of the auxiliary pixel region 232 of the second pixel unit 212 is changed. Specifically, if it is detected that the voltage of the auxiliary pixel region 232 of the second pixel unit 212 changes, it is detected that the capacitance in the same pixel unit is short-circuited with the auxiliary pixel region. On the other hand, if it is detected that the voltage of the secondary pixel region 232 of the second pixel unit 212 does not change, it is detected that the capacitance in the same pixel unit and the secondary pixel region are not short-circuited.
  • the first pixel unit 211 or the second pixel unit 212 it is also possible to provide a voltage signal only to the first pixel unit 211 or the second pixel unit 212. If only the corresponding pixel unit detects a voltage, it is indicated that there is no case where the first pixel unit 211 and the second pixel unit 212 are short-circuited with the capacitor. Conversely, if both the first pixel unit 211 and the second pixel unit 212 detect a voltage signal, it is indicated that at least one of the first pixel unit 211 and the second pixel unit 212 has a case where the auxiliary pixel region is short-circuited with the capacitor. It should be understood that the voltage signal at this time is greater than or equal to 6V. In this case, in order to save costs and simplify the process, a shorting bar can be omitted.
  • the shorting bars L1 and L2 are used in the detecting phase, and in the normal display phase, the connection of the first scanning line G21 and the shorting bar L1 and the connection of the second scanning line G22 and the shorting bar L2 need to be disconnected. .
  • the above is exemplified by the detection principle of the structure in which the arrangement of the first pixel unit 211 and the second pixel unit 212 shown in FIG. 2 is reversed. It should be understood that the first pixel unit 211 and the second pixel unit 212 are arranged in the same manner. And in the structure in which the capacitors 241 and 242 are respectively disposed adjacent to the main pixel region 221 of the first pixel unit 211 and the main pixel region 222 of the second pixel unit 212, the detection principle is also the same. At this time, it is detected whether the capacitor in the same pixel unit is short-circuited with the main pixel region.
  • the present invention also provides a TFT detecting method which is applied to the TFT substrate 20 described above.
  • 4 is a flowchart of a method for detecting a TFT substrate according to an embodiment of the present invention. As shown in FIG. 4, the detection method of the present invention includes the following steps:
  • Step S1 providing a scan driving signal to the second pixel unit 212 to supply a voltage signal to the second pixel unit 212.
  • a scan driving signal is first supplied to the second scan line G22 to turn on the switch tubes 29 and 30 electrically connected to the second scan line G22, and then supply voltage signals to the open switch tubes 29 and 30 to pass through the switch tube 29.
  • the sum signal 30 transmits the voltage signal to the main pixel area 222 and the sub-pixel area 232 of the second pixel unit 212 electrically connected thereto.
  • the voltage signal is a low voltage signal.
  • Step S2 providing a scan driving signal to the first pixel unit 211 to provide a voltage signal different from the second pixel unit 212 to the first pixel unit 211 while opening the first switch tube 25 and the second switch tube 26, so that the second
  • the auxiliary pixel region 231 of the first pixel unit 211 of the +1 row is electrically connected to the capacitance 242 of the second pixel unit 212 of the 2n+2th row through the first switching transistor 25, and the second pixel unit 212 of the 2n+2th row
  • the auxiliary pixel region 232 is electrically connected to the capacitor 241 of the first pixel unit 211 of the 2n+1th row through the second switching transistor 26.
  • Step S3 detecting whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area by detecting whether the voltage of the auxiliary pixel area of the second pixel unit 212 is changed. Specifically, if it is detected that the voltage of the auxiliary pixel region 232 of the second pixel unit 212 changes, it is detected that the capacitance in the same pixel unit is short-circuited with the main pixel region or the auxiliary pixel region.
  • the capacitors 241 and 242 are respectively disposed adjacent to the auxiliary pixel regions 231 and 232 as shown in FIG. 2, it is detected in this step whether the capacitance in the same pixel unit is short-circuited with the auxiliary pixel region. If the capacitors 241 and 242 are disposed adjacent to the main pixel regions 221 and 222, respectively, this step detects whether the capacitance in the same pixel unit is shorted to the main pixel region.
  • the supply of the scan driving signal to the second pixel unit 212 is stopped before the step of supplying the scan driving signal to the first pixel unit 211. That is, the scan driving signals are supplied to the first scanning line G21 and the second scanning line G22 at the time division.
  • the difference between the voltage signals supplied to the first pixel unit 211 and the second pixel unit 212 is greater than or equal to 6V. As described above, the voltage signal supplied to the first pixel unit 211 is 16V, and the voltage signal supplied to the second pixel unit 212 is 1V.
  • first pixel unit 211 or the second pixel unit 212 it is also possible to supply a voltage signal only to the first pixel unit 211 or the second pixel unit 212. If only the corresponding pixel unit detects a voltage, it is indicated that there is no case where the first pixel unit 211 and the second pixel unit 212 are short-circuited with the capacitor. Conversely, if both the first pixel unit 211 and the second pixel unit 212 detect a voltage signal, it is indicated that at least one of the first pixel unit 211 and the second pixel unit 212 has a case where the auxiliary pixel region is short-circuited with the capacitor. It should be understood that the voltage signal at this time is greater than or equal to 6V.
  • the present invention can detect whether the capacitance in the same pixel unit is short-circuited with the main pixel area or the auxiliary pixel area, so that repair can be performed in time to improve product quality.

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Abstract

一种液晶面板（200）、TFT基板（20）以及TFT基板（20）的检测方法。TFT基板（20）包括多个像素单元（21），第2n+1行的第一像素单元（211）的辅像素区（231）与第2n+2行的第二像素单元（212）的电容（242）电连接，第2n+2行的第二像素单元（212）的辅像素区（232）与第2n+1行的第一像素单元（211）的电容（241）电连接，对第一像素单元（211）和第二像素单元（212）分别提供不相等的电压信号。通过上述方式，能检测出同一像素单元中的电容与辅像素区是否短接，从而及时进行修补，改善产品品质。

Description

一种液晶面板、TFT基板及其检测方法
【技术领域】
本发明涉及显示技术领域，尤其是涉及一种液晶面板、TFT基板及其检测方法。
【背景技术】
在大视角的液晶显示器中，通常将像素单元分为主像素区（Main区）和辅像素区（Sub区），并使得Sub区的电压低于Main区的电压。为了使得Sub区的电压低于Main区的电压，“电荷分享”(charge-sharing)是一种常用的方式，具体请参阅图1，图1为现有技术的采用“电荷分享”方式的像素单元的结构图。图1所示的像素单元100分为Main区101和Sub区102，当扫描线G11提供扫描驱动信号时，开关管103和104同时打开时，信号线S11（Data）同时向Main区101和Sub区102的像素电极，即ITO（Indium tin oxide 氧化铟锡）薄膜充电，然后扫描线G11停止提供扫描驱动信号，共享扫描线G12开始提供扫描驱动信号，开关管105打开，分压电容C11与Sub区102的像素电极导通，分担一部分Sub区102的像素电极上的电荷，使Sub区102的像素电极的电压降低到适当比例，从而与main区101的像素电极一起显示，以形成大视角的效果。
然而图1所示的像素单元100是在4Mask（掩膜）制程的中制得，分压电容C11通常采用MII（双层金属）电容结构，即分压电容C11结构为：M1（第一层金属）、G-SiNx（栅层氮化硅），PA-SiNx（填充氮化层），ITO导电薄膜。然而，对于包含有该MII电容结构的像素单元，在制程过程中很容易因为ITO微粒（particle）的存在，会出现蚀刻残留，容易产生ITO残留，导致Sub区102的ITO与分压电容C11的ITO发生短接（Short）。从而当扫描线G11提供扫描驱动信号时，数据线S11同时对Sub区102像素电极和Main区101像素电极以及分压电容C11充电。当扫描线G11停止提供扫描驱动信号，共享扫描线G12提供扫描驱动信号时，由于分压电容C11的ITO电位与Sub区102的ITO电位相等，分压电容C11无法分担Sub区102电荷，使得分压失效，从而无法拉低Sub区102电位，不能形成大视角的效果。进一步的，还会使得该缺陷像素比正常像素更亮，从而在中低灰阶下产生微亮点，影响液晶面板的品质。
【发明内容】
本发明主要解决的技术问题是提供一种液晶面板、TFT基板及其检测方法，能够检测出同一像素单元中的电容与主像素区或辅像素区是否发生短接，从而可以及时进行修补，改善产品品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT基板，该TFT基板包括：
多个呈矩阵设置的像素单元，其中每一所述像素单元包括主像素区、辅像素区和电容，所述像素单元包括分布于奇数行的第一像素单元和分布于偶数行的第二像素单元，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的电容电连接，第2n+2行的所述第二像素单元的辅像素区与第2n+1行的所述第一像素单元的电容电连接，n为自然数；
其中，对所述第一像素单元和所述第二像素单元分别提供不相等的电压信号以检测同一所述像素单元中的电容与主像素区或辅像素区是否短接。
其中，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的辅像素区彼此靠近，第2n+1行的所述第一像素单元的主像素区与第2n+2行的所述第二像素单元的主像素区彼此远离；
第2n+1行的所述第一像素单元的电容设置在其辅像素区与第2n+2行的所述第二像素单元之间，第2n+2行的所述第二像素单元的电容设置在其辅像素区与第2n+1行的所述第一像素单元之间。
其中，同一行像素单元中的主像素区和辅像素区接收的电压信号相等。
其中，所述TFT基板还包括第一扫描线、第二扫描线、共享扫描线、第一开关管和第二开关管，其中：
所述第一扫描线电连接所述第一像素单元；
所述第二扫描线电连接所述第二像素单元；
所述第一开关管分别电连接所述共享扫描线、第2n+1行的第一像素单元的所述辅像素区和第2n+2行的第二像素单元的所述电容；
所述第二开关管分别电连接所述共享扫描线、第2n+2行的第二像素单元的所述辅像素区和第2n+1行的第一像素单元的所述电容；
所述共享线进一步电连接所述第一扫描线，使得对所述第一扫描线提供扫描驱动信号时，所述共享扫描线上的所述第一开关管和所述第二开关管均导通。
其中，对所述第一扫描线和对所述第二扫描线分时提供扫描驱动信号。
其中，对所述第一像素单元和所述第二像素单元提供的电压信号的差值大于或等于6V。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶面板，该液晶面板包括TFT基板，该TFT基板包括：
多个呈矩阵设置的像素单元，其中每一所述像素单元包括主像素区、辅像素区和电容，所述像素单元包括分布于奇数行的第一像素单元和分布于偶数行的第二像素单元，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的电容电连接，第2n+2行的所述第二像素单元的辅像素区与第2n+1行的所述第一像素单元的电容电连接，n为自然数；
其中，对所述第一像素单元和所述第二像素单元分别提供不相等的电压信号以检测同一所述像素单元中的电容与主像素区或辅像素区是否短接。
其中，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的辅像素区彼此靠近，第2n+1行的所述第一像素单元的主像素区与第2n+2行的所述第二像素单元的主像素区彼此远离；
第2n+1行的所述第一像素单元的电容设置在其辅像素区与第2n+2行的所述第二像素单元之间，第2n+2行的所述第二像素单元的电容设置在其辅像素区与第2n+1行的所述第一像素单元之间。
其中，同一行像素单元中的主像素区和辅像素区接收的电压信号相等。
其中，所述TFT基板还包括第一扫描线、第二扫描线、共享扫描线、第一开关管和第二开关管，其中：
所述第一扫描线电连接所述第一像素单元；
所述第二扫描线电连接所述第二像素单元；
所述第一开关管分别电连接所述共享扫描线、第2n+1行的第一像素单元的所述辅像素区和第2n+2行的第二像素单元的所述电容；
所述第二开关管分别电连接所述共享扫描线、第2n+2行的第二像素单元的所述辅像素区和第2n+1行的第一像素单元的所述电容；
所述共享线进一步电连接所述第一扫描线，使得对所述第一扫描线提供扫描驱动信号时，所述共享扫描线上的所述第一开关管和所述第二开关管均导通。
其中，对所述第一扫描线和对所述第二扫描线分时提供扫描驱动信号。
其中，对所述第一像素单元和所述第二像素单元提供的电压信号的差值大于或等于6V。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种TFT基板的检测方法，其中，该TFT基板为前文所述的前四项TFT基板，该检测方法包括以下步骤：
向第二像素单元提供扫描驱动信号，以对所述第二像素单元提供电压信号；
向第一像素单元提供扫描驱动信号，以对所述第一像素单元提供不同于第二像素单元的电压信号，同时打开第一开关管和第二开关管，使得第2n+1行的第一像素单元的辅像素区通过第一开关管电连接第2n+2行的第二像素单元的电容，以及第2n+2行的第二像素单元的辅像素区通过第二开关管电连接第2n+1行的第一像素单元的电容；
通过检测所述第二像素单元的辅像素区的电压信号是否变化来检测同一像素单元中的电容与主像素区或辅像素区是否短接，其中，若检测到所述第二像素单元的辅像素区的电压信号发生变化，则检测为同一像素单元中的电容与主像素区或辅像素区发生短接；若检测到所述第二像素单元的辅像素区的电压信号没有变化，则检测为同一像素单元中的电容与主像素区或辅像素区没有发生短接。
其中，所述向第一像素单元提供扫描驱动信号的步骤之前还包括：
停止向第二像素单元提供扫描驱动信号。
其中，对所述第一像素单元和所述第二像素单元提供的电压信号的差值大于或等于6V。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT基板括多个呈矩阵设置的像素单元，其中每一所述像素单元包括主像素区、辅像素区和电容，所述像素单元包括分布于奇数行的第一像素单元和分布于偶数行的第二像素单元，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的电容电连接，第2n+2行的所述第二像素单元的辅像素区与第2n+1行的所述第一像素单元的电容电连接，n为自然数。其中，对所述第一像素单元和所述第二像素单元分别提供不相等的电压信号以检测同一所述像素单元中的电容与主像素区或辅像素区是否短接。由此，能够检测出同一像素单元中的电容与主像素区或辅像素区是否发生短接，从而可以及时进行修补，改善产品品质。
【附图说明】
图1是现有技术的像素单元的结构图；
图2是本发明实施例提供的一种液晶面板的结构示意图；
图3是图2所示的液晶面板中的相邻的两行像素单元的结构示意图；
图4是本发明实施例提供的一种TFT基板的检测方法的流程图。
【具体实施方式】
请一并参阅图2和图3，图2是本发明实施例提供的一种液晶面板的结构示意图，图3是图2所示的液晶面板中的相邻的两行像素单元的结构示意图。如图2和图3所示，本实施例的液晶面板200包括TFT（Thin Film Transistor，薄膜晶体管）基板20，TFT基板20包括多个成矩阵设置的像素单元21。其中每一像素单元21均包括一主像素区22、辅像素区23以及电容24。
像素单元21包括分布于奇数行的第一像素单元211和分布于偶数行的第二像素单元212。本实施例中，奇数用2n+1表示，偶数用2n+2表示，n为自然数，例如0、1、2、3…。本实施例中，第2n+1行的第一像素单元211的辅像素区231与第2n+2行的第二像素单元212的电容242电连接，第2n+2行的第二像素单元212的辅像素区232与第2n+1行的第一像素单元211的电容241电连接。
优选的，第2n+1行的第一像素单元211的辅像素区231与第2n+2行的第二像素单元212的辅像素区232彼此靠近，第2n+1行的第一像素单元211的主像素区221与第2n+2行的第二像素单元212的主像素区222彼此远离。也就是说第2n+1行的第一像素单元211的排列方式与第2n+2行的第二像素单元212的排列方式相反。例如图2所示，第一行的第一像素单元211的辅像素区231与第二行的第二像素单元212的辅像素区232彼此靠近，第一行的第一像素单元211的主像素区221与第二行的第二像素单元212的主像素区222彼此远离。同理，其他行的像素单元的排列方式也相同。
并且，如图3所示，第2n+1行的第一像素单元211的电容241设置在其辅像素区231与第2n+2行的第二像素单元212之间，第2n+2行的第二像素单元212的电容242设置在其辅像素区232与第2n+1行的第一像素单元211之间。由此使得辅像素区231与电容241相邻设置，辅像素区232与电容242相邻设置，并且两个电容241和242设置在两个辅像素区231和232之间。
在其他实施例中，也可以设置第一像素单元211和第二像素单元212的排列方式相同，并且电容241和242分别与第一像素单元211的主像素区221和第二像素单元212的主像素区222相邻设置。
其中，对同一行的像素单元的主像素区和辅像素区提供的电压信号相等。且对第一像素单元211和第二像素单元212分别提供不相等的电压信号，以检测同一像素单元中的电容与主像素区或辅像素区是否短接。优选的，对第一像素单元211和第二像素单元212提供的电压信号的差值大于或等于6V。本实施例中，具体实现的电路结构如下文所述：
TFT基板20还包括多条平行设置的第一扫描线G21、第二扫描线G22、共享扫描线G23、第一数据线S20、第二数据线S21、开关管25、26、27、28、29以及30。
其中，第一扫描线G21的数量与第一像素单元211的行数相等，数据线S20的数量与第一像素单元211的列数相等。每一第一扫描线G21电连接对应的一行第一像素单元211，每一数据线S20电连接对应的一列第一像素单元211。具体地，如图3所示，第一扫描线G21电连接开关管27和28的控制端，数据线S20电连接开关管27、28的输入端，开关管27、28的输出端分别电连接第一像素单元211的主像素区221和辅像素区231，应理解，开关管27、28的输出端具体是分别电连接主像素区221和辅像素区231的ITO电极。在第一扫描线G21提供扫描驱动信号时，开关管27和28同时打开，开关管27和28的输入端和输出端分别相互导通，则数据线S20提供的电压信号通过导通的输入端和输出端后分别提供给主像素区221和辅像素区231，以对主像素区221和辅像素区231进行充电。
如图2所示，在进行TFT基板20的短接检测时，所有的第一扫描线G21都连接到同一条短路棒（shorting bar）L1上。以同时给第一扫描线G21提供扫描驱动信号来同时打开所有的第一像素单元211的开关管27和28，从而同时对第一像素单元211的主像素区221和辅像素区231进行充电。
应理解，在进行TFT基板20的短接检测时，所有的数据线S20也可以都连接在同一条短路棒上，用以同时提供同一电压信号给第一像素单元211。
第二扫描线G22的数量与第二像素单元212的行数相等，数据线S21的数量与第二像素单元212的列数相等。每一第二扫描线G22电连接对应的一行第二像素单元212，每一数据线S21电连接对应的一列第二像素单元212。具体地，如图3所示，第二扫描线G22电连接开关管29和30的控制端，数据线S21电连接开关管29、30的输入端，开关管29和30的输出端分别电连接第二像素单元212的主像素区222和辅像素区232。应理解，开关管29和30的输出端具体是分别电连接主像素区222和辅像素区232的ITO电极。在第二扫描线G22提供扫描驱动信号时，开关管29和30同时打开，开关管29和30的输入端和输出端分别相互导通，则数据线S21提供的电压信号通过导通的输入端和输出端后分别提供给主像素区222和辅像素区232，以对主像素区222和辅像素区232进行充电。
如图2所示，在进行TFT基板20的短接检测时，所有的第二扫描线G22都连接到同一条短路棒（shorting bar）L2上。以同时给第二扫描线G22提供扫描驱动信号来同时打开所有的第二像素单元212的开关管29和30，从而同时对第二像素单元212的主像素区222和辅像素区232进行充电。
应理解，在进行TFT基板20的短接检测时，所有的数据线S21也可以都连接在同一条短路棒上，用以同时提供同一电压信号给第二像素单元212。
共享扫描线G23设置在第一像素单元211和第二像素单元212之间。并且共享扫描线G23进一步与第一扫描线G21电连接，更具体的，是和其相邻的两条第一扫描线G21中，在正常工作阶段，即非检测阶段时，提供的扫描驱动信号较迟的第一扫描线G21连接。
开关管25分别电连接共享扫描线G23、第2n+1行的第一像素单元211的辅像素区213和第2n+2行的第二像素单元212的电容242。具体的，开关管25的数量和第一像素单元211的电容241的数量相等。其中，每一开关管25的控制端电连接一共享扫描线G23，输入端和输出端分别电连接该共享扫描线G23两侧的第一像素单元211的辅像素区213和第二像素单元212的电容242。
第二开关管26分别电连接共享扫描线G23、第2n+2行的第二像素单元212的辅像素区232和第2n+1行的第一像素单元211的电容241。具体的，开关管26的数量和第二像素单元212的电容242的数量相等。其中，每一开关管26的控制端电连接一共享扫描线G23，输入端和输出端分别电连接该共享扫描线G23两侧的第二像素单元212的辅像素区232和第一像素单元211的电容241。
值得注意的是，如图3所示，相邻的两个电容241和242分别对应的开关管25和26共享同一条共享扫描线G23。由此减少了共享扫描线的数量，提高了像素单元的开口率，从而能够提供液晶面板200的穿透率。
在其他实施例中，如不考虑穿透率，还可以设置开关管25和26分别电连接一条共享扫描线G23。
其中，以上所述的开关管的控制端为开关管的栅极，输入端为开关管的源极或漏极的其中一个，输出端为源极或漏极的另外一个。
以下将介绍本实施例的TFT基板20的检测原理：
其中，对第一扫描线G21和对第二扫描线G22分时提供扫描驱动信号。
本实施例举例图2所示的第一像素单元211和第二像素单元212的排列方式相反的结构的检测原理：首先给短路棒L2高电平信号，短路棒L1低电平信号，则所有的偶数行的第二像素单元212的第二扫描线G22都接收到扫描驱动信号，从而对应的开关管29和30打开，数据线S21将电压信号提供给对应的主像素区222和辅像素区232，举例此时提供的电压信号为1V，则所有的偶数行的第二像素单元212的主像素区222和辅像素区232写入1V像素电压。接着给短路棒L2提供低电平信号，以关闭开关管29和30，结束对主像素区222和辅像素区232的充电。
然后给短路棒L1高电平信号，则所有的奇数行的第一像素单元211的第一扫描线G21都接收到扫描驱动信号，从而对应的开关管27和28打开，数据线S20将电压信号提供给对应的主像素区221和辅像素区231，举例此时提供的电压信号为16V，则所有的奇数行的第一像素单元211的主像素区221和辅像素区231写入16V像素电压。
值得注意的是，此时所有的共享扫描线G23也会接收到扫描驱动信号，则开关管25和26也会打开，使得电容241和242分别充电。
具体地，若第一像素单元211和第二像素单元212的辅像素区与电容均没有发生短接，电容241是对第二像素单元212的辅像素区232进行分压，即将辅像素区232的1V电压进行分压。而电容242是通过辅像素区231从数据线S20中获得电压信号，与第一像素单元211的辅像素区231一样获得16V的电压信号。
若第一像素单元211和第二像素单元212的至少一个的辅像素区和电容发生短接，则就会导致数据线S20通过短接的电容向第二像素单元212的辅像素区232充电，使得辅像素区232的电压由1V变大到16V。具体而言，若第二像素单元212的辅像素区232与电容242发生短接，则此辅像素区232通过电容242与第一像素单元211的辅像素区231电相连，导致数据线S20通过短接的电容242向此辅像素区232写入16V电压信号。同理，若第一像素单元211的辅像素区231与电容241发生短接，则此辅像素区231通过电容241与第二像素单元212的辅像素区232电相连，导致数据线S20也会向此辅像素区232写入16V电压信号。由此看出，无论是奇数行的第一像素单元211的辅像素区231与电容241短接还是偶数行的第二像素单元212的辅像素区232与电容242短接，都会导致偶数行的第二像素单元212的辅像素区232的电压从1V变化到16V。此电压差能够让Array Test（阵列检查）检查出来。因此，本发明的该种电路结构能够在Array Test时，将像素单元的辅像素区与电容发生短接的缺陷检测出来，从而及时对缺陷像素单元进行修补。
承前所述，本发明实施例提供了分时分别向第一像素单元211和第二像素单元212提供高、低电压信号来检测像素单元的辅像素区和主像素区是否发生短接。总体来说，前文是通过检测第二像素单元212的辅像素区232的电压是否变化检测同一像素单元中的电容与辅像素区是否短接。具体而言，若检测到第二像素单元212的辅像素区232的电压发生变化，则检测为同一像素单元中的电容与辅像素区发生短接。反之，若检测到第二像素单元212的辅像素区232的电压没有变化，则检测为同一像素单元中的电容与辅像素区没有发生短接。
在其他实施例中，还可以只向第一像素单元211或第二像素单元212提供电压信号。若只有对应的像素单元检测到电压，则说明第一像素单元211和第二像素单元212均不存在辅像素区与电容短接的情况。相反的，若第一像素单元211和第二像素单元212都检测到电压信号，则说明第一像素单元211和第二像素单元212的至少一个存在辅像素区与电容短路的情况。应理解，此时的电压信号大于或等于6V。此时为了节约成本和简化流程，可以省略掉一根短路棒。
使得注意的是，短路棒L1和L2是在检测阶段才用到，在正常显示阶段，需要断开第一扫描线G21和短路棒L1的连接，以及第二扫描线G22和短路棒L2的连接。
以上举例的是图2所示的第一像素单元211和第二像素单元212的排列方式相反的结构的检测原理，应理解，在第一像素单元211和第二像素单元212的排列方式相同，并且电容241和242分别与第一像素单元211的主像素区221和第二像素单元212的主像素区222相邻设置的结构中，其检测原理亦相同。此时检测的是同一像素单元中电容与主像素区是否发生短接。
本发明还提供了一种TFT检测方法，该方法应用在前文所述的TFT基板20中。具体请参阅图4所示，图4是本发明实施例提供的一种TFT基板的检测方法的流程图，图4所示，本发明的检测方法包括以下步骤：
步骤S1：向第二像素单元212提供扫描驱动信号，以对第二像素单元212提供电压信号。
具体的，首先向第二扫描线G22提供扫描驱动信号，以打开与第二扫描线G22电连接的开关管29和30，然后向打开的开关管29和30提供电压信号，以通过开关管29和30将该电压信号传输到与其电连接的第二像素单元212的主像素区222和辅像素区232中。其中，该电压信号为低电压信号。
步骤S2：向第一像素单元211提供扫描驱动信号，以对第一像素单元211提供不同于第二像素单元212的电压信号，同时打开第一开关管25和第二开关管26，使得第2n+1行的第一像素单元211的辅像素区231通过第一开关管25电连接第2n+2行的第二像素单元212的电容242，以及第2n+2行的第二像素单元212的辅像素区232通过第二开关管26电连接第2n+1行的第一像素单元211的电容241。
步骤S3：通过检测第二像素单元212的辅像素区的电压是否变化检测同一像素单元中的电容与主像素区或辅像素区是否短接。具体而言，若检测到第二像素单元212的辅像素区232的电压发生变化，则检测为同一像素单元中的电容与主像素区或辅像素区发生短接。反之，若检测到第二像素单元212的辅像素区232的电压没有变化，则检测为同一像素单元中的电容与主像素区或辅像素区没有发生短接。具体检测过程如前文所述，在此不再赘述。
其中，若电容241和242的是如图2所示那样分别与辅像素区231和232相邻设置，则本步骤检测到的是同一像素单元中的电容与辅像素区是否短接。若电容241和242的是分别与主像素区221和222相邻设置，则本步骤检测到的是同一像素单元中的电容与主像素区是否短接。
优选的，向第一像素单元211提供扫描驱动信号的步骤之前停止向第二像素单元212提供扫描驱动信号。即分时对第一扫描线G21和第二扫描线G22提供扫描驱动信号。
其中，对第一像素单元211和第二像素单元212提供的电压信号的差值大于或等于6V。如前文所述，对第一像素单元211提供的电压信号为16V，对第二像素单元212提供的电压信号为1V。
值得注意的是，还可以只向第一像素单元211或第二像素单元212提供电压信号。若只有对应的像素单元检测到电压，则说明第一像素单元211和第二像素单元212均不存在辅像素区与电容短接的情况。相反的，若第一像素单元211和第二像素单元212都检测到电压信号，则说明第一像素单元211和第二像素单元212的至少一个存在辅像素区与电容短路的情况。应理解，此时的电压信号大于或等于6V。
综上所述，本发明可以检测出同一像素单元中的电容与主像素区或辅像素区是否发生短接，从而可以及时进行修补，改善产品品质。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种TFT基板，其中，所述TFT基板包括：
    多个呈矩阵设置的像素单元，其中每一所述像素单元包括主像素区、辅像素区和电容，所述像素单元包括分布于奇数行的第一像素单元和分布于偶数行的第二像素单元，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的电容电连接，第2n+2行的所述第二像素单元的辅像素区与第2n+1行的所述第一像素单元的电容电连接，n为自然数；
    其中，对所述第一像素单元和所述第二像素单元分别提供不相等的电压信号以检测同一所述像素单元中的电容与主像素区或辅像素区是否短接。
  2. 根据权利要求1所述的TFT基板，其中，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的辅像素区彼此靠近，第2n+1行的所述第一像素单元的主像素区与第2n+2行的所述第二像素单元的主像素区彼此远离；
    第2n+1行的所述第一像素单元的电容设置在其辅像素区与第2n+2行的所述第二像素单元之间，第2n+2行的所述第二像素单元的电容设置在其辅像素区与第2n+1行的所述第一像素单元之间。
  3. 根据权利要求2所述的TFT基板，其中，同一行像素单元中的主像素区和辅像素区接收的电压信号相等。
  4. 根据权利要求3所述的TFT基板，其中，所述TFT基板还包括第一扫描线、第二扫描线、共享扫描线、第一开关管和第二开关管，其中：
    所述第一扫描线电连接所述第一像素单元；
    所述第二扫描线电连接所述第二像素单元；
    所述第一开关管分别电连接所述共享扫描线、第2n+1行的第一像素单元的所述辅像素区和第2n+2行的第二像素单元的所述电容；
    所述第二开关管分别电连接所述共享扫描线、第2n+2行的第二像素单元的所述辅像素区和第2n+1行的第一像素单元的所述电容；
    所述共享线进一步电连接所述第一扫描线，使得对所述第一扫描线提供扫描驱动信号时，所述共享扫描线上的所述第一开关管和所述第二开关管均导通。
  5. 根据权利要求4所述的TFT基板，其中，对所述第一扫描线和对所述第二扫描线分时提供扫描驱动信号。
  6. 根据权利要求1所述的TFT基板，其中，对所述第一像素单元和所述第二像素单元提供的电压信号的差值大于或等于6V。
  7. 一种液晶面板，其中，所述液晶面板包括TFT基板，所述TFT基板包括：
    多个呈矩阵设置的像素单元，其中每一所述像素单元包括主像素区、辅像素区和电容，所述像素单元包括分布于奇数行的第一像素单元和分布于偶数行的第二像素单元，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的电容电连接，第2n+2行的所述第二像素单元的辅像素区与第2n+1行的所述第一像素单元的电容电连接，n为自然数；
    其中，对所述第一像素单元和所述第二像素单元分别提供不相等的电压信号以检测同一所述像素单元中的电容与主像素区或辅像素区是否短接。
  8. 根据权利要求7所述的液晶面板，其中，第2n+1行的所述第一像素单元的辅像素区与第2n+2行的所述第二像素单元的辅像素区彼此靠近，第2n+1行的所述第一像素单元的主像素区与第2n+2行的所述第二像素单元的主像素区彼此远离；
    第2n+1行的所述第一像素单元的电容设置在其辅像素区与第2n+2行的所述第二像素单元之间，第2n+2行的所述第二像素单元的电容设置在其辅像素区与第2n+1行的所述第一像素单元之间。
  9. 根据权利要求8所述的液晶面板，其中，同一行像素单元中的主像素区和辅像素区接收的电压信号相等。
  10. 根据权利要求9所述的液晶面板，其中，所述TFT基板还包括第一扫描线、第二扫描线、共享扫描线、第一开关管和第二开关管，其中：
    所述第一扫描线电连接所述第一像素单元；
    所述第二扫描线电连接所述第二像素单元；
    所述第一开关管分别电连接所述共享扫描线、第2n+1行的第一像素单元的所述辅像素区和第2n+2行的第二像素单元的所述电容；
    所述第二开关管分别电连接所述共享扫描线、第2n+2行的第二像素单元的所述辅像素区和第2n+1行的第一像素单元的所述电容；
    所述共享线进一步电连接所述第一扫描线，使得对所述第一扫描线提供扫描驱动信号时，所述共享扫描线上的所述第一开关管和所述第二开关管均导通。
  11. 根据权利要求10所述的液晶面板，其中，对所述第一扫描线和对所述第二扫描线分时提供扫描驱动信号。
  12. 根据权利要求7所述的液晶面板，其中，对所述第一像素单元和所述第二像素单元提供的电压信号的差值大于或等于6V。
  13. 一种TFT基板的检测方法，其中，所述TFT基板为权利要求4所述的TFT基板，其中，所述检测方法包括以下步骤：
    向第二像素单元提供扫描驱动信号，以对所述第二像素单元提供电压信号；
    向第一像素单元提供扫描驱动信号，以对所述第一像素单元提供不同于第二像素单元的电压信号，同时打开第一开关管和第二开关管，使得第2n+1行的所述第一像素单元的辅像素区通过所述第一开关管电连接第2n+2行的所述第二像素单元的电容，以及第2n+2行的所述第二像素单元的辅像素区通过所述第二开关管电连接第2n+1行的所述第一像素单元的电容；
    通过检测所述第二像素单元的辅像素区的电压信号是否变化来检测同一像素单元中的电容与主像素区或辅像素区是否短接，其中，若检测到所述第二像素单元的辅像素区的电压信号发生变化，则检测为同一像素单元中的电容与主像素区或辅像素区发生短接；若检测到所述第二像素单元的辅像素区的电压信号没有变化，则检测为同一像素单元中的电容与主像素区或辅像素区没有发生短接。
  14. 根据权利要求13所述的检测方法，其中，所述向第一像素单元提供扫描驱动信号的步骤之前还包括：
    停止向第二像素单元提供扫描驱动信号。
  15. 根据权利要求14所述的检测方法，其中，对所述第一像素单元和所述第二像素单元提供的电压信号的差值大于或等于6V。
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