WO2016106887A1 - 一种阵列基板及其检测电路 - Google Patents

一种阵列基板及其检测电路 Download PDF

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Publication number
WO2016106887A1
WO2016106887A1 PCT/CN2015/071132 CN2015071132W WO2016106887A1 WO 2016106887 A1 WO2016106887 A1 WO 2016106887A1 CN 2015071132 W CN2015071132 W CN 2015071132W WO 2016106887 A1 WO2016106887 A1 WO 2016106887A1
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Prior art keywords
detection
line
lines
switching
signal
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PCT/CN2015/071132
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English (en)
French (fr)
Inventor
王醉
郭晋波
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深圳市华星光电技术有限公司
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Priority to US14/418,624 priority Critical patent/US9620045B2/en
Publication of WO2016106887A1 publication Critical patent/WO2016106887A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate and a detection circuit thereof.
  • Shorting Bar a peripheral trace called a shorting bar surrounding the panel is usually designed outside the display area, and the scanning lines are respectively extracted according to an odd number (ODD) and an even number (EVEN).
  • ODD odd number
  • EVEN even number
  • This design is to check whether there are short circuits or open circuits in the display panel by different electrical signals for the odd and even scan lines in the detection process of the TFT process. Other types of data can be checked with different data signals. bad.
  • the Shorting Bar is disconnected or removed after inspection and does not affect the normal display of the finished product.
  • FIG. 1 is a schematic diagram showing the circuit structure of a charging shared array substrate having a shorting bar in the prior art.
  • the N+2 row charge gate line signal is used to control the opening and closing of the Nth row of the charge sharing scan line (Share Gate Line). If a short circuit occurs between the charge scan line and the charge share scan line of the Nth line, since the shared scan line of the Nth line is connected to the charge scan line of the N+2th row, the order is odd or even in order.
  • the short-circuit bar detection method is taken out by the above-mentioned odd-even lines, and the short-circuit defect cannot be detected in the TFT process section. It can only be detected by means of box lighting or even finished product inspection, resulting in poor horizontal scanning lines and reduced yield.
  • An array substrate in which three detecting lines are disposed in a short-circuit bar region is also provided in the prior art, as shown in FIG.
  • the detection lines G1, G2, and G3 are sequentially connected to three consecutive rows of charging scan lines in the display area, and sequentially provide detection signals to the three detection lines.
  • This scheme is capable of detecting a short circuit between the charge scan line and the charge share scan line in the same row. Defects, but the detection method is more complicated and takes longer. Especially after the mass production of the products, since the various processes have been gradually stabilized, the probability of occurrence of the short-circuit defects mentioned above is extremely low, and the continued use of this scheme will result in low detection efficiency and affect the production capacity.
  • the technical problem to be solved by the present invention is that the detection method of the TFT process stage in the prior art is single, and the detection mode cannot be switched according to the yield condition of each period of the production of the product, and the defect with low detection efficiency is detected.
  • the embodiment of the present application first provides a detection circuit for an array substrate, including:
  • a detecting unit including first to sixth detecting lines
  • a switching signal access unit for receiving a switching control signal
  • a detection signal access unit for receiving the first or second detection signal
  • a switching unit including first and second switching lines, the first and second switching lines being connected between the detecting unit, the switching signal access unit, and the detection signal access unit;
  • the first switching line under the control of the switching control signal, the first switching line is turned on, so that the first to sixth detecting lines are divided into three groups, and the first detecting signals are sequentially provided to the three groups of detecting lines, or
  • the second switching line is turned on, so that the first to sixth detecting lines are divided into two groups, and the second detecting signals are sequentially supplied to the two sets of detecting lines.
  • the first switching line includes:
  • the first to sixth transistors have a gate coupled to the first control line, and a first end of the first to sixth transistors respectively coupled to the first to sixth detection lines;
  • the second ends of the first and fourth transistors are each connected to the first signal sharing point
  • the second ends of the second and fifth transistors are both connected to the second signal sharing point
  • the second ends of the third and sixth transistors Both are connected to a third signal sharing point.
  • the three sets of detecting lines are the first and fourth detecting lines, the second and fifth detecting lines, and the third and sixth detecting lines, respectively.
  • the second switching line includes:
  • the seventh to twelfth transistors have a gate coupled to the first control line, and a first end thereof correspondingly coupled to the first to sixth detection lines;
  • the second ends of the seventh, ninth and eleventh transistors are each connected to a fourth signal sharing point, and the second ends of the eighth, tenth and twelfth transistors are all connected to a fifth signal sharing point.
  • the two sets of detection lines are the first, third, and fifth detection lines, and the second, fourth, and sixth detection lines, respectively.
  • the detection signal access unit includes first to third detection points, where
  • the first ends of the first to third detection points are respectively connected to the first to third signal sharing points, to sequentially provide the first detection signals to the three groups of detection lines;
  • the second ends of the first and third detection points respectively connect the fourth and fifth signal sharing points to sequentially provide the second detection signals to the two sets of detection lines.
  • the switching signal access unit includes first and second control switches, the first control switch is coupled to the first control line to provide a first control signal, and the second control switch is coupled to the second control line to provide a And a second control signal, wherein the potentials of the first and second control signals are opposite in polarity.
  • An embodiment of the present application further provides an array substrate, including a display area and the detection circuit described above, the display area includes a plurality of row sub-regions, and each row of sub-regions is provided with a charging line and a sharing line, and each row of sub-areas The shared line is connected to the charging line of the sub-area whose row number is increased to an even number;
  • the first to sixth detection lines in the detection area are connected one-to-one to the charging lines of successive six rows of sub-areas in the display area.
  • the first detection signals are sequentially provided to the three sets of detection lines to detect line defects of the charging lines and the shared lines in each sub-area;
  • a second detection signal is sequentially supplied to the two sets of detection lines to detect line defects of the charging line and the shared line in the adjacent row sub-areas.
  • the row number difference of the sub-regions that received the first detection signal through the charging line is a multiple of three.
  • the invention has the beneficial effects that two switches and three test points are designed for the detection circuit, and different test modes can be switched by opening and closing of the two switches, so that switching can be performed under two detection states according to the production condition, thereby improving the detection efficiency.
  • six detection lines are arranged in the detection area to provide two detection states, and different detection signals are provided for the six detection lines in two states, thereby generating different detection effects.
  • FIG. 1 is a schematic diagram of a circuit structure of a charging shared array substrate having a shorting bar in the prior art
  • FIG. 2 is a schematic diagram of a circuit structure of another charging shared array substrate having a shorting bar in the prior art
  • FIG. 3 is a schematic diagram of a line structure of an array substrate according to an embodiment of the invention.
  • FIG. 4 is a schematic structural diagram of a detecting circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing an operation state of a detecting circuit in a first detecting mode according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram showing an operation state of a detecting circuit in a second detecting mode according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing the circuit structure of the array substrate provided in this embodiment.
  • the array substrate includes a display area 310 and a detection circuit 320.
  • the detection circuit 302 is disposed on one side of the display area 310.
  • a plurality of rows of sub-regions 311 are disposed in the display area 310, and the sub-regions are arranged in an array to form a sub-pixel array at a later stage of the process.
  • the charging line and the scanning line are set in each sub-area, and the sharing line of each sub-area is connected to the charging line of the sub-area whose row number has a value of 2, that is, the charging line of each sub-area is shared by the previous line.
  • the line provides the signal.
  • the Nth sub-area sets the charging line C(N) and the shared line S(N)
  • the N-2th sub-area sets the charging line C(N-2) and the shared line S. (N-2), wherein the N-2th line shared line S(N-2) is connected to the Nth row charging line C(N), thereby controlling the shared line S by using the scanning signal on the charging line C(N) (N-2) is turned on or off.
  • the detection circuit 320 includes a detection unit 321, a switching signal access unit 322, a detection signal access unit 323, and a switching unit 324.
  • the first to sixth detection lines G1 G G6 are provided in the detecting unit 321 for providing a detection signal to the display area 310 to complete defect detection of the charging line and the scanning line in the display area 310.
  • the detection lines G1 to G6 are connected one-to-one to the charging lines of the six consecutive sub-areas in the display area.
  • the first detection line G1 is connected to the charging line C (N+2) of the N+2th row sub-area
  • the second detection line G2 is connected to the charging line C of the (N+1th) sub-area ( N+1)
  • the third to sixth detection lines G3 to G6 are respectively connected to the charging lines of the Nth row, the N-1th row, the N-2th row, and the N-3th row subregion.
  • the handover signal access unit 322 is configured to receive a handover control signal. As shown in FIG. 3, in a preferred example, the switching signal access unit includes a first control switch Sw1 and a second control switch Sw2, respectively receiving the first and second control signals.
  • the detection signal access unit 323 is configured to receive the first or second detection signal.
  • the detection signal access unit 323 is provided with first detection points Te1, second detection points Te2, and third detection points Te3 which are independent of each other.
  • the switching unit 324 is connected between the detecting unit 321, the switching signal access unit 322, and the detection signal access unit 323, and can switch different detection modes according to the first and second control signals.
  • the circuit configuration of the switching unit 324 is schematically illustrated in FIG.
  • the switching unit includes a first switching line 410 and a second switching line 420, respectively implementing different detection modes.
  • the first switching line 410 includes a first control line L1 and first to sixth transistors (T1 to T6).
  • the first control line L1 is connected to the first control switch S1 to receive the first control signal.
  • the first ends of T1 to T6 are coupled to the first to sixth detection lines (G1 to G6), respectively.
  • the second ends of the first and fourth transistors (T1 and T4) are both connected to the first signal sharing point A, and the second ends of the second and fifth transistors (T2 and T5) are both connected to the second signal sharing point B,
  • the second ends of the third and sixth transistors (T3 and T6) are both connected to the third signal sharing point C.
  • the first switching line 410 is connected to the detection signal access unit 323 to receive the first detection signal. Specifically, the first end of the first detecting point Te1 is connected to the first signal sharing point A, the first end of the second detecting point Te2 is connected to the second signal sharing point B, and the first end of the third detecting point Te3 is connected to the third end. Signal sharing point C.
  • the second switching line 420 includes a second control line L2 and seventh to twelfth transistors (T7 to T12).
  • the second control line L2 is connected to the second control switch S2 to receive the second control signal.
  • the gates of T7 to T12 are coupled to the second control line L2, and the first ends of T7 to T12 are respectively coupled to the first to sixth detection lines (G1 to G6).
  • the second ends of the seventh, ninth and eleventh transistors (T7, T9 and T11) are each connected to a fourth signal sharing point D, the eighth, tenth and twelfth transistors (T8, T10 and T12) Both ends are connected to the fifth signal sharing point E.
  • the second switching line 420 is connected to the detection signal access unit 323 to receive the second detection signal. Specifically, the second end of the first detection point Te1 is connected to the fourth signal sharing point D, and the second end of the third detection point Te3 is connected to the fifth signal sharing point E.
  • the switching unit 324 is described below in conjunction with FIGS. 3, 5, and 6 to implement two different detection modes.
  • the first to sixth detection lines are divided into three groups, and the first detection signals are sequentially supplied to the three detection lines; in the second detection mode, the first to sixth are made.
  • the detection lines are divided into two groups, which in turn provide a second detection signal to the two sets of detection lines.
  • the first detection mode is suitable for the initial stage of mass production of the array substrate. Due to the poor cleanliness of the process environment, particles such as dust particles have an effect on the process of photolithography and exposure, resulting in short-circuit defects between the charging line and the scanning line in each sub-area. Such short-circuit defects may occur in sub-areas of the display area, and may also occur in line bridging areas outside the sub-areas. For example, as shown in FIG.
  • a short circuit between the charging line C(N) and the shared line S(N) occurs at the short-circuit position 307 inside the N-th sub-region, or a short-circuited position outside the N+1th sub-region
  • a short circuit between the charging line C(N+1) and the shared line S(N+1) occurs at 308.
  • the detection is performed using the first detection mode, that is, the first control signal is supplied to the first control switch Sw1, and the first detection signal is supplied to the first to third detection points (Te1 to Te3).
  • the first control signal is at a high level, so that the first control switch Sw1 is turned on, and further provides a high level signal to the gates of the first to sixth transistors (T1 to T6) through the first control line L1. .
  • T1 to T6 are turned on, so that the first to sixth detecting lines G1 to G6 can each receive the first detection signals supplied from the first to third detecting points (Te1 to Te3).
  • the second control signal of the low level may be supplied to the second control switch Sw2 such that the second control switch Sw2 is in a stable off state.
  • the first detection signal may include three consecutive detection periods t1, t2, and t3.
  • the detection signal is supplied to the first detection point Te1 during the time period t1, and the detection signals are simultaneously supplied to the detection lines G1 and G4 via the first end of the Te1 and the first sharing point A.
  • no detection signal is provided at the second detection point Te2 and the third detection point Te3, and there is no detection signal on G2, G5, and G3, G6.
  • the N+2th charging line C(N+2) and the Nth row shared line S(N) can receive the first detection signal from the detection line G1, and similarly, the N-1th charging line.
  • the C(N-1) and the N-3th line shared line S(N-3) are capable of receiving the first detection signal from the detection line G4.
  • the N+5th row charging line C(N+5) and the N+3th row sharing line S(N+3) can also receive the first detection signal from the detecting line G4. That is, the line numbers of the sub-areas that receive the first detection signal through the charging line are N-1, N+2, and N+5, and the difference of the line numbers is 3 or 6.
  • the detecting method of the present embodiment can detect short-circuit defects of the charging line and the shared line in the sub-area of the Nth row.
  • the N+1th charging line C(N+1) and the N-1th shared line S(N-1) can receive the first detection signal from G2
  • the (N-2) and N-4th line shared line S(N-4) can receive the first detection signal from G5. That is to say, the line numbers of the sub-areas that receive the first detection signal through the charging line are N+1 and N-2, and the difference of the line numbers is 3.
  • the detecting method of the present embodiment can detect short-circuit defects of the charging line and the shared line in the (N+1)th sub-area.
  • a detection signal is supplied to the third detection point Te3 during the t3 period, thereby further providing detection signals to the detection lines G3 and G6 via the first end and the third sharing point C of Te3, at the first detection point Te1.
  • the detection signal is not present on the second detection point Te2, and the short-circuit defect of the charging line and the shared line in the sub-area of the N-1th row can be detected.
  • the first to sixth detection lines G1 to G6 can be divided into three groups, that is, G1 and G4 are the first group, G2 and G5 are the second group, and G3 and G6 are the third group.
  • the first detection signal is sequentially supplied to the three sets of scanning lines. Thereby, accurate detection is completed, and the detection rate of short-circuit defects in the array substrate can be improved. However, the detection time required in this state is longer and the efficiency is lower.
  • the second detection mode is suitable for the mass production phase. Since the process conditions tend to be stable, short-circuit defects rarely occur between the charging line and the scanning line in each sub-area. In this case, if the operation continues in accordance with the first detection state, the detection efficiency is low.
  • the detection is performed using the second detection mode, that is, the second control signal is supplied to the second control switch Sw2, and the second detection signals are supplied to the first and third detection points (Te1 and Te3).
  • the second control signal is at a high level, so that the second control switch Sw2 is turned on, and further provides a high level to the gates of the seventh to twelfth transistors (T7 to T12) through the second control line L2. signal.
  • T7 to T12 are turned on, so that the first to sixth detecting lines G1 to G6 can each receive the second detection signals supplied from the first and third detecting points (Te1 and Te3).
  • the first control signal of the low level may be supplied to the first control switch Sw1 such that the first control switch Sw1 is in a stable off state.
  • the first to sixth detection lines G1 G G6 are divided into two groups, that is, G1, G3, and G5 are the first group, and G2, G4, and G6 are the second group, and the two groups are sequentially scanned.
  • the line provides a second detection signal.
  • the second detection signal may include two consecutive detection periods t1 and t2.
  • the detection state of this detection state is high, and the productivity can be improved as compared with the first detection state.
  • this detection state it is possible to check whether there is a short circuit or an open circuit in the array substrate by giving different electrical signals of the odd and even scan lines, and other types of defects can be detected by using different data signals.
  • the N+2 charge sharing type array substrate six detection lines are disposed in the detection area, and two detection states are provided. In the two states, different detection signals are provided for the six detection lines, and different detection effects are generated. Two switches and three test points are designed for the detection circuit, and different test modes can be switched by opening and closing of the two switches, so that switching can be performed in two detection states according to the production condition, thereby improving the detection efficiency.
  • the display area is N+2, and the shared line of each sub-area is connected to the charging line of the sub-area with the line number increasing value of 2, that is, the charging line of each sub-area is separated by the front.
  • the shared line of one line provides the signal. It will be readily understood by those skilled in the art that for the N+4, N+6, etc., the shared line is satisfied that the shared line of each sub-area is connected to the charging line of the sub-area whose row number is increased to an even number.
  • the detection circuit provided in the embodiment performs detection.

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Abstract

一种阵列基板及其检测电路（320）。阵列基板包括显示区（310）和检测电路（320）；检测电路（320）包括检测单元（321），其包括第一至第六检测线路（G1-G6）；切换信号接入单元（322），其用于接收切换控制信号；检测信号接入单元（323），其用于接收第一或第二检测信号；切换单元（324），其包括第一（410）和第二切换线路（420），第一（410）和第二切换线路（420）连接在检测单元（321）、切换信号接入单元（322）和检测信号接入单元（323）之间。

Description

一种阵列基板及其检测电路
相关申请的交叉引用
本申请要求享有2014年12月31日提交的名称为“一种阵列基板及其检测电路”的中国专利申请CN 201410856207.9的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板及其检测电路。
背景技术
在传统的显示面板线路设计中，通常会在显示区域的外侧设计有环绕面板的称为短路杆(Shorting Bar)的外围走线，并将扫描线按照奇数(ODD)和偶数(EVEN)分别引出至外围走线，即整个面板上的奇数和偶数扫描线在显示区域的外围各自短接在一起。这种设计是为了在TFT制程的检测环节中，可以通过给奇数和偶数扫描线不同的电讯号来检查显示面板内是否存在短路或断路的情况，配合不同的数据信号还可以检查出其他类型的不良。短路杆(Shorting Bar)在检测后被断开或去除，不会影响到成品的正常显示。
为了改善垂直取向液晶显示器在大视角出现的色偏现象，会采用充电共享(Charge Sharing)的像素设计方案。图1为现有技术中具有短路杆的充电共享阵列基板的线路结构示意图。采用第N+2行充电扫描线(Charge Gate Line)信号来控制第N行电荷共享扫描线(Share Gate Line)的开启和关闭。如果第N行的充电扫描线和电荷共享扫描线之间发生短路，由于第N行的共享扫描线与后面第N+2行的充电扫描线相连，使得二者在顺序上皆为奇数或偶数，那么通过上述奇偶行分别引出短路杆的检测方式并无法在TFT制程段检出上述短路缺陷。只能依靠成盒(Cell)点灯甚至成品检测的方式方能检出，导致产品出现水平扫描线不良，良率降低。
现有技术中还提供一种在短路杆区域设置三条检测线路的阵列基板，如图2所示。检测线路G1、G2和G3依次连接至显示区域中的连续三行充电扫描线，并向三条检测线路依次提供检测信号。这种方案能够检测同一行中充电扫描线和电荷共享扫描线之间的短路 缺陷，但检测方式更加复杂、耗时更长。特别是产品批量生产量后，由于各项制程已逐步稳定，上述短路缺陷出现的几率极低，继续采用该方案就会导致检测效率低下，影响产能。
发明内容
本发明所要解决的技术问题是现有技术中TFT制程阶段检测方式单一，并不能根据产品生产各个时期的良率状况切换检测方式，检测效率较低的缺陷。
为了解决上述技术问题，本申请的实施例首先提供一种阵列基板的检测电路，包括：
检测单元，其包括第一至第六检测线路；
切换信号接入单元，其用于接收切换控制信号；
检测信号接入单元，其用于接收第一或第二检测信号；
切换单元，其包括第一和第二切换线路，所述第一和第二切换线路连接在检测单元、切换信号接入单元和检测信号接入单元之间；
其中，在切换控制信号的控制下，第一切换线路导通，使得第一至第六检测线路分成三组，依次向所述三组检测线路提供第一检测信号，或者
第二切换线路导通，使得第一至第六检测线路分成两组，依次向所述两组检测线路提供第二检测信号。
在一个实施例中，所述第一切换线路包括：
第一控制线，其连接切换信号接入单元；
第一至第六晶体管，其栅极耦接第一控制线，其第一端分别对应耦接第一至第六检测线路；
其中，第一和第四晶体管的第二端均连接至第一信号共享点，第二和第五晶体管的第二端均连接至第二信号共享点，第三和第六晶体管的第二端均连接至第三信号共享点。
在一个实施例中，在第一切换线路导通的情况下，所述三组检测线路分别为第一和第四检测线路、第二和第五检测线路、第三和第六检测线路。
在一个实施例中，所述第二切换线路包括：
第二控制线，其连接切换信号接入单元；
第七至第十二晶体管，其栅极耦接第一控制线，其第一端分别对应耦接第一至第六检测线路；
其中，第七、第九和第十一晶体管的第二端均连接至第四信号共享点，第八、第十和第十二晶体管的第二端均连接至第五信号共享点。
在一个实施例中，在第二切换线路导通的情况下，所述两组检测线路分别为第一、第三和第五检测线路，以及第二、第四和第六检测线路。
在一个实施例中，所述检测信号接入单元包括第一至第三检测点，其中，
第一至第三检测点的第一端分别对应连接第一至第三信号共享点，以向所述三组检测线路依次提供第一检测信号；
第一和第三检测点的第二端分别对应连接第四和第五信号共享点，以向所述两组检测线路依次提供第二检测信号。
在一个实施例中，所述切换信号接入单元包括第一和第二控制开关，第一控制开关连接第一控制线以提供第一控制信号，第二控制开关连接第二控制线以提供第二控制信号，其中，第一和第二控制信号的电位极性相反。
本申请的实施例还提供一种阵列基板，包括显示区以及上文所述的检测电路，所述显示区包括若干行子区域，每行子区域设置充电线和共享线，每行子区域的的共享线连接至行号增加值为偶数的子区域的充电线；
所述检测区中的第一至第六检测线路一一对应地连接至显示区中的连续六行子区域的充电线。
在一个实施例中，在第一切换线路导通的情况下，依次向所述三组检测线路提供第一检测信号，以检测每行子区域中充电线和共享线的线路缺陷；
在第二切换线路导通的情况下，依次向所述两组检测线路提供第二检测信号，以检测相邻行子区域中充电线和共享线的线路缺陷。
在一个实施例中，在第一切换线路导通的情况下，通过充电线接收到第一检测信号的子区域的行号差值为3的倍数。
本发明的有益效果在于为检测电路设计两个开关以及三个测试点，可通过两个开关的开闭切换不同的测试模式，因而可以根据生产状况在两种检测状态下进行切换，提高检测效率。针对充电共享型阵列基板，在检测区域设置六条检测线路，提供两种检测状态，在两种状态下为六条检测线路提供不同的检测信号，产生不同的检测效果。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案或现有技术的进一步理解，并且构成说明书的一部分，但并不构成对本申请技术方案的限制。
图1是现有技术中具有短路杆的充电共享阵列基板的线路结构示意图；
图2是现有技术中另一种具有短路杆的充电共享阵列基板的线路结构示意图；
图3是根据本发明实施例的阵列基板的线路结构示意图；
图4是根据本发明实施例的检测电路的结构示意图；
图5是根据本发明实施例的第一检测模式下检测电路的工作状态示意图；
图6是根据本发明实施例的第二检测模式下检测电路的工作状态示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。本申请实施例以及实施例中的各个特征，在不相冲突的前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
图3是本实施例提供的阵列基板的线路结构示意图。该阵列基板包括显示区310和检测电路320，检测电路302设置于显示区310的一侧。
显示区310中设置多行子区域311，这些子区域以阵列的形式排列，以在制程后期形成亚像素阵列。每行子区域中设置充电线和扫描线，并且，每行子区域的共享线连接至行号增加值为2的子区域的充电线，即每行子区域的充电线为前面相隔一行的共享线提供信号。
举例而言，如图3所示，第N行子区域设置充电线C(N)和共享线S(N)，第N-2行子区域设置充电线C(N-2)和共享线S(N-2)，其中，第N-2行共享线S(N-2)连接至第N行充电线C(N)，从而利用充电线C(N)上的扫描信号来控制共享线S(N-2)的开启或者关闭。
检测电路320包括检测单元321、切换信号接入单元322、检测信号接入单元323和切换单元324。
其中，检测单元321中设置第一至第六检测线路G1～G6，用于向显示区310提供检测信号，以完成对显示区310中充电线和扫描线的缺陷检测。检测线路G1～G6一一对应地连接至显示区中的连续六行子区域的充电线。
在图3的示例中，第一检测线路G1连接至第N+2行子区域的充电线C(N+2)，第二检测线路G2连接至第N+1行子区域的充电线C(N+1)，类似的，第三至第六检测线路G3～G6分别连接至第N行、第N-1行、第N-2行和第N-3行子区域的充电线。
切换信号接入单元322用于接收切换控制信号。如图3所示，在一个优选地示例中，切换信号接入单元包括第一控制开关Sw1和第二控制开关Sw2，分别接收第一和第二控制信号。
检测信号接入单元323用于接收第一或第二检测信号。检测信号接入单元323中设置互相独立的第一检测点Te1、第二检测点Te2和第三检测点Te3。
切换单元324连接在检测单元321、切换信号接入单元322和检测信号接入单元之间323，可根据第一和第二控制信号切换不同检测模式。
在一个优选的示例中，切换单元324的电路结构示意如图4所示。切换单元包括第一切换线路410和第二切换线路420，分别实现不同的检测模式。
第一切换线路410包括第一控制线L1和第一至第六晶体管(T1至T6)。第一控制线L1连接第一控制开关S1，从而接收第一控制信号。T1至T6的栅极耦接第一控制线L1，T1至T6的第一端分别对应耦接第一至第六检测线路(G1至G6)。第一和第四晶体管(T1和T4)的第二端均连接至第一信号共享点A，第二和第五晶体管(T2和T5)的第二端均连接至第二信号共享点B，第三和第六晶体管(T3和T6)的第二端均连接至第三信号共享点C。
第一切换线路410与检测信号接入单元323连接，来接收第一检测信号。具体而言，第一检测点Te1的第一端连接第一信号共享点A，第二检测点Te2的第一端连接第二信号共享点B，第三检测点Te3的第一端连接第三信号共享点C。
第二切换线路420包括第二控制线L2和第七至第十二晶体管(T7至T12)。第二控制线L2连接第二控制开关S2，从而接收第二控制信号。T7至T12的栅极耦接第二控制线L2，T7至T12的第一端分别对应耦接至第一至第六检测线路(G1至G6)。第七、第九和第十一晶体管(T7、T9和T11)的第二端均连接至第四信号共享点D，第八、第十和第十二晶体管(T8、T10和T12)的第二端均连接至第五信号共享点E。
第二切换线路420与检测信号接入单元323连接，来接收第二检测信号。具体而言，第一检测点Te1的第二端连接第四信号共享点D，第三检测点Te3的第二端连接第五信号共享点E。
以下结合图3、图5和图6说明切换单元324实现两种不同检测模式。
具体而言，在第一种检测模式下，使得第一至第六检测线路分成三组，依次向三组检测线路提供第一检测信号；在第二种检测模式下，使得第一至第六检测线路分成两组，依次向两组检测线路提供第二检测信号。
第一种检测模式适用于阵列基板的量产初期。由于制程环境的清洁程度较差，诸如灰尘颗粒的微粒对光刻、曝光的制程操作造成影响，导致每行子区域中的充电线和扫描线之间容易出现短路缺陷。这种短路缺陷可能出现在显示区的子区域中，也可能出现在子区域外部的线路桥接区域。例如，如图3所示，第N行子区域内部的短路位置307处出现充电线C(N)和共享线S(N)之间的短路，或者第N+1行子区域外部的短路位置308处出现充电线C(N+1)和共享线S(N+1)之间的短路。
在这种情况下，采用第一检测模式进行检测，即，向第一控制开关Sw1提供第一控制信号，并为第一至第三检测点(Te1至Te3)提供第一检测信号。如图5所示，第一控制信号为高电平，使得第一控制开关Sw1打开，进而通过第一控制线L1向第一至第六晶体管(T1至T6)的栅极提供高电平信号。这样以来，T1至T6打开，使得第一至第六检测线路G1至G6均可接收由第一至第三检测点(Te1至Te3)提供的第一检测信号。为避免第二切换线路420带来的不良影响，优选地，可向第二控制开关Sw2提供低电平的第二控制信号，使得第二控制开关Sw2处于稳定的关闭状态。
第一检测信号可以包括连续三个检测时间段t1、t2和t3。
在t1时间段内向第一检测点Te1提供检测信号，进而经由Te1的第一端和第一共享点A同时向检测线路G1和G4提供检测信号。这时，在第二检测点Te2和第三检测点Te3均不提供检测信号，在G2、G5和G3、G6上不存在检测信号。正常情况下，第N+2行充电线C(N+2)和第N行共享线S(N)能够接收到来自检测线路G1的第一检测信号，同样地，第N-1行充电线C(N-1)和第N-3行共享线S(N-3)能够接收到来自检测线路G4的第一检测信号。进一步来说，第N+5行充电线C(N+5)和第N+3行共享线S(N+3)也能够接收到来自检测线路G4的第一检测信号。也就是说，通过充电线接收到第一检测信号的子区域的行号为N-1、N+2和N+5，行号的差值为3或者6。
如图3所示，若在阵列基板的短路位置307处存在短路缺陷，则由于第N行充电线C(N)与共享线S(N)短路连接，第N行充电线C(N)上也能够接收到第一检测信号，进而从检测线路G3上接收到第一检测信号。则可经由第三共享点C在第三检测点处接收到第一检测信号。这样以来，本实施例的检测方法能够检测到第N行子区域中充电线和共享线的短路缺陷。
容易理解，在t1时间段内，若第N+2行充电线C(N+2)或者第N行共享线S(N)不能接收到第一检测信号，则说明充电线C(N+2)或者共享线S(N)出现了断路。
在t2时间段内向第二检测点Te2提供检测信号，进而经由Te2的第一端和第二共享 点B同时向检测线路G2和G5提供检测信号，这时在G1、G4和G3、G6上不存在检测信号。正常情况下，第N+1行充电线C(N+1)和第N-1行共享线S(N-1)能够接收到来自G2的第一检测信号，第N-2行充电线C(N-2)和第N-4行共享线S(N-4)能够接收到来自G5的第一检测信号。也就是说，通过充电线接收到第一检测信号的子区域的行号为N+1和N-2，行号的差值为3。
若在阵列基板的短路位置308处存在短路缺陷，则由于第N+3行充电线C(N+3)与共享线S(N+1)短路连接，第N+3行充电线C(N+3)上也能够接收到第一检测信号，进而从检测线路G6上接收到第一检测信号。则可经由第三共享点C在第三检测点处接收到第一检测信号。这样以来，本实施例的检测方法能够检测到第N+1行子区域中充电线和共享线的短路缺陷。
容易理解，在t2时间段内，若第N+1行充电线C(N+1)或者第N-1行共享线S(N-1)不能接收到第一检测信号，则说明充电线C(N+1)或者共享线S(N-1)出现了断路。
类似的，在t3时间段内向第三检测点Te3提供检测信号，从而进而经由Te3的第一端和第三共享点C同时向检测线路G3和G6提供检测信号，这时在第一检测点Te1和第二检测点Te2上不存在检测信号，可以检测第N-1行子区域中充电线和共享线的短路缺陷。
因此，可以在第一检测状态下，将第一至第六检测线路G1至G6分成三组，即G1和G4为第一组，G2和G5为第二组，G3和G6为第三组，依次向这三组扫描线路提供第一检测信号。从而完成精确检测，能够提高阵列基板中短路缺陷的检出率。但是这一状态下需要的检测时间较长，效率较低。
第二种检测模式适用于批量生产阶段。由于制程条件趋于稳定，每行子区域中的充电线和扫描线之间很少会出现短路缺陷，在这种情况下，如果继续按照第一种检测状态操作，导致检测效率低下。
在这种情况下，采用第二检测模式进行检测，即，向第二控制开关Sw2提供第二控制信号，并为第一和第三检测点(Te1和Te3)提供第二检测信号。如图6所示，第二控制信号为高电平，使得第二控制开关Sw2打开，进而通过第二控制线L2向第七至第十二晶体管(T7至T12)的栅极提供高电平信号。这样以来，T7至T12打开，使得第一至第六检测线路G1至G6均可接收由第一和第三检测点(Te1和Te3)提供的第二检测信号。类似地，为避免第一切换线路410带来的不良影响，优选地，可向第一控制开关Sw1提供低电平的第一控制信号，使得第一控制开关Sw1处于稳定的关闭状态。
在第二检测状态下，将第一至第六检测线路G1～G6分成两组，即G1、G3和G5为第一组，G2、G4和G6为第二组，并依次向这两组扫描线路提供第二检测信号。第二检测信号可以包括连续两个检测时间段t1和t2。
在t1时间段内向第一检测点Te1提供第二检测信号，进而经由Te1的第二端和第四共享点D同时向检测线路G1、G3和G5提供第二检测信号，这时在G2、G4和G6上不存在检测信号，因此，在第二检测点Te2和第三检测点Te3上不存在检测信号。若第N行和第N-1行子区域的充电线中发生短路，在充电线C(N-1)上接收到来自G3的第二检测信号，进而在检测线路G4上接收到第二检测信号，则在第三检测点Te3上接收到第二检测信号。从而能够检测出相邻行子区域中充电线的短路缺陷。
在t2时间段内向第三检测点Te3提供第二检测信号，进而经由Te3的第二端和第五共享点E同时向G2、G4和G6提供第二检测信号，这时在G1、G3和G5上不存在检测信号。类似地也能够检测到相邻行子区域中充电线和共享线的线路缺陷。
这种检测状态的检测效率较高，与第一检测状态相比能够提高产能。这种检测状态下，通过给奇数和偶数扫描线不同的电讯号来检查阵列基板内是否存在短路或断路的情况，配合不同的数据信号还可以检查出其他类型的不良。
本实施例针对N+2充电共享型阵列基板，在检测区域设置6条检测线路，提供两种检测状态，在两种状态下为6条检测线路提供不同的检测信号，产生不同的检测效果。为检测电路设计两个开关以及三个测试点，可通过两个开关的开闭切换不同的测试模式，因而可以根据生产状况在两种检测状态下进行切换，提高检测效率。
在第二种检测模式下，由于仅需要两种检测信号，在检测信号接入区中仅设置两个检测点即可。从而简化外部检测机台配置，省去不必要的信号发生装置和探测装置。
上述实施例中显示区为N+2的走线桥接方式，每行子区域的的共享线连接至行号增加值为2的子区域的充电线，即每行子区域的充电线为前面相隔一行的共享线提供信号。本领域技术人员容易理解，对于N+4、N+6等走线桥接方式，只要满足每行子区域的的共享线连接至行号增加值为偶数的子区域的充电线，即可采用本实施例中提供的检测电路进行检测。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种阵列基板的检测电路，包括：
    检测单元，其包括第一至第六检测线路；
    切换信号接入单元，其用于接收切换控制信号；
    检测信号接入单元，其用于接收第一或第二检测信号；
    切换单元，其包括第一和第二切换线路，所述第一和第二切换线路连接在检测单元、切换信号接入单元和检测信号接入单元之间；
    其中，在切换控制信号的控制下，第一切换线路导通，使得第一至第六检测线路分成三组，依次向所述三组检测线路提供第一检测信号，或者
    第二切换线路导通，使得第一至第六检测线路分成两组，依次向所述两组检测线路提供第二检测信号。
  2. 如权利要求1所述的阵列基板的检测电路，其中，所述第一切换线路包括：
    第一控制线，其连接切换信号接入单元；
    第一至第六晶体管，其栅极耦接第一控制线，其第一端分别对应耦接第一至第六检测线路；
    其中，第一和第四晶体管的第二端均连接至第一信号共享点，第二和第五晶体管的第二端均连接至第二信号共享点，第三和第六晶体管的第二端均连接至第三信号共享点。
  3. 如权利要求2所述的阵列基板的检测电路，其中，在第一切换线路导通的情况下，所述三组检测线路分别为第一和第四检测线路、第二和第五检测线路、第三和第六检测线路。
  4. 如权利要求2所述的阵列基板的检测电路，其中，所述第二切换线路包括：
    第二控制线，其连接切换信号接入单元；
    第七至第十二晶体管，其栅极耦接第一控制线，其第一端分别对应耦接第一至第六检测线路；
    其中，第七、第九和第十一晶体管的第二端均连接至第四信号共享点，第八、第十和第十二晶体管的第二端均连接至第五信号共享点。
  5. 如权利要求4所述的阵列基板的检测电路，其中，在第二切换线路导通的情况下，所述两组检测线路分别为第一、第三和第五检测线路，以及第二、第四和第六检测线路。
  6. 如权利要求4所述的阵列基板的检测电路，其中，所述检测信号接入单元包括第 一至第三检测点，
    第一至第三检测点的第一端分别对应连接第一至第三信号共享点，以向所述三组检测线路依次提供第一检测信号；
    第一和第三检测点的第二端分别对应连接第四和第五信号共享点，以向所述两组检测线路依次提供第二检测信号。
  7. 如权利要求6所述的阵列基板的检测电路，其中，所述切换信号接入单元包括第一和第二控制开关，第一控制开关连接第一控制线以提供第一控制信号，第二控制开关连接第二控制线以提供第二控制信号，其中，第一和第二控制信号的电位极性相反。
  8. 一种阵列基板，包括显示区以及阵列基板的检测电路；
    所述阵列基板的检测电路包括：
    检测单元，其包括第一至第六检测线路；
    切换信号接入单元，其用于接收切换控制信号；
    检测信号接入单元，其用于接收第一或第二检测信号；
    切换单元，其包括第一和第二切换线路，所述第一和第二切换线路连接在检测单元、切换信号接入单元和检测信号接入单元之间；
    其中，在切换控制信号的控制下，第一切换线路导通，使得第一至第六检测线路分成三组，依次向所述三组检测线路提供第一检测信号，或者
    第二切换线路导通，使得第一至第六检测线路分成两组，依次向所述两组检测线路提供第二检测信号；
    所述显示区包括若干行子区域，每行子区域设置充电线和共享线，每行子区域的的共享线连接至行号增加值为偶数的子区域的充电线；
    所述检测单元中的第一至第六检测线路一一对应地连接至显示区中的连续六行子区域的充电线。
  9. 根据权利要求8所述的阵列基板，其中，所述第一切换线路包括：
    第一控制线，其连接切换信号接入单元；
    第一至第六晶体管，其栅极耦接第一控制线，其第一端分别对应耦接第一至第六检测线路；
    其中，第一和第四晶体管的第二端均连接至第一信号共享点，第二和第五晶体管的第二端均连接至第二信号共享点，第三和第六晶体管的第二端均连接至第三信号共享点。
  10. 根据权利要求9所述的阵列基板，其中，在第一切换线路导通的情况下，所述三 组检测线路分别为第一和第四检测线路、第二和第五检测线路、第三和第六检测线路。
  11. 根据权利要求9所述的阵列基板，其中，所述第二切换线路包括：
    第二控制线，其连接切换信号接入单元；
    第七至第十二晶体管，其栅极耦接第一控制线，其第一端分别对应耦接第一至第六检测线路；
    其中，第七、第九和第十一晶体管的第二端均连接至第四信号共享点，第八、第十和第十二晶体管的第二端均连接至第五信号共享点。
  12. 根据权利要求11所述的阵列基板，其中，在第二切换线路导通的情况下，所述两组检测线路分别为第一、第三和第五检测线路，以及第二、第四和第六检测线路。
  13. 根据权利要求11所述的阵列基板，其中，所述检测信号接入单元包括第一至第三检测点，
    第一至第三检测点的第一端分别对应连接第一至第三信号共享点，以向所述三组检测线路依次提供第一检测信号；
    第一和第三检测点的第二端分别对应连接第四和第五信号共享点，以向所述两组检测线路依次提供第二检测信号。
  14. 根据权利要求13所述的阵列基板，其中，所述切换信号接入单元包括第一和第二控制开关，第一控制开关连接第一控制线以提供第一控制信号，第二控制开关连接第二控制线以提供第二控制信号，其中，第一和第二控制信号的电位极性相反。
  15. 根据权利要求8所述的阵列基板，其中，在第一切换线路导通的情况下，依次向所述三组检测线路提供第一检测信号，以检测每行子区域中充电线和共享线的线路缺陷；
    在第二切换线路导通的情况下，依次向所述两组检测线路提供第二检测信号，以检测相邻行子区域中充电线和共享线的线路缺陷。
  16. 根据权利要求8所述的阵列基板，其中，在第一切换线路导通的情况下，通过充电线接收到第一检测信号的子区域的行号差值为3的倍数。
  17. 根据权利要求13所述的阵列基板，其中，在第一切换线路导通的情况下，依次向所述三组检测线路提供第一检测信号，以检测每行子区域中充电线和共享线的线路缺陷；
    在第二切换线路导通的情况下，依次向所述两组检测线路提供第二检测信号，以检测相邻行子区域中充电线和共享线的线路缺陷。
  18. 根据权利要求13所述的阵列基板，其中，在第一切换线路导通的情况下，通过 充电线接收到第一检测信号的子区域的行号差值为3的倍数。
  19. 根据权利要求14所述的阵列基板，其中，在第一切换线路导通的情况下，依次向所述三组检测线路提供第一检测信号，以检测每行子区域中充电线和共享线的线路缺陷；
    在第二切换线路导通的情况下，依次向所述两组检测线路提供第二检测信号，以检测相邻行子区域中充电线和共享线的线路缺陷。
  20. 根据权利要求14所述的阵列基板，其中，在第一切换线路导通的情况下，通过充电线接收到第一检测信号的子区域的行号差值为3的倍数。
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