Classifications

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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/02—Pretreatment of the material to be coated
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  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/04—Coating on selected surface areas, e.g. using masks
  • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/40—Oxides
  • C23C16/401—Oxides containing silicon
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  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
  • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
  • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
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  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
  • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
  • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
  • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
  • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
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  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
  • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
  • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
  • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
  • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• • H—ELECTRICITY
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
  • H01L21/76281—Lateral isolation by selective oxidation of silicon
• • H—ELECTRICITY
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
  • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/053—Oxides composed of metals from groups of the periodic table
  • H01L2924/0544—14th Group
  • H01L2924/05442—SiO2

Definitions

• Embodiments of the present disclosure generally relate to methods for forming a film on a semiconductor surface.
• Voids occur when deposited material adheres not only to the bottom of features but also to sidewalls, growing across the feature before it is completely filled. Such voids result in decreased reliability of integrated circuits.
• TEOS tetraethyl orthosilicate
• Embodiments described herein generally relate to the deposition and treatment of thin films for gap filling. More particularly, the embodiments described herein relate to selective deposition of silicon oxide films for feature-filling applications.
• One embodiment herein provides a method for selectively forming a silicon oxide layer on a substrate, comprising selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature may include a deposition surface and one or more sidewalls, the one or more sidewalls may include either a silicon oxide or a silicon nitride material.
• the deposition surface may essentially consist of silicon, and the selectively deposited silicon oxide layer may be formed by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature, wherein the silicon oxide layer selectively deposits on the deposition surface of the substrate.
• TEOS tetraethyl orthosilicate
• Another embodiment herein provides a method for selectively forming a silicon oxide layer on a substrate, comprising selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature may include a deposition surface and one or more sidewalls, the one or more sidewalls may include either a silicon oxide or a silicon nitride material.
• the deposition surface may essentially consist of silicon, and the selectively deposited silicon oxide layer may be formed by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature, wherein the silicon oxide layer selectively deposits on the deposition surface of the substrate.
• the method may further include etching the selectively deposited silicon oxide layer and repeating flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature and etching the selectively deposited silicon oxide layer one or more times.
• TEOS tetraethyl orthosilicate
• Another embodiment herein provides a method for selectively forming a silicon oxide layer on a substrate, comprising selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature may include a deposition surface and one or more sidewalls, wherein each of the sidewalls may have a base and a cap.
• the cap of the one or more sidewalls may comprise a silicon nitride material .
• a surface area of the cap may comprise at least one-third of a surface area of the sidewalk
• the deposition surface may essentially consist of silicon.
• the selectively deposited silicon oxide layer may be formed by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature, wherein the silicon oxide layer selectively deposits on the deposition surface of the substrate.
• TEOS tetraethyl orthosilicate
• Figure 1 is a schematic cross-sectional view of a processing chamber according to one embodiment.
• Figure 2A is a block diagram of a method of selectively depositing a silicon oxide layer according to one embodiment.
• Figures 2B-2D are side cross-sectional views of a feature formed on a surface of a substrate by use of the blocks discussed in conjunction with Figure 2A.
• Figure 3 is a histogram comparing wet etch rate on a silicon substrate to wet etch rate on a silicon nitride substrate.
• Figure 4 is a schematic cross-sectional view of a film deposited according to one embodiment.
• Figure 5 is a method for directionally treating a film for selective deposition of silicon oxide according to one embodiment.
• Figure 6 is a schematic cross-sectional view of a substrate with patterned features for selective deposition according to one embodiment.
• Embodiments described herein generally provide a method for filling features formed on a substrate.
• embodiments described herein generally provide for selective deposition of a silicon oxide material within dielectric- containing patterned features on a substrate.
• FIG. 1 is a schematic cross-sectional view of a processing chamber 100 for use in selectively depositing films according to one embodiment.
• the processing chamber 100 may include a Producer GT chamber that is available from Applied Materials, Inc. of Santa Clara, California.
• the processing chamber 100 includes two processing regions 1 18, 120.
• Chamber body 102 includes sidewall 1 12, interior wall 1 14, and bottom wall 1 16, which define the processing regions 1 18, 120.
• the bottom wall 1 16 in each processing region 118, 120 defines at least two passages 122, 124 through which a stem 126 of a heater pedestal 128 and a rod 130 of a wafer lift pin assembly are disposed, respectively.
• the sidewall 1 12 and the interior wall 1 14 define two cylindrical annular processing regions 1 18, 120.
• a circumferential pumping channel 125 is formed in the chamber walls defining the processing regions 1 18, 120 for exhausting gases from the processing regions 1 18, 120 and controlling the pressure within each region 1 18, 120.
• the pumping channels 125 of each processing region 1 18, 120 are preferably connected to a common exhaust pump via a common exhaust channel (not shown) and exhaust conduits (not shown).
• Each region is preferably pumped down to a selected pressure by the pump and the connected exhaust system allows equalization of the pressure within each region.
• the pressure in the processing chamber during operation may be between 200 Torr and 700 Torr.
• Each of the processing regions 1 18, 120 preferably includes a gas distribution assembly 108 disposed through the chamber lid 104 to deliver gases into the processing regions 1 18, 120.
• the gas distribution assembly 108 of each processing region includes a gas inlet passage 140 which delivers gas into a showerhead assembly 142.
• a gas source (not shown) is connected to the gas inlet passage 140, and is configured to deliver one or more precursor gases (e.g. , TEOS, ozone, ammonia) and/or inert gases (e.g., nitrogen) to the processing regions 1 18 and 120 through the showerhead assembly 142.
• An RF feedthrough provides a bias potential to the showerhead assembly 142 to facilitate generation of a plasma between the showerhead assembly 142 and the heater pedestal 128.
• the heater pedestal 128 is movably disposed in each processing region 118, 120 by a stem 126 which is connected to the underside of a support plate and extends through the bottom of the chamber body 102 where it is connected to a drive system 103.
• the stem 126 moves upward and downward in the chamber 106 to move the heater pedestal 128 to position a wafer thereon or remove a wafer therefrom for processing.
• the chamber body 102 defines a plurality of vertical gas passages for each reactant gas and cleaning gas suitable for the selected process to be delivered in the chamber through the gas distribution assembly 108.
• Gas inlet connections 141 are disposed at the bottom of the chamber 106 to connect the gas passages formed in the chamber wall to the gas inlet lines 139.
• Gas inlet lines 139 in turn connect to gas source lines (not shown) and are controlled for delivery of gas to each processing region 1 18, 120.
• the vacuum control system for the processing chamber 100 of the present disclosure may include a plurality of vacuum pumps in communication with various regions of the processing chamber 100, with each region having its own setpoint pressure.
• An RF power delivery system is used to deliver RF energy to each processing region 1 18, 120 through each gas distribution assembly 108.
• Figure 2A is a block diagram 200 of a method of selectively depositing a silicon oxide layer according to one embodiment.
• Figures 2B-2D are side cross- sectional views of a feature formed on a surface of a substrate 280 by following the blocks discussed in conjunction with Figure 2A.
• a silicon wafer is pre- cleaned in preparation for deposition. Pre-cleaning may be necessary in some cases because bare silicon oxidizes in air and forms an undesirable native oxide layer. To ensure a good result, the wafer surface may be stripped of the native oxide layer and replaced with a hydrogen-terminated surface using either a wet or dry cleaning treatment.
• a silicon-containing layer 282 is deposited on the silicon substrate 280.
• the silicon-containing layer 282 may comprise, for example, silicon oxide (Si0 2 ) or silicon nitride (SiN). This silicon-containing layer 282 may be deposited by flowing a silicon precursor and an oxygen or nitrogen gas or plasma into the processing chamber.
• the silicon-containing layer is patterned, resulting in one or more features 284 being formed in the silicon-containing dielectric layer 282.
• the patterning process may include, for example, applying a photoresist, exposing and developing the photoresist to form a pattern on the silicon-containing layer, wet or dry etching the exposed portions of the silicon-containing layer, removing the photoresist, and cleaning the patterned surfaces (e.g. , items 281 , 283 and 285 in Figure 2C) to prepare for additional processing.
• a photoresist e.g. , items 281 , 283 and 285 in Figure 2C
• the resulting silicon oxide layer may have a high level of silicon-hydrogen bonds.
• a typical deposition process may include delivering flows of monosilane SiH 4 , molecular oxygen 0 2 , and H 2 , although it should be understood that other precursor gases can be used.
• the selective deposition of silicon oxide into the patterned features 284 that are formed in the silicon-containing layer 282, which is performed at a later block, depends at least partially upon the silicon-containing deposited dielectric layer 282 having few or no hydrogen bonds at its exposed surface.
• any silicon oxide containing layer that has a hydrogen terminated surface such as a silane-formed silicon-containing layer, may need to be further treated to prevent the deposition of the selectively deposited silicon oxide film during block 250, from growing on these surfaces (e.g. , feature sidewalls and field region).
• the further treatment may include exposing the patterned surfaces of the silicon-containing layer, which was formed during block 220, to a plasma during block 240 to replace the hydrogen terminated surface.
• the plasma treatment at block 240 may comprise exposing the surface of the silicon-containing layer to a plasma containing NH 3 or N 2 to remove the hydrogen bonds from the formed silicon-containing layer (e.g. , Si0 2 layer).
• the silicon-containing layer 282 deposited at block 220 may be formed using a tetraethyl orthosilicate (TEOS) precursor to form a dielectric layer, such as a Si0 2 or SiN layer. It is believed that a silicon-containing layer 282 that is formed using a TEOS precursor will have significantly fewer or no hydrogen bonds on its surface, so the optional plasma treatment at block 240 may be omitted.
• TEOS tetraethyl orthosilicate
• a silicon oxide layer 286 is selectively deposited in the patterned features 284.
• the silicon oxide layer 286 is deposited by flowing TEOS and ozone (0 3 ) into the processing chamber.
• the deposition process may be either a thermal process or a plasma-enhanced process.
• the thermal process may be performed using a deposition process that uses ozone (O3) and TEOS in a temperature range of about 350-500°C and a pressure range of 20-620 Torr.
• a controlled plasma may be formed adjacent to the substrate 280 by RF energy applied from the RF power supply.
• the tetraethyl orthosilicate (TEOS) may flow into the processing chamber at a rate between about 400 mg/minute and 2 g/minute.
• the ozone may flow into the processing chamber at a rate of about 10% to 18% by mass.
• FIG. 7 illustrates a void 350 that may result from growth on sidewalls 283 of a feature 284 rather than simple bottom-up growth.
• the selective deposition process performed during block 250 has been observed to be able to minimize or prevent the formation of voids and seams by creating a growth condition on the bottom 281 of a feature 284 and a condition of limited or no growth on the sidewalls 283 of the feature 284.
• the features 284, into which the selectively deposited film is formed are composed of silicon oxide or silicon nitride or a combination thereof.
• the surface of the patterned silicon-containing layer will have fewer Si-H bonds, and therefore offers few nucleation sites to promote initiation of growth of the selectively deposited layer.
• the bottom 281 of the feature 284 ( Figure 2D), which can be considered as a deposition surface, may be composed of silicon, which has a high degree of Si-H bonds and therefore offers many nucleation sites to promote growth. Therefore, at block 250, the TEOS and ozone process results in deposition occurring preferentially on the bottom 281 of the feature 284, where the substrate 280 is composed of silicon.
• the TEOS and ozone-formed selectively deposited silicon oxide layer 286 does not adhere well to the sidewalls 283 of the features 284, which are composed of silicon nitride, silicon oxide, or combination thereof. Therefore, the silicon oxide layer 286 that is selectively deposited using TEOS and ozone forms and adheres preferentially to the silicon substrate 280, resulting in uniform bottom-up growth of the silicon oxide layer without significant growth or adherence to the sidewalls 283. This process results in minimization of voids.
• a substrate with Si-H bonding at its surface will provide nucleation sites, which allow for uniform or conformal growth on the substrate surface. Without Si-H bonds to promote growth, any growth of the selectively deposited layer on these types of surfaces will be non-uniform or island-like. Because growth occurs preferentially on the substrate 280, growth begins at the bottom 281 (i.e., deposition surface) of the patterned features 284 on the surface of the substrate 280. This generates uniform growth of the silicon oxide layer 286 with minimal voiding.
• a silicon oxide formed by the processes disclosed in block 250 does not deposit evenly, for example, on a silicon nitride surface or a surface of a conventional thermal silicon oxide layer. As a result, the silicon oxide layer 286 selectively grows from the bottom 281 of the patterned feature 284, resulting in reducing voiding by use of a bottom-up fill process.
• the silicon oxide layer 286 formed during block 250 may undesirably adhere and grow on the sidewalls 283 of the features 284 (e.g., trenches).
• the selectively deposited silicon oxide layer may be optionally etched using dilute hydrofluoric acid (DHF) to remove the low quality and thin formed layer on the sidewalls 283 and field region 285.
• DHF dilute hydrofluoric acid
• the substrate may be again subjected to the selective deposition process of block 250.
• the substrate may be optionally annealed, such as thermally processed using a lamp or other heat source, at block 270.
• the temperature in the substrate during the anneal block 270 may be between 300° Celsius and 480° Celsius.
• the substrate may be optionally etched by either dry or wet etch.
• One advantage of selective deposition of silicon oxide is the relative improvement of wet etch rate of the film formed during block 250.
• a higher wet etch rate may indicate a lower density and/or higher porosity of dielectric material. Therefore, the much lower wet etch rate of SiO x on a Si surface as opposed to SiN on a Si surface demonstrates the enhanced uniformity and therefore higher quality of the SiO layer.
• Figures 3A and 3B demonstrate the effectiveness of etching a selectively deposited silicon oxide layer.
• a silicon-containing layer 310 is deposited over a substrate 300, as in block 220 of Figure 2A.
• the silicon-containing layer 310 is patterned to form features 320, as in block 230 of Figure 2A.
• Silicon nitride caps 330 are then provided on the patterned silicon- containing layer 310. The process for this block is discussed in greater detail below.
• a silicon oxide layer 340 is then selectively deposited in the features 320 of the patterned silicon-containing layer 310, as in block 250 of Figure 2A. As discussed, the silicon oxide layer 340 formed in the features 320 is a high quality layer because of preferential growth of the selective silicon oxide on a silicon substrate and forming layer.
• the film is then etched, which may be achieved by exposure to 100:1 DHF.
• FIG. 4 is a histogram comparing wet etch rate on a silicon substrate to wet etch rate on a silicon nitride substrate.
• Figure 4 assumes a 100: 1 DHF wet etch condition. As shown in Figure 4, the DHF wet etch rate of SiN is more than double the DHF wet etch rate of Si.
• the much lower wet etch rate of SiO on a Si surface as opposed to SiN on a Si surface demonstrates the enhanced uniformity and therefore higher quality of the SiO layer.
• the film quality of the selectively grown film layer is high relative to portions of the selectively grown films formed on the nitride or unprepared oxide film.
• Figures 5A-5D demonstrate a method for directionally treating a film for selective deposition of silicon oxide according to one embodiment to form the silicon nitride caps 330 on top of the patterned silicon-containing layer 310.
• the advantage of the silicon nitride caps 330 is to prevent deposition of SiO on the sidewalls of the features 320 during the processes described in conjunction with block 250, resulting in enhanced bottom-up feature filling with minimization of voids and improved quality of the resulting film.
• One method for depositing the silicon nitride caps 330 is by directionally treating the substrate with a nitride-containing plasma. Examples of such a nitride-containing plasma may be NH 3 or N2.
• Figure 5A shows a patterned substrate before performing the nitridation process.
• a plasma 510 is directed at the patterned silicon-containing layer 310 from an angle.
• the patterned silicon-containing layer 310 blocks the lower portion of the adjacent feature from the directional plasma treatment, creating a shadowing effect. As a result, only the top portions of each feature 320 are exposed to the directional plasma treatment.
• the plasma 510 is directed at the patterned silicon- containing layer 310 from another angle or the substrate is rotated relative to the impinging beam to assure that a uniform nitridation process is performed on the surface of the substrate.
• the directional plasma treatment thus results in a silicon- containing layer 310 with features 320 wherein the top portions of the patterned silicon-containing layer 320 are nitrided. Because of the preferential growth of silicon oxide on silicon substrate rather than silicon nitride, when the directionally treated substrate is exposed to precursor gases described in block 250, the resulting silicon oxide film grows preferentially starting at the surface of the silicon substrate to fill the features. This preferential growth bottom-up growth prevents growth in from the sidewalls and results in a higher quality film with minimal voiding in the features 320.
• the surface area of the nitride caps 330 may be formed onto the substrate 31 0 so that it totals at least about one-third of the total surface area of the features 320.
• Figure 6 is a schematic cross-sectional view of a substrate 300 with a patterned silicon- containing layer 310 and features 320 for selective deposition according to this embodiment, where the nitride caps 330 have a surface area totaling at least about one-third of the surface area of the features 320.
• Embodiments of present disclosure provide preferential bottom-up growth of silicon oxide by selective deposition of silicon oxide films using TEOS and ozone at sub-atmospheric pressure.
• Oxide film deposited by this process grows on bare silicon surface and shows no growth/island like growth on silicon nitride and thermal silicon oxide surface. Because of the preferential growth of silicon oxide on silicon substrate rather than silicon nitride, when the directionally treated substrate is exposed to precursor gases, the resulting silicon oxide film grows preferentially starting at the surface of the silicon substrate to fill the features. This preferential growth bottom-up growth prevents growth in from the sidewalls and results in a higher quality film with minimal voiding in the features.

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