WO2016176873A1 - 一种tft显示器件及其制作方法 - Google Patents

一种tft显示器件及其制作方法 Download PDF

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Publication number
WO2016176873A1
WO2016176873A1 PCT/CN2015/079175 CN2015079175W WO2016176873A1 WO 2016176873 A1 WO2016176873 A1 WO 2016176873A1 CN 2015079175 W CN2015079175 W CN 2015079175W WO 2016176873 A1 WO2016176873 A1 WO 2016176873A1
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Prior art keywords
metal layer
silicon nitride
nitride film
display device
ito conductive
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French (fr)
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谢克成
洪日
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/895,433 priority Critical patent/US20170160608A1/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/503—Arrangements improving the resistance to shock

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a TFT display device and a method of fabricating the same.
  • TFT Thin Film Field Effect Transistor
  • the manufacturing process of display devices is relatively complicated and requires a lot of processes to be completed.
  • high-temperature processes such as metal film formation, non-metal film formation, dry etching, etc. These processes must be in a high temperature environment.
  • electrostatic discharge Electro-Static The discharge, ESD
  • ESD Electro-Static The discharge
  • the TFT display device will be easily damaged by ESD.
  • ESD protection of TFT display devices there are relatively effective methods.
  • ESD is likely to occur in the upper and lower metal overlap regions, as shown in Figure a and Figure b of Figure 1.
  • the upper and lower layers of metal overlap are overlapped, if the static electricity carried is too large, ESD breakdown will occur in the upper and lower overlapping areas. It is common practice to reduce the metal line width of the overlap region to reduce the ESD damage to the metal line.
  • the technical problem to be solved by the present invention is to provide a TFT display device and a manufacturing method thereof, which can reduce the damage of the ESD to the TFT display device, improve the product yield, and improve the product competitiveness.
  • a technical solution adopted by the present invention is to provide a TFT display device comprising: a first metal layer, a first silicon nitride film deposited on the first metal layer; and a second metal layer deposited on a first silicon nitride film is etched to form a pattern, and a second silicon nitride film is deposited on the second metal layer; a via hole, a region where the second metal layer overlaps with the first metal layer, the first metal layer and/or Or the second metal layer is disconnected, and the first silicon nitride film and the second silicon nitride film are etched away by using via holes in the off position, and the ITO conductive film is deposited to connect the disconnection position; wherein, the via hole Passing through the first silicon nitride film and the second silicon nitride film, contacting the first metal layer and/or the second metal layer, and when the first metal layer is broken, the ITO conductive film and the first metal layer at the via position
  • the ITO conductive film is coated on the second silicon nitride film.
  • the ITO conductive film at the via position contacts the second metal layer, and the disconnected position of the second metal layer is electrically connected through the ITO conductive film.
  • a TFT display device including: a first metal layer, a first silicon nitride film deposited on the first metal layer; a second metal layer, deposited Forming a pattern on the first silicon nitride film, depositing a second silicon nitride film on the second metal layer; via holes, overlapping regions of the second metal layer and the first metal layer, the first metal layer and / or the second metal layer is broken, the first silicon nitride film and the second silicon nitride film are etched away using via holes in the off position, and the ITO conductive film is deposited to make the disconnection position connected.
  • the via hole passes through the first silicon nitride film and the second silicon nitride film, and is in contact with the first metal layer and/or the second metal layer.
  • the ITO conductive film is coated on the second silicon nitride film.
  • the ITO conductive film at the via position is in contact with the first metal layer, and the disconnection position of the first metal layer is electrically connected through the ITO conductive film.
  • the ITO conductive film at the via position contacts the second metal layer, and the disconnected position of the second metal layer is electrically connected through the ITO conductive film.
  • another technical solution adopted by the present invention is to provide a method for fabricating a TFT display device, comprising: depositing a first silicon nitride film on a first metal layer; and forming a first silicon nitride film on the first silicon nitride film Depositing a second metal layer and etching to form a pattern, a second silicon nitride film deposited on the second metal layer; and a first metal layer and/or a second metal in a region where the second metal layer overlaps with the first metal layer
  • the layer is broken, and the first silicon nitride film and the second silicon nitride film are etched away using via holes in the off position, and the ITO conductive film is deposited to connect the disconnection position.
  • the via hole passes through the first silicon nitride film and the second silicon nitride film, and is in contact with the first metal layer and/or the second metal layer.
  • the ITO conductive film is coated on the second silicon nitride film.
  • the ITO conductive film at the via position is in contact with the first metal layer, and the disconnection position of the first metal layer is electrically connected through the ITO conductive film.
  • the ITO conductive film at the via position contacts the second metal layer, and the disconnected position of the second metal layer is electrically connected through the ITO conductive film.
  • the TFT display device of the present invention deposits a first silicon nitride film on the first metal layer; the second metal layer is deposited on the first silicon nitride film, Forming a pattern by etching, depositing a second silicon nitride film on the second metal layer; in a region where the second metal layer overlaps with the first metal layer, the first metal layer and/or the second metal layer are disconnected, and are disconnected.
  • the position uses a via to etch away the first silicon nitride film and the second silicon nitride film, and deposits an ITO conductive film to connect the disconnection position, thereby reducing the ESD damage to the TFT display device and improving the product yield. To enhance product competitiveness.
  • FIG. 1 is a schematic diagram of ESD breakdown of a TFT display device in the prior art
  • FIG. 2 is a cross-sectional structural view showing a TFT display device according to a first embodiment of the present invention
  • FIG. 3 is a schematic plan view showing the structure of the TFT display device of FIG. 2;
  • FIG. 4 is a cross-sectional structural view showing a TFT display device according to a second embodiment of the present invention.
  • Figure 5 is a plan view showing the planar structure of the TFT display device of Figure 4.
  • FIG. 6 is a schematic flow chart of a method of fabricating a TFT display device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional structural view of a TFT display device according to a first embodiment of the present invention.
  • the TFT display device 20 includes a first metal layer 21, a second metal layer 22, a first silicon nitride film 23, a via hole 24, an ITO conductive film 25, and a second silicon nitride film 26.
  • a first silicon nitride film 23 is deposited on the first metal layer 21.
  • the second metal layer 22 is deposited on the first silicon nitride film 23 and patterned by etching.
  • a second silicon nitride film 26 is deposited on the second metal layer 22; in a region where the second metal layer 22 overlaps with the first metal layer 21, the first metal layer 21 and/or the second metal layer 22 are disconnected, and are disconnected
  • the position uses the via holes 24 to etch away the first silicon nitride film 23 and the second silicon nitride film 26, and deposits the ITO conductive film 25 to connect the disconnection position.
  • the metal traces having a large peripheral line width on the display area of the TFT display device are changed into traces composed of ITO thin films, and the ends of the metal traces are connected by via-hole bridging, thereby reducing the line width and the metal walking.
  • ESD is generated on the lower trace of the metal trace on the metal trace, which disperses and guides the ESD on the TFT display device, thereby reducing the ESD damage to the TFT display device, improving the yield of the product, and improving the competitiveness of the product.
  • the ITO conductive film 25 is coated on the second silicon nitride film 26.
  • the via hole 24 passes through the first silicon nitride film 23 and the second silicon nitride film 26 to be in contact with the first metal layer 21 and/or the second metal layer 22.
  • the first silicon nitride film 23 and the second silicon nitride film 26 may be formed of the same silicon nitride film, such as a SiNx film. In other embodiments of the invention, different silicon nitride films may also be employed.
  • FIG. 2 is a cross-sectional structural view showing a region where the second metal layer 22 overlaps with the first metal layer 21, the first metal layer 21 is broken
  • FIG. 3 is a corresponding plan view
  • 27 is an anatomical line.
  • FIG. 4 is a cross-sectional structural view showing a region where the second metal layer 32 overlaps with the first metal layer 31, and the second metal layer 32 is broken
  • FIG. 5 is a corresponding plan view
  • 37 is an anatomical line.
  • a first silicon nitride film 33 is deposited on the first layer of metal 31
  • a second layer of metal 32 is deposited on the first silicon nitride film 33
  • a pattern is formed through an etching process
  • a second silicon nitride film is deposited on the second layer of metal 32.
  • the off position of the second layer of metal 32 is etched away using the via 34 to deposit the first silicon nitride film 33 and the second silicon nitride film 36, and the ITO conductive film 35 is deposited on the second silicon nitride film 36.
  • the ITO conductive film 35 at the position of the via hole 34 is in contact with the second metal layer 32, and the disconnection position of the second metal layer 32 is electrically connected through the ITO conductive film 35.
  • the conductivity of the via material is inconsistent, and the ESD on the TFT display device is dispersed and guided by the difference in capacitance between the different materials, thereby reducing the ESD to the TFT display device.
  • FIG. 6 is a schematic flow chart of a method of fabricating a TFT display device according to an embodiment of the present invention. As shown in FIG. 6, the manufacturing method of the TFT display device includes:
  • Step S10 depositing a first silicon nitride film on the first metal layer.
  • Step S11 depositing a second metal layer on the first silicon nitride film, and etching to form a pattern, and depositing a second silicon nitride film on the second metal layer.
  • Step S12 in a region where the second metal layer overlaps with the first metal layer, the first metal layer and/or the second metal layer are disconnected, and the first silicon nitride film and the second nitrogen are etched away by using via holes in the off position. A silicon film is formed and an ITO conductive film is deposited to connect the disconnection position.
  • the ITO conductive film is coated on the second silicon nitride film.
  • the via hole passes through the first silicon nitride film and the second silicon nitride film to be in contact with the first metal layer and/or the second metal layer.
  • the ITO conductive film at the via position is in contact with the first metal layer, so that the disconnected position of the first metal layer is electrically conductive through the ITO.
  • the film connection is turned on.
  • the ITO conductive film at the via position is in contact with the second metal layer, so that the disconnection position of the second metal layer is connected through the ITO conductive film. through.
  • the first metal layer and the second metal layer may be disconnected, and the first metal layer and the second metal layer may be disconnected in a region where the second metal layer overlaps with the first metal layer. The positions are respectively connected by different or the same ITO conductive film connection.
  • the metal traces having a large peripheral line width on the display area of the TFT display device are changed into traces composed of ITO thin films, and the ends of the metal traces are connected by via-hole bridging, thereby reducing the line width and the metal walking.
  • ESD is generated by the lower line across the metal trace on the smaller line and line width.
  • a via material having inconsistent conductivity such as a metal and an ITO conductive film, respectively, may be used, and the ESD on the TFT display device may be dispersed and guided by a difference in capacitance between different materials. Thereby reducing ESD damage to the TFT display device, improving product yield and enhancing product competitiveness.
  • the first silicon nitride film 23 and the second silicon nitride film 26 may be the same silicon nitride film, such as a SiNx film. In other embodiments of the invention, different silicon nitride films may also be employed.
  • the TFT display device of the present invention deposits a first silicon nitride film on the first metal layer; the second metal layer is deposited on the first silicon nitride film, and is patterned by etching, the second metal upper layer Depositing a second silicon nitride film; in a region where the second metal layer overlaps with the first metal layer, the first metal layer and/or the second metal layer are disconnected, and the via hole is used to etch away the silicon nitride film at the off position And depositing an ITO conductive film to make the disconnection position conductive, can reduce the ESD damage to the TFT display device, improve product yield, and enhance product competitiveness.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种TFT显示器件及其制作方法，TFT显示器件（20）包括：第一金属层（21），在第一金属层（21）上沉积第一氮化硅薄膜（23）；第二金属层（22），沉积在第一氮化硅薄膜（23）上，经过刻蚀形成图案，第二金属层（22）上沉积有第二氮化硅薄膜（26）；过孔（24），在第二金属层（22）与第一金属层（21）重叠区域，第一金属层（21）和/或第二金属层（22）断开，在断开位置使用过孔（24）刻蚀掉第一氮化硅薄膜（23）和第二氮化硅薄膜（26），并沉积ITO导电薄膜（25）以使断开位置连接导通。通过上述方式，能够降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。

Description

[根据细则37.2由ISA制定的发明名称]　一种TFT显示器件及其制作方法
【技术领域】
本发明涉及液晶显示领域，尤其是涉及一种TFT显示器件及其制作方法。
【背景技术】
薄膜场效应晶体管（Thin Film Transistor，TFT）显示器件的制作过程相对比较复杂，需要经过很多个工序才能制作完成，其中又有很多高温工序，比如金属成膜，非金属成膜，干刻等工序，这些工序必须在高温环境下作业，静电放电 (Electro-Static discharge，ESD)产生的几率相对较高，如果产品的设计对ESD的防护不好，TFT显示器件将很容易被ESD击伤。目前对TFT显示器件ESD防护的措施非常多，也有相对有效的方法。一般ESD容易发生在上下层金属交叠区域，如图1中的图a和图b所示。当上下两层金属跨线重叠的时候，如果所携带的静电流过大时，上下重叠区将发生ESD击穿现象。一般做法是将交叠区域的金属线宽减小，以减少ESD对金属线路的击伤。
【发明内容】
本发明主要解决的技术问题是提供一种TFT显示器件及其制作方法，能够降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT显示器件，包括：第一金属层，在第一金属层上沉积第一氮化硅薄膜；第二金属层，沉积在第一氮化硅薄膜上，经过刻蚀形成图案，第二金属层上沉积有第二氮化硅薄膜；过孔，在第二金属层与第一金属层重叠区域，第一金属层和/或第二金属层断开，在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜，并沉积ITO导电薄膜以使断开位置连接导通；其中，过孔穿过第一氮化硅薄膜和第二氮化硅薄膜，与第一金属层和/或第二金属层接触，第一金属层断开时，过孔位置的ITO导电薄膜与第一金属层接触，使第一金属层的断开位置通过ITO导电薄膜连接导通。
其中，ITO导电薄膜涂覆在第二氮化硅薄膜上。
其中，第二金属层断开时，过孔位置的ITO导电薄膜与第二金属层接触，使第二金属层的断开位置通过ITO导电薄膜连接导通。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT显示器件，包括：第一金属层，在第一金属层上沉积第一氮化硅薄膜；第二金属层，沉积在第一氮化硅薄膜上，经过刻蚀形成图案，第二金属层上沉积有第二氮化硅薄膜；过孔，在第二金属层与第一金属层重叠区域，第一金属层和/或第二金属层断开，在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜，并沉积ITO导电薄膜以使断开位置连接导通。
其中，过孔穿过第一氮化硅薄膜和第二氮化硅薄膜，与第一金属层和/或第二金属层接触。
其中，ITO导电薄膜涂覆在第二氮化硅薄膜上。
其中，第一金属层断开时，过孔位置的ITO导电薄膜与第一金属层接触，使第一金属层的断开位置通过ITO导电薄膜连接导通。
其中，第二金属层断开时，过孔位置的ITO导电薄膜与第二金属层接触，使第二金属层的断开位置通过ITO导电薄膜连接导通。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT显示器件的制作方法，包括：在第一金属层上沉积第一氮化硅薄膜；在第一氮化硅薄膜上沉积第二金属层，并经过刻蚀形成图案，第二金属层上沉积有第二氮化硅薄膜；在第二金属层与第一金属层重叠区域，第一金属层和/或第二金属层断开，在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜，并沉积ITO导电薄膜以使断开位置连接导通。
其中，过孔穿过第一氮化硅薄膜和第二氮化硅薄膜，与第一金属层和/或第二金属层接触。
其中，ITO导电薄膜涂覆在第二氮化硅薄膜上。
其中，第一金属层断开时，过孔位置的ITO导电薄膜与第一金属层接触，使第一金属层的断开位置通过ITO导电薄膜连接导通。
其中，第二金属层断开时，过孔位置的ITO导电薄膜与第二金属层接触，使第二金属层的断开位置通过ITO导电薄膜连接导通。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT显示器件通过在第一金属层上沉积第一氮化硅薄膜；第二金属层沉积在第一氮化硅薄膜上，经过刻蚀形成图案，第二金属层上沉积有第二氮化硅薄膜；在第二金属层与第一金属层重叠区域，第一金属层和/或第二金属层断开，在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜，并沉积ITO导电薄膜以使断开位置连接导通，能够降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。
【附图说明】
图1是现有技术中的TFT显示器件的ESD击穿的示意图；
图2是本发明第一实施例的TFT显示器件的剖面结构示意图；
图3是图2中的TFT显示器件的平面结构示意图；
图4是本发明第二实施例的TFT显示器件的剖面结构示意图；
图5是图4中的TFT显示器件的平面结构示意图；
图6是本发明实施例的TFT显示器件的制作方法的流程示意图。
【具体实施方式】
请参阅图2，图2是本发明第一实施例的TFT显示器件的剖面结构示意图。如图2所示，TFT显示器件20包括：第一金属层21、第二金属层22、第一氮化硅薄膜23、过孔24、ITO导电薄膜25以及第二氮化硅薄膜26。在第一金属层21上沉积第一氮化硅薄膜23。第二金属层22沉积在第一氮化硅薄膜23上，经过刻蚀形成图案。第二金属层22上沉积有第二氮化硅薄膜26；在第二金属层22与第一金属层21重叠区域，第一金属层21和/或第二金属层22断开，在断开位置使用过孔24刻蚀掉第一氮化硅薄膜23和第二氮化硅薄膜26，并沉积ITO导电薄膜25以使断开位置连接导通。如此，通过将TFT显示器件上显示区外围线宽较大的金属走线更改成由ITO薄膜组成的走线，并通过过孔桥接方式连通金属走线的两端，减少线宽较大金属走线与线宽较小金属走线上下跨线产生ESD，分散与导走TFT显示器件上的ESD，从而降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。
在本发明实施例中，ITO导电薄膜25涂覆在第二氮化硅薄膜26上。过孔24穿过第一氮化硅薄膜23和第二氮化硅薄膜26，与第一金属层21和/或第二金属层22接触。第一氮化硅薄膜23和第二氮化硅薄膜26可以采用相同的氮化硅薄膜，如SiNx薄膜。在本发明的其他实施例中，也可以采用不同的氮化硅薄膜。
图2表示在第二金属层22与第一金属层21重叠区域，第一金属层21断开的剖面结构图，图3为对应的平面结构图，27为解剖线。此时，过孔24位置处的ITO导电薄膜25与第一金属层21接触，使第一金属层21的断开位置通过ITO导电薄膜25连接导通。
图4表示在第二金属层32与第一金属层31重叠区域，第二金属层32断开的剖面结构图，图5为对应的平面结构图，37为解剖线。第一层金属31上沉积第一氮化硅薄膜33，第一氮化硅薄膜33上沉积第二层金属32，经过刻蚀制程形成图案，第二层金属32上沉积第二氮化硅薄膜36，第二层金属32的断开位置使用过孔34将第一氮化硅薄膜33和第二氮化硅薄膜36刻蚀掉，在第二氮化硅薄膜36上沉积ITO导电薄膜35。此时，过孔34位置处的ITO导电薄膜35与第二金属层32接触，使第二金属层32的断开位置通过ITO导电薄膜35连接导通。如此，通过在第二金属层22与第一金属层21重叠区域使用过孔材料导电性不一致，利用不同材料间电容差异分散与导走TFT显示器件上的ESD，从而降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。
图6是本发明实施例的TFT显示器件的制作方法的流程示意图。如图6所示，TFT显示器件的制作方法包括：
步骤S10：在第一金属层上沉积第一氮化硅薄膜。
步骤S11：在第一氮化硅薄膜上沉积第二金属层，并经过刻蚀形成图案，第二金属层上沉积有第二氮化硅薄膜。
步骤S12：在第二金属层与第一金属层重叠区域，第一金属层和/或第二金属层断开，在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜，并沉积ITO导电薄膜以使断开位置连接导通。
其中，ITO导电薄膜涂覆在第二氮化硅薄膜上。过孔穿过第一氮化硅薄膜和第二氮化硅薄膜，与第一金属层和/或第二金属层接触。具体地，在第二金属层与第一金属层重叠区域，第一金属层断开时，过孔位置的ITO导电薄膜与第一金属层接触，使第一金属层的断开位置通过ITO导电薄膜连接导通。在第二金属层与第一金属层重叠区域，第二金属层断开时，过孔位置的ITO导电薄膜与第二金属层接触，使第二金属层的断开位置通过ITO导电薄膜连接导通。当然在本发明的其他实施例中，也可以在第二金属层与第一金属层重叠区域，第一金属层和第二金属层皆断开，第一金属层和第二金属层的断开位置分别通过不同或相同的ITO导电薄膜连接导通。如此，通过将TFT显示器件上显示区外围线宽较大的金属走线更改成由ITO薄膜组成的走线，并通过过孔桥接方式连通金属走线的两端，减少线宽较大金属走线与线宽较小金属走线上下跨线产生ESD。另外，在第二金属层与第一金属层重叠区域使用导电性不一致的过孔材料，如分别为金属和ITO导电薄膜，可以利用不同材料间电容差异分散与导走TFT显示器件上的ESD，从而降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。
在本发明实施例中，第一氮化硅薄膜23和第二氮化硅薄膜26可以采用相同的氮化硅薄膜，如SiNx薄膜。在本发明的其他实施例中，也可以采用不同的氮化硅薄膜。
综上所述，本发明的TFT显示器件通过在第一金属层上沉积第一氮化硅薄膜；第二金属层沉积在第一氮化硅薄膜上，经过刻蚀形成图案，第二金属上层沉积有第二氮化硅薄膜；在第二金属层与第一金属层重叠区域，第一金属层和/或第二金属层断开，在断开位置使用过孔刻蚀掉氮化硅薄膜，并沉积ITO导电薄膜以使断开位置连接导通，能够降低ESD对TFT显示器件的击伤，提高产品良率，提升产品竞争力。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种TFT显示器件，其中，所述TFT显示器件包括：
    第一金属层，在所述第一金属层上沉积第一氮化硅薄膜；
    第二金属层，沉积在所述第一氮化硅薄膜上，经过刻蚀形成图案，所述第二金属层上沉积有第二氮化硅薄膜；
    过孔，在所述第二金属层与所述第一金属层重叠区域，所述第一金属层和/或所述第二金属层断开，在所述断开位置使用所述过孔刻蚀掉所述第一氮化硅薄膜和所述第二氮化硅薄膜，并沉积ITO导电薄膜以使所述断开位置连接导通；
    其中，所述过孔穿过所述第一氮化硅薄膜和所述第二氮化硅薄膜，与所述第一金属层和/或所述第二金属层接触，所述第一金属层断开时，所述过孔位置的所述ITO导电薄膜与所述第一金属层接触，使所述第一金属层的断开位置通过所述ITO导电薄膜连接导通。
  2. 根据权利要求1所述的TFT显示器件，其中，所述ITO导电薄膜涂覆在所述第二氮化硅薄膜上。
  3. 根据权利要求1所述的TFT显示器件，其中，所述第二金属层断开时，所述过孔位置的所述ITO导电薄膜与第二金属层接触，使所述第二金属层的断开位置通过所述ITO导电薄膜连接导通。
  4. 一种TFT显示器件，其中，所述TFT显示器件包括：
    第一金属层，在所述第一金属层上沉积第一氮化硅薄膜；
    第二金属层，沉积在所述第一氮化硅薄膜上，经过刻蚀形成图案，所述第二金属层上沉积有第二氮化硅薄膜；
    过孔，在所述第二金属层与所述第一金属层重叠区域，所述第一金属层和/或所述第二金属层断开，在所述断开位置使用所述过孔刻蚀掉所述第一氮化硅薄膜和所述第二氮化硅薄膜，并沉积ITO导电薄膜以使所述断开位置连接导通。
  5. 根据权利要求4所述的TFT显示器件，其中，所述过孔穿过所述第一氮化硅薄膜和所述第二氮化硅薄膜，与所述第一金属层和/或所述第二金属层接触。
  6. 根据权利要求5所述的TFT显示器件，其中，所述ITO导电薄膜涂覆在所述第二氮化硅薄膜上。
  7. 根据权利要求4所述的TFT显示器件，其中，所述第一金属层断开时，所述过孔位置的所述ITO导电薄膜与所述第一金属层接触，使所述第一金属层的断开位置通过所述ITO导电薄膜连接导通。
  8. 根据权利要求4所述的TFT显示器件，其中，所述第二金属层断开时，所述过孔位置的所述ITO导电薄膜与第二金属层接触，使所述第二金属层的断开位置通过所述ITO导电薄膜连接导通。
  9. 一种TFT显示器件的制作方法，其中，所述制作方法包括：
    在第一金属层上沉积第一氮化硅薄膜；
    在所述第一氮化硅薄膜上沉积第二金属层，并经过刻蚀形成图案，所述第二金属层上沉积有第二氮化硅薄膜；
    在所述第二金属层与所述第一金属层重叠区域，所述第一金属层和/或所述第二金属层断开，在所述断开位置使用过孔刻蚀掉所述第一氮化硅薄膜和所述第二氮化硅薄膜，并沉积ITO导电薄膜以使所述断开位置连接导通。
  10. 根据权利要求9所述的制作方法，其中，所述过孔穿过所述第一氮化硅薄膜和所述第二氮化硅薄膜，与所述第一金属层和/或所述第二金属层接触。
  11. 根据权利要求9所述的制作方法，其中，所述ITO导电薄膜涂覆在所述第二氮化硅薄膜上。
  12. 根据权利要求9所述的制作方法，其中，所述第一金属层断开时，所述过孔位置的所述ITO导电薄膜与所述第一金属层接触，使所述第一金属层的断开位置通过所述ITO导电薄膜连接导通。
  13. 根据权利要求9所述的制作方法，其中，所述第二金属层断开时，所述过孔位置的所述ITO导电薄膜与第二金属层接触，使所述第二金属层的断开位置通过所述ITO导电薄膜连接导通。
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