CN103996657A - 一种薄膜晶体管基板及其制作方法和液晶显示器 - Google Patents

一种薄膜晶体管基板及其制作方法和液晶显示器 Download PDF

Info

Publication number
CN103996657A
CN103996657A CN201410201456.4A CN201410201456A CN103996657A CN 103996657 A CN103996657 A CN 103996657A CN 201410201456 A CN201410201456 A CN 201410201456A CN 103996657 A CN103996657 A CN 103996657A
Authority
CN
China
Prior art keywords
layer
vapor deposition
chemical vapor
deposition films
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410201456.4A
Other languages
English (en)
Other versions
CN103996657B (zh
Inventor
李金磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201410201456.4A priority Critical patent/CN103996657B/zh
Priority to US14/382,718 priority patent/US9477127B2/en
Priority to PCT/CN2014/077528 priority patent/WO2015172343A1/zh
Publication of CN103996657A publication Critical patent/CN103996657A/zh
Application granted granted Critical
Publication of CN103996657B publication Critical patent/CN103996657B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02592Microstructure amorphous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1262Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136231Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

本发明适用于显示技术领域,提供了一种薄膜晶体管基板的制作方法:在基板表面上依次形成第一金属层、第一化学气相沉积膜层、第二金属层、以及第二化学气相沉积膜层;在第二化学气相沉积膜层上形成光阻;用光罩对所述光阻进行曝光和显影,光罩对应的位置为共享电容区域;对第二化学气相沉积膜层上的光阻被去除的过孔区域进行过孔蚀刻;对光阻进行灰化,去除所述共享电容区域的光阻;蚀刻共享电容区域的氮化硅层;形成一像素电极层。本发明让共享电容的两个金属电极间夹着的介质仅为氮化硅层,让共享电容的大小在金属电极极性变化时保持不变,可以改善画质,还可以节省液晶电视的背光电能损耗。

Description

一种薄膜晶体管基板及其制作方法和液晶显示器
技术领域
本发明属于显示技术领域,尤其涉及一种薄膜晶体管基板的制作方法、薄膜晶体管基板及薄膜晶体管液晶显示器。
背景技术
大尺寸的TFT-LCD(Thin Film Transistor Liquid Crystal Display,超薄膜晶体管液晶显示器)在平板电视领域获得了广泛的应用。平板电视区别于电脑显示屏或手机屏的显著要求是需要比较广的视角,以便让人能在比较随意的角度都能够看清电视显示的画面。
对于VA(Vertical Alignment,垂直配向技术)面板来讲,增加视角的比较传统的方法是将一个像素细分成两个子像素,每个子像素都因像素电极ITO(Indium Tin Oxide,掺锡氧化铟)方向的不同,分成4domain的结构。其中一个子像素的像素电极通过一个TFT开关连接到一个电荷共享电容上。当这个TFT开关打开时,子像素的电荷会部分流入到电荷共享电容,导致这个子像素的电压比另一个子像素的电压略小,从而使得两个子像素的亮度不一样。这样便可以形成8domain结构,可以增加画面的视角。
一般来讲,电荷共享电容都由信号线金属电极和金属栅电极作为电容极板,中间夹着As层的绝缘层形成MIM(Metal injection Molding,金属注射成形)结构。在5道光罩工艺中,因As层的有源成非晶硅层和欧姆接触层(掺杂磷元素的硅层)都被蚀刻掉,所以电荷共享电容的两个金属极板之间夹着的仅为氮化硅绝缘层。这种电容的大小不会随着金属极板正负极性的变化而变化。
TFT-LCD阵列基板的生产为了加大产能,减少生产成本,目前已经由5道光罩工艺改进到4道光罩工艺,即在CVD(Chemical Vapor Deposition,化学气相沉积)成膜形成栅极绝缘层和有源层后,取消曝光和蚀刻步骤,直接进行第二金属电极层的成膜,然后用半灰阶光罩,搭配湿式蚀刻和干式蚀刻,形成信号电极和TFT沟道。用4道光罩工艺形成的电荷共享电容,信号线金属电极与栅电极间夹的是完整的CVD的膜,包括氮化硅绝缘层,非晶硅层和欧姆接触层。电荷共享电容的两个金属极板之间夹着有非晶硅层和欧姆接触层、氮化硅绝缘层时,区别于仅有氮化硅绝缘层的状况,在两个金属极板的正负极性变化时,电容的大小会发生变化。这一电容的变化会导致画面有影像残留和闪烁等异常,导致画质下降和可靠性降低。
发明内容
本发明的目的在于提供一种薄膜晶体管基板的制作方法、薄膜晶体管基板及薄膜晶体管液晶显示器,旨在解决采用现有技术形成的电荷共享电容,在其两个金属极板的正负极性变化时,电容的大小会发生变化,这一电容的变化会导致画面有影像残留和闪烁等异常,导致画质下降和可靠性降低问题。
本发明是这样实现的,一种薄膜晶体管基板的制作方法,所述薄膜晶体管基板的制作方法包括以下步骤:
提供一基板,在所述基板表面上依次形成第一金属层、第一化学气相沉积膜层、第二金属层、以及第二化学气相沉积膜层;其中,所述第一金属层包括共享电容的下电极,所述第一化学气相沉积膜层及所述第二化学气相沉积膜层均分别包括氮化硅层;
在所述第二化学气相沉积膜层上形成光阻;
用光罩对所述光阻进行曝光和显影,所述光罩对应的位置为共享电容区域;
对所述第二化学气相沉积膜层上的光阻被去除的过孔区域进行过孔蚀刻;
对所述光阻进行灰化,去除所述共享电容区域的光阻;
蚀刻所述共享电容区域的氮化硅层;
形成一像素电极层,其中所述像素电极层包括共享电容的上电极。
本发明的另一目的在于提供一种薄膜晶体管基板,所述薄膜晶体管基板包括:
一基板,在所述基板表面上依次设置第一金属层、第一化学气相沉积膜层、第二金属层、第二化学气相沉积膜层、以及像素电极层;其中,所述第一金属层包括共享电容的下电极,所述第一化学气相沉积膜层及所述第二化学气相沉积膜层均分别包括氮化硅层;所述像素电极层包括共享电容的上电极,所述共享电容的上下电极层之间夹着所述第一化学气相沉积膜层的氮化硅层与所述第二化学气相沉积膜层的氮化硅层;或者是所述共享电容的上下电极层之间只夹着第一化学气相沉积膜层的氮化硅层。
本发明的另一目的在于提供一种包括上面所述的薄膜晶体管基板的薄膜晶体管液晶显示器。
在本发明中,采用第一金属层和像素电极层做共享电容的两个电极板,其中第二CVD膜层的光刻工艺中的光罩采用半灰阶光罩曝光工艺,一方面,可以让共享电容的两个金属电极间夹着的介质仅为氮化硅层,让共享电容的大小在金属电极极性变化时保持不变,可以改善画质和可靠性。
另一方面,因第二CVD膜层的光刻工艺中的光罩采用半灰阶光罩曝光工艺,除了正常的刻出过孔外,还可以对共享电容的两个金属极板之间绝缘层进行蚀刻。这样就减少了共享电容的两个金属极板之间绝缘层的厚度,增加了共享电容的大小。这样在相同的共享电容大小下,共享电容的金属电极就可以做的更小,可以增加面板的开口率。面板开口率增加后,相对于相同的画面亮度,背光源的功率可以减小,可以节省液晶电视的背光电能损耗。
附图说明
图1是本发明实施例一提供的薄膜晶体管基板的制作方法的实现流程示意图;
图2是本发明实施例二提供的薄膜晶体管基板的制作方法的实现流程示意图;
图3是本发明实施例提供的电荷共享的像素结构示意图;
图4是图3中B-B’位置的剖面图;
图5是本发明实施例提供的共享电容的两电极之间的氮化硅厚度变小的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
在本发明实施例中,采用第一金属层和像素电极层做电荷共享电容的两个电极板,其中第二CVD(化学气相沉积)膜层的光罩采用半灰阶光罩曝光工艺,一方面,可以让电荷共享电容的两个金属电极间夹着的介质仅为氮化硅层,让电荷共享电容的大小在金属电极极性变化时保持不变,可以改善画质;另一方面,还可以减少电荷共享电容的两个金属极板之间绝缘层的厚度,增加电荷共享电容的大小。这样在相同的电荷共享电容大小下,电荷共享电容的金属电极便可以做的更小,可以增加面板的开口率。
请参阅图1,为本发明实施例一提供的薄膜晶体管基板的制作方法的实现流程,其包括以下步骤:
在步骤S10中,提供一基板,在所述基板表面上依次形成第一金属层、第一化学气相沉积膜层、第二金属层、以及第二化学气相沉积膜层;其中,所述第一金属层包括共享电容的下电极,所述第一化学气相沉积膜层及所述第二化学气相沉积膜层均分别包括氮化硅层;
在本发明实施例中,在所述基板表面上形成第一化学气相沉积膜层的步骤包括:
在所述基板上依次连续成膜一氮化硅层、一非晶硅层、一欧姆接触层,并形成第一化学气相沉积膜层区域图样。
作为本发明一优选实施例,在所述基板表面上形成第一化学气相沉积膜层后,还包括以下步骤:
在所述第一化学气相沉积膜层上形成光阻;
对所述光阻进行曝光和显影;
对所述第一化学气相沉积膜层上的光阻被去除的共享电容区域进行蚀刻,以蚀刻掉第一化学气相沉积膜层中的共享电容区域对应位置的非晶硅层和欧姆接触层;
在所述基板表面上形成第二金属层后,蚀刻掉共享电容区域对应位置的第二金属层。
在步骤S20中,在所述第二化学气相沉积膜层上形成光阻;
在步骤S30中,用光罩对所述光阻进行曝光和显影,所述光罩对应的位置为共享电容区域;
在本发明实施例中,所述光罩采用的是半灰阶光罩,所述半灰阶光罩对应的位置为共享电容的上电极的区域。
在步骤S40中,对所述第二化学气相沉积膜层上的光阻被去除的过孔区域进行过孔蚀刻;
在步骤S50中,对所述光阻进行灰化,去除所述共享电容区域的光阻;
在本发明实施例中,所述对所述光阻进行灰化,去除所述共享电容区域的光阻的步骤包括:
进行光阻的灰化,及在干刻气体中使用氧气,对光阻进行氧化去除;
调整灰化的秒数,当共享电容区域的光阻被灰化去除时,便停止灰化。
在步骤S60中,蚀刻所述共享电容区域的氮化硅层;
作为本发明一优选实施例,所述蚀刻所述共享电容区域的氮化硅层的步骤包括:
蚀刻掉所述第二化学气相沉积膜层的部分氮化硅层,以使所述共享电容的上下电极层之间夹着第一化学气相沉积膜层的氮化硅层与第二化学气相沉积膜层的氮化硅层。
作为本发明另一优选实施例,所述蚀刻所述共享电容区域的氮化硅层的步骤包括:
蚀刻掉所述第二化学气相沉积膜层的全部氮化硅层,以使所述共享电容的上下电极层之间只夹着第一化学气相沉积膜层的氮化硅层。
在本发明实施例中,在所述蚀刻所述共享电容区域的氮化硅层的步骤之后,还包括:
去除剩余的光阻。
在步骤S70中,形成一像素电极层,其中所述像素电极层包括共享电容的上电极。
请参阅图2,为本发明实施例二提供的薄膜晶体管基板的制作方法的实现流程示意图,所述方法包括以下步骤:
在步骤S101中,提供一基板,在所述基板表面上沉积第一金属层,并形成所述第一金属层的图样,其中所述第一金属层的图样包括共享电容的下电极;
优选地,基板可以为玻璃基板。
在本发明实施例中,在基板表面上沉积第一金属层,并接着利用黄光及蚀刻工艺形成第一金属层的图样,其中该第一金属层的图样包括晶体管的栅极电极、共享电容的下电极及连接垫的垫电极。
在步骤S102中,在所述基板上成膜一第一化学气相沉积膜层,并形成所述第一化学气相沉积膜层区域图样,其中所述第一化学气相沉积膜层区域图样包括氮化硅层;
在本发明实施例中,第一CVD膜层包括一氮化硅层、一非晶硅层、一欧姆接触层。步骤S102具体为:在所述基板上依次连续成膜一氮化硅层、一非晶硅层、一欧姆接触层,并形成第一CVD膜层区域图样。
在本发明实施例中,以化学气相沉积在所述基板上依次连续成膜一氮化硅层、一非晶硅层、一欧姆接触层,并接着利用黄光及蚀刻工艺形成第一CVD膜层区域图样。
作为本发明一优选实施例,在所述基板表面上形成第一CVD膜层后,还包括以下步骤:
在所述第一CVD膜层上形成光阻;
对所述光阻进行曝光和显影;
对所述第一CVD膜层上的光阻被去除的共享电容区域进行蚀刻,以蚀刻掉第一CVD膜层中的共享电容区域对应位置的非晶硅层和欧姆接触层。
在步骤S103中,再以溅射沉积第二金属层,并形成所述第二金属层的图样;
在本发明实施例中,溅射沉积第二金属层后,并接着利用黄光及蚀刻工艺形成第二金属层的图样,所述第二金属层包括信号电极。
作为本发明一优选实施例,在形成第二金属层后,蚀刻掉共享电容区域对应位置的第二金属层。
在步骤S104中,在所述基板上全面沉积一第二化学气相沉积膜层;
在本发明实施例中,第二CVD膜层可以为氮化硅层。
在步骤S105中,在所述第二化学气相沉积膜层上涂抹光阻;
在步骤S106中,用半灰阶光罩对所述光阻进行曝光,接着对光阻进行显影;
在本发明实施例中,所述半灰阶光罩上半灰阶区域所对应的位置为共享电容两极板相对的区域,具体地,所述半灰阶光罩对应的位置为共享电容的上电极的区域。
在步骤S107中,对所述第二化学气相沉积膜层上的光阻被去除的过孔区域进行过孔蚀刻;
在本发明实施例中,优选地,进行过孔蚀刻采用的是干蚀刻。
在步骤S108中,对所述光阻进行灰化,去除共享电容区域的半灰阶光阻;
优选地,对所述光阻进行灰化,去除所述共享电容区域的半灰阶光阻,其采用的是干蚀刻工艺。
在本发明实施例中,如光阻层的厚度可为1.5um~2.2um,当过孔区域的光阻被去除,电荷共享电容两极板相对位置区域的光阻厚度为0.3um~0.6um,其它未曝光区域的光阻厚度保持不变。
作为本发明一优选实施例,所述对光阻进行灰化,去除所述共享电容区域的半灰阶光阻的步骤包括:
进行光阻灰化时(即在干刻气体中使用氧气,对光阻进行氧化去除),调整灰化的秒数,当共享电容区域的光阻被灰化去除时,便停止灰化。
在步骤S109中,蚀刻所述共享电容区域的氮化硅层;
在本发明实施例中,优选地,蚀刻所述共享电容区域的氮化硅层采用的是干蚀刻。电荷共享电容区域的SiNx膜厚可为100~400纳米。
作为本发明一优选实施例,在步骤S109之后,还包括:
去除剩余的光阻。
在步骤S110中,再以溅射沉积一像素电极层,并形成所述像素电极层的图样,其中所述像素电极层的图样包括共享电容的上电极。
在本发明实施例中,溅射沉积一像素电极层后,并接着利用黄光及蚀刻工艺形成所述像素电极层的图样。
其中,像素电极层可以是铟锡氧化物ITO或铟锌氧化物IZO等等。
通过上述薄膜晶体管基板的制作方法得到的电荷共享的像素结构如图3所示。
如图3所示,图3中标号11和13分别为第n根扫描线和第n+1根扫描线,12,15,19为与扫描线同一次光刻工艺做成,12是公共电极,15是遮光线,19为电荷共享电容的下电极。
在图3中,标号14是信号线,17是两个背对背的TFT元件,通过源极18和漏极16分别给主像素(main pixel)和子像素(sub pixel)提供电信号。标号230是main pixel的ITO电极,200是sub pixel的ITO电极。标号210是电荷共享电容的TFT。标号221是电荷共享电容的上电极。
在本发明实施例中,电荷共享方式是通过如下方式来达到广视角的目的:扫描线11提供开启电压时,TFT元件17开启,将信号线的电压信号写入到mainpixel230和sub pixel200中,之后扫描线11提供关闭电压,而扫描线13提供开启电压,这时共享电容的TFT210开启,将sub pixel200上的电荷共享到共享电容中。这样main pixel和sub pixel的电压将不同,通过米字状电极便能够达到8domain的效果,从而增加了广视角的效果。这种8domain广视角的效果要优于4domain的广视角的效果。
图3中的共享电容的上电极221,是与ITO电极层相同的层别,通过过孔与共享电容的TFT210相连。图4是图3中B-B’位置的剖面图。共享电容的上电极212是ITO,是与ITO像素电极层相同的层别;共享电容的下电极215是第一金属层,是与扫描电极层相同的层别。所述第二CVD积膜层包括氮化硅层;当蚀刻掉所述第二化学气相沉积膜层的部分氮化硅层,所述共享电容的上下电极层之间夹着第一CVD膜层的氮化硅层(非晶硅层和磷掺杂的非晶硅都已经蚀刻掉)与第二CVD膜层的氮化硅层。所述第一化学气相沉积膜层的氮化硅层厚度为300~400纳米,第二化学气相沉积膜层的氮化硅层厚度为200~250纳米;这样图3中的共享电容之间氮化硅的总厚度是500~650纳米。这种共享电容虽然电容的大小不会随着两个金属基板的正负极性变化发生变化,但金属基板间的距离较大,共享电容的电容值较小。
平板电容的计算公式:C=εε0*(S/d),ε为相对介电常数,ε0为真空介电常数,S为平行电极板的面积,d为极板间的距离。
因此,如何保持共享电容的大小不变的前提下,缩小共享电容极板的面积,增加开口率,正是本发明所要阐述的内容。
本发明所阐述的共享电容设计与图3一样,只是制作方法上有所不同。本发明实施例是在第二CVD膜层镀膜后,进行曝光工艺,其所用的光罩为半灰阶光罩,半灰阶光罩区域恰好设计在共享电容的上极板的区域,而正常的过孔区域为全开不变。相应的,曝光后的干蚀刻工艺也由一步干蚀刻工艺变成三步的干蚀刻工艺:刻过孔,灰化半灰阶光阻,蚀刻共享电容区域的SiNx。通过控制蚀刻秒数,可以保证共享电容区域的SiNx剩余厚度在100~400纳米。
采用本发明实施例提供的制作工艺,可以使共享电容的两电极之间的SiNx厚度变小,如图5所示。共享电容之间的距离减少,相应的两电极的面积也可以减小,这样就增加了Pixel的开口率,面板的穿透率会相应增加,面板便更具有节能的特性。同时,共享电容之间的介质是单一介质SiNx,不含非晶硅层和磷掺杂的非晶硅,电容的大小不会随基板的极性发生变化,增加了面板的可靠性和减少了闪烁等不良。
本发明实施例还提供了一种薄膜晶体管基板,所述薄膜晶体管基板包括:
一基板,在所述基板表面上依次设置第一金属层、第一化学气相沉积膜层、第二金属层、第二化学气相沉积膜层、以及像素电极层;其中,所述第一金属层包括共享电容的下电极,所述第一化学气相沉积膜层及所述第二化学气相沉积膜层均分别包括氮化硅层;所述像素电极层包括共享电容的上电极,所述共享电容的上下电极层之间夹着所述第一化学气相沉积膜层的氮化硅层与所述第二化学气相沉积膜层的氮化硅层;或者是所述共享电容的上下电极层之间只夹着第一化学气相沉积膜层的氮化硅层。
作为本发明一实施例,当蚀刻掉所述第二化学气相沉积膜层的部分氮化硅层,以使所述共享电容的上下电极层之间夹着第一化学气相沉积膜层的氮化硅层与第二化学气相沉积膜层的氮化硅层,从而使得所述共享电容之间氮化硅的总厚度可以是500~650纳米。
作为本发明另一实施例,当蚀刻掉所述第二化学气相沉积膜层的全部氮化硅层,以使所述共享电容的上下电极层之间只夹着第一化学气相沉积膜层的氮化硅层,从而使得所述共享电容之间氮化硅的总厚度可以是100~400纳米。
本发明实施例还提供了一种包括上面所述的薄膜晶体管基板的薄膜晶体管液晶显示器。然而,可以理解的是,所述薄膜晶体管液晶显示器可为TFT-LCD。
综上所述,本发明实施例采用第一金属层和像素电极层做共享电容的两个电极板,其中第二CVD膜层的光刻工艺中的光罩采用半灰阶光罩曝光工艺,一方面,可以让共享电容的两个金属电极间夹着的介质仅为氮化硅层,让共享电容的大小在金属电极极性变化时保持不变,可以改善画质和可靠性。
另一方面,因第二CVD膜层的光刻工艺中的光罩采用半灰阶光罩曝光工艺,除了正常的刻出过孔外,还可以对共享电容的两个金属极板之间绝缘层进行蚀刻。这样就减少了共享电容的两个金属极板之间绝缘层的厚度,增加了共享电容的大小。这样在相同的共享电容大小下,共享电容的金属电极就可以做的更小,可以增加面板的开口率。面板开口率增加后,相对于相同的画面亮度,背光源的功率可以减小,可以节省液晶电视的背光电能损耗。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。

Claims (10)

1.一种薄膜晶体管基板的制作方法,其特征在于,所述薄膜晶体管基板的制作方法包括以下步骤:
提供一基板,在所述基板表面上依次形成第一金属层、第一化学气相沉积膜层、第二金属层、以及第二化学气相沉积膜层;其中,所述第一金属层包括共享电容的下电极,所述第一化学气相沉积膜层及所述第二化学气相沉积膜层均分别包括氮化硅层;
在所述第二化学气相沉积膜层上形成光阻;
用光罩对所述光阻进行曝光和显影,所述光罩对应的位置为共享电容区域;
对所述第二化学气相沉积膜层上的光阻被去除的过孔区域进行过孔蚀刻;
对所述光阻进行灰化,去除所述共享电容区域的光阻;
蚀刻所述共享电容区域的氮化硅层;
形成一像素电极层,其中所述像素电极层包括共享电容的上电极。
2.如权利要求1所述的薄膜晶体管基板的制作方法,其特征在于,所述光罩采用的是半灰阶光罩,所述半灰阶光罩对应的位置为共享电容的上电极的区域。
3.如权利要求1所述的薄膜晶体管基板的制作方法,其特征在于,在所述基板表面上形成第一化学气相沉积膜层的步骤包括:
在所述基板上依次连续成膜一氮化硅层、一非晶硅层、一欧姆接触层,并形成第一化学气相沉积膜层区域图样。
4.如权利要求3所述的薄膜晶体管基板的制作方法,其特征在于,在所述基板表面上形成第一化学气相沉积膜层后,还包括以下步骤:
在所述第一化学气相沉积膜层上形成光阻;
对所述光阻进行曝光和显影;
对所述第一化学气相沉积膜层上的光阻被去除的共享电容区域进行蚀刻,以蚀刻掉第一化学气相沉积膜层中的共享电容区域对应位置的非晶硅层和欧姆接触层;
在所述基板表面上形成第二金属层后,蚀刻掉共享电容区域对应位置的第二金属层。
5.如权利要求4所述的薄膜晶体管基板的制作方法,其特征在于,所述蚀刻所述共享电容区域的氮化硅层的步骤包括:
蚀刻掉所述第二化学气相沉积膜层的部分氮化硅层,以使所述共享电容的上下电极层之间夹着第一化学气相沉积膜层的氮化硅层与第二化学气相沉积膜层的氮化硅层。
6.如权利要求4所述的薄膜晶体管基板的制作方法,其特征在于,所述蚀刻所述共享电容区域的氮化硅层的步骤包括:
蚀刻掉所述第二化学气相沉积膜层的全部氮化硅层,以使所述共享电容的上下电极层之间只夹着第一化学气相沉积膜层的氮化硅层。
7.如权利要求1所述的薄膜晶体管基板的制作方法,其特征在于,在所述蚀刻所述共享电容区域的氮化硅层的步骤之后,还包括:
去除剩余的光阻。
8.一种薄膜晶体管基板,其特征在于,所述薄膜晶体管基板包括:
一基板,在所述基板表面上依次设置第一金属层、第一化学气相沉积膜层、第二金属层、第二化学气相沉积膜层、以及像素电极层;其中,所述第一金属层包括共享电容的下电极,所述第一化学气相沉积膜层及所述第二化学气相沉积膜层均分别包括氮化硅层;所述像素电极层包括共享电容的上电极,所述共享电容的上下电极层之间夹着所述第一化学气相沉积膜层的氮化硅层与所述第二化学气相沉积膜层的氮化硅层;或者是所述共享电容的上下电极层之间只夹着第一化学气相沉积膜层的氮化硅层。
9.如权利要求8所述的薄膜晶体管基板,其特征在于,
所述共享电容之间氮化硅的总厚度是500~650纳米,或者
所述共享电容之间氮化硅的总厚度是100~400纳米。
10.一种包括权利要求8或9任一项所述的薄膜晶体管基板的薄膜晶体管液晶显示器。
CN201410201456.4A 2014-05-13 2014-05-13 一种薄膜晶体管基板及其制作方法和液晶显示器 Active CN103996657B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410201456.4A CN103996657B (zh) 2014-05-13 2014-05-13 一种薄膜晶体管基板及其制作方法和液晶显示器
US14/382,718 US9477127B2 (en) 2014-05-13 2014-05-15 Thin film transistor substrate, manufacture method thereof and liquid crystal display
PCT/CN2014/077528 WO2015172343A1 (zh) 2014-05-13 2014-05-15 一种薄膜晶体管基板及其制作方法和液晶显示器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410201456.4A CN103996657B (zh) 2014-05-13 2014-05-13 一种薄膜晶体管基板及其制作方法和液晶显示器

Publications (2)

Publication Number Publication Date
CN103996657A true CN103996657A (zh) 2014-08-20
CN103996657B CN103996657B (zh) 2016-06-22

Family

ID=51310772

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410201456.4A Active CN103996657B (zh) 2014-05-13 2014-05-13 一种薄膜晶体管基板及其制作方法和液晶显示器

Country Status (3)

Country Link
US (1) US9477127B2 (zh)
CN (1) CN103996657B (zh)
WO (1) WO2015172343A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016176873A1 (zh) * 2015-05-06 2016-11-10 深圳市华星光电技术有限公司 一种tft显示器件及其制作方法
CN113314546A (zh) * 2021-05-21 2021-08-27 深圳市华星光电半导体显示技术有限公司 阵列基板及阵列基板测试方法、显示面板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581043B (zh) * 2016-10-04 2017-05-01 友達光電股份有限公司 畫素結構

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231434A (zh) * 2006-09-08 2008-07-30 三星电子株式会社 阵列面板及其驱动方法
CN101236343A (zh) * 2008-03-03 2008-08-06 上海广电光电子有限公司 液晶显示装置、像素结构及其驱动方法
US20110267554A1 (en) * 2007-11-26 2011-11-03 Young-Chol Yang Liquid crystal display

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101282397B1 (ko) * 2004-12-07 2013-07-04 삼성디스플레이 주식회사 표시 장치용 배선, 상기 배선을 포함하는 박막 트랜지스터표시판 및 그 제조 방법
KR20080101582A (ko) * 2007-05-18 2008-11-21 삼성전자주식회사 액정 표시 장치
KR20120021537A (ko) * 2010-08-06 2012-03-09 삼성전자주식회사 액정 표시 장치
CN103680447B (zh) * 2013-12-12 2016-01-13 深圳市华星光电技术有限公司 液晶显示设备及其像素驱动方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231434A (zh) * 2006-09-08 2008-07-30 三星电子株式会社 阵列面板及其驱动方法
US20110267554A1 (en) * 2007-11-26 2011-11-03 Young-Chol Yang Liquid crystal display
CN101236343A (zh) * 2008-03-03 2008-08-06 上海广电光电子有限公司 液晶显示装置、像素结构及其驱动方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016176873A1 (zh) * 2015-05-06 2016-11-10 深圳市华星光电技术有限公司 一种tft显示器件及其制作方法
CN113314546A (zh) * 2021-05-21 2021-08-27 深圳市华星光电半导体显示技术有限公司 阵列基板及阵列基板测试方法、显示面板

Also Published As

Publication number Publication date
US20160274392A1 (en) 2016-09-22
US9477127B2 (en) 2016-10-25
WO2015172343A1 (zh) 2015-11-19
CN103996657B (zh) 2016-06-22

Similar Documents

Publication Publication Date Title
KR101243809B1 (ko) 박막트랜지스터의 제조방법 및 이를 이용한 tft 어레이기판의 제조방법
CN102955312B (zh) 一种阵列基板及其制作方法、显示装置
CN102629585B (zh) 一种显示装置、薄膜晶体管、阵列基板及其制造方法
CN105487315A (zh) Tft阵列基板
US9711544B2 (en) Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, display device
US11031419B2 (en) Array substrate, method for manufacturing the same, and display device
CN102566172A (zh) 用于面内切换模式的液晶显示器件的阵列基板及其制作方法
CN104280951A (zh) 阵列基板及其制造方法、显示装置
CN102967978B (zh) 阵列基板及其制造方法、显示装置
US20150212380A1 (en) Pixel structure and liquid crystal panel
US10312266B2 (en) Display substrate and manufacturing method thereof, and display device
CN107132710A (zh) 一种阵列基板及其制备方法、显示面板
CN105093756A (zh) 液晶显示像素结构及其制作方法
CN104090401A (zh) 阵列基板及其制备方法、显示装置
US10403761B2 (en) Array substrate and manufacturing method thereof, and display device
CN102569185A (zh) 阵列基板及其制造方法和液晶显示器
CN102650783A (zh) 一种显示装置、tft-lcd像素结构及其制作方法
CN101021658A (zh) 液晶显示面板的半导体结构及其制作方法
CN103996657B (zh) 一种薄膜晶体管基板及其制作方法和液晶显示器
US9679921B2 (en) Display substrate and method of fabricating the same
CN105870132A (zh) Tft阵列基板及其制作方法
WO2015021720A1 (zh) 一种阵列基板及其制备方法及显示装置
CN101464603B (zh) 液晶显示装置
CN105572981B (zh) 阵列基板、显示面板以及液晶显示装置
CN100461379C (zh) 液晶显示器的像素结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant