WO2016011692A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2016011692A1
WO2016011692A1 PCT/CN2014/084821 CN2014084821W WO2016011692A1 WO 2016011692 A1 WO2016011692 A1 WO 2016011692A1 CN 2014084821 W CN2014084821 W CN 2014084821W WO 2016011692 A1 WO2016011692 A1 WO 2016011692A1
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Prior art keywords
trace
layer
array substrate
insulating layer
jumper
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Application number
PCT/CN2014/084821
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English (en)
French (fr)
Inventor
李金磊
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/416,898 priority Critical patent/US9490271B2/en
Publication of WO2016011692A1 publication Critical patent/WO2016011692A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate, a method of manufacturing the same, and a display device.
  • liquid crystal displays have become the most common display devices.
  • the array substrate is an important component in the liquid crystal display, including a display area and a peripheral area (non-display area). Some traces are provided in the peripheral area of the array substrate, and some traces are required to be connected. As shown in FIG. 1, on the base substrate 00, the first trace 11 and the second trace 12 located in the first metal layer (the poplar metal layer) need to be connected, but the first trace 11 and the second trace The third line 13 is also interposed between the lines 12, which requires the first line 1 and the second line 12 to be connected across the line.
  • the existing method of connecting the wires is to provide a jumper 3 on the first insulating layer 2 covering the first metal layer, a second metal layer (source and drain metal layer) where the jumper 3 is located, and a second metal
  • the layer is covered with a second insulating layer 4rad and then a via 51 penetrating the first insulating layer 2 and the second insulating layer 4 is formed, and a via 52 penetrating the second insulating layer 4 is passed through the via hole 51, 52 connects the first trace 11 and the second trace 12 to the jumper 3 to realize the over-the-line connection of the first trace 11 and the second trace 12.
  • the material of the transparent electrode 6 is usually selected from indium tin oxide (ITO) or indium zinc oxide (IZO), and its resistivity is two orders of magnitude higher than that of the metal, resulting in the first trace 11, the second trace 12 and the jumper 3
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • An object of the present invention is to provide an array substrate, a method for fabricating the same, and a display device, which solve the technical problem of large impedance at the cross-line connection in the conventional array substrate.
  • the present invention provides an array substrate, including:
  • the jumper in the second metal layer on the first insulating layer, the jumper is connected to the first trace and the second trace through the via to make the first trace And the second trace is electrically connected through the jumper.
  • the array substrate further includes a second insulating layer covering the second metal layer.
  • the array substrate further includes a transparent electrode layer on the second insulating layer.
  • the first trace, the second trace and the jumper are both located in a board edge region of the array substrate.
  • the present invention also provides a method of manufacturing the above array substrate, comprising:
  • Step 1 forming a pattern of a first metal layer on the base substrate, including a first trace and a second trace; Step 2, forming a pattern of the first insulating layer overlying the first metal layer, wherein A via hole corresponding to the first trace and the second trace is included;
  • Step 3 forming a pattern of a second metal layer on the first insulating layer, including a jumper connected to the first trace and the second trace through the via hole, so that the first A trace and the second trace are conducted through the jumper.
  • step 2 comprising: forming a first insulating layer covering the first metal layer;
  • the manufacturing method further includes - step 4, forming a pattern of the second insulating layer overlying the second metal layer.
  • the manufacturing method further includes:
  • Step 5 forming a pattern of the transparent electrode layer on the second insulating layer.
  • the first trace, said second trace and the jumper are located on the array substrate board edge region of t>
  • the present invention further provides a display apparatus comprising a color filter substrate and the array Substrate.
  • the present invention has the following beneficial effects: in the array substrate provided by the present invention, by providing a via hole in the first insulating layer, the jumper wire located in the second metal layer can directly pass through the via hole directly with the first trace and the second The traces are in contact without connecting the jumper wires to the first traces and the second traces through the transparent electrodes.
  • the simplification of the structure of the array substrate is also simplified, and the contact resistance between the jumper and the first trace and the second trace is reduced, and the reliability of the electrical signal transmission is improved, and the power consumption of the entire array substrate is also reduced.
  • FIG. 1 is a schematic view of a cross-line connection of a conventional array substrate
  • FIG. 2 is a schematic diagram of a jumper connection of an array substrate according to an embodiment of the present invention.
  • 3a to 3h are schematic diagrams showing a manufacturing process of an array substrate according to an embodiment of the present invention. detailed description
  • the array substrate provided by the embodiment of the invention includes a display area and a peripheral area (board edge area).
  • a cross-line connection is employed in the peripheral area.
  • the jumper connection specifically includes a base substrate 100, and the first trace 11, the second trace 12, and the third trace 3 located in the first metal layer (gate metal layer) are covered by a first insulating layer 2 (gate insulating layer) on the first metal layer, and a jumper 3 in the second metal layer (source drain metal layer) on the first insulating layer 2.
  • a via 5 corresponding to the first trace 11 and the second trace 12 is opened on the first insulating layer 2, the jumper 3 crosses the third trace 3, and passes through the via 5 and the first trace 11 is connected to the second trace 12 such that the first trace 11 and the second trace 12 are turned on through the jumper 3.
  • the array substrate further includes a second insulating layer 4 (passivation layer) overlying the second metal layer, and a transparent electrode layer (not shown) on the second insulating layer 4.
  • a second insulating layer 4 passivation layer
  • a transparent electrode layer not shown
  • the jumper 3 can directly contact the first trace 11 and the second trace 2 through the via 5 without the jumper 3 and the first trace 11 passing through the transparent electrode.
  • the second trace 12 is connected.
  • the simplification of the structure of the array substrate is also simplified, and the contact resistance between the jumper 3 and the first trace 1 1 and the second trace 12 is reduced, thereby improving the reliability of electrical signal transmission and reducing the overall array substrate. Power consumption.
  • the jumper 3 is directly in contact with the first trace 11 and the second trace 12, and the contact resistance of the jumper 3 is small, so that there is no need to provide many vias, so the etching is performed.
  • the generated charge accumulation is extremely small, so that the occurrence of electrostatic discharge can be effectively avoided, and the yield of the array substrate is improved.
  • an embodiment of the present invention further provides a method for manufacturing the array substrate, including:
  • a pattern of the first metal layer is formed on the base substrate 100 as shown in FIG. 3a.
  • a pattern of the first metal layer may be formed by a process of exposure, development, etching, etc. by using a conventional patterning process, and the pattern of the first metal layer formed includes a gate line and a common electrode line located in the display area (not shown) And the first trace 1 1 , the second trace 12 and the third trace 13 located in the peripheral area.
  • step S2 specifically includes:
  • a first insulating layer 2 covering the first metal layer is formed, and the thickness thereof is preferably 3000A to 4000A.
  • the active layer 20 may be specifically divided into a semiconductor layer (amorphous silicon layer) and a doped semiconductor layer (phosphorus-doped amorphous silicon layer), wherein the thickness of the semiconductor layer is preferably 1000 A to 1500 A, and the thickness of the miscellaneous semiconductor layer is preferably 300A to 50 ⁇ ) ⁇ .
  • S23 coating the active layer 20 with a photoresist 7, preferably having a thickness of 1.5 ⁇ m to 2,2 ⁇ m.
  • the photoresist is exposed using a gray scale mask.
  • the all-transmission region corresponds to the pupil region at the cross-line connection
  • the opaque region corresponds to the silicon island region of the thin film transistor (TFT)
  • the remaining region is a semi-transmissive region.
  • the insulating region of the array substrate corresponds to the insulating region of the array substrate.
  • the photoresist in the via region is completely exposed, the photoresist in the insulating region is partially exposed, and the photoresist in the silicon island region is not exposed.
  • step S24 Since the gray scale mask is used in step S24, after the photoresist 7 is developed, the photoresist in the via region is completely removed; part of the photoresist in the insulating region is removed, and the photoresist in the insulating region is removed. The thickness becomes 0 wrench3 m to 0.7 ⁇ , as shown in Fig. 3c; and the photoresist in the silicon island region (not shown) is completely retained, and its thickness is still 1. 5 ⁇ 2, 2 ⁇ ⁇
  • S26 etching the active layer 20 of the via region and the first insulating layer 2 to form via holes 5 corresponding to the first trace 1 1 and the second trace 12, as shown in FIG. 3d.
  • the active layer 20 and the first insulating layer 2 of the via region are etched away by charged particles by a dry etching process.
  • an overetching method can be employed, but since there are only two via holes 5 in this embodiment, the charge accumulation on the first trace 11 and the second trace 12 It is also very small, so that the occurrence of electrostatic discharge can be effectively avoided, and the yield of the array substrate can be improved.
  • the thickness of the photoresist 7 is reduced by an ashing process to remove the photoresist in the insulating region, as shown in Fig. 3e.
  • the thickness of the photoresist in the silicon island region (not shown) is also reduced, but will not be completely removed.
  • the active layer 20 of the insulating region is etched away, as shown in Fig. 3f.
  • the active layer 20 of the insulating region is etched away by charged particles by a dry etching process.
  • the etching time in this step is short, so that only the active layer 20 of the insulating region can be etched away, while the first insulating layer 2 of the insulating region is retained.
  • a pattern of the second metal layer is formed on the first insulating layer 2. It includes a data line, a source, a drain (not shown) located in the display area, and a jumper 3 located in the peripheral area.
  • the jumper 3 is connected to the first trace 11 and the second trace 12 through the via 5, so that the first trace 11 and the second trace 12 are turned on through the jumper 3, as shown in Fig. 3g.
  • the method for manufacturing the array substrate may further include:
  • a pattern of a transparent electrode layer formed on the second insulating layer including a pixel electrode in each pixel of the display region, and possibly an electrode for other uses (non-cross-line connection use) in the peripheral region.
  • the above steps S3, S4, and S5 can be realized by a conventional patterning process, by exposure, development, etching, and the like.
  • the array substrate provided by the embodiment of the invention can be fabricated by the manufacturing method, the structure of the array substrate is simplified, the contact resistance between the jumper and the first trace and the second trace is reduced, and the array substrate can be improved. Yield rate.
  • the manufacturing method only five masks are required, and the array substrate can be fabricated by five patterning processes, so that the manufacturing cost and manufacturing difficulty of the array substrate are not increased due to structural changes at the jumper connection. .
  • the embodiment of the invention further provides a display device, which may specifically be a liquid crystal television, a liquid crystal display, a mobile phone, a flat panel Computer, etc.
  • the display device includes a color film substrate and the above-described array substrate and the like provided by the embodiments of the present invention.
  • the display device provided by the embodiment of the present invention has the same technical features as the array substrate provided in the above embodiments, so that the same technical problem can be solved and the same technical effect can be achieved. While the embodiments of the present invention have been described above, the described embodiments are merely illustrative of the embodiments of the invention, and are not intended to limit the invention. Any modification and variation of the form and details of the invention may be made by those skilled in the art without departing from the spirit and scope of the invention. It is still subject to the scope defined by the appended claims.

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板，包括：位于第一金属层中的第一走线（11）和第二走线（12）；覆盖于第一金属层上的第一绝缘层（2），在第一绝缘层（2）上开设有对应于第一走线（11）和第二走线（12）的过孔（5）；位于第一绝缘层（2）上的第二金属层中的跨接线（3），跨接线（3）通过过孔（5）与第一走线（11）和第二走线（12）连接，使第一走线（11）和第二走线（12）通过跨接线（3）导通，从而解决了现有的阵列基板中跨接线连接处的阻抗较大的技术问题。

Description

阵列基板及其制造方法、 显示装置 本申请要求享有 2014年 7月 22日提交的名称为"阵列基板及其制造方法、显示装置" 的中国专利申请 CN201410351748.6的优先权， 其全部内容通过引用并入本文中。
本发明涉及显示技术领域， 具体地说， 涉及一种阵列基板及其制造方法、 显示装置。
不
随着显示技术的发展， 液晶显示器己经成为最为常见的显示装置。
阵列基板是液晶显示器中的重要部件，其中包括显示区域和外围区域（非显示区域）。 在阵列基板的外围区域设置有一些走线， 而且有些走线之间需要连接。如图 1所示， 在衬 底基板 00上， 位于第一金属层（楊极金属层）的第一走线 11和第二走线 12需要连接起 来， 但第一走线 11和第二走线 12之间还隔着第：三走线 13， 这就需要将第一走线 1和第 二走线 12进行跨线连接。 现有的跨线连接方法是， 在覆盖着第一金属层上的第一绝缘层 2上设置跨接线 3, 跨接线 3位于的第二金属层 （源漏极金属层） ， 在第二金属层上覆盖 第二绝缘层 4„然后形成穿透第一绝缘层 2和第二绝缘层 4的过孔 51 , 以及穿透第二绝缘 层 4的过孔 52 , 再利用透明电极 6通过过孔 51、 52将第一走线 11、 第二走线 12与跨接 线 3连接， 从而实现第一走线 11与第二走线 12的跨线连接。
透明电极 6的材料通常选用铟锡氧化物 （ITO) 或铟锌氧化物 （IZO) ， 其电阻率比 金属高出 2个数量级， 导致第一走线 11、 第二走线 12与跨接线 3之间的接触阻抗较大， 不利于电信号的传输， 而且增加了阵列基板整体的功耗。 发明内容
本发明的目的在于提供一种阵列基板及其制造方法、显示装置， 以解决现有的阵列基 板中跨线连接处的阻抗较大的技术问题。 本发明提供一种阵列基板， 包括；
位于第一金属层中的第一走线和第二走线；
覆盖于所述第一金属层上的第一绝缘层，在所述第一绝缘层上开设有对应于所述第一 走线和所述第二走线的过孔；
位于所述第一绝缘层上的第二金属层中的跨接线,所述跨接线通过所述过孔与所述第 一走线和所述第二走线连接， 使所述第一走线与所述第二走线通过所述跨接线导通。
进一步， 该阵列基板还包括覆盖亍所述第二金属层上的第二绝缘层。
进一步， 该阵列基板还包括位于所述第二绝缘层上的透明电极层。 优选的，所述第一走线、所述第二走线和所述跨接线均位于所述阵列基板的板边区域。 本发明还提供了上述阵列基板的制造方法， 包括：
步骤 1 , 在衬底基板上形成第一金属层的图形， 其中包括第一走线和第二走线； 步骤 2, 形成覆盖在所述第一金属层上的第一绝缘层的图形， 其中包括对应于所述第 一走线和所述第二走线的过孔；
歩骤 3, 在所述第一绝缘层上形成第二金属层的图形， 其中包括通过所述过孔与所述 第一走线和所述第二走线连接的跨接线，使所述第一走线与所述第二走线通过所述跨接线 导通。
优选的， 在所述步骤 2中， 包括； 形成覆盖在所述第一金属层上的第一绝缘层；
形成覆盖在所述第一绝缘层上的有源层；
在所述有源层上涂覆光刻胶；
利用灰阶光罩对光刻胶进行曝光；
对光刻胶进行显影， 去除过孔区域的光刻胶；
蚀刻掉所述过孔区域的有源层和第一绝缘层，形成对应于所述第一走线和所述第二走 线的 ϋ孔；
对光刻胶进行灰化， 去除绝缘区域的光刻胶；
蚀刻掉所述绝缘区域的有源层； 去除剩余的光刻胶。
进一步， 该制造方法还包括- 歩骤 4, 形成覆盖在所述第二金属层上的第二绝缘层的图形。
进一步， 该制造方法还包括；
步骤 5， 在所述第二绝缘层上形成透明电极层的图形。
优选的，所述第一走线、所述第二走线和所述跨接线均位于所述阵列基板的板边区域 t> 本发明还提供一种显示装置， 包括彩膜基板和上述的阵列基板。
本发明带来了以下有益效果：本发明提供的阵列基板中，通过在第一绝缘层上开设过 孔， 使位于第二金属层的跨接线能够通过过孔直接与第一走线、第二走线相接触， 而不需 要通过透明电极将跨接线与第一走线、第二走线连接。不仅简化了阵列基板的结构， 还降 低了跨接线与第一走线、第二走线之间的接触阻抗， 丛而提高了电信号传输的可靠性， 也 降低了阵列基板整体的功耗。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及 »图中所特别指出的结构来实现和获得。 附圏说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的 »图 做简单的介绍：
图 1是现有的阵列基板的跨线连接处的示意图；
图 2是本发明实施例提供的阵列基板的跨线连接处的示意图；
图 3a至图 3h是本发明实施例提供的阵列基板的制造过程的示意图。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术 手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是, 只要不构成冲突， 本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形 成的技术方案均在本发明的保护范围之内。
本发明实施例提供的阵列基板包括显示区域和外围区域 （板边区域） 。 本实施例中， 在外围区域采用了跨线连接。 如图 2所示， 跨线连接处具体包括衬底基板 100， 位于第一 金属层（栅极金属层） 中的第一走线 11、 第二走线 12和第三走线 3， 覆盖于第一金属层 上的第一绝缘层 2 (栅绝缘层）， 以及位于第一绝缘层 2上的第二金属层（源漏极金属层) 中的跨接线 3。
其中， 在第一绝缘层 2上开设有对应于第一走线 11和第二走线 12的过孔 5 , 跨接线 3跨过第三走线 3, 并通过过孔 5与第一走线 11和第二走线 12连接， 使第一走线 11与 第二走线 12通过跨接线 3导通。
此外， 该阵列基板还进一步包括覆盖于第二金属层上的第二绝缘层 4 (钝化层） ， 以 及位于第二绝缘层 4上的透明电极层 （图中未示出） 。
本发明实施例提供的阵列基板中， 跨接线 3能够通过过孔 5直接与第一走线 11、 第 二走线 2相接触， 而不需要通过透明电极将跨接线 3与第一走线 11、 第二走线 12连接。 不仅简化了阵列基板的结构， 还降低了跨接线 3与第一走线 1 1、 第二走线 12之间的接触 阻抗， 从而提高了电信号传输的可靠性， 也降低了阵列基板整体的功耗。
另夕卜， 在现有技术中 （如图 1所示） ， 由亍透明电极 6的电阻率高于金属， 所以会在 跨线连接处设置大量的密集的过孔，以在一定程度上降低第一金属层与第二金属层之间的 接触阻抗。 但是， 过孔是利用带电粒子通过干法蚀刻而成， 而且为了保证第一绝缘层 2、 第二绝缘层 4能够被完全蚀刻掉， 还会采用过蚀刻的方法， 使带电粒子与第一金属层、第 二金属层过多接触， 而造成第一金属层、 第二金属层上产生电荷积累， 过孔越多， 电荷积 累也越多。 过多的电荷积累会导致阵列基板上的跨线连接处或其他部位发生静电放电 ( Electro-Static Discharge, 简称 ESD) , 造成击穿、 短路等不良后果， 降低了阵列基扳的 良品率。
相比于现有技术， 本实施例中， 跨接线 3直接与第一走线 11、 第二走线 12接触， 本 身的接触阻抗就很小， 所以不需要设置很多过孔， 所以在蚀刻过孔 5的过程中， 所产生的 电荷积累极少， 从而能够有效避免静电放电的发生， 提高了阵列基板的良品率。
如图 3a至图 3h所示， 本发明实施例还提供了该阵列基板的制造方法， 包括：
SI : 如图 3a所示， 在衬底基板 100上形成第一金属层的图形。 本步骤可采用常规的构图工艺， 经曝光、 显影、 蚀刻等工序形成第一金属层的图形， 所形成的第一金属层的图形包括位于显示区域的栅线、 公共电极线（图中未示出） ， 以及 位于外围区域的第一走线 1 1、 第二走线 12和第三走线 13。
82： 形成覆盖在第一金属层上的第一绝缘层的图形， 其中包括对应于第一走线和第
本实施例中，第一绝缘层的图形与有源层的图形在同一次构图工艺中形成， 因此步骤 S2具体包括：
S21 : 如图 3b所示， 形成覆盖在第一金属层上的第一绝缘层 2 , 其厚度优选为 3000A 至 4000A。
S22 : 形成覆盖在第一绝缘层 2上的有源层 20。 有源层 20具体可分为半导体层 （非晶硅层） 和掺杂半导体层 （磷掺杂非晶硅层） ， 其中半导体层的厚度优选为 1000A至 1500A,惨杂半导体层的厚度优选为 300A至 50ί)Α。
S23 : 在有源层 20上涂覆光刻胶 7， 其厚度优选为 1.5μπι至 2,2μιη。
824： 利用灰阶光罩对光刻胶进行曝光。
本实施例采用的灰阶光罩中，全透光区域对应于跨线连接处的 ϋ孔区域，不透光区域 对应于薄膜晶体管（TFT) 的硅岛区域， 其余区域为半透光区域， 对应于阵列基板的绝缘 区域。
利用该灰阶光罩对光刻胶进行曝光之后，过孔区域的光刻胶被完全曝光，绝缘区域的 光刻胶被部分曝光， 硅岛区域的光刻胶没有被曝光。
825： 对光刻胶进行显影。
因为在歩骤 S24中采用了灰阶光罩， 所以对光刻胶 7进行显影之后， 完全去除了过 孔区域的光刻胶； 去除绝缘区域的部分光刻胶， 使绝缘区域的光刻胶的厚度变为 0„3 m 至 0.7μη，如图 3c所示；而硅岛区域（图中未示出）的光刻胶完全保留，其厚度仍为 1。5μηι 全 2,2μτηα
S26: 蚀刻掉过孔区域的有源层 20和第一绝缘层 2 , 形成对应于第一走线 1 1和第二 走线 12的过孔 5 , 如图 3d所示。 通过干法蚀刻工艺， 利用带电粒子蚀刻掉过孔区域的有源层 20和第一绝缘层 2。 为 了保证第一绝缘层 2能够被完全蚀刻掉， 可以采用过蚀刻的方法，但由于本实施例中仅有 两个过孔 5 , 所以第一走线 11和第二走线 12上的电荷积累也非常少， 从而能够有效避免 静电放电的发生， 提高阵列基板的良品率。
S27: 对光刻胶 7进行灰化。
具体的， 利用灰化工艺削减光刻胶 7的厚度， 从而去除绝缘区域的光刻胶， 如图 3e 所示。 同时， 硅岛区域 （图中未示出） 的光刻胶的厚度也会减小， 但不会被完全去除。
S28: 蚀刻掉绝缘区域的有源层 20, 如图 3f所示。 通过干法蚀刻工艺， 利用带电粒子蚀刻掉绝缘区域的有源层 20。 相比于歩骤 S26, 本歩骤中的饨刻时间较短， 因此能够只蚀刻掉绝缘区域的有源层 20， 而保留绝缘区域的 第一绝缘层 2。
S29: 利用灰化工艺， 去除 （硅岛区域） 剩余的光刻胶。
S3： 在第一绝缘层 2上形成第二金属层的图形。 其中包括位于显示区域的数据线、 源极、 漏极（图中未示出） ， 以及位于外围区域的 跨接线 3。 跨接线 3通过过孔 5与第一走线 11和第二走线 12连接， 使第一走线 11与第 二走线 12通过跨接线 3导通， 如图 3g所示。
进一步， 该阵列基板的制造方法还可以包括：
S4: 如图 3h所示， 形成覆盖在第二金属层上的第二绝缘层 4的图形， 其中包括位于 显示区域的每个像素中的过孔， 还可能包括位亍外圏区域的其他用途 （非跨线连接用途） 的过孔。
85： 在第二绝缘层上形成透明电极层的图形， 其中包括位于显示区域的每个像素中 的像素电极， 还可能包括位于外围区域的其他用途 （非跨线连接用途） 的电极。
上述步骤 S3、 S4 , S5均可采用常规的构图工艺， 经曝光、 显影、 蚀刻等工序实现。 采用该制造方法能够制成上述本发明实施例提供的阵列基板， 简化了阵列基板的结 构，降低了跨接线与第一走线、第二走线之间的接触阻抗，还能够提高阵列基板的良品率。 并且， 该制造方法中， 也只需五个光罩， 经五次构图工艺就能够制成阵列基板， 因此并不 会因为跨线连接处的结构变化， 而增加阵列基板的制造成本和制造难度。
本发明实施例还提供一种显示装置， 具体可以是液晶电视、 液晶显示器、 手机、 平板 电脑等。 该显示装置包括彩膜基板和上述本发明实施例提供的阵列基板等部件。 因为本发明实施例提供的显示装置，与上述实施例提供的阵列基板具有相同的技术特 征， 所以也能解决相同的技术问题， 达到相同的技术效果。 虽然本发明所公开的实施方式如上,但所述的内容只是为了便于理解本发明而采用的 实施方式， 并非用以限定本发明。任何本发明所属技术领域内的技术人员， 在不脱离本发 明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但 本发明的专利保护范围， 仍须以所附的权利要求书所界定的范围为准。

Claims

扠利耍求书
一种阵列基板， 包括： 位于第一金属层中的第一走线和第二走线；
覆盖于所述第一金属层上的第一绝缘层，在所述第一绝缘层上开设有对应于所述第一 走线和所述第二走线的过孔； 位于所述第一绝缘层上的第二金属层中的跨接线,所述跨接线通过所述过孔与所述第 一走线和所述第二走线连接， 使所述第一走线与所述第二走线通过所述跨接线导通。
2、 如权利要求 1所述的阵列基板， 其中， 还包括覆盖于所述第二金属层上的第二绝 缘层。
3、 如权利要求 2所述的阵列基板， 其中， 还包括位于所述第二绝缘层上的透明电极 层。
4、 如权利要求 1所述的阵列基板， 其中， 所述第一走线、 所述第二走线和所述跨接 线均位于所述阵列基板的板边区域。
5、 一种阵列基板的制造方法， 包括- 歩骤 1 , 在衬底基板上形成第一金属层的图形， 其中包括第一走线和第二走线； 步骤 2, 形成覆盖在所述第一金属层上的第一绝缘层的图形， 其中包括对应于所述第 一走线和所述第二走线的过孔；
步骤 3， 在所述第一绝缘层上形成第二金属层的图形， 其中包括通过所述过孔与所述 第一走线和所述第二走线连接的跨接线，使所述第一走线与所述第二走线通过所述跨接线 导通。
6、 如权利要求 5所述的方法， 其中， 在所述步骤 2中， 包括： 形成覆盖在所述第一金属层上的第一绝缘层； 形成覆盖在所述第一绝缘层上的有源层； 在所述有源层上涂覆光刻胶； 利^灰阶光罩对光刻胶进行曝光； 对光刻胶进行显影， 去除过孔区域的光刻胶； 蚀刻掉所述过孔区域的有源层和第一绝缘层，形成对应于所述第一走线和所述第二走 线的过孔；
对光刻胶进行灰化， 去除绝缘区域的光刻胶；
蚀刻掉所述绝缘区域的有源层；
去除剩余的光刻胶。
7、 如权利要求 5所述的方法， 其中， 还包括：
步骤 4, 形成覆盖在所述第二金属层上的第二绝缘层的图形。
8、 如权利要求 7所述的方法， 其中， 还包括：
歩骤 5 , 在所述第二绝缘层上形成透明电极层的图形。
9、 如权利要求 5所述的方法， 其中， 所述第一走线、 所述第二走线和所述跨接线均 位于所述阵列基板的板边区域。
10、 一种显示装置， 包括彩膜基板和阵列基板；
所述阵列基板， 包括：
位于第一金属层中的第一走线和第二走线；
覆盖于所述第一金属层上的第一绝缘层，在所述第一绝缘层上开设有对应于所述第一 走线和所述第二走线的过孔；
位于所述第一绝缘层上的第二金属层中的跨接线,所述跨接线通过所述过孔与所述第 一走线和所述第二走线连接， 使所述第一走线与所述第二走线通过所述跨接线导通。
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